ISO1042BDW [TI]
具有 70V 总线故障保护功能和灵活数据速率的隔离式 CAN 收发器 | DW | 16 | -40 to 125;型号: | ISO1042BDW |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 70V 总线故障保护功能和灵活数据速率的隔离式 CAN 收发器 | DW | 16 | -40 to 125 电信 光电二极管 电信集成电路 |
文件: | 总44页 (文件大小:3164K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
具有 70V 总线故障保护功能和灵活数据速率的 ISO1042 隔离式 CAN 收发
器
1 特性
3 说明
1
•
符合 ISO 11898-2:2016 和 ISO 11898-5:2007 物
理层标准
ISO1042 器件是一款符合 ISO11898-2 (2016) 标准规
格的电隔离控制器局域网 (CAN) 收发器。ISO1042 器
件提供 ±70V 直流总线故障保护功能和 ±30V 共模电压
范围。该器件在 CAN FD 模式下最高支持 5Mbps 数据
速率,与经典 CAN 相比可实现更为快速的载荷传输。
该器件采用二氧化硅 (SiO2) 绝缘隔栅,可承受
•
支持经典的最高 1Mbps CAN 和最高 5Mbps FD
(灵活数据速率)
•
•
低环路延迟:152ns
保护 功能
–
–
–
–
直流总线故障保护电压:±70V
总线引脚的 HBM ESD 容差:±16kV
驱动器显性超时 (TXD DTO)
5000VRMS 的电压和 1060VRMS 的工作电压。电磁兼容
性得到了显著增强,可实现系统级 ESD、EFT 和浪涌
并符合辐射标准。与隔离式电源一起使用,此器件可抵
御高电压冲击,并防止总线的噪声电流进入本地接地。
ISO1042 器件可用于基础型和增强型隔离(请参阅 增
强型和基础型隔离选项)。ISO1042 器件支持 –40°C
至 +125°C 的宽环境温度范围。该器件可采用 SOIC-
16 (DW) 和更为小巧的 SOIC-8 (DWV) 封装。
VCC1 和 VCC2 欠压保护
•
•
•
•
共模电压范围:±30V
未上电时的理想无源、高阻抗总线终端
高 CMTI:100kV/µs
V
CC1 电压范围:1.71V 至 5.5V
–
支持连接到 CAN 控制器的 1.8V、2.5V、3.3V
和 5.0V 逻辑接口
器件信息(1)
器件型号
ISO1042
封装
SOIC (8)
SOIC (16)
封装尺寸(标称值)
5.85mm × 7.50mm
10.30mm x 7.50mm
•
•
V
CC2 电压范围:4.5V 至 5.5V
优异的电磁兼容性 (EMC)
–
–
系统级 ESD、EFT 和浪涌抗扰性
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
低辐射
•
•
•
•
环境温度范围:–40°C 至 +125°C
16-SOIC 和 8-SOIC 封装选项
可用的汽车版本:ISO1042-Q1
安全相关认证:
增强型和基础型隔离选项
特性
ISO1042x
加强版
ISO1042Bx
基础版
保护级别
浪涌测试电压
隔离额定值
10000VPK
5000VRMS
6000VPK
5000VRMS
–
符合 DIN VDE V 0884-11:2017-01 标准的
7071VPK VIOTM 和 1500VPK VIORM(增强型和基
本型选项)
1060VRMS/1500 1060VRMS/1500V
工作电压
VPK
PK
–
–
–
UL 1577 标准下,长达 1 分钟的 5000VRMS 隔
离
703A I2C
IEC 60950-1、IEC 60601-1 和 EN 61010-1 认
证
VCC2
8
VCC1
1
VCC1
VCC2
CQC、TUV 和 CSA 认证
VDD
7
6
2
3
CANH
CANL
TXD
MCU
RXD
DGND
TXD
RXD
2 应用
ISO1042
CAN Bus
•
•
•
•
•
•
交流和伺服驱动器
光伏逆变器
4
5
GND2
GND1
PLC 和 DCS 通信模块
升降机和自动扶梯
工业电源
Galvanic
Isolation Barrier
Digital
Ground
ISO
Ground
Copyright © 2017, Texas Instruments Incorporated
电池充电和管理
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLLSF09
ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Transient Immunity.................................................... 5
6.4 Recommended Operating Conditions....................... 5
6.5 Thermal Information.................................................. 6
6.6 Power Ratings........................................................... 6
6.7 Insulation Specifications............................................ 7
6.8 Safety-Related Certifications..................................... 8
6.9 Safety Limiting Values .............................................. 8
6.10 Electrical Characteristics - DC Specification........... 9
6.11 Switching Characteristics...................................... 11
6.12 Insulation Characteristics Curves ......................... 12
6.13 Typical Characteristics.......................................... 13
Parameter Measurement Information ................ 15
7.1 Test Circuits ............................................................ 15
8
9
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
9.3 DeviceNet Application............................................. 27
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 31
12.1 文档支持................................................................ 31
12.2 接收文档更新通知 ................................................. 31
12.3 社区资源................................................................ 31
12.4 商标....................................................................... 31
12.5 静电放电警告......................................................... 31
12.6 Glossary................................................................ 31
13 机械、封装和可订购信息....................................... 31
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision D (October 2019) to Revision E
Page
•
•
已更改 更改了新的安全认证.................................................................................................................................................... 1
Changed Safety Related Certifications section to include new safety certification................................................................ 8
Changes from Revision C (October 2018) to Revision D
Page
•
已添加 ISO1042-Q1(链接) ................................................................................................................................................. 1
Changes from Revision B (July 2018) to Revision C
Page
•
初始发行版 ............................................................................................................................................................................. 1
Changes from Revision A (May 2018) to Revision B
Page
•
Increased the size of the GND2 plane and changed the NC pin to GND2 in the 16-DW Layout Example......................... 30
Changes from Original (December 2017) to Revision A
Page
•
Changed pin 10 from NC to GND2......................................................................................................................................... 3
2
Copyright © 2017–2019, Texas Instruments Incorporated
ISO1042
www.ti.com.cn
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
VCC1
GND1
TXD
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
NC
CANH
CANL
VCC2
RXD
NC
NC
GND2
GND2
GND1
Not to scale
Pin Functions—16 Pins
PIN
NAME
I/O
DESCRIPTION
NO.
1
VCC1
GND1
TXD
NC
—
—
I
Digital-side supply voltage, Side 1
2
Digital-side ground connection, Side 1
3
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
4
—
O
Not connected
5
RXD
NC
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
6
—
—
—
Not connected
7
NC
Not connected
8
GND1
Digital-side ground connection, Side 1
9
GND2
—
Transceiver-side ground connection, Side 2
10
11
12
13
14
15
16
VCC2
CANL
CANH
NC
—
I/O
I/O
—
Transceiver-side supply voltage, Side 2. Must be externally connected to pin 16.
Low-level CAN bus line
High-level CAN bus line
Not connected
GND2
VCC2
—
Transceiver-side ground connection, Side 2
Transceiver-side supply voltage, Side 2. Must be externally connected to pin 11.
—
Copyright © 2017–2019, Texas Instruments Incorporated
3
ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
DWV Package
8-Pin SOIC
Top View
VCC1
TXD
1
2
3
4
8
7
6
5
VCC2
CANH
CANL
GND2
RXD
GND1
Not to scale
Pin Functions—8 Pins
PIN
NAME
I/O
DESCRIPTION
NO.
1
VCC1
TXD
—
I
Digital-side supply voltage, Side 1
2
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
Digital-side ground connection, Side 1
3
RXD
O
4
GND1
GND2
CANL
CANH
VCC2
—
—
I/O
I/O
—
5
Transceiver-side ground connection, Side 2
Low-level CAN bus line
6
7
High-level CAN bus line
8
Transceiver-side supply voltage, Side 2
4
Copyright © 2017–2019, Texas Instruments Incorporated
ISO1042
www.ti.com.cn
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
-0.5
-0.5
MAX
UNIT
V
VCC1
VCC2
Supply voltage, side 1
Supply voltage, side 2
6
6
V
Logic input and output voltage range (TXD and
RXD)
VIO
-0.5
VCC1+0.5(3)
V
IO
Output current on RXD pin
-15
-70
-70
-40
-65
15
70
mA
V
VBUS
VBUS_DIFF
TJ
Voltage on bus pins (CANH, CANL)
Differential voltage on bus pins (CANH-CANL)
Junction temperature
70
V
150
150
℃
℃
TSTG
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
UNIT
Electrostatic discharge
All pins(1)
±6000
V
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
CANH and CANL to GND2(1)
±16000
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
V
All pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Transient Immunity
PARAMETER
TEST CONDITIONS
VALUE
UNIT
Pulse 1; CAN bus terminals (CANH, CANL) to
GND2
-100
V
V
V
V
Pulse 2; CAN bus terminals (CANH, CANL) to
GND2
75
ISO7637-2 Transients according to GIFT - ICT
CAN EMC test specification
VPULSE
Pulse 3a; CAN bus terminals (CANH, CANL) to
GND2
-150
100
Pulse 3b; CAN bus terminals (CANH, CANL) to
GND2
6.4 Recommended Operating Conditions
MIN
MAX
1.89
5.5
UNIT
V
Supply Voltage, Side 1, 1.8-V operation
VCC1
1.71
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation
Supply Voltage, Side 2
2.25
4.5
V
VCC2
TA
5.5
V
Operating ambient temperature
-40
125
°C
Copyright © 2017–2019, Texas Instruments Incorporated
5
ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
6.5 Thermal Information
ISO1042
THERMAL METRIC(1)
DW (SOIC)
16 PINS
69.9
DWV (SOIC)
8 PINS
100
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
31.8
40.8
29.0
51.8
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.2
16.8
ΨJB
28.6
49.8
RΘJC(bot)
-
-
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See 图 17, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, A repetitive pattern on
TXD with 1 ms time period, 990 µs LOW
time, and 10 µs HIGH time.
PD
Maximum power dissipation (both sides)
385
mW
See 图 19, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, Input a 2-V pk-pk 2.5-
MHz 50% duty cycle differential square
wave on CANH-CANL
PD1
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
25
mW
mW
See 图 17, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, A repetitive pattern on
TXD with 1 ms time period, 990 µs LOW
time, and 10 µs HIGH time.
PD2
360
6
Copyright © 2017–2019, Texas Instruments Incorporated
ISO1042
www.ti.com.cn
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
6.7 Insulation Specifications
PARAMETER
SPECIFICATIONS
TEST CONDITIONS
UNIT
DW-16
DWV-8
IEC 60664-1
CLR
External clearance(1)
Side 1 to side 2 distance through air
>8
>8.5
mm
mm
Side 1 to side 2 distance across package
surface
CPG
External Creepage(1)
>8
>8.5
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
>17
>600
I
>17
>600
I
µm
V
According to IEC 60664-1
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
I-IV
I-III
Overvoltage category
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
1060
1500
7071
1500
1060
1500
7071
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test;
VIOWM
Maximum isolation working voltage
Maximum transient isolation voltage
DC voltage
VTEST = VIOTM, t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
VPK
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 10000 VPK 6250
(qualification)
Maximum surge isolation voltage
ISO1042(3)
6250
4615
≤ 5
VPK
VIOSM
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6000 VPK
(qualification)
Maximum surge isolation voltage
ISO1042B(3)
4615
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM
,
≤ 5
tm = 10 s
Method a: After environmental tests subgroup
1, Vini = VIOTM, tini = 60 s;
ISO1042: Vpd(m) = 1.6 × VIORM, tm = 10 s
ISO1042B: Vpd(m) = 1.2 × VIORM, tm = 10 s
≤ 5
≤ 5
≤ 5
≤ 5
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM
,
tini = 1 s;
ISO1042: Vpd(m) = 1.875 × VIORM, tm = 1 s
ISO1042B: Vpd(m) = 1.5 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
1
1
pF
> 1012
> 1011
> 109
2
> 1012
> 1011
> 109
2
VIO = 500 V, 100°C ≤ TA ≤ 150°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
40/125/
21
40/125/
21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST
1.2 × VISO , t = 1 s (100% production)
=
VISO
Withstand isolation voltage
5000
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO1042 is suitable for safe electrical insulation and ISO1042B is suitable for basic electrical insulation only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
Copyright © 2017–2019, Texas Instruments Incorporated
7
ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
6.8 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010/A1:2019,
EN 60950-
1:2006/A2:2013 and EN
62368-1:2014
Certified according to IEC Recognized under UL
Certified according to DIN
VDE V 0884-11:2017- 01
Certified according to
GB4943.1-2011
60950-1, IEC 62368-1
and IEC 60601-1
1577 Component
Recognition Program
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2 and IEC
62368-1 2nd Ed., for
pollution degree 2,
material group I
ISO1042: 800 VRMS
reinforced isolation
ISO1042B: 1060 VRMS
basic isolation
EN 61010-1:2010
/A1:2019
ISO1042: 600 VRMS
reinforced isolation
ISO1042B: 1000 VRMS
basic isolation
Maximum transient
isolation voltage,
7071 VPK
;
Maximum repetitive peak
isolation voltage,
Reinforced insulation,
Altitude ≤ 5000 m, Tropical
Climate,
700 VRMS maximum working
voltage
Single protection,
5000 VRMS
1500 VPK
;
----------------
EN 60950-
Maximum surge isolation
voltage,
ISO1042: 6250 VPK
(Reinforced)
ISO1042B: 4615 VPK
(Basic)
----------------
1:2006/A2:2013 and EN
62368-1:2014
ISO1042-: 800 VRMS
reinforced isolation
ISO1042B: 1060 VRMS
basic isolation
CSA 60601- 1:14 and IEC
60601-1 Ed. 3.1+A1,
ISO1042: 2 MOPP
(Means of Patient
Protection) 250 VRMS (354
VPK) maximum working
voltage
Certificates:
Reinforced: 40040142
Basic: 40047657
Certificate:
Master contract number:
220991
File number: E181974 CQC15001121716 (DW-16) Client ID number: 77311
CQC18001199096 (DWV-8)
6.9 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
DW-16 PACKAGE
TEST CONDITIONS
MIN TYP MAX UNIT
RθJA = 69.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图 1
RθJA = 69.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图 1
RθJA = 69.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图 1
RθJA = 69.9°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see 图 1
325
496
mA
650
Safety input, output, or supply
current
IS
946
Safety input, output, or total
power
PS
TS
RθJA = 69.9°C/W, TJ = 150°C, TA = 25°C, see 图 3
1788 mW
150 °C
Maximum safety temperature
DWV-8 PACKAGE
RθJA = 100°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图 2
RθJA = 100°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图 2
RθJA = 100°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图 2
RθJA = 100°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see 图 2
227
347
mA
454
Safety input, output, or supply
current
IS
661
Safety input, output, or total
power
PS
TS
RθJA = 100°C/W, TJ = 150°C, TA = 25°C, see 图 4
1250 mW
150 °C
Maximum safety temperature
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
8
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6.10 Electrical Characteristics - DC Specification
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CHARACTERISTICS
VCC1 =1.71 V to 1.89 V, TXD = 0 V, bus
dominant
2.3
2.4
1.2
1.3
3.5
3.5
2.1
2.1
mA
mA
mA
mA
VCC1 = 2.25 V to 5.5 V, TXD = 0 V, bus
dominant
ICC1
Supply current Side 1
Supply current Side 2
VCC1 = 1.71 V to 1.89 V, TXD = VCC1
,
bus recessive
VCC1 = 2.25 V to 5.5 V, TXD = VCC1, bus
recessive
TXD = 0 V, bus dominant, RL = 60 Ω
TXD = VCC1, bus recessive, RL = 60 Ω
43
73.4
4.1
mA
mA
V
ICC2
2.8
UVVCC1
UVVCC1
Rising under voltage detection, Side 1
Falling under voltage detection, Side 1
1.7
1.0
75
V
VHYS(UVC Hysterisis voltage on VCC1 undervoltage
C1)
125
mV
lock-out
UVVCC2
UVVCC2
Rising under voltage detection, side 2
Falling under voltage detection, side 2
4.2
4.0
4.45
4.25
V
V
3.8
VHYS(UVC Hysterisis voltage on VCC2 undervoltage
200
mV
lock-out
C2)
TXD TERMINAL
VIH
VIL
IIH
High level input voltage
0.7×VCC1
V
V
Low level input voltage
0.3×VCC1
1
High level input leakage current
Low level input leakage current
TXD = VCC1
TXD = 0V
uA
uA
IIL
-20
VIN = 0.4 x sin(2 x π x 1E+6 x t) + 2.5 V,
VCC1 = 5 V
CI
Input capacitance
3
pF
RXD TERMINAL
See 图 18, IO = -4 mA for 4.5 V ≤ VCC1
5.5 V
≤
-0.4
-0.2
-0.1
-0.1
-0.2
-0.07
-0.04
-0.045
0.2
V
V
V
V
V
V
V
V
See 图 18, IO = -2 mA for 3.0 V ≤ VCC1
≤ 3.6 V
VOH
VCC1
-
High level output voltage
See 图 18, IO = -1 mA for 2.25 V ≤ VCC1
≤ 2.75 V
See 图 18, IO = -1 mA for 1.71 V ≤ VCC1
≤ 1.89 V
See 图 18, IO = 4 mA for 4.5 V ≤ VCC1
≤
0.4
0.2
0.1
0.1
5.5 V
See 图 18, IO = 2 mA for 3.0 V ≤ VCC1
≤ 3.6 V
0.07
VOL
Low level output voltage
See 图 18, IO = 1 mA for 2.25 V ≤ VCC1
2.75 V
≤
≤
0.035
0.04
See 图 18, IO = 1 mA for 1.71 V ≤ VCC1
1.89 V
DRIVER ELECTRICAL CHARACTERISTICS
See 图 15 and 图 16, TXD = 0 V, 50 Ω ≤
RL ≤ 65 Ω, CL = open
Bus output voltage(Dominant), CANH
VO(DOM)
2.75
0.5
4.5
2.25
3.0
V
V
V
See 图 15 and 图 16, TXD = 0 V, 50 Ω ≤
RL ≤ 65 Ω, CL = open
Bus output voltage(Dominant), CANL
Bus output voltage(recessive), CANH
and CANL
See 图 15 and 图 16, TXD = VCC1, RL
=
0.5 x
VCC2
VO(REC)
2.0
open
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Electrical Characteristics - DC Specification (continued)
Over recommended operating conditions (unless otherwise noted)
PARAMETER
Differential output voltage, CANH-CANL See 图 15 and 图 16, TXD = 0 V, 45 Ω ≤
(dominant) L ≤ 50 Ω, CL = open
Differential output voltage, CANH-CANL See 图 15 and 图 16, TXD = 0 V, 50 Ω ≤
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.4
3.0
3.0
V
R
VOD(DOM)
1.5
1.5
V
(dominant)
Differential output voltage, CANH-CANL See 图 15 and 图 16, TXD = 0 V, RL
(dominant) 2240 Ω, CL = open
Differential output voltage, CANH-CANL See 图 15 and 图 16, TXD = VCC1, RL
(recessive) 60 Ω, CL = open
Differential output voltage, CANH-CANL See 图 15 and 图 16, TXD = VCC1, RL
RL ≤ 65 Ω, CL = open
=
5.0
V
=
=
-120.0
-50.0
-400.0
-100.0
12.0
50.0
400.0
mV
mV
mV
mA
mA
mA
VOD(REC)
(recessive)
open, CL = open
DC Output symmetry (VCC2 - VO(CANH)
-
See 图 15 and 图 16, RL = 60 Ω, CL =
VSYM_DC
VO(CANL)
)
open, TXD = VCC1 or 0 V
See 图 23, VCANH = -5 V to 40 V, CANL
= open, TXD = 0 V
ISO(SS_DO Short circuit current steady state output
current, dominant
M)
See 图 23, VCANL = -5 V to 40 V, CANH
100.0
5.0
= open, TXD = 0 V
ISO(SS_RE Short circuit current steady state output
See 图 23, -27 V ≤ VBUS ≤ 32 V, VBUS
-5.0
current, recessive
= CANH = CANL, TXD = VCC1
C)
RECEIVER ELECTRICAL CHARACTERISTICS
Differential input threshold voltage
See 图 18 and 表 1, |VCM| ≤ 20 V
500.0
400.0
900.0
VIT
Differential input threshold voltage
See 图 18 and 表 1, 20 V ≤ |VCM| ≤ 30 V
1000.0
mV
Hysteresis voltage for differential input
threshold
VHYS
See 图 18 and 表 1
120
VCM
Input common mode range
See 图 18 and 表 1
-30.0
30.0
4.8
V
CANH = CANL = 5 V, VCC2 to GND via 0
Ω and 47 kΩ resistor
IOFF(LKG) Power-off bus input leakage current
uA
Input capacitance to ground (CANH or
CANL)
CI
TXD = VCC1
TXD = VCC1
24.0
12.0
30
15
pF
pF
Differential input capacitance (CANH-
CANL)
CID
RID
RIN
Differential input resistance
TXD = VCC1 ; -30 V ≤ VCM ≤ +30 V
TXD = VCC1 ; -30 V ≤ VCM ≤ +30 V
30.0
15.0
80.0
40.0
kΩ
kΩ
Input resistance (CANH or CANL)
Input resistance matching: (1 -
RIN(CANH)/RIN(CANL)) x 100%
RIN(M)
VCANH = VCANL = 5 V
-2.0
2.0
%
THERMAL SHUTDOWN
TTSD
Thermal shutdown temperature
170
5
℃
℃
TTSD_HYS
T
Thermal shutdown hysteresis
10
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6.11 Switching Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
70
TYP
125
122
155
152
MAX
198.0
192.0
215.0
UNIT
ns
DEVICE SWITCHING CHARACTERISTICS
See 图 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤
V
CC1 ≤ 1.89 V
tPROP(LO Total loop delay, driver input TXD to
receiver RXD, recessive to dominant
OP1)
See 图 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤
70
ns
V
CC1 ≤ 5.5 V
See 图 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤ VCC1
70
ns
≤
1.89 V
tPROP(LO Total loop delay, driver input TXD to
receiver RXD, dominant to recessive
OP2)
See 图 20, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤
CC1 ≤ 5.5 V
70
215.0
300.0
ns
V
Time for device to return to normal
tUV_RE_E
NABLE
Re-enable time after Undervoltage event operation from VCC1 or VCC2 under
voltage event
µs
CMTI
Common mode transient immunity
VCM = 1200 VPK, See 图 24
85
100
kV/µs
DRIVER SWITCHING CHARACTERISTICS
Propagation delay time, HIGH TXD to
driver recessive
tpHR
76
61
120
120
Propagation delay time, LOW TXD to
driver dominant
See 图 17, RL = 60 Ω and CL = 100
pF; input rise/fall time (10% to 90%) on
TXD =1 ns
tpLD
ns
tsk(p)
tR
Pulse skew (|tpHR - tpLD|)
14
45
45
Differential output signal rise time
Differential output signal fall time
tF
See 图 17 and 图 31 , RTERM = 60 Ω,
CSPLIT = 4.7 nF, CL = open, RL = open,
TXD = 250 kHz, 1 MHz
Output symmetry (dominant or
recessive) (VO(CANH) + VO(CANL)) / VCC2
VSYM
0.9
1.2
1.1
3.8
V/V
ms
tTXD_DTO Dominant time out
See 图 22, RL = 60 Ω and CL = open
RECEIVER SWITCHING CHARACTERISTICS
Propagation delay time, bus recessive
input to RXD high output
tpRH
75
63
130
130
ns
ns
Propogation delay time, bus dominant
input to RXD low output
tpDL
See 图 19, CL(RXD) = 15 pF
tR
tF
Output signal rise time(RXD)
Output signal fall time(RXD)
1.4
1.8
ns
ns
FD TIMING PARAMETERS
See 图 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on CAN bus output pins with
tBIT(TXD) = 500 ns
435.0
155.0
400
530.0
210.0
550.0
220.0
ns
ns
ns
ns
tBIT(BUS)
See 图 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on CAN bus output pins with
tBIT(TXD) = 200 ns
See 图 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on RXD output pins with tBIT(TXD)
= 500 ns
tBIT(RXD)
See 图 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on RXD output pins with tBIT(TXD)
= 200 ns
120.0
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Switching Characteristics (continued)
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See 图 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD)
- tBIT(BUS)
Receiver timing symmetry with tBIT(TXD)
500 ns
=
=
-65.0
40.0
15.0
ns
∆tREC
See 图 21, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC =
tBIT(RXD) - tBIT(BUS)
Receiver timing symmetry with tBIT(TXD)
200 ns
-45.0
ns
6.12 Insulation Characteristics Curves
1000
700
600
500
400
300
200
100
0
VCC1 =1.89 V
VCC1 = 2.75 V
VCC1 = 3.6 V
VCC1 = VCC2 = 5.5 V
VCC1 = 1.89 V
VCC1 = 2.75 V
VCC1 = 3.6 V
900
800
VCC1 = VCC2 = 5.5 V
700
600
500
400
300
200
100
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D003
D001
图 1. Thermal Derating Curve for Limiting Current per VDE
图 2. Thermal Derating Curve for Limiting Current per VDE
for DW-16 Package
for DWV-8 Package
2000
1800
1600
1400
1200
1000
800
1400
1200
1000
800
600
400
200
0
600
400
200
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D004
D002
图 3. Thermal Derating Curve for Limiting Power per VDE for
图 4. Thermal Derating Curve for Limiting Power per VDE for
DW-16 Package
DWV-8 Package
12
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6.13 Typical Characteristics
50
45
40
35
30
25
2.3
2.25
2.2
VCC1=1.71 V
VCC1=1.8 V
VCC1=2.5 V
VCC1=3.3 V
VCC1=5 V
VCC1=5.5 V
2.15
2.1
2.05
2
1.95
1.9
20
15
10
5
1.85
1.8
Recessive
Dominant
500 kbps
1 Mbps
2 Mbps
5 Mbps
1.75
1.7
1.65
1.6
0
1.55
4.5 4.6 4.7 4.8 4.9
5
VCC2 (V)
5.1 5.2 5.3 5.4 5.5
0
0.5
1
1.5
2
2.5
3
Data Rate (Mbps)
3.5
4
4.5
5
D001
D002
VCC1 = 5 V
RL = 60 Ω
CL(RXD) = 15 pF
VCC2 = 5 V
RL = 60 Ω
CL(RXD) = 15 pF
Temp = 25°C
Temp = 25°C
图 5. ICC2 vs VCC2 for Recessive, Dominant and Different
图 6. ICC1 vs Datarate
CAN Datarates
45
40
35
30
25
20
3
Recessive
Dominant
500 kbps
1 Mbps
2 Mbps
5 Mbps
2.75
2.5
2.25
2
1.75
1.5
1.25
1
Recessive
Dominant
500 kbps
1 Mbps
2 Mbps
5 Mbps
15
10
5
0
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
D003
D004
VCC1 = VCC2 = 5 V
RL = 60 Ω
CL(RXD) = 15 pF
VCC1 = VCC2 = 5 V
Temp = 25°C
RL = 60 Ω
CL(RXD) = 15 pF
图 7. ICC2 vs Ambient Temperature for Recessive, Dominant
and Different CAN Datarates
图 8. : ICC1 vs Ambient Temperature for Recessive,
Dominant and Different CAN Datarates.
180
3
2.5
2
tPROP(LOOP1)
tPROP(LOOP2)
170
160
150
140
130
120
110
100
1.5
1
0.5
0
-60 -40 -20
0
20
40
60
80 100 120 140
-55
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
Temperature (èC)
D005
D001
VCC1 = VCC2 = 5 V
RL = 60 Ω
CL(RXD) = 15 pF
VCC = 5 V
CL = Open
VCC1 = 5 V
RL = 60 Ω
图 9. Loop Delay vs Ambient Temperature
图 10. VOD(DOM) Over Temperature
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Typical Characteristics (接下页)
3
2.5
2
1.5
1
0.5
VCC1 = VCC2 = 5 V
CL(RXD) = 15 pF
RL = 60 Ω
CL = 100 pF
0
4.5 4.6 4.7 4.8 4.9
5
VCC (V)
5.1 5.2 5.3 5.4 5.5
D002
图 12. Typical TXD, RXD, CANH and CANL Waveforms at 1
VCC1 = 5 V
CL = Open
RL = 60 Ω
Mbps
Temp = 25°C
图 11. VOD(DOM) Over VCC
TXD = VCC1
RL = 60 Ω
VCC1 = VCC2 = 5 V
TXD = VCC1
RL = 60 Ω
VCC1 = VCC2 = 5 V
图 13. Glitch Free Power Up on VCC1 – CAN Bus Remains
图 14. Glitch Free Power Up on VCC2 – CAN Bus Remains
Recessive
Recessive
14
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
7 Parameter Measurement Information
7.1 Test Circuits
IO(CANH)
CANH
II
0 or
Vcc1
VOD
RL
VO(CANH)
V
O(CANL)
+
2
TXD
CANL
IO(CANL)
GND1
GND2
VI
VOC
VO(CANH)
VO(CANL )
GND1
GND2
图 15. Driver Voltage, Current and Test Definitions
Dominant
V
O
(CANH)
» 3.5 V
Recessive
2.5 V
»
V
1.5 V
O (CANL)
»
图 16. Bus Logic State Voltage Definitions
Vcc
0 V
CANH
CANL
V
Vcc/2
Vcc/2
I
TXD
RL
VO
CL
t
t
PLH
PHL
V
O(D)
90%
10%
0.9V
VI
V
O
0.5V
(SEE NOTE A)
V
t
t
f
O(R)
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
图 17. Driver Test Circuit and Voltage Waveforms
CANH
IO
VI(CANH) VI(CANL)
RXD
+
VIC
VID
CANL
=
2
VI(CANH)
VO
VI(CANL)
GND2
GND1
图 18. Receiver Voltage and Current Definitions
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Test Circuits (接下页)
CANH
I
O
3.5 V
RXD
V
2.4 V
I
2 V
CANL
1.5 V
pHL
t
t
pLH
0.7 Vcc 1
V
V
OH
O
V
I
CL(RXD)
90 %
10 %
(SEE NOTE A)
1 .5 V
0.3 Vcc 1
V
O
V
t
t
f
OL
r
GND 1
GND 2
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
图 19. Receiver Test Circuit and Voltage Waveforms
表 1. Receiver Differential Input Voltage Threshold Test
INPUT
VCANL
OUTPUT
VCANH
-29.5 V
30.5 V
|VID
|
RXD
-30.5 V
29.5 V
1000 mV
1000 mV
900 mV
900 mV
500 mV
500 mV
400 mV
400 mV
X
L
L
VOL
-19.55 V
20.45 V
-19.75 V
20.25 V
-29.8 V
30.2 V
-20.45 V
19.55 V
-20.25 V
19.75 V
-30.2 V
29.8 V
L
L
H
H
H
H
H
VOH
Open
Open
CANH
CANL
TXD
RXD
CL
RL
V
Vcc
I
50%
TXD Input
0 V
V
t
loop2
t
loop1
OH
50%
50%
RXD Output
+
V
OL
CL(RXD)
GND1
VO
_
图 20. tLOOP Test Circuit and Voltage Waveforms
16
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
VI
70%
TXD
CANH
30%
30%
0V
tBIT(TXD)
TXD
5 x tBIT
VI
CL
RL
CANL
tBIT(BUS)
900 mV
VDIFF
RXD
500 mV
CL(RXD)
GND1
VO
VOH
70%
RXD
30%
tBIT(RXD)
VOL
图 21. CAN FD Timing Parameter Measurement
Vcc
0 V
V
I
CANH
CANH
TXD
R
V
C
OD
L
L
V
OD(D)
(see Note A )
GND 1
900 mV
V
I
V
OD
500 mV
tTXD_DTO
0 V
A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
图 22. Dominant Time-out Test Circuit and Voltage Waveforms
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
+
VBUS
CANL
VBUS
0V
0V
œ
GND2
or
VBUS
VBUS
图 23. Driver Short-Circuit Current Test Circuit and Waveforms
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ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
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C = 0.1 F
m
1%
V
V
CC 1
CC2
V
CC 1
±
CANH
60 W
C = 0.1 F ±1%
m
+
GND1
TXD
GND
2
V
V
OL
OH
or
S1
CANL
0 V
RXD
V
V
OL
OH
or
1 k W
GND 1
GND 2
C
L
= 15 pF
(includes probe and
jig capacitance )
V
CM
图 24. Common-Mode Transient Immunity Test Circuit
18
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ISO1042
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
8 Detailed Description
8.1 Overview
The ISO1042 device is a digitally isolated CAN transceiver that offers ±70-V DC bus fault protection and ±30-V
common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing much
faster transfer of payload compared to classic CAN. The ISO1042 device has an isolation withstand voltage of
5000 VRMS and is available in basic and reinforced isolation with a surge test voltage of 6 kVPK and 10 kVPK
respectively. The device can operate from 1.8-V, 2.5-V, 3.3-V, and 5-V supplies on side 1 and a 5-V supply on
side 2. This supply range is of particular advantage for applications operating in harsh industrial environments
because the low voltage on side 1 enables the connection to low-voltage microcontrollers for power
conservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the bus signals.
8.2 Functional Block Diagram
VCC1
VCC2
CANH
CANL
+
RXD
œ
TXD
GND1
GND2
8.3 Feature Description
8.3.1 CAN Bus States
The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic
low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a
common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic
high. The host microprocessor of the CAN node uses the TXD pin to drive the bus and receives data from the
bus on the RXD pin. See 图 25 and 图 26.
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19
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Feature Description (接下页)
4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time (t)
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
图 25. Bus States (Physical Bit Representation)
CANH
RXD
VCC / 2
CANL
图 26. Simplified Recessive Common Mode Bias and Receiver
8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
The VCC1 supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V,
and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible.
注
The TXD pin is very weakly internally pulled up to VCC1. An external pullup resistor should
be used to make sure that the TXD pin is biased to recessive (high) level to avoid issues
on the bus if the microprocessor does not control the pin and the TXD pin floats. The TXD
pullup strength and CAN bit timing require special consideration when the device is used
with an open-drain TXD output on the CAN controller of the microprocessor. An adequate
external pullup resistor must be used to make sure that the TXD output of the
microprocessor maintains adequate bit timing input to the input on the transceiver.
20
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ISO1042
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
Feature Description (接下页)
8.3.3 Protection Features
8.3.3.1 TXD Dominant Timeout (DTO)
The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware
or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit
timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge
occurs before the timeout period expires, which frees the bus for communication between other nodes on the
network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD
DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased
to the recessive level during a TXD dominant timeout.
TXD fault stuck dominant
Example: PCB failure or bad software
Fault is repaired and transmission
capability is restored
TXD
(driver)
tTXD_DTO
Driver disabled freeing bus for other nodes
Bus would be stuck dominant, blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
communication after the tTXD_DTO time.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus nodes
Communication from
repaired nodes
RXD
(receiver)
Communication from
local node
Communication from
other bus nodes
Communication from
repaired nodes
图 27. Example Timing Diagram for TXD DTO
注
The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the
minimum possible transmitted data rate of the device. The CAN protocol allows a
maximum of eleven successive dominant bits (on TXD) for the worst case, where five
successive dominant bits are followed immediately by an error frame. This, along with the
tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data
rate with 公式 1.
Minimum Data Rate = 11 / tTXD_DTO
(1)
8.3.3.2 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the
CAN driver circuits, blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the
recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown
condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature
(TTSD_HYST) below the thermal shutdown temperature (TTSD) of the device.
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ISO1042
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www.ti.com.cn
Feature Description (接下页)
8.3.3.3 Undervoltage Lockout and Default State
The supply pins have undervoltage detection that places the device in protected or default mode which protects
the bus during an undervoltage event on the VCC1 or VCC2 supply pins. If the bus-side power supply, VCC2, is less
than about 4 V, the power shutdown circuits in the ISO1042 device disable the transceiver to prevent false
transmissions because of an unstable supply. If the VCC1 supply is still active when this occurs, the receiver
output (RXD) goes to a default HIGH (recessive) value. 表 2 summarizes the undervoltage lockout and fail-safe
behavior.
表 2. Undervoltage Lockout and Default State
VCC1
VCC2
DEVICE STATE
Functional
BUS OUTPUT
Per Device State and TXD
Recessive
RXD
> UVVCC1
<UVVCC1
>UVVCC1
> UVVCC2
> UVVCC2
< UVVCC2
Mirrors Bus
Protected
Undetermined
Protected
High Impedance
Recessive (Default High)
注
After an undervoltage condition is cleared and the supplies have returned to valid levels,
the device typically resumes normal operation in 300 µs.
8.3.3.4 Floating Pins
Pullup and pulldown resistors should be used on critical pins to place the device into known states if the pins
float. The TXD pin should be pulled up through a resistor to the VCC1 pin to force a recessive input level if the
microprocessor output to the pin floats.
8.3.3.5 Unpowered Device
The device is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which
is critical if some nodes of the network are unpowered while the rest of the of network remains in operation.
8.3.3.6 CAN Bus Short Circuit Current Limiting
The device has two protection features that limit the short circuit current when a CAN bus line has a short-circuit
fault condition. The first protection feature is driver current limiting (both dominant and recessive states) and the
second feature is TXD dominant state time out to prevent permanent higher short circuit current of the dominant
state during a system fault. During CAN communication the bus switches between dominant and recessive
states, therefore the short circuit current may be viewed either as the instantaneous current during each bus
state or as an average current of the two states. For system current (power supply) and power considerations in
the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the
ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and
PHY that force either recessive or dominant at certain times:
•
•
•
•
Control fields with set bits
Bit stuffing
Interframe space
TXD dominant time out (fault case limiting)
These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high
percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant
bits and their respective short circuit currents. Use 公式 2 to calculate the average short circuit current.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC
]
where
•
•
•
IOS(AVG) is the average short circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
22
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ISO1042
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
•
•
•
•
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short circuit current
IOS(SS)_DOM is the dominant steady state short circuit current
(2)
注
Consider the short circuit current and possible fault cases of the network when sizing the
power ratings of the termination resistance and other network components.
8.4 Device Functional Modes
表 3 and 表 4 list the driver and receiver functions. 表 5 lists the functional modes for the ISO1042 device.
表 3. Driver Function Table
INPUT
TXD(1)
OUTPUTS
DRIVEN BUS STATE
CANH(1)
CANL(1)
L
H
Z
L
Z
Dominant
Recessive
H
(1) H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See 图 25 and 图 26 for
bus state and common mode bias information.
表 4. Receiver Function Table
CAN DIFFERENTIAL INPUTS
DEVICE MODE
BUS STATE
RXD PIN(2)
(1)
VID = VCANH – VCANL
VID ≥ VIT(MAX)
Dominant
?
L
?
VIT(MIN) < VID < VIT(MAX)
VID ≤ VIT(MIN)
Normal
Recessive
Open
H
H
Open (VID ≈ 0 V)
(1) See Receiver Electrical Characteristics section for input thresholds.
(2) H = high level, L = low level, ? = indeterminate.
表 5. Function Table(1)
DRIVER
RECEIVER
OUTPUT
INPUTS
TXD
L(3)
OUTPUTS
DIFFERENTIAL INPUTS
VID = CANH–CANL(2)
BUS STATE
BUS STATE
RXD
CANH
CANL
H
Z
Z
Z
L
Z
Z
Z
DOMINANT
RECESSIVE
RECESSIVE
RECESSIVE
VID ≥ VIT(MAX)
VIT(MIN) < VID < VIT(MAX)
VID ≤ VIT(MIN)
L
?
DOMINANT
?
H
Open
X
H
H
RECESSIVE
RECESSIVE
Open (VID ≈ 0 V)
(1) H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
(2) See Receiver Electrical Characteristics section for input thresholds.
(3) Logic low pulses to prevent dominant time-out.
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ISO1042
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www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO1042 device can be used with other components from Texas Instruments such as a microcontroller, a
transformer driver, and a linear voltage regulator to form a fully isolated CAN interface.
9.2 Typical Application
4
8
1
3
5
4
GND
D2
IN
OUT
NC
EN
SN6505
3
2
7
6
3.3 V
TPS76350
EN
VCC
2
GND
1
5
CLK
D1
11,16
1
VCC1
VCC2
2
3
GND1
VDD
14
13
NC
TXD
TXD
ISO1042
4
5
NC
CANH
MCU
12
RXD
RXD
CANL
L1 3.3V
NC
Optional bus
protection
function
6
DGND
N
PSU
7
8
NC
9,10,15
0V
PE
GND1
GND2
Galvanic
Isolation Barrier
Protective Chasis
Earth
Digital
Ground
ISO
Ground
Ground
图 28. Application Circuit With ISO1042 in 16-SOIC Package
24
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ISO1042
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
Typical Application (接下页)
4
8
1
3
5
4
GND
D2
IN
OUT
NC
EN
SN6505
3
2
7
6
3.3 V
TPS76350
EN
VCC
D1
2
GND
1
5
CLK
8
3.3 V
1
VCC1
TXD
VCC2
VDD
7
6
2
3
CANH
CANL
TXD
MCU
RXD
ISO1042
RXD
Optional bus
protection
function
DGND
4
5
GND2
GND1
Galvanic
Isolation Barrier
Digital
Ground
ISO
Ground
Copyright © 2017, Texas Instruments Incorporated
图 29. Application Circuit With ISO1042 in 8-SOIC Package
9.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1042 device only requires external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
9.2.2.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.
A large number of nodes requires transceivers with high input impedance such as the ISO1042 transceivers.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 Standard. These organizations and standards have made system-level trade-offs for data rate, cable
length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen,
DeviceNet, and NMEA2000.
The ISO1042 device is specified to meet the 1.5-V requirement with a 50-Ω load, incorporating the worst case
including parallel transceivers. The differential input resistance of the ISO1042 device is a minimum of 30 kΩ. If
100 ISO1042 transceivers are in parallel on a bus, this requirement is equivalent to a 300-Ω differential load
worst case. That transceiver load of 300 Ω in parallel with the 60 Ω gives an equivalent loading of 50 Ω.
Therefore, the ISO1042 device theoretically supports up to 100 transceivers on a single bus segment. However,
for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings,
network imbalances, ground offsets and signal integrity, therefore a practical maximum number of nodes is
typically much lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by
careful system design and data-rate tradeoffs. For example, CANopen network design guidelines allow the
network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes, and a
significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. Using this flexibility requires the
responsibility of good network design and balancing these tradeoffs.
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ISO1042
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Typical Application (接下页)
9.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a
node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed
from the bus.
Node 1
Node 2
Node 3
Node n
(with termination)
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
图 30. Typical CAN Bus
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can be used.
(See 图 31). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM / 2
CAN
Transceiver
CAN
Transceiver
RTERM
CSPLIT
RTERM / 2
CANL
CANL
图 31. CAN Bus Termination Concepts
26
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
Typical Application (接下页)
9.2.3 Application Curve
图 32. Typical TXD, RXD, CANH and CANL Waveforms at 1 Mbps
9.3 DeviceNet Application
VCC1
VCC1
ISO1211D
SENSE
2.25 kꢀ
VCC1
560 ꢀ
VDD
24 V
Sense
OUT
GND1
IN
FGND
VCC1
ISO
Ground
TPS7B82-Q1
LDO
ISO1042
VCC2 = 5 V
24 V
8
1
2
VCC2
VCC1
VOUT
VIN
MCU
TXD
GND
CANH
CANL
7
CANH
CANL
TXD
RXD
3
6
5
RXD
DGND
24RET
4
GND2
GND1
Digital
Ground
ISO Ground
VCC2 = 5V
BSS123
VCC1
VOUT VIN
D2
GND
EN
LDO
GND
VCC
24 V
SN6505
D1
CLK
BSS123
1 : 4
图 33. ISO1042, ISO1211 and SN6505 Used in a DeviceNet Application
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ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
DeviceNet Application (接下页)
图 33 shows an application circuit for using ISO1042, ISO1211 and SN6505 in a DeviceNet application. ISO1042
is used to isolate the CAN interface. The ISO1211 24-V digital input receiver is used to detect the absence or
presence of the 24-V field supply. The SN6505 push-pull transformer driver, is used to create an auxiliary
isolated power supply for the micro-controller side using the 24-V field supply.
10 Power Supply Recommendations
To make sure operation is reliable at all data rates and supply voltages, a 0.1-µF bypass capacitor is
recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to
the supply pins as possible. In addition, a bulk capacitance, typically 4.7 μF, should be placed near the VCC2
supply pin. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as TI's SN6505B. For such
applications, detailed power supply design, and transformer selection recommendations are available in the
SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet.
28
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ISO1042
www.ti.com.cn
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Suggested placement and routing of ISO1042 bypass capacitors and optional TVS diodes is shown in 图 35 and
图 36. In particular, place the VCC2 bypass capacitors on the top layer, as close to the device pins as possible,
and complete the connection to the VCC2 and GND2 pins without using vias. Note that the SOIC-16 variant needs
two VCC2 bypass capacitor, one on each VCC2 pin.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over lower-
cost alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater
strength and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this space
FR-4
free from planes,
traces, pads, and
vias
40 mils
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 34. Recommended Layer Stack
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ISO1042
ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
Layout Example (接下页)
Minimize
distance to
VCC
VCC1
0.1 µF
VCC2
GND2
NC
VCC1
GND1
TXD
NC
C
C
C
0.1 µF
C1
C2
CANH
CANL
VCC2
CAN
BUS
MCU
D1
RXD
NC
0.1 µF
GND2
GND2
NC
GND1
GND1
PLANE
GND2
PLANE
VCC2
图 35. 16-DW Layout Example
Minimize
distance to VCC
VCC2
C
C
VCC1
VCC2
CANH
CANL
GND2
VCC1
C1
C2
TXD
CAN
BUS
D1
MCU
RXD
GND1
GND1
PLANE
GND2
PLANE
图 36. 8-DWV Layout Example
30
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ZHCSI90E –DECEMBER 2017–REVISED OCTOBER 2019
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档:
•
•
•
•
•
•
•
德州仪器 (TI),《数字隔离器设计指南》
德州仪器 (TI),《ISO1042DW 隔离式 CAN 收发器评估模块》 用户指南
德州仪器 (TI),在不牺牲性能或占用空间的情况下隔离您的 CAN 系统 TI 技术手册
德州仪器 (TI),《隔离相关术语》
德州仪器 (TI),高电压增强型隔离:定义和测试方法
德州仪器 (TI),如何在隔离式 CAN 系统中隔离信号和电源 TI 技术手册
德州仪器 (TI),《如何设计具有正确总线保护的隔离式 CAN 系统》 应用报告
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1042BDW
ISO1042BDWR
ISO1042BDWV
ISO1042BDWVR
ISO1042DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
16
16
8
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ISO1042B
2000 RoHS & Green
64 RoHS & Green
1000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
64 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO1042B
ISO1042B
ISO1042B
ISO1042
ISO1042
ISO1042
ISO1042
DWV
DWV
DW
8
16
16
8
ISO1042DWR
ISO1042DWV
ISO1042DWVR
DW
DWV
DWV
8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1042BDWR
ISO1042BDWVR
ISO1042DWR
SOIC
SOIC
SOIC
SOIC
DW
DWV
DW
16
8
2000
1000
2000
1000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
10.75 10.7
12.05 6.15
10.75 10.7
12.05 6.15
2.7
3.3
2.7
3.3
12.0
16.0
12.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
16
8
ISO1042DWVR
DWV
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO1042BDWR
ISO1042BDWVR
ISO1042DWR
SOIC
SOIC
SOIC
SOIC
DW
DWV
DW
16
8
2000
1000
2000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
16
8
ISO1042DWVR
DWV
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO1042BDW
ISO1042BDWV
ISO1042DW
DW
DWV
DW
SOIC
SOIC
SOIC
SOIC
16
8
40
64
40
64
506.98
505.46
506.98
505.46
12.7
13.94
12.7
4826
4826
4826
4826
6.6
6.6
6.6
6.6
16
8
ISO1042DWV
DWV
13.94
Pack Materials-Page 3
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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