ISO1042BQDWVQ1 [TI]
具有 70V 总线故障保护功能和灵活数据速率的汽车类隔离式 CAN 收发器 | DWV | 8 | -40 to 125;
| 型号： | ISO1042BQDWVQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 70V 总线故障保护功能和灵活数据速率的汽车类隔离式 CAN 收发器 | DWV | 8 | -40 to 125 电信 光电二极管 电信集成电路 |
| 文件： | 总44页 (文件大小：2990K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO1042-Q1
ZHCSIX9B –OCTOBER 2018 –REVISED OCTOBER 2020
具有70V 总线故障保护功能和灵活数据速率的ISO1042-Q1 汽车隔离式CAN 收
发器
5Mbps 数据速率，与经典CAN 相比可实现更为快速的
载荷传输。该器件采用二氧化硅 (SiO2) 绝缘隔栅，可
1 特性
• AEC Q100 标准：符合汽车应用要求
• 1 级：–40°C 至+125°C 环境温度
• 提供功能安全
承受 5000VRMS 的电压和 1060VRMS 的工作电压。电
磁兼容性得到了显著增强，可实现系统级 ESD、EFT
和浪涌并符合辐射标准。与隔离式电源一起使用，此器
件可抵御高电压冲击，并防止总线的噪声电流进入本地
接地。ISO1042-Q1 器件提供基础型和增强型隔离（请
参阅增强型和基础型隔离选项）。ISO1042-Q1 器件支
持 –40°C 至 +125°C 的宽环境温度范围，该器件采用
SOIC-16 (DW) 封装和较小的SOIC-8 (DWV) 封装。
– 可提供用于功能安全系统设计的文档
• 符合ISO 11898-2:2016 物理层标准
• 支持经典的最高1Mbps CAN 和最高5Mbps FD
（灵活数据速率）
• 低环路延迟：152ns
• 保护特性
器件信息
– 直流总线故障保护电压：±70V
– 总线引脚的HBM ESD 容差：±16kV
– 驱动器显性超时(TXD DTO)
– VCC1 和VCC2 欠压保护
器件型号(1)
ISO1042-Q1
封装尺寸（标称值）
5.85mm × 7.50mm
10.30mm × 7.50mm
封装
SOIC (8)
SOIC (16)
• 共模电压范围：±30V
• 未上电时的理想无源、高阻抗总线终端
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 高CMTI：100kV/µs
• VCC1 电压范围：1.71V 至5.5V
增强型和基础型隔离选项
ISO1042x-Q1
ISO1042Bx-Q1
特性
– 支持连接到CAN 控制器的1.8V、2.5V、3.3V
和5.0V 逻辑接口
• VCC2 电压范围：4.5V 至5.5V
• 优异的电磁兼容性(EMC)
保护级别
增强型
基本型
6000VPK
5000VRMS
10000VPK
5000VRMS
浪涌测试电压
隔离额定值
1060VRMS
1500VPK
/
1060VRMS
1500VPK
/
工作电压
– 系统级ESD、EFT 和浪涌抗扰性
– 低辐射
• 16-SOIC 和8-SOIC 封装选项
• 提供工业版本：ISO1042
• 安全相关认证：
VCC2
8
VCC1
1
VCC1
VCC2
VDD
TXD
7
2
3
CANH
TXD
RXD
ISO1042-Q1
CAN Bus
6
MCU
RXD
DGND
CANL
– 符合DIN VDE V 0884-11:2017-01 标准的
4
5
7071VPK
VIOTM 和1500VPK VIORM（增强型和基
GND2
GND1
本型选项）
Galvanic
Isolation Barrier
Digital
Ground
ISO
Ground
– UL 1577 标准下，长达1 分钟的5000VRMS 隔
离
应用示意图
– CQC、TUV 和CSA 认证
2 应用
• 起动机/发电机
• 电池管理系统(BMS)
• 直流/直流转换器
• 车载充电器(OBC) 和无线充电器
• 逆变器和电机控制
3 说明
ISO1042-Q1 器件是一款符合 ISO11898-2 (2016) 标准
规格的电隔离控制器局域网 (CAN) 收发器。ISO1042-
Q1 器件提供 ±70V 直流母线故障保护功能和 ±30V 共
模电压范围。该器件在 CAN FD 模式下最高支持
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFA5
ISO1042-Q1
ZHCSIX9B –OCTOBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
Table of Contents
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................24
9 Application and Implementation..................................25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 25
10 Power Supply Recommendations..............................28
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................31
12.1 Documentation Support.......................................... 31
12.2 Receiving Notification of Documentation Updates..31
12.3 支持资源..................................................................31
12.4 Trademarks.............................................................31
12.5 静电放电警告.......................................................... 31
12.6 术语表..................................................................... 31
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Transient Immunity......................................................5
6.4 Recommended Operating Conditions.........................5
6.5 Thermal Information....................................................6
6.6 Power Ratings.............................................................6
6.7 Insulation Specifications............................................. 7
6.8 Safety-Related Certifications...................................... 8
6.9 Safety Limiting Values.................................................8
6.10 Electrical Characteristics - DC Specification...........10
6.11 Switching Characteristics........................................12
6.12 Insulation Characteristics Curves........................... 13
6.13 Typical Characteristics............................................14
7 Parameter Measurement Information..........................16
7.1 Test Circuits.............................................................. 16
Information.................................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2020) to Revision B (October 2020)
Page
• 添加了“功能安全”要点....................................................................................................................................1
Changes from Revision * (October 2018) to Revision A (January 2020)
Page
• 更改了新的安全认证........................................................................................................................................... 1
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English Data Sheet: SLLSFA5
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5 Pin Configuration and Functions
VCC1
GND1
TXD
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
NC
CANH
CANL
VCC2
RXD
NC
NC
GND2
GND2
GND1
Not to scale
图5-1. DW Package 16-Pin SOIC Top View
表5-1. Pin Functions—16 Pins
PIN
NAME
I/O
DESCRIPTION
NO.
1
VCC1
GND1
TXD
NC
Digital-side supply voltage, Side 1
—
—
I
2
Digital-side ground connection, Side 1
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
Not connected
3
4
—
5
RXD
NC
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
Not connected
6
—
—
—
7
NC
Not connected
8
GND1
Digital-side ground connection, Side 1
9
GND2
Transceiver-side ground connection, Side 2
—
10
11
12
13
14
15
16
VCC2
CANL
CANH
NC
Transceiver-side supply voltage, Side 2. Must be externally connected to pin 16.
Low-level CAN bus line
—
I/O
I/O
High-level CAN bus line
Not connected
—
—
—
GND2
VCC2
Transceiver-side ground connection, Side 2
Transceiver-side supply voltage, Side 2. Must be externally connected to pin 11.
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VCC1
TXD
1
2
3
4
8
7
6
5
VCC2
CANH
CANL
GND2
RXD
GND1
Not to scale
图5-2. DWV Package 8-Pin SOIC Top View
表5-2. Pin Functions—8 Pins
PIN
NAME
I/O
DESCRIPTION
NO.
1
VCC1
TXD
Digital-side supply voltage, Side 1
—
I
2
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
Digital-side ground connection, Side 1
3
RXD
O
4
GND1
GND2
CANL
CANH
VCC2
—
—
5
Transceiver-side ground connection, Side 2
Low-level CAN bus line
6
I/O
I/O
7
High-level CAN bus line
8
Transceiver-side supply voltage, Side 2
—
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
-0.5
-0.5
MAX
UNIT
V
VCC1
VCC2
Supply voltage, side 1
Supply voltage, side 2
6
6
V
Logic input and output voltage range (TXD and
RXD)
VIO
-0.5
VCC1+0.5(3)
V
IO
Output current on RXD pin
-15
-70
-70
-40
-65
15
70
mA
V
VBUS
VBUS_DIFF
TJ
Voltage on bus pins (CANH, CANL)
Differential voltage on bus pins (CANH-CANL)
Junction temperature
70
V
150
150
℃
℃
TSTG
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
UNIT
Electrostatic discharge
All pins(1)
±6000
V
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001
CANH and CANL to GND2(1)
±16000
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
V
All pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Transient Immunity
PARAMETER
TEST CONDITIONS
VALUE
UNIT
Pulse 1; CAN bus terminals (CANH, CANL) to
GND2
-100
V
V
V
V
Pulse 2; CAN bus terminals (CANH, CANL) to
GND2
75
ISO7637-2 Transients according to GIFT - ICT
CAN EMC test specification
VPULSE
Pulse 3a; CAN bus terminals (CANH, CANL) to
GND2
-150
100
Pulse 3b; CAN bus terminals (CANH, CANL) to
GND2
6.4 Recommended Operating Conditions
MIN
MAX
1.89
5.5
UNIT
V
Supply Voltage, Side 1, 1.8-V operation
VCC1
1.71
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation
2.25
4.5
V
VCC2
TA
Supply Voltage, Side 2
5.5
V
Operating ambient temperature
-40
125
°C
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6.5 Thermal Information
ISO1042-Q1
THERMAL METRIC(1)
DW (SOIC)
16 PINS
69.9
DWV (SOIC)
8 PINS
100
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
31.8
40.8
29.0
51.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.2
16.8
ΨJT
28.6
49.8
ΨJB
RΘJC(bot)
-
-
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See 图7-3, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, A repetitive pattern on
TXD with 1 ms time period, 990 µs LOW
time, and 10 µs HIGH time.
PD
Maximum power dissipation (both sides)
385
mW
See 图7-5, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, Input a 2-V pk-pk 2.5-
MHz 50% duty cycle differential square
wave on CANH-CANL
PD1
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
25
mW
mW
See 图7-3, VCC1 = VCC2 = 5.5 V, TJ =
150°C, RL = 50 Ω, A repetitive pattern on
TXD with 1 ms time period, 990 µs LOW
time, and 10 µs HIGH time.
PD2
360
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6.7 Insulation Specifications
SPECIFICATIONS
PARAMETER
TEST CONDITIONS
UNIT
DW-16
DWV-8
IEC 60664-1
CLR
CPG
External clearance(1)
External Creepage(1)
Side 1 to side 2 distance through air
>8
>8.5
mm
mm
Side 1 to side 2 distance across package
surface
>8
>8.5
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
>17
>600
I
>17
>600
I
µm
V
According to IEC 60664-1
I-IV
I-III
I-IV
I-III
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
1060
1500
7071
1500
1060
1500
7071
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test;
VIOWM
Maximum isolation working voltage
Maximum transient isolation voltage
DC voltage
VTEST = VIOTM, t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
VPK
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 10000 VPK 6250
(qualification)
Maximum surge isolation voltage
ISO1042-Q1 (3)
6250
4615
≤5
VPK
VIOSM
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6000 VPK
(qualification)
Maximum surge isolation voltage
ISO1042B-Q1 (3)
4615
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM
,
≤5
tm = 10 s
Method a: After environmental tests
subgroup 1, Vini = VIOTM, tini = 60 s;
ISO1042-Q1: Vpd(m) = 1.6 × VIORM, tm = 10 s
ISO1042B-Q1: Vpd(m) = 1.2 × VIORM, tm = 10
s
≤5
≤5
≤5
≤5
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM
,
tini = 1 s;
ISO1042-Q1: Vpd(m) = 1.875 × VIORM, tm = 1 s
ISO1042B-Q1: Vpd(m) = 1.5 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
1
1
pF
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
> 1012
> 1011
> 109
2
> 1012
> 1011
> 109
2
VIO = 500 V, 100°C ≤TA ≤150°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
40/125/
21
40/125/
21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST
1.2 × VISO , t = 1 s (100% production)
=
VISO
Withstand isolation voltage
5000
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
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(2) ISO1042-Q1 is suitable for safe electrical insulation and ISO1042B-Q1 is suitable for basic electrical insulation only within the safety
ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
6.8 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010/A1:2019,
EN 60950-1:2006/A2:2013
and EN 62368-1:2014
Certified according to IEC Recognized under UL
60950-1, IEC 62368-1 and 1577 Component
Certified according to DIN
VDE V 0884-11:2017- 01
Certified according to
GB4943.1-2011
IEC 60601-1
Recognition Program
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2 and IEC
62368-1 2nd Ed., for
pollution degree 2,
material group I
EN 61010-1:2010 /
A1:2019
ISO1042-Q1: 600 VRMS
reinforced isolation
ISO1042B-Q1: 1000 VRMS
basic isolation
Maximum transient
isolation voltage,
7071 VPK
;
Maximum repetitive peak ISO1042-Q1: 800 VRMS
isolation voltage, reinforced isolation
1500 VPK ISO1042B-Q1: 1060 VRMS Single protection,
Maximum surge isolation basic isolation 5000 VRMS
Reinforced insulation,
Altitude ≤5000 m, Tropical
Climate,
700 VRMS maximum working
voltage
;
----------------
EN 60950-1:2006/A2:2013
and EN 62368-1:2014
ISO1042-Q1: 800 VRMS
reinforced isolation
ISO1042B-Q1: 1060 VRMS
basic isolation
voltage,
ISO1042-Q1: 6250 VPK
(Reinforced)
----------------
CSA 60601- 1:14 and IEC
60601-1 Ed. 3.1+A1,
ISO1042B-Q1: 4615 VPK ISO1042-Q1: 2 MOPP
(Basic)
(Means of Patient
Protection) 250 VRMS (354
VPK) maximum working
voltage
Certificates:
Reinforced: 40040142
Basic: 40047657
Certificate:
Master contract number:
220991
File number: E181974 CQC15001121716 (DW-16) Client ID number: 77311
CQC18001199096 (DWV-8)
6.9 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DW-16 PACKAGE
325
RθJA = 69.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图6-1
RθJA = 69.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图6-1
RθJA = 69.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图6-1
RθJA = 69.9°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see 图6-1
496
mA
650
Safety input, output, or supply
current
IS
946
Safety input, output, or total
power
PS
TS
1788 mW
150 °C
RθJA = 69.9°C/W, TJ = 150°C, TA = 25°C, see 图6-3
Maximum safety temperature
DWV-8 PACKAGE
227
RθJA = 100°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图6-2
RθJA = 100°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图6-2
RθJA = 100°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图6-2
RθJA = 100°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see 图6-2
347
mA
454
Safety input, output, or supply
current
IS
661
Safety input, output, or total
power
PS
TS
1250 mW
150 °C
RθJA = 100°C/W, TJ = 150°C, TA = 25°C, see 图6-4
Maximum safety temperature
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
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The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.10 Electrical Characteristics - DC Specification
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CHARACTERISTICS
VCC1 =1.71 V to 1.89 V, TXD = 0 V, bus
dominant
2.3
2.4
1.2
1.3
3.5
3.5
2.1
2.1
mA
mA
mA
mA
VCC1 = 2.25 V to 5.5 V, TXD = 0 V, bus
dominant
ICC1
Supply current Side 1
Supply current Side 2
VCC1 = 1.71 V to 1.89 V, TXD = VCC1, bus
recessive
VCC1 = 2.25 V to 5.5 V, TXD = VCC1, bus
recessive
43
73.4
4.1
mA
mA
V
TXD = 0 V, bus dominant, RL = 60 Ω
TXD = VCC1, bus recessive, RL = 60 Ω
ICC2
2.8
UVVCC1 Rising under voltage detection, Side 1
UVVCC1 Falling under voltage detection, Side 1
VHYS(UVC Hysterisis voltage on VCC1 undervoltage
1.7
1.0
75
V
125
mV
lock-out
C1)
UVVCC2 Rising under voltage detection, side 2
UVVCC2 Falling under voltage detection, side 2
VHYS(UVC Hysterisis voltage on VCC2 undervoltage
4.2
4.0
4.45
4.25
V
V
3.8
200
mV
lock-out
C2)
TXD TERMINAL
VIH
VIL
IIH
High level input voltage
0.7×VCC1
V
V
Low level input voltage
0.3×VCC1
1
High level input leakage current
Low level input leakage current
TXD = VCC1
TXD = 0V
uA
uA
IIL
-20
VIN = 0.4 x sin(2 x πx 1E+6 x t) + 2.5 V,
VCC1 = 5 V
CI
Input capacitance
3
pF
RXD TERMINAL
See 图7-4, IO = -4 mA for 4.5 V ≤VCC1
≤5.5 V
-0.4
-0.2
-0.1
-0.1
-0.2
-0.07
-0.04
-0.045
0.2
V
V
V
V
V
V
V
V
See 图7-4, IO = -2 mA for 3.0 V ≤VCC1
≤3.6 V
VOH
VCC1
-
High level output voltage
See 图7-4, IO = -1 mA for 2.25 V ≤VCC1
≤2.75 V
See 图7-4, IO = -1 mA for 1.71 V ≤VCC1
≤1.89 V
See 图7-4, IO = 4 mA for 4.5 V ≤VCC1
≤5.5 V
0.4
0.2
0.1
0.1
See 图7-4, IO = 2 mA for 3.0 V ≤VCC1
≤3.6 V
0.07
VOL
Low level output voltage
See 图7-4, IO = 1 mA for 2.25 V ≤VCC1
≤2.75 V
0.035
0.04
See 图7-4, IO = 1 mA for 1.71 V ≤VCC1
≤1.89 V
DRIVER ELECTRICAL CHARACTERISTICS
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Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See 图7-1 and 图7-2, TXD = 0 V, 50
Ω≤RL ≤65 Ω, CL = open
Bus output voltage(Dominant), CANH
2.75
4.5
V
VO(DOM)
See 图7-1 and 图7-2, TXD = 0 V, 50 Ω
≤RL ≤65 Ω, CL = open
Bus output voltage(Dominant), CANL
0.5
2.0
2.25
3.0
V
V
Bus output voltage(recessive), CANH and
CANL
0.5 x
VCC2
See 图7-1 and 图7-2, TXD = VCC1, RL =
open
VO(REC)
Differential output voltage, CANH-CANL See 图7-1 and 图7-2, TXD = 0 V, 45 Ω
(dominant)
1.4
3.0
V
≤RL ≤50 Ω, CL = open
Differential output voltage, CANH-CANL See 图7-1 and 图7-2, TXD = 0 V, 50 Ω
VOD(DOM)
1.5
3.0
V
(dominant)
≤RL ≤65 Ω, CL = open
Differential output voltage, CANH-CANL See 图7-1 and 图7-2, TXD = 0 V, RL =
1.5
5.0
V
(dominant)
Differential output voltage, CANH-CANL See 图7-1 and 图7-2, TXD = VCC1, RL =
2240 Ω, CL = open
-120.0
-50.0
-400.0
-100.0
12.0
50.0
400.0
mV
mV
mV
mA
mA
mA
(recessive)
60 Ω, CL = open
VOD(REC)
Differential output voltage, CANH-CANL
(recessive)
See 图7-1 and 图7-2, TXD = VCC1, RL =
open, CL = open
DC Output symmetry (VCC2 - VO(CANH)
VO(CANL)
-
See 图7-1 and 图7-2, RL = 60 Ω, CL =
open, TXD = VCC1 or 0 V
VSYM_DC
)
See 图7-9, VCANH = -5 V to 40 V, CANL
= open, TXD = 0 V
ISO(SS_DO Short circuit current steady state output
current, dominant
M)
See 图7-9, VCANL = -5 V to 40 V, CANH
100.0
5.0
= open, TXD = 0 V
ISO(SS_RE Short circuit current steady state output
See 图7-9, -27 V ≤VBUS ≤32 V,
-5.0
current, recessive
VBUS = CANH = CANL, TXD = VCC1
C)
RECEIVER ELECTRICAL CHARACTERISTICS
Differential input threshold voltage
500.0
400.0
900.0
See 图7-4 and 表7-1, |VCM| ≤20 V
VIT
See 图7-4 and 表7-1, 20 V ≤|VCM| ≤
30 V
Differential input threshold voltage
1000.0
mV
Hysteresis voltage for differential input
threshold
VHYS
120
See 图7-4 and 表7-1
See 图7-4 and 表7-1
VCM
Input common mode range
-30.0
30.0
4.8
V
CANH = CANL = 5 V, VCC2 to GND via 0
Ωand 47 kΩresistor
IOFF(LKG) Power-off bus input leakage current
uA
Input capacitance to ground (CANH or
CANL)
CI
TXD = VCC1
TXD = VCC1
24.0
12.0
30
15
pF
pF
Differential input capacitance (CANH-
CANL)
CID
RID
RIN
Differential input resistance
30.0
15.0
80.0
40.0
TXD = VCC1 ; -30 V ≤VCM ≤+30 V
TXD = VCC1 ; -30 V ≤VCM ≤+30 V
kΩ
kΩ
Input resistance (CANH or CANL)
Input resistance matching: (1 -
RIN(CANH)/RIN(CANL)) x 100%
RIN(M)
VCANH = VCANL = 5 V
-2.0
2.0
%
THERMAL SHUTDOWN
TTSD
Thermal shutdown temperature
170
5
℃
℃
TTSD_HYS
Thermal shutdown hysteresis
T
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6.11 Switching Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE SWITCHING CHARACTERISTICS
See 图7-6, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤
70
125
198.0
192.0
215.0
ns
V
CC1 ≤1.89 V
tPROP(LOO Total loop delay, driver input TXD to
receiver RXD, recessive to dominant
P1)
See 图7-6, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤
70
70
70
122
155
152
ns
ns
ns
V
CC1 ≤5.5 V
See 图7-6, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤VCC1
≤
1.89 V
tPROP(LOO Total loop delay, driver input TXD to
receiver RXD, dominant to recessive
P2)
See 图7-6, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤
215.0
300.0
V
CC1 ≤5.5 V
Time for device to return to normal
Re-enable time after Undervoltage event operation from VCC1 or VCC2 under
voltage event
tUV_RE_EN
µs
ABLE
CMTI
Common mode transient immunity
85
100
kV/µs
VCM = 1200 VPK, See 图7-10
DRIVER SWITCHING CHARACTERISTICS
Propagation delay time, HIGH TXD to
driver recessive
tpHR
76
61
120
120
Propagation delay time, LOW TXD to
driver dominant
tpLD
See 图7-3, RL = 60 Ωand CL = 100
pF; input rise/fall time (10% to 90%) on
TXD =1 ns
ns
tsk(p)
tR
Pulse skew (|tpHR - tpLD|)
14
45
45
Differential output signal rise time
Differential output signal fall time
tF
See 图7-3 and 图9-4 , RTERM = 60 Ω,
CSPLIT = 4.7 nF, CL = open, RL = open,
TXD = 250 kHz, 1 MHz
Output symmetry (dominant or recessive)
(VO(CANH) + VO(CANL)) / VCC2
VSYM
0.9
1.2
1.1
3.8
V/V
ms
tTXD_DTO Dominant time out
See 图7-8, RL = 60 Ωand CL = open
RECEIVER SWITCHING CHARACTERISTICS
Propagation delay time, bus recessive
input to RXD high output
tpRH
75
63
130
130
ns
ns
Propogation delay time, bus dominant
input to RXD low output
tpDL
See 图7-5, CL(RXD) = 15 pF
tR
tF
Output signal rise time(RXD)
Output signal fall time(RXD)
1.4
1.8
ns
ns
FD TIMING PARAMETERS
See 图7-7, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on CAN bus output pins with
tBIT(TXD) = 500 ns
435.0
155.0
530.0
210.0
ns
ns
tBIT(BUS)
See 图7-7, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on CAN bus output pins with
tBIT(TXD) = 200 ns
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Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See 图7-7, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on RXD output pins with tBIT(TXD)
= 500 ns
400
550.0
ns
tBIT(RXD)
See 图7-7, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on RXD output pins with tBIT(TXD)
= 200 ns
120.0
-65.0
220.0
40.0
ns
ns
See 图7-7, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD)
- tBIT(BUS)
Receiver timing symmetry with tBIT(TXD)
500 ns
=
=
∆tREC
See 图7-7, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC =
tBIT(RXD) - tBIT(BUS)
Receiver timing symmetry with tBIT(TXD)
200 ns
-45.0
15.0
ns
6.12 Insulation Characteristics Curves
1000
700
VCC1 =1.89 V
VCC1 = 1.89 V
VCC1 = 2.75 V
VCC1 = 3.6 V
900
800
700
600
500
400
300
200
100
0
VCC1 = 2.75 V
VCC1 = 3.6 V
VCC1 = VCC2 = 5.5 V
600
500
400
300
200
100
0
VCC1 = VCC2 = 5.5 V
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D003
D001
图6-1. Thermal Derating Curve for Limiting Current
图6-2. Thermal Derating Curve for Limiting Current
per VDE for DW-16 Package
per VDE for DWV-8 Package
2000
1800
1600
1400
1200
1000
800
1400
1200
1000
800
600
400
200
0
600
400
200
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D004
D002
图6-3. Thermal Derating Curve for Limiting Power 图6-4. Thermal Derating Curve for Limiting Power
per VDE for DW-16 Package per VDE for DWV-8 Package
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6.13 Typical Characteristics
50
45
40
35
30
25
2.3
2.25
2.2
VCC1=1.71 V
VCC1=1.8 V
VCC1=2.5 V
VCC1=3.3 V
VCC1=5 V
VCC1=5.5 V
2.15
2.1
2.05
2
1.95
1.9
20
15
10
5
1.85
1.8
Recessive
Dominant
500 kbps
1 Mbps
2 Mbps
5 Mbps
1.75
1.7
1.65
1.6
0
1.55
4.5 4.6 4.7 4.8 4.9
5
VCC2 (V)
5.1 5.2 5.3 5.4 5.5
0
0.5
1
1.5
2
2.5
3
Data Rate (Mbps)
3.5
4
4.5
5
D001
D002
VCC1 = 5 V
CL(RXD) = 15 pF
VCC2 = 5 V
Temp = 25°C
CL(RXD) = 15 pF
RL = 60 Ω
RL = 60 Ω
Temp = 25°C
图6-5. ICC2 vs VCC2 for Recessive, Dominant and
图6-6. ICC1 vs Datarate
Different CAN Datarates
45
40
35
30
25
20
3
2.75
2.5
2.25
2
Recessive
Dominant
500 kbps
1 Mbps
2 Mbps
5 Mbps
1.75
1.5
1.25
1
Recessive
Dominant
500 kbps
1 Mbps
2 Mbps
5 Mbps
15
10
5
0
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
D003
D004
VCC1 = VCC2 = 5 V
CL(RXD) = 15 pF
VCC1 = VCC2 = 5 V
Temp = 25°C
CL(RXD) = 15 pF
RL = 60 Ω
RL = 60 Ω
图6-7. ICC2 vs Ambient Temperature for Recessive,
Dominant and Different CAN Datarates
图6-8. : ICC1 vs Ambient Temperature for
Recessive, Dominant and Different CAN Datarates.
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180
170
160
150
140
130
120
110
100
3
2.5
2
tPROP(LOOP1)
tPROP(LOOP2)
1.5
1
0.5
0
-55
-60 -40 -20
0
20
40
60
80 100 120 140
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
Temperature (èC)
D005
D001
VCC1 = VCC2 = 5 V
CL(RXD) = 15 pF
RL = 60 Ω
VCC = 5 V
CL = Open
VCC1 = 5 V
RL = 60 Ω
图6-9. Loop Delay vs Ambient Temperature
图6-10. VOD(DOM) Over Temperature
3
2.5
2
1.5
1
0.5
VCC1 = VCC2 = 5 V
CL(RXD) = 15 pF
CL = 100 pF
RL = 60 Ω
0
4.5 4.6 4.7 4.8 4.9
5
VCC (V)
5.1 5.2 5.3 5.4 5.5
图6-12. Typical TXD, RXD, CANH and CANL
D002
Waveforms at 1 Mbps
VCC1 = 5 V
CL = Open
RL = 60 Ω
Temp = 25°C
图6-11. VOD(DOM) Over VCC
TXD = VCC1
VCC1 = VCC2 = 5 V
RL = 60 Ω
TXD = VCC1
VCC1 = VCC2 = 5 V
RL = 60 Ω
图6-13. Glitch Free Power Up on VCC1 –CAN Bus
图6-14. Glitch Free Power Up on VCC2 –CAN Bus
Remains Recessive
Remains Recessive
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7 Parameter Measurement Information
7.1 Test Circuits
IO(CANH)
CANH
II
TXD
0 or
Vcc1
VOD
RL
VO(CANH)
V
O(CANL)
+
2
CANL
IO(CANL)
GND1
GND2
VI
VOC
VO(CANH)
VO(CANL )
GND1
GND2
图7-1. Driver Voltage, Current and Test Definitions
Dominant
V
O
(CANH)
» 3.5 V
Recessive
2.5 V
»
V
1.5 V
O (CANL)
»
图7-2. Bus Logic State Voltage Definitions
Vcc
0 V
CANH
CANL
V
Vcc/2
Vcc/2
I
TXD
RL
VO
CL
t
t
PLH
PHL
V
O(D)
90%
10%
0.9V
VI
V
O
0.5V
(SEE NOTE A)
V
t
t
f
O(R)
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤125 kHz, 50% duty cycle,
tr ≤6 ns, tf ≤6 ns, ZO = 50 Ω.
图7-3. Driver Test Circuit and Voltage Waveforms
CANH
IO
VI(CANH) VI(CANL)
RXD
+
VIC
VID
CANL
=
2
VI(CANH)
VO
VI(CANL)
GND2
GND1
图7-4. Receiver Voltage and Current Definitions
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CANH
CANL
I
O
3.5 V
RXD
V
2.4 V
I
2 V
1.5 V
t
t
pHL
pLH
V
V
OH
O
V
CL(RXD)
90 %
10 %
I
0.7 Vcc 1
(SEE NOTE A)
0.3 Vcc 1
1 .5 V
V
O
V
t
t
f
OL
r
GND 1
GND 2
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤125 kHz, 50% duty cycle,
tr ≤6 ns, tf ≤6 ns, ZO = 50 Ω.
图7-5. Receiver Test Circuit and Voltage Waveforms
表7-1. Receiver Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
-29.5 V
30.5 V
VCANL
-30.5 V
29.5 V
|VID|
1000 mV
1000 mV
900 mV
900 mV
500 mV
500 mV
400 mV
400 mV
X
RXD
L
L
VOL
-19.55 V
20.45 V
-19.75 V
20.25 V
-29.8 V
30.2 V
-20.45 V
19.55 V
-20.25 V
19.75 V
-30.2 V
29.8 V
L
L
H
H
H
H
H
VOH
Open
Open
CANH
CANL
TXD
RXD
CL
RL
V
Vcc
I
50%
TXD Input
0 V
V
t
loop2
t
loop1
OH
50%
50%
RXD Output
+
V
OL
CL(RXD)
GND1
VO
_
图7-6. tLOOP Test Circuit and Voltage Waveforms
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VI
70%
TXD
CANH
30%
30%
0V
tBIT(TXD)
TXD
5 x tBIT
VI
CL
RL
CANL
tBIT(BUS)
900 mV
VDIFF
RXD
500 mV
CL(RXD)
GND1
VO
VOH
70%
RXD
30%
tBIT(RXD)
VOL
图7-7. CAN FD Timing Parameter Measurement
Vcc
V
I
CANH
CANH
TXD
0 V
R
V
C
OD
L
L
V
OD(D)
(see Note A )
GND 1
900 mV
V
I
V
OD
500 mV
tTXD_DTO
0 V
A. The input pulse is supplied by a generator having the following characteristics: tr ≤6 ns, tf ≤6 ns, ZO = 50 Ω.
图7-8. Dominant Time-out Test Circuit and Voltage Waveforms
200 ꢀs
IOS
IOS
CANH
TXD
VBUS
IOS
+
VBUS
CANL
VBUS
0V
0V
œ
GND2
or
VBUS
VBUS
图7-9. Driver Short-Circuit Current Test Circuit and Waveforms
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C = 0.1 F
m
1%
V
V
CC 1
CC2
V
CC 1
±
CANH
C = 0.1 F ±1%
m
+
GND1
TXD
GND
2
V
V
OL
60 W
OH
or
S1
CANL
0 V
RXD
V
V
OL
OH
or
1 k W
GND 1
GND 2
C
L
= 15 pF
(includes probe and
jig capacitance )
V
CM
图7-10. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO1042-Q1 device is a digitally isolated CAN transceiver that offers ±70-V DC bus fault protection and ±30-
V common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing much
faster transfer of payload compared to classic CAN. The ISO1042-Q1 device has an isolation withstand voltage
of 5000 VRMS and is available in basic and reinforced isolation with a surge test voltage of 6 kVPK and 10 kVPK
respectively. The device can operate from 1.8-V, 2.5-V, 3.3-V, and 5-V supplies on side 1 and a 5-V supply on
side 2. This supply range is of particular advantage for applications operating in harsh industrial environments
because the low voltage on side 1 enables the connection to low-voltage microcontrollers for power
conservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the bus signals.
8.2 Functional Block Diagram
VCC1
VCC2
CANH
CANL
+
RXD
œ
TXD
GND1
GND2
8.3 Feature Description
8.3.1 CAN Bus States
The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic
low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a
common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic
high. The host microprocessor of the CAN node uses the TXD pin to drive the bus and receives data from the
bus on the RXD pin. See 图8-1 and 图8-2.
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4
3
2
1
CANH
Vdiff(D)
Vdiff(R)
CANL
Time (t)
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
图8-1. Bus States (Physical Bit Representation)
CANH
RXD
VCC / 2
CANL
图8-2. Simplified Recessive Common Mode Bias and Receiver
8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
The VCC1 supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V,
and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible.
备注
The TXD pin is very weakly internally pulled up to VCC1. An external pullup resistor should be used to
make sure that the TXD pin is biased to recessive (high) level to avoid issues on the bus if the
microprocessor does not control the pin and the TXD pin floats. The TXD pullup strength and CAN bit
timing require special consideration when the device is used with an open-drain TXD output on the
CAN controller of the microprocessor. An adequate external pullup resistor must be used to make sure
that the TXD output of the microprocessor maintains adequate bit timing input to the input on the
transceiver.
8.3.3 Protection Features
8.3.3.1 TXD Dominant Timeout (DTO)
The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware
or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit
timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge
occurs before the timeout period expires, which frees the bus for communication between other nodes on the
network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD
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DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased
to the recessive level during a TXD dominant timeout.
TXD fault stuck dominant
Example: PCB failure or bad software
Fault is repaired and transmission
capability is restored
TXD
(driver)
tTXD_DTO
Driver disabled freeing bus for other nodes
Bus would be stuck dominant, blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
communication after the tTXD_DTO time.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus nodes
Communication from
repaired nodes
RXD
(receiver)
Communication from
local node
Communication from
other bus nodes
Communication from
repaired nodes
图8-3. Example Timing Diagram for TXD DTO
备注
The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven
successive dominant bits (on TXD) for the worst case, where five successive dominant bits are
followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum
data rate. Calculate the minimum transmitted data rate with 方程式1.
Minimum Data Rate = 11 / tTXD_DTO
(1)
8.3.3.2 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the
CAN driver circuits, blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the
recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown
condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature
(TTSD_HYST) below the thermal shutdown temperature (TTSD) of the device.
8.3.3.3 Undervoltage Lockout and Default State
The supply pins have undervoltage detection that places the device in protected or default mode which protects
the bus during an undervoltage event on the VCC1 or VCC2 supply pins. If the bus-side power supply, VCC2, is
less than about 4 V, the power shutdown circuits in the ISO1042-Q1 device disable the transceiver to prevent
false transmissions because of an unstable supply. If the VCC1 supply is still active when this occurs, the receiver
output (RXD) goes to a default HIGH (recessive) value. 表 8-1 summarizes the undervoltage lockout and fail-
safe behavior.
表8-1. Undervoltage Lockout and Default State
VCC1
VCC2
DEVICE STATE
BUS OUTPUT
Per Device State and TXD
Recessive
RXD
> UVVCC1
<UVVCC1
> UVVCC2
> UVVCC2
Functional
Mirrors Bus
Undetermined
Protected
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表8-1. Undervoltage Lockout and Default State (continued)
VCC1
VCC2
DEVICE STATE
BUS OUTPUT
RXD
>UVVCC1
< UVVCC2
Protected
High Impedance
Recessive (Default High)
备注
After an undervoltage condition is cleared and the supplies have returned to valid levels, the device
typically resumes normal operation in 300 µs.
8.3.3.4 Floating Pins
Pullup and pulldown resistors should be used on critical pins to place the device into known states if the pins
float. The TXD pin should be pulled up through a resistor to the VCC1 pin to force a recessive input level if the
microprocessor output to the pin floats.
8.3.3.5 Unpowered Device
The device is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which
is critical if some nodes of the network are unpowered while the rest of the of network remains in operation.
8.3.3.6 CAN Bus Short Circuit Current Limiting
The device has two protection features that limit the short circuit current when a CAN bus line has a short-circuit
fault condition. The first protection feature is driver current limiting (both dominant and recessive states) and the
second feature is TXD dominant state time out to prevent permanent higher short circuit current of the dominant
state during a system fault. During CAN communication the bus switches between dominant and recessive
states, therefore the short circuit current may be viewed either as the instantaneous current during each bus
state or as an average current of the two states. For system current (power supply) and power considerations in
the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the
ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and
PHY that force either recessive or dominant at certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high
percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant
bits and their respective short circuit currents. Use 方程式2 to calculate the average short circuit current.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC
]
(2)
where
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
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备注
Consider the short circuit current and possible fault cases of the network when sizing the power
ratings of the termination resistance and other network components.
8.4 Device Functional Modes
表 8-2 and 表 8-3 list the driver and receiver functions. 表 8-4 lists the functional modes for the ISO1042-Q1
device.
表8-2. Driver Function Table
INPUT
TXD(1)
L
OUTPUTS
DRIVEN BUS STATE
CANH(1)
CANL(1)
H
Z
L
Z
Dominant
Recessive
H
(1) H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See 图8-1 and 图8-2
for bus state and common mode bias information.
表8-3. Receiver Function Table
CAN DIFFERENTIAL INPUTS
DEVICE MODE
BUS STATE
RXD PIN(1)
(3)
VID = VCANH –VCANL
Dominant
?
L
?
VID ≥VIT(MAX)
VIT(MIN) < VID < VIT(MAX)
VID ≤VIT(MIN)
Normal
Recessive
Open
H
H
Open (VID ≈0 V)
(1) H = high level, L = low level, ? = indeterminate.
表8-4. Function Table
DRIVER
OUTPUTS
RECEIVER
INPUTS(1)
DIFFERENTIAL INPUTS
OUTPUT
RXD
BUS STATE
BUS STATE
VID = CANH–CANL(3)
TXD
L(2)
H
CANH
CANL
H
Z
Z
Z
L
Z
Z
Z
DOMINANT
RECESSIVE
RECESSIVE
RECESSIVE
L
?
DOMINANT
?
VID ≥VIT(MAX)
VIT(MIN) < VID < VIT(MAX)
VID ≤VIT(MIN)
Open
X
H
H
RECESSIVE
RECESSIVE
Open (VID ≈0 V)
(1) H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
(2) Logic low pulses to prevent dominant time-out.
(3) See Receiver Electrical Characteristics section for input thresholds.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO1042-Q1 device can be used with other components from Texas Instruments such as a microcontroller,
a transformer driver, and a linear voltage regulator to form a fully isolated CAN interface.
9.2 Typical Application
4
8
1
3
5
4
GND
D2
IN
OUT
EN
SN6505-Q1
3
2
7
6
3.3 V
TPS76350-Q1
EN
VCC
D1
2
GND
NC
1
5
CLK
11,16
3.3 V
1
VCC1
VCC2
2
3
GND1
VDD
14
13
NC
TXD
RXD
TXD
ISO1042-Q1
4
5
NC
CANH
MCU
12
RXD
CANL
NC
Optional bus
protection
function
6
DGND
7
8
NC
9,10,15
GND1
GND2
Galvanic
Isolation Barrier
Digital
Ground
ISO
Ground
图9-1. Application Circuit With ISO1042-Q1 in 16-SOIC Package
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4
8
1
3
5
4
GND
D2
IN
OUT
EN
SN6505-Q1
3
2
7
6
3.3 V
TPS76350-Q1
EN
VCC
D1
2
GND
NC
1
5
CLK
8
3.3 V
1
VCC1
TXD
VCC2
VDD
7
6
2
3
CANH
TXD
MCU
RXD
CANL
ISO1042-Q1
RXD
Optional bus
protection
function
DGND
4
5
GND2
GND1
Galvanic
Isolation Barrier
Digital
Ground
ISO
Ground
图9-2. Application Circuit With ISO1042-Q1 in 8-SOIC Package
9.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1042-Q1 device only requires external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
9.2.2.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A large number of nodes requires transceivers with high input impedance such as the ISO1042-Q1
transceivers.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 Standard. These organizations and standards have made system-level trade-offs for data rate, cable
length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen,
DeviceNet, and NMEA2000.
The ISO1042-Q1 device is specified to meet the 1.5-V requirement with a 50-Ω load, incorporating the worst
case including parallel transceivers. The differential input resistance of the ISO1042-Q1 device is a minimum of
30 kΩ. If 100 ISO1042-Q1 transceivers are in parallel on a bus, this requirement is equivalent to a 300-Ω
differential load worst case. That transceiver load of 300 Ω in parallel with the 60 Ω gives an equivalent loading
of 50 Ω. Therefore, the ISO1042-Q1 device theoretically supports up to 100 transceivers on a single bus
segment. However, for CAN network design margin must be given for signal loss across the system and cabling,
parasitic loadings, network imbalances, ground offsets and signal integrity, therefore a practical maximum
number of nodes is typically much lower. Bus length may also be extended beyond the original ISO 11898
standard of 40 m by careful system design and data-rate tradeoffs. For example, CANopen network design
guidelines allow the network to be up to 1 km with changes in the termination resistance, cabling, less than 64
nodes, and a significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. Using this flexibility requires the
responsibility of good network design and balancing these tradeoffs.
9.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ωcharacteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
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to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a
node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed
from the bus.
Node 1
Node 2
Node 3
Node n
(with termination)
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
图9-3. Typical CAN Bus
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can be used.
(See 图 9-4). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM / 2
CAN
Transceiver
CAN
Transceiver
RTERM
CSPLIT
RTERM / 2
CANL
CANL
图9-4. CAN Bus Termination Concepts
9.2.3 Application Curve
图9-5. Typical TXD, RXD, CANH and CANL Waveforms at 1 Mbps
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10 Power Supply Recommendations
To make sure operation is reliable at all data rates and supply voltages, a 0.1-µF bypass capacitor is
recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to
the supply pins as possible. In addition, a bulk capacitance, typically 4.7 μF, should be placed near the VCC2
supply pin. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as TI's SN6505B. For such
applications, detailed power supply design, and transformer selection recommendations are available in the
SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 节 11.2). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Suggested placement and routing of ISO1042-Q1 bypass capacitors and optional TVS diodes is shown in 图
11-2 and 图 11-3. In particular, place the VCC2 bypass capacitors on the top layer, as close to the device pins as
possible, and complete the connection to the VCC2 and GND2 pins without using vias. Note that the SOIC-16
variant needs two VCC2 bypass capacitor, one on each VCC2 pin.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over lower-
cost alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater
strength and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this space
FR-4
free from planes,
traces, pads, and
vias
40 mils
0r ~ 4.5
Power plane
10 mils
Low-speed traces
图11-1. Recommended Layer Stack
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Minimize
distance to
VCC
VCC1
0.1 µF
VCC2
GND2
NC
VCC1
GND1
TXD
NC
C
C
C
0.1 µF
C1
C2
CANH
CANL
VCC2
CAN
BUS
MCU
D1
RXD
NC
0.1 µF
GND2
GND2
NC
GND1
GND1
GND2
PLANE
PLANE
VCC2
图11-2. 16-DW Layout Example
Minimize
distance to VCC
VCC2
C
C
VCC1
VCC2
CANH
CANL
GND2
VCC1
C1
C2
TXD
CAN
BUS
D1
MCU
RXD
GND1
GND1
PLANE
GND2
PLANE
图11-3. 8-DWV Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, ISO1042DW Isolated CAN Transceiver Evaluation Module User's Guide
• Texas Instruments, Isolate your CAN systems without compromising on performance or space TI TechNote
• Texas Instruments, Isolation Glossary
• Texas Instruments, High-voltage reinforced isolation: Definitions and test methodologies
• Texas Instruments, How to Isolate Signal and Power in Isolated CAN Systems TI TechNote
• Texas Instruments, How to Design Isolated CAN Systems With Correct Bus Protection Application Report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1042BQDWQ1
ISO1042BQDWRQ1
ISO1042BQDWVQ1
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
16
16
8
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
ISO1042BQ1
2000 RoHS & Green
64 RoHS & Green
1000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
64 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
ISO1042BQ1
DWV
ISO1042B
Q1
ISO1042BQDWVRQ1
ACTIVE
SOIC
DWV
8
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042B
Q1
ISO1042QDWQ1
ISO1042QDWRQ1
ISO1042QDWVQ1
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
16
16
8
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
ISO1042Q1
ISO1042Q1
DWV
ISO1042
Q1
ISO1042QDWVRQ1
ACTIVE
SOIC
DWV
8
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO1042
Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1042BQDWRQ1
ISO1042BQDWVRQ1
ISO1042QDWRQ1
ISO1042QDWVRQ1
SOIC
SOIC
SOIC
SOIC
DW
DWV
DW
16
8
2000
1000
2000
1000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
10.75 10.7
12.05 6.15
10.75 10.7
12.05 6.15
2.7
3.3
2.7
3.3
12.0
16.0
12.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
16
8
DWV
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO1042BQDWRQ1
ISO1042BQDWVRQ1
ISO1042QDWRQ1
ISO1042QDWVRQ1
SOIC
SOIC
SOIC
SOIC
DW
DWV
DW
16
8
2000
1000
2000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
16
8
DWV
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO1042BQDWQ1
ISO1042BQDWVQ1
ISO1042QDWQ1
ISO1042QDWVQ1
DW
DWV
DW
SOIC
SOIC
SOIC
SOIC
16
8
40
64
40
64
506.98
505.46
506.98
505.46
12.7
13.94
12.7
4826
4826
4826
4826
6.6
6.6
6.6
6.6
16
8
DWV
13.94
Pack Materials-Page 3
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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