ISO124U [TI]
±10V 输入、精密电压检测低成本隔离式放大器
| DVA | 8 | -25 to 85;
| 型号： | ISO124U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ±10V 输入、精密电压检测低成本隔离式放大器 | DVA | 8 | -25 to 85 放大器 分离技术 隔离技术 光电二极管 |
| 文件： | 总29页 (文件大小：1494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
ISO124 ±10V 输入精密隔离放大器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
100% 经过高电压击穿测试
ISO124 是一款高精度隔离放大器，该放大器采用了全
新的占空比调制-解调技术。信号以数字的形式通过
2pF 差动电容隔离层进行传输。通过数字调制，其隔
离层特点不但不会影响信号完整性，而且为隔离层提供
出色的可靠性和优秀的高频瞬变抗扰性。两种隔离层电
容器都嵌入到封装的塑料主体内。
额定 1500Vrms
高 IMR：频率 60Hz 时为 140dB
非线性：0.010%（最大值）
双极运算：VO = ±10V
封装：PDIP-16 和 SOIC-28
易用性：固定单位增益配置
电源范围：±4.5V 至 ±18V
ISO124 易于使用。无需外部组件即可运行。以下是其
重要规格：最大 0.010% 的非线性值、50kHz 信号带
宽和 200µV/°C VOS 漂移。ISO124 器件提供 ±4.5V 至
±18V 的电源范围，±5mA（采用 VS1 时）和 ±5.5mA
（采用 VS2 时）静态电流，广泛适用于各种 应用。
2 应用
•
工业过程控制：
–
变送器隔离器、热电偶隔离器、RTD、压力电
桥和流量计，4mA 至 20mA 环路隔离
ISO124 采用 16 引脚 PDIP 和 28 引线 SOIC 塑料表
面贴装封装。
•
•
•
•
•
消除接地环路
电机和 SCR 控制
电源监控
器件信息(1)
器件型号
ISO124
封装
PDIP (16)
SOIC (28)
封装尺寸（标称值）
17.90mm × 7.50mm
20.01mm × 6.61mm
基于 PC 的数据采集
测试设备
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
简化原理图
VIN
VOUT
–VS2
Gnd 2
+VS2
–VS1
Gnd 1
+VS1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS074
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8
9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Applications ................................................ 11
Power Supply Recommendations...................... 19
9.1 Signal and Supply Connections.............................. 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 器件和文档支持 ..................................................... 21
11.1 文档支持 ............................................................... 21
11.2 接收文档更新通知 ................................................. 21
11.3 社区资源................................................................ 21
11.4 商标....................................................................... 21
11.5 静电放电警告......................................................... 21
11.6 术语表 ................................................................... 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
Changes from Revision D (July 2016) to Revision E
Page
•
•
已更改 将 16 引脚 SOIC 封装更改为 16 引脚 PDIP 封装，以便与数据表最后的封装选项附录中显示的产品相匹配............. 1
Changed DVA and NVF pin configuration labels to match content shown in the package option addendum at the
end of the data sheet.............................................................................................................................................................. 3
•
•
•
Changed parameter name from "vs temperature" to "Input offset drift" in Electrical Characteristics table............................ 5
Changed parameter name from "vs power supply" to "Power-supply rejection ratio" in Electrical Characteristics table ...... 5
Changed location of supply voltage specifications from the Electrical Characteristics table to the Recommended
Operating Conditions table ..................................................................................................................................................... 5
•
•
•
•
Changed parameter name from "Quiescent current" to "High-side analog supply current", and changed symbol from
"VS1" to "IVS1" in Electrical Characteristics table ..................................................................................................................... 5
Changed parameter name from "Quiescent current" to "Low-side analog supply current", and changed symbol from
"VS2" to "IVS2" in Electrical Characteristics table ..................................................................................................................... 5
Changed location of Temperature specifications from the Electrical Characteristics table to the Recommended
Operating Conditions table ..................................................................................................................................................... 5
Deleted Thermal resistance parameters from Electrical Characteristics table; see Thermal Information table..................... 5
Changes from Revision C (September 2005) to Revision D
Page
•
已添加 增加了 ESD 额定值表、特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、布局 部分、器件
和文档支持 部分以及机械、封装和可订购信息 部分。........................................................................................................... 1
2
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
5 Pin Configuration and Functions
NVF Package
16-Pin PDIP
Top View
DVA Package
28-Pin SOIC
Top View
+VS1
–VS1
+VS1
–VS1
1
2
16 Gnd 1
15 VIN
1
2
28 Gnd 1
27 VIN
VOUT
7
8
10
9
VOUT 13
16
15
–VS2
+VS2
–VS2
+VS2
Gnd 2
Gnd 2 14
Pin Functions
PIN
I/O
DESCRIPTION
NAME
Gnd 1
Gnd 2
VIN
PDIP
16
8
SOIC
28
14
27
13
1
—
—
I
High-side ground reference
Low-side ground reference
High-side analog input
15
7
VOUT
+VS1
–VS1
+VS2
–VS2
O
Low-side analog output
1
—
—
—
—
High-side positive analog supply
High-side negative analog supply
Low-side positive analog supply
Low-side negative analog supply
2
2
9
15
16
10
Copyright © 1997–2018, Texas Instruments Incorporated
3
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
±18
UNIT
V
Supply voltage
Analog input voltage, VIN
Continuous isolation voltage
Junction temperature
Output short to common
Storage temperature, Tstg
100
V
1500
Vrms
°C
125
Continuous
125
–40
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±4.5
±4.5
NOM
±15
MAX
±18
UNIT
VS1
VS2
VIN
TA
High-side analog supply voltage (±VS1 to GND1)
Low-side analog supply voltage (±VS2 to GND2)
Analog input voltage
V
V
±15
±18
±10
V
Operating temperature
–25
85
°C
6.4 Thermal Information
ISO124
THERMAL METRIC(1)
DVA (SOIC)
28 PINS
79.8
NVF (PDIP)
UNIT
16 PINS
51.0
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
32.9
32.4
42.2
29.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
6.6
10.4
ψJB
40.9
29.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
6.5 Electrical Characteristics
at TA = +25°C , VS1 = VS2 = ±15 V, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISOLATION
Rated voltage
Continuous ac 60 Hz
1500
2400
Vac
Vac
100% test(1)
Test time = 1 s, partial discharge ≤ 5 pC
Isolation mode rejection
Barrier impedance
Leakage current at 60 Hz
60 Hz
140
1014 || 2
0.18
dB
Ω || pF
µArms
VISO = 240 Vrms
0.5
GAIN
Nominal gain
Gain error
VO = ±10 V
VO = ±10 V
1
±0.05
±10
V/V
±0.50
%FSR
ppm/°C
%FSR
Gain vs temperature
Nonlinearity(2)
±0.005 ±0.010
INPUT OFFSET VOLTAGE
Initial offset
±20
±50
mV
Input offset drift
PSR
R
±200
µV/°C
Power-supply rejection ratio
±2
4
mV/V
Noise
µV/√Hz
INPUT
Input voltage
Resistance
±10
±12.5
200
V
kΩ
OUTPUT
Output voltage
±10
±5
±12.5
±15
0.1
V
mA
Current drive
Capacitive load drive
µF
Ripple voltage(3)
20
mVp-p
FREQUENCY RESPONSE
Small-signal bandwidth
Slew rate
50
2
kHz
V/µs
µs
Settling Time 0.10%
VO = ±10 V
VO = ±10 V
50
Settling Time 0.01%
350
150
µs
Overload recovery time
POWER SUPPLIES
µs
IVS1 High-side analog supply current
IVS2 Low-side analog supply current
±5.0
±5.5
±7.0
±7.0
mA
mA
(1) Tested at 1.6x rated, fail on 5-pC partial discharge.
(2) Nonlinearity is the peak deviation of the output voltage from the best-fit straight line, and is expressed as the ratio of deviation to FSR.
(3) Ripple frequency is at carrier frequency (500 kHz).
Copyright © 1997–2018, Texas Instruments Incorporated
5
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
6.6 Typical Characteristics
at TA = +25°C, and VS = ±15 V (unless otherwise noted)
+10
0
+10
0
–10
–10
0
50
0
100
500
1000
Time (µs)
Time (µs)
f = 20 kHz
f = 2 kHz
Figure 2. Sine Response
Figure 1. Sine Response
+10
+10
0
0
–10
–10
0
500
1000
50
0
100
Time (µs)
Time (µs)
Figure 3. Step Response
Figure 4. Step Response
160
140
120
100
80
Max DC Rating
2.1k
1k
Degraded
Performance
100
Typical
Performance
60
0
40
100
1k
10k
100k
1M
10M
100M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 5. Isolation Voltage vs Frequency
Figure 6. IMR vs Frequency
6
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
Typical Characteristics (continued)
at TA = +25°C, and VS = ±15 V (unless otherwise noted)
60
100mA
10mA
1mA
54
40
+VS1, +VS2
1500Vrms
100µA
10µA
1µA
–VS1, –VS2
20
240Vrms
0
0.1µA
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 7. PSRR vs Frequency
Figure 8. Isolation Leakage Current vs Frequency
100kHz
VOUT/VIN
Frequency
0
–10
–20
–30
–40
250
200
150
100
50
Out
0
500k
1M
1.5M
Input Frequency (Hz)
NOTE: Shaded area shows aliasing frequencies that cannot
be removed by a low-pass filter at the output.
Figure 9. Signal Response to Inputs Greater than 250 kHz
Copyright © 1997–2018, Texas Instruments Incorporated
7
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The ISO124 isolation amplifier uses an input and an output section galvanically isolated by matched 1-pF
isolating capacitors built into the plastic package. The input is duty-cycle modulated and transmitted digitally
across the barrier. The output section receives the modulated signal, converts it back to an analog voltage and
removes the ripple component inherent in the demodulation. Input and output sections are fabricated, then laser
trimmed for exceptional circuitry matching common to input and output sections. The sections are then mounted
on opposite ends of the package with the isolating capacitors mounted between the two sections. The ISO124
contains 250 transistors.
7.1.1 Modulator
An input amplifier (A1, as shown in Functional Block Diagram) integrates the difference between the input current
(VIN/200 kΩ) and a switched ±100-µA current source. This current source is implemented by a switchable 200-µA
source and a fixed 100-µA current sink. To understand the basic operation of the modulator, assume that VIN = 0
V. The integrator will ramp in one direction until the comparator threshold is exceeded. The comparator and
sense amp will force the current source to switch; the resultant signal is a triangular waveform with a 50% duty
cycle. The internal oscillator forces the current source to switch at 500 kHz. The resultant capacitor drive is a
complementary duty-cycle modulation square wave
7.1.2 Demodulator
The sense amplifier detects the signal transitions across the capacitive barrier and drives a switched current
source into integrator A2. The output stage balances the duty-cycle modulated current against the feedback
current through the 200-kΩ feedback resistor, resulting in an average value at the VOUT pin equal to VIN. The
sample-and-hold amplifiers in the output feedback loop serve to remove undesired ripple voltages inherent in the
demodulation process.
8
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
7.2 Functional Block Diagram
Isolation Barrier
200µA
200µA
1pF
1pF
1pF
1pF
Sense
100µA
100µA
150pF
Sense
200kΩ
150pF
200kΩ
VIN
VOUT
A2
A1
S/H
S/H
G = 6
G = 1
Osc
Gnd 1
–VS1
Gnd 2
–VS2
+VS1
+VS2
7.3 Feature Description
7.3.1 Isolation Amplifier
The ISO124 is a precision analog isolation amplifier. The input signal is transmitted digitally across a high-voltage
differential capacitive barrier. With digital modulation, the barrier characteristics do affect signal integrity, resulting
in excellent reliability and high-frequency transient immunity.
7.4 Device Functional Modes
The ISO124 device does not have any additional functional modes.
Copyright © 1997–2018, Texas Instruments Incorporated
9
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Carrier Frequency Considerations
The ISO124 amplifier transmits the signal across the isolation barrier by a 500-kHz duty-cycle modulation
technique. For input signals having frequencies below 250 kHz, this system works like any linear amplifier. But
for frequencies above 250 kHz, the behavior is similar to that of a sampling amplifier. Figure 9 shows this
behavior graphically; at input frequencies above 250 kHz, the device generates an output signal component of
reduced magnitude at a frequency below 250 kHz. This is the aliasing effect of sampling at frequencies less than
two times the signal frequency (the Nyquist frequency). At the carrier frequency and its harmonics, both the
frequency and amplitude of the aliasing go to zero.
8.1.2 Isolation Mode Voltage Induced Errors
IMV can induce errors at the output as indicated by the plots of IMV vs Frequency. It should be noted that if the
IMV frequency exceeds 250 kHz, the output also will display spurious outputs (aliasing) in a manner similar to
that for VIN > 250 kHz and the amplifier response will be identical to that shown in Figure 9.This occurs because
IMV-induced errors behave like input-referred error signals. To predict the total error, divide the isolation voltage
by the IMR shown in Figure 11 and compute the amplifier response to this input-referred error signal from the
data shown in Figure 9. For example, if a 800-kHz 1000-Vrms IMR is present, then a total of [(–60 dB) + (–30
dB)] x (1000 V) = 32-mV error signal at 200 kHz plus a 1-V, 800-kHz error signal will be present at the output.
8.1.3 High IMV dV/dt Errors
As the IMV frequency increases and the dV/dt exceeds 1000 Vµs, the sense amp may start to false trigger, and
the output will display spurious errors. The common-mode current being sent across the barrier by the high slew
rate is the cause of the false triggering of the sense amplifier. Lowering the power-supply voltages below ±15 V
may decrease the dV/dt to 500 V/M s for typical performance.
8.1.4 High Voltage Testing
TI has adopted a partial discharge test criterion that conforms to the German VDE0884 Optocoupler Standards.
This method requires the measurement of minute current pulses (< 5 pC) while applying 2400-Vrms, 60-Hz high-
voltage stress across every ISO124 isolation barrier. No partial discharge may be initiated to pass this test. This
criterion confirms transient overvoltage (1.6 × 1500 Vrms) protection without damage to the ISO124. Lifetest
results verify the absence of failure under continuous rated voltage and maximum temperature.
This new test method represents the “state-of-the art” for nondestructive high-voltage reliability testing. It is
based on the effects of nonuniform fields that exist in heterogeneous dielectric material during barrier
degradation. In the case of void nonuniformities, electric field stress begins to ionize the void region before
bridging the entire high-voltage barrier. The transient conduction of charge during and after the ionization can be
detected externally as a burst of 0.01–0.1-µs current pulses that repeat on each ac voltage cycle. The minimum
ac barrier voltage that initiates partial discharge is defined as the “inception voltage.” Decreasing the barrier
voltage to a lower level is required before partial discharge ceases and is defined as the “extinction voltage.” The
package insulation processes have been characterized and developed to yield an inception voltage in excess of
2400 Vrms so that transient overvoltages below this level will not damage the ISO124. The extinction voltage is
above 1500 Vrms so that even overvoltage induced partial discharge will cease once the barrier voltage is
reduced to the 1500-Vrms (rated) level. Older high-voltage test methods relied on applying a large enough
overvoltage (above rating) to break down marginal parts, but not so high as to damage good ones. Our new
partial discharge testing gives us more confidence in barrier reliability than breakdown/no breakdown criteria.
10
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
8.2 Typical Applications
8.2.1 Output Filters
C2
1000pF
Isolation Barrier
R1
R2
9.76kΩ
OPA237
VOUT = VIN
4.75kΩ
VIN
ISO124
–VS2
C1
+VS2
220pF
Gnd2
Gnd1
–VS1
10µH
+VS1
10µH
VS1
10µH
10µH
VS2
1µF
1µF
1µF 1µF 1µF
1µF 1µF 1µF
For more information concerning output filters, see Simple Output Filter Elminiates ISO Amp Output Ripple and Keeps
Full Bandwidth and FilterPro™ MFB and Sallen-Key Low-Pass Filter Design Program User Guide.
Figure 10. ISO124 With Output Filter for Improved Ripple
8.2.1.1 Design Requirements
The ISO124 isolation amplifiers (ISO amps) have a small (10 to 20 mVp-p typical) residual demodulator ripple at
the output. A simple filter can be added to eliminate the output ripple without decreasing the 50kHz signal
bandwidth of the ISO amp.
8.2.1.2 Detailed Design Procedure
The ISO124 device is designed to have a 50-kHz single-pole (Butterworth) signal response. By cascading the
ISO amp with a simple 50-kHz, Q = 1, two-pole, low-pass filter, the overall signal response becomes three-pole
Butterworth. The result is a maximally flat 50-kHz magnitude response and the output ripple reduced below the
noise level. Figure 10 shows the complete circuit. The two-pole filter is a unity-gain Sallen-Key type consisting of
A1, R1, R2, C1, and C2. The values shown give Q = 1 and f–3dB bandwidth = 50 kHz. Because the op amp is
connected as a unity-gain follower, gain and gain accuracy of the ISO amp are unaffected. Using a precision op
amp such as the OPA602 also preserves the DC accuracy of the ISO amp.
Copyright © 1997–2018, Texas Instruments Incorporated
11
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
Typical Applications (continued)
8.2.1.3 Application Curves
+3
0
–3
1
–9
2
–15
–21
–27
2k
5k
10k
20k
50k
100k 200k
Frequency (Hz)
1) Standard ISO124 has 50kHz single-pole (Butterworth) re-
sponse.
2) ISO124 with cascaded 50kHz, Q = 1, two-pole, low-pass
filter has three-pole Butterworth response.
Figure 12. Standard ISO124 (Approximately 20-mVp-p
Output Ripple)
Figure 11. Gain vs. Frequency
Figure 13. Filtered ISO124 (No Visible Output Ripple)
Figure 14. Step Response of Standard ISO124
Figure 15. Step Response of ISO124 With Added Twopole
Output Filter
Figure 16. Large-signal, 10-kHz Sine-wave Response of
ISO124 With and Without Output Filter
12
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
Typical Applications (continued)
8.2.2 Battery Monitor
Figure 17 provides a means to monitor the cell voltage on a 600-V battery stack by using the battery as a power
source for the isolated voltage.
This Section Repeated 49 Times.
ISO124
+V
10kΩ
1
e1 = 12V
e1
9
V =
10kΩ
2
15
7
8
10
e2 = 12V
2
16
–V
Charge/Discharge Control
Control
Section
ISO124
+V –V
+V
7
4
e49 = 12V
e50 = 12V
1
15
INA105
9
25kΩ
25kΩ
7
10kΩ
5
6
2
8
10
2
16
10kΩ
–V
25kΩ
25kΩ
e50
3
V =
2
1
(Derives input power from the battery.)
Figure 17. Battery Monitor for a 600-V Battery Power System
Copyright © 1997–2018, Texas Instruments Incorporated
13
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
Typical Applications (continued)
8.2.3 Programmable Gain Amplifier
In applications where variable gain configurations are required, a programmable gain amplifier like the PGA102
can be used with the ISO124 device. Figure 18 uses an ISO150 device to provide gain pin selection options to
the PGA102 device.
A0
A1
ISO150
+15V– 15V
+15V –15V
1
2
1
9
6
10
2
5
15 15
7
7
8
VIN
VOUT
PGA102
ISO124
8
4
3
16
Figure 18. Programmable-Gain Isolation Channel With Gains of 1, 10, and 100
14
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
Typical Applications (continued)
8.2.4 Thermocouple Amplifier
For isolated temperature measurements, Figure 19 provides an application solution using the INA114 or INA128
devices, feeding the input stage of the ISO124 device. The table provides suggested resistor values based on
the type of thermistor used in the application.
+15V
2
10.0V
6
4
REF102
Thermocouple
R4
+15V –15V +15V –15V
R1
27kΩ
+15V
Isothermal
Block with
1N4148(1)
2
1
2
7
ISO124
10
+In
9
INA114
or
INA128
7
1
8
6
15
VOUT
RG
8
5
R2
1MΩ
–In
4
16
3
R3
R5
50Ω
100Ω
–15V
SEEBACK
ISA
COEFFICIENT
R2
R4
R6
100
Zero Adj
TYPE
MATERIAL
(µV/°C)
(R3 = 100Ω) (R5 + R6 = 100Ω)
Chromel
Constantan
Iron
E
J
58.5
50.2
39.4
38.0
3.48kΩ
4.12kΩ
5.23kΩ
5.49kΩ
56.2kΩ
64.9kΩ
80.6kΩ
84.5kΩ
Ground Loop Through Conduit
NOTE: (1) –2.1mV/°C at 2.00µA.
Constantan
Chromel
Alumel
K
T
Copper
Constantan
Figure 19. Thermocouple Amplifier With Ground Loop Elimination,
Cold Junction Compensation, and Up-scale Burn-out
Copyright © 1997–2018, Texas Instruments Incorporated
15
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
Typical Applications (continued)
8.2.5 Isolated 4-mA to 20-mA Instrument Loop
For isolated temperature measurements in a 4-mA to 20-mA loop, Figure 20 provides a solution using the
XTR101 and RCV420 devices. A high-performance PT100 resistance temperature detector (RTD) provides the
user with an isolated 0-V to 5-V representation of the isolated temperature measurement.
1
13
3
14
10
4-20mA
0.8mA
0.8mA
+VS = 15V on PWS740
RG
XTR105
0.01µF
4
ISO124
+V
16
7
2
1
3
6
15
RCV420
14 15
RTD
(1)
9
RZ
2
VOUT
(PT100)
7
5, 13
10
4
RCM
8
0V - 5V
10
11
12
1kΩ
2
16
–V
Gnd
1.6mA
–VS = –15V
on PWS740
Figure 20. Isolated 4- to 20-mA Instrument Loop (RTD Shown)
8.2.6 Single-Supply Operation of the ISO124 Isolation Amplifier
The circuit shown in Figure 21 uses a 5.1-V Zener diode to generate the negative supply for an ISO12x from a
single supply on the high-voltage side of the isolation amplifier. The input measuring range will be dependent on
the applied voltage as noted in the accompanying table.
VS1 (+15V)
7
VS
INPUT RANGE
(V)(1)
INA105
(V)
Difference Amp
2
5
10kΩ
20+
15
–2 to +10
–2 to +5
–2 to +2
+VS2 (+15V)
R1
R2
1
12
6
1
15
In
9
7
VOUT = VIN
ISO124
(1)
RC
R3
R4
Signal Source
VIN
8
3
Gnd
16
10
Com 2
RS
+
4
Reference
2
IN4689
5.1V
–VS1
–VS2 (–15V)
NOTE: Because the amplifier is unity gain, the input range is also the output range. The output can go to –2 V because the
output section of the ISO amp operates from dual supplies.
For additional information see Single-Supply Operation of Isolation Amplifiers.
Figure 21. Single-Supply Operation of the ISO124 Isolation Amplifier Schematic
16
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
Typical Applications (continued)
8.2.7 Input-Side Powered ISO Amplifier
The user side of the ISO124 device can be powered from the high voltage side using an isolated DC-DC
converter as shown in Figure 22.
1
2
5
6
7
DCP011515DB
or
DCV011515D
0.47µF
0.47µF
0.47µF
VIN
–15V, 20mA
+15V, 20mA
Input
Gnd
16 15
10
9
Auxiliary
Isolated
Power
Gnd VIN
V– V+
Output
Input
Output
ISO124
Section
Section
V+ V–
VO Gnd
1
2
7
8
Output
Gnd
+15V
–15V
VO
Figure 22. Input-Side Powered ISO Amplifier Schematic
Copyright © 1997–2018, Texas Instruments Incorporated
17
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
Typical Applications (continued)
8.2.8 Powered ISO Amplifier With Three-Port Isolation
Figure 23 illustrates an application solution that provides isolated power to both the user and high-voltage sides
of the ISO124 amplifier.
+15V Gnd
1
2
5
6
7
DCP011515DB
or
DCV011515D
DCP011515DB
or
DCV011515D
7
6
5
2
1
0.47µF
0.47µF
0.47µF
0.47µF
0.47µF
VIN
–15V, 20mA
+15V, 20mA
Input
Gnd
16 15
10
9
Auxiliary
Isolated
Power
Gnd VIN
V– V+
Output
Input
Output
ISO124
Section
Section
Auxiliary
Isolated
Power
V+ V–
VO Gnd
Output
1
2
7
8
Output
Gnd
+15V, 20mA
–15V, 20mA
VO
Figure 23. Powered ISO Amplifier With Three-Port Isolation Schematic
18
Copyright © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
9 Power Supply Recommendations
9.1 Signal and Supply Connections
Each power-supply pin should be bypassed with 1-µF tantalum capacitors located as close to the amplifier as
possible. The internal frequency of the modulator/demodulator is set at 500 kHz by an internal oscillator.
Therefore, if it is desired to minimize any feedthrough noise (beat frequencies) from a DC-DC converter, use a π
filter on the supplies (see Figure 10). The ISO124 output has a 500-kHz ripple of 20 mV, which can be removed
with a simple 2-pole low-pass filter with a 100-kHz cutoff using a low-cost op amp (see Figure 10).
The input to the modulator is a current (set by the 200-kΩ integrator input resistor) that makes it possible to have
an input voltage greater than the input supplies, as long as the output supply is at least ±15 V. It is therefore
possible, when using an unregulated DC-DC converter, to minimize PSR related output errors with ±5-V voltage
regulators on the isolated side and still get the full ±10-V input and output swing.
Isolation Barrier
VOUT
VIN
ISO124
–VS2
Gnd
Gnd
+VS2
–VS1
+VS1
VS1
VS2
1µF
1µF
1µF
1µF
Figure 24. Basic Signal and Power Connections
Copyright © 1997–2018, Texas Instruments Incorporated
19
ISO124
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
To maintain the isolation barrier of the device, the distance between the high-side ground (pin 16 or 28) and the
low-side ground (pin 8 or 14) should be kept at maximum; that is, the entire area underneath the device should
be kept free of any conducting materials.
10.2 Layout Example
1 µF
SMD
0603
+VS1
-VS1
1 µF
SMD
0603
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
1 µF
SMD
0603
Figure 25. ISO124 Layout Example
20
版权 © 1997–2018, Texas Instruments Incorporated
ISO124
www.ti.com.cn
ZHCSID3E –SEPTEMBER 1997–REVISED JUNE 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
隔离放大器的单电源操作。
简单输出滤波器消除 ISO 放大器输出波纹并保持满带宽。
FilterPro™ 用户指南。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
FilterPro, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航栏。
版权 © 1997–2018, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO124P
ISO124U
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
NVF
8
8
8
8
8
25
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
ISO124P
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DVA
20
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO
124U
ISO124U/1K
ISO124U/1KE4
ISO124UE4
DVA
1000 RoHS & Green
1000 RoHS & Green
ISO
124U
DVA
ISO
124U
DVA
20
RoHS & Green
ISO
124U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO124U/1K
SOIC
DVA
8
1000
330.0
24.4
10.9
18.3
3.2
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DVA
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
ISO124U/1K
8
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO124P
ISO124U
NVF
DVA
DVA
PDIP
SOIC
SOIC
8
8
8
25
20
20
506
507
507
13.97
12.83
12.83
11230
5080
5080
4.32
6.6
ISO124UE4
6.6
Pack Materials-Page 3
MECHANICAL DATA
MPDS105 – AUGUST 2001
DVA (R-PDSO-G8/28)
PLASTIC SMALL-OUTLINE
C
A
18,10
17,70
0,25 M B M
28
15
B
7,60
7,40
10,65
10,01
D
Index
Area
1
14
2,65
2,35
0,75
0,25
x 45°
C
Seating
Plane
0,10
0,32
0,23
0,51
0,33
1,27
0,30
0,10
G
0,25
M C A M B S
0°–8°
1,27
0,40
F
4202103/B 08/01
NOTES: A. All linear dimensions are in millimeters.
G. Lead width, as measured 0,36 mm or greater
above the seating plane, shall not exceed a
maximum value of 0,61 mm.
H. Lead-to-lead coplanarity shall be less than
0,10 mm from seating plane.
B. This drawing is subject to change without notice.
C. Body length dimension does not include mold
flash, protrusions, or gate burrs. Mold flash, protrusions,
and gate burrs shall not exceed 0,15 mm per side.
D. Body width dimension does not include inter-lead flash
or portrusions. Inter-lead flash and protrusions
shall not exceed 0,25 mm per side.
I. Falls within JEDEC MS-013-AE with the exception
of the number of leads.
E. The chamfer on the body is optional. If it is not present,
a visual index feature must be located within the
cross-hatched area.
F. Lead dimension is the length of terminal for soldering
to a substrate.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI072 – AUGUST 2001
NVF (R-PDIP-T8/16)
PLASTIC DUAL-IN-LINE
D
0.775 (21,34)
0.735 (18,67)
16
9
0.280 (7,11)
0.240 (6,10)
D
1
8
Index
Area
0.195 (4,95)
0.115 (2,92)
0.210 (5,33)
0.070 (1,78)
0.045 (1,14)
0.325 (8,26)
0.300 (7,62)
0.045 (1,14)
0.030 (0,76)
MAX
C
Seating Plane
Base Plane
E
0.300 (7,63)
0.150 (3,81)
0.115 (2,92)
0.005 (0,13)
MIN 4 PL
1/2 Lead
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
0.060 (1,52)
D
0.022 (0,56)
0.014 (0,36)
0.015 (0,38)
MIN
F
0.010 (0,25)
C
0.000 (0,00)
M
0.430 (10,92)
MAX
F
4202501/A 08/01
A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001-BB with the exception of lead
count.
D. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
E. Dimensions measured with the leads constrained to be
perpendicular to Datum C.
F. Dimensions are measured at the lead tips with the leads
unconstrained.
G. A visual index feature must be located within the
cross-hatched area.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
重要声明和免责声明
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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