ISO1500DBQ [TI]
1Mbps、半双工、3kVrms 超小型隔离式 RS-485 和 RS-422 收发器 | DBQ | 16 | -40 to 125;
| 型号： | ISO1500DBQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1Mbps、半双工、3kVrms 超小型隔离式 RS-485 和 RS-422 收发器 | DBQ | 16 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总36页 (文件大小：2470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
采用超小型封装的 ISO1500 3kVRMS 基础型隔离式 RS-485/RS-422 收发器
1 特性
3 说明
1
•
•
•
•
符合或超出 TIA/EIA-485-A 要求
ISO1500 器件是适用于 TIA/EIA RS-485 和 RS-422 应
用的电隔离差动线路 收发器。该器件采用超小型 16
引脚 SSOP 封装，具有一个 3 通道数字隔离器和一个
RS-485 收发器。该收发器的总线引脚受到 IEC ESD
接触放电和 IEC EFT 事件保护。接收器输出具有针对
总线开路、短路和空闲情况的失效防护。与其他集成的
隔离式 RS-485 解决方案或采用光耦合器和非隔离式
RS-485 收发器的分立式实施相比，ISO1500 的小解决
方案尺寸可极大地减少所需的布板空间。
半双工收发器
低 EMI 1Mbps 数据速率
总线 I/O 保护
–
±16kV HBM ESD
1.71V 至 5.5V 逻辑侧电源 (VCC1)，4.5V 至 5.5V
总线侧电源 (VCC2
•
)
•
•
•
•
•
•
•
1/8 单位负载：多达 256 个总线节点
失效防护接收器（总线开路、短路和空闲）
100kV/µs（典型值）高共模瞬态抗扰度
扩展温度范围为 -40°C 至 +125°C
适用于热插拔功能的无干扰加电和断电
超小型 SSOP (DBQ-16) 封装
该器件用于长距离通信。隔离会破坏通信节点之间的接
地回路，从而获得更大的共模电压范围。经测试，每个
器件的对称隔离层可在总线收发器和逻辑电平接口之间
按照 UL 1577 标准提供为时 1 分钟的 3000VRMS 隔
离。
安全相关认证：
–
–
–
符合 DIN VDE V 0884-11:2017-01 标准的
4242VPK VIOTM 和 566VPK VIORM
ISO1500 器件可由 1 侧的 1.71V 至 5.5V 电压供电，
从而使器件可与低压 FPGA 和 ASIC 相连接。2 侧的
电源电压范围为 4.5V 至 5.5V。该器件支持 -40°C 至
+125°C 的宽工作环境温度范围。
符合 UL 1577 标准且长达 1 分钟的 3000 VRMS
隔离
IEC 60950-1、IEC 62368-1 和 IEC 61010-1 认
证
器件信息(1)
–
–
CQC、TUV 和 CSA 认证
器件型号
ISO1500
封装
SSOP (16)
封装尺寸（标称值）
VDE、UL、CQC 和 TUV 认证完成；等待 CSA
审批
4.90mm × 3.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
•
•
电表
简化原理图
保护继电器
工厂自动化与控制
HVAC 系统和楼宇自动化
电机驱动器
Logic Supply
Bus-Side Supply
VCC1
VCC2
VDD
DE
D
ISO1500
A
B
MCU
RS485 Bus
R
RE
GND1
Isolated Ground
DGND
Logic Ground
GND2
Galvanic Isolation
Barrier
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF21
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Power Ratings........................................................... 5
6.6 Insulation Specifications............................................ 6
6.7 Safety-Related Certifications..................................... 7
6.8 Safety Limiting Values .............................................. 7
6.9 Electrical Characteristics: Driver ............................... 8
6.10 Electrical Characteristics: Receiver ........................ 8
6.11 Supply Current Characteristics: Side 1(ICC1) .......... 9
6.12 Supply Current Characteristics: Side 2(ICC2) .......... 9
6.13 Switching Characteristics: Driver .......................... 10
6.14 Switching Characteristics: Receiver...................... 10
6.15 Insulation Characteristics Curves ......................... 10
6.16 Typical Characteristics.......................................... 11
7
8
Parameter Measurement Information ................ 15
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 23
9
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 27
12.1 文档支持 ............................................................... 27
12.2 接收文档更新通知 ................................................. 27
12.3 社区资源................................................................ 27
12.4 商标....................................................................... 27
12.5 静电放电警告......................................................... 27
12.6 Glossary................................................................ 27
13 机械、封装和可订购信息....................................... 27
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (May 2019) to Revision C
Page
•
•
•
•
已更改 证书相关信息 特性 部分中的 VDE 和 CSA 安全相关认证说明 ................................................................................... 1
Added footnote to Pin function table for NC pin..................................................................................................................... 3
Changed Insulation Specifications table with test condition for VIOSM and qPD (Partial discharge) ................................... 6
Changed certificate related info in Safety-Related Certifications section............................................................................... 7
Changes from Revision A (December 2018) to Revision B
Page
•
已添加 向特性列表中添加了 HBM ESD.................................................................................................................................. 1
Changes from Original (September 2018) to Revision A
Page
•
已更改 将器件状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
DBQ Package
16-Pin SSOP
Top View
VCC1
GND1
R
1
2
3
4
5
6
7
8
16
VCC2
GND2
NC
15
14
13
12
11
10
9
RE
B
DE
A
D
NC
NC
VCC2
GND2
GND1
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
12
13
6
A
B
D
I/O
I/O
I
Transceiver noninverting input or output (I/O) on the bus side
Transceiver inverting input or output (I/O) on the bus side
Driver input
Driver enable. This pin enables the driver output when high and disables the driver output when low
or open.
DE
5
I
2
8
GND1
—
Ground connection for VCC1
Ground connection for VCC2
9
GND2
NC(1)
—
—
15
7
11
14
3
No internal connection
Receiver output
R
O
I
Receiver enable. This pin disables the receiver output when high or open and enables the receiver
output when low.
RE
VCC1
4
1
—
Logic-side power supply
10
16
Transceiver-side power supply. These pins are not connected internally and must be shorted
externally on PCB.
VCC2
—
(1) Device functionality is not affected if NC pins are connected to supply or ground on PCB
Copyright © 2018–2019, Texas Instruments Incorporated
3
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
-0.5
-0.5
-0.5
-15
MAX
UNIT
V
VCC1
VCC2
VIO
Supply voltage, side 1
6
Supply voltage, side 2
6
V
Logic voltage level (D, DE, RE, R)
Output current on R pin
VCC1+0.5(3)
V
IO
15
18
mA
V
VBUS
TJ
Voltage on bus pins (A, B, Y, Z w.r.t GND2)
Junction temperature
-18
-40
150
150
℃
℃
TSTG
Storage temperature
-65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
UNIT
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
All pins except bus pins(1)
Bus terminals to GND2(1)
±4000
V
±16000
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
V
All pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
1.89
5.5
UNIT
Supply Voltage, Side 1, 1.8-V operation
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation
Supply Voltage, Side 2
1.71
V
V
VCC1
2.25
VCC2
VI
4.5
5.5
V
Common mode voltage at any bus terminal: A or B
High-level input voltage (D, DE, RE inputs)
Low-level input voltage (D, DE, RE inputs)
Differential input voltage
-7
12
V
VIH
VIL
VID
IO
0.7*VCC1
VCC1
0.3*VCC1
12
V
0
-12
-60
-4
V
V
Output current, Driver
60
mA
mA
Ω
IOR
RL
Output current, Receiver
4
Differential load resistance
54
1/tUI
TA
Signaling rate
1
Mbps
°C
Operating ambient temperature
-40
125
6.4 Thermal Information
ISO1500
DBQ (SSOP)
16 PINS
112.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
57.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
Thermal Information (continued)
ISO1500
THERMAL METRIC(1)
DBQ (SSOP)
16 PINS
64.0
UNIT
RθJB
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
32.1
ΨJB
63.7
RθJC(bot)
--
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
278
28
UNIT
PD
Maximum power dissipation (both sides) VCC1 = VCC2 = 5.5 V, TA=125°C, TJ =
mW
mW
150°C, A-B load = 54 Ω ||50pF, Load on
R=15pF
Input a 500kHz 50% duty cycle square
wave to D pin with
PD1
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
PD2
250
mW
VDE=VCC1, VRE=GND1
Copyright © 2018–2019, Texas Instruments Incorporated
5
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6.6 Insulation Specifications
SPECIFICATIONS
DBQ-16
PARAMETER
TEST CONDITIONS
UNIT
IEC 60664-1
(1)
CLR
CPG
DTI
External clearance
External creepage
Side 1 to side 2 distance through air
>3.7
mm
mm
µm
V
(1)
Side 1 to side 2 distance across package surface >3.7
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
>17
>600
I
CTI
According to IEC 60664-1
Overvoltage category
Rated mains voltage ≤ 300 VRMS
I-III
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar)
566
400
566
4242
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test;
VIOWM
Maximum isolation working voltage
DC voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST
1.2 × VIOTM, t = 1 s (100% production)
=
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage
VPK
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 10000 VPK (qualification)
4000
VPK
(3)
ISO1500
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 ≤ 5
s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM , tm = 10 s
≤ 5
(4)
qpd
Apparent charge
pC
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM, tini
=
1 s;
≤ 5
Vpd(m) = 1.875 × VIORM , tm = 1 s
(5)
CIO
RIO
Barrier capacitance, input to output
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~1
pF
> 1012
> 1011
> 109
2
(5)
Insulation resistance, input to output
VIO = 500 V, 100°C ≤ TA ≤ 150°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
40/125/21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST = 1.2
× VISO , t = 1 s (100% production)
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO1500 is suitable for safe electrical insulation within the safety ratings. Compliance with the safety ratings shall be ensured by means
of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
6
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010/A1:2019,
EN 60950-
1:2006/A2:2013 and EN
62368-1:2014
Plan to certify according
to IEC 60950-1, IEC
62368-1
Recognized under UL
1577 Component
Recognition Program
Certified according to DIN
VDE V 0884-11:2017- 01
Certified according to
GB4943.1-2011
Maximum transient
isolation voltage,
EN 61010-
1:2010/A1:2019,
Basic insulation, Altitude ≤ 300 VRMS basic isolation
CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.,
for pollution degree 2,
material group I: 370
VRMS
4242 VPK
;
Maximum repetitive peak
isolation voltage,
Single protection,
3000 VRMS
5000 m, Tropical Climate,
400 VRMS maximum
working voltage
----------------
EN 60950-
1:2006/A2:2013 and EN
62368-1:2014, 400 VRMS
basic isolation
566 VPK
;
Maximum surge isolation
voltage,
4000 VPK
Certificate number:
40040142
Certificate number:
CQC18001199097
Certificate planned
File number: E181974
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
DBQ-16 PACKAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 67.9°C/W, VI = 5.5 V, TJ = 150°C,
201
308
403
586
TA = 25°C, see 图 1
θJA = 67.9°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C, see 图 1
θJA = 67.9°C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C, see 图 1
θJA = 67.9°C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C, see 图 1
θJA = 67.9°C/W, TJ = 150°C, TA = 25°C,
see 图 2
R
IS
Safety input, output, or supply current
mA
R
R
R
PS
TS
Safety input, output, or total power
Maximum safety temperature
1105
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
Copyright © 2018–2019, Texas Instruments Incorporated
7
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6.9 Electrical Characteristics: Driver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Open circuit voltage, unloaded bus,
4.5 V ≤ VCC2 ≤ 5.5 V
1.5
4.3
VCC2
V
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V,
4.5 V < VCC2 < 5.5 V (see 图 19)
1.5
2
2.5
2.9
2.5
V
V
V
Driver differential-output voltage
magnitude
|VOD
|
RL = 100 Ω (see 图 20), RS-422 load
RL = 54 Ω (see 图 20), RS-485 load,
4.5 V < VCC2 < 5.5 V
1.5
Change in differential output voltage
between two states
Δ|VOD
|
RL = 54 Ω or RL = 100 Ω, see 图 20
RL = 54 Ω or RL = 100 Ω, see 图 20
RL = 54 Ω or RL = 100 Ω, see 图 20
–50
–50
50
3
mV
V
VOC
Common-mode output voltage
0.5 × VCC2
change in steady-state common-mode
output voltage between two states
ΔVOC(SS)
VOC(PP)
IOS
50
mV
Peak-to-peak common-mode output
voltage
RL = 54 Ω or RL = 100 Ω, see 图 20
300
mV
mA
VD = VCC1 or VD = VGND1, VDE = VCC1
–7 V ≤ VO ≤ 12 V, see 图 28
,
Short-circuit output current
–175
175
10
Ii
Input current
VD and VDE = 0 V or VD and VDE = VCC1
–10
85
µA
CMTI
Common-mode transient immunity
VD= VCC1 or GND1, VCM = 1200V, See 图 22
100
kV/µs
6.10 Electrical Characteristics: Receiver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max are over recommended operating conditions unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, One bus
input at –7 V or 12 V, other input at 0 V
Ii1
Bus input current
–100
100
µA
–7 V ≤ Common mode voltage on bus terminals ≤
12 V
(1)
VTH+
VTH–
Vhys
Positive-going input threshold voltage
See
–100
–145
45
–50
mV
mV
mV
Negative-going input threshold
voltage
–7 V ≤ Common mode voltage on bus terminals ≤
12 V
(1)
–200
20
See
–7 V ≤ Common mode voltage on bus terminals ≤
12 V
Input hysteresis (VTH+ – VTH–
)
VCC1=5V+/-10%, IOH = –4 mA, VID = 200 mV
VCC1=3.3V+/-10%, IOH = –2 mA, VID = 200 mV
VCC1 – 0.4
VCC1 – 0.3
V
V
VOH
Output high voltage on the R pin
Output low voltage on the R pin
VCC1=2.5V+/-10%, 1.8V+/-5%, IOH = –1 mA, VID
200 mV
=
VCC1 – 0.2
V
VCC1=5V+/-10%, IOL = 4 mA, VID = –200 mV
VCC1=3.3V+/-10%, IOL = 2 mA, VID = –200 mV
0.4
0.3
V
V
VOL
VCC1=2.5V+/-10%, 1.8V+/-5%, IOL = 1 mA, VID
–200 mV
=
0.2
V
Output high-impedance current on
the R pin
IOZ
VR = 0 V or VR = VCC1, VRE = VCC1
–1
1
µA
Ii
Input current on the RE pin
VRE = 0 V or VRE = VCC1
–10
85
10
µA
CMTI
Common-mode transient immunity
VID = 1.5 V or -1.5 V, VCM= 1200 V , See 图 22
100
kV/µs
(1) Under any specific conditions, VTH+ is ensured to be at least Vhys higher than VTH–
.
8
Copyright © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
6.11 Supply Current Characteristics: Side 1(ICC1
)
Bus loaded or unloaded (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRIVER ENABLED, RECEIVER DISABLED
Logic-side
VD = VCC1, VCC1 = 5 V ± 10%
supply current
2.6
2.6
3.2
3.2
4.4
4.4
5.1
5.1
mA
mA
mA
mA
Logic-side
VD = VCC1, VCC1 = 3.3 V ± 10%
supply current
Logic-side
supply current
D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
D = 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
Logic-side
supply current
DRIVER ENABLED, RECEIVER ENABLED
Logic-side
supply current
VRE = VGND1, VD = VCC1, VCC1 = 5 V ± 10%
2.6
2.6
3.4
3.2
4.4
4.4
5.2
5.2
mA
mA
mA
mA
Logic-side
supply current
VRE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10%
Logic-side
supply current
VRE = VGND1, D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF
VRE = VGND1, D= 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF
Logic-side
supply current
DRIVER DISABLED, RECEIVER ENABLED
Logic-side
supply current
V
(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 5 V ± 10%
(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 3.3 V ± 10%
1.5
1.5
1.7
1.7
3.1
3.1
3.2
3.2
mA
mA
mA
mA
Logic-side
supply current
V
Logic-side
supply current
(A-B) =1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF
(A-B) = 1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF
Logic-side
supply current
DRIVER DISABLED, RECEIVER DISABLED
Logic-side
supply current
VDE = VGND1, VD = VCC1, VCC1 = 5 V ± 10%
VDE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10%
1.5
1.5
3.1
3.1
mA
mA
Logic-side
supply current
(1) CL(R) is the load capacitance on the R pin.
6.12 Supply Current Characteristics: Side 2(ICC2
)
VRE = VGND1 or VRE = VCC1 (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRIVER ENABLED, BUS UNLOADED
Bus-side supply
VD = VCC1, VCC2 = 5 V ± 10%
2.5
4.4
mA
current
DRIVER ENABLED, BUS LOADED
Bus-side supply
VD = VCC1, RL = 54 Ω, VCC2 = 5 V ± 10%
52
60
70
80
mA
mA
current
Bus-side supply
current
D =1Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
DRIVER DISABLED, BUS LOADED OR UNLOADED
Bus-side supply
VD = VCC1, VCC2 = 5 V ± 10%
current
2.4
3.9
mA
Copyright © 2018–2019, Texas Instruments Incorporated
9
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6.13 Switching Characteristics: Driver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs over recommended operating conditions unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1Mbps DEVICE
tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see 图 21
tPHL, tPLH Propagation delay
210
210
3
300
300
30
ns
ns
ns
ns
ns
RL = 54 Ω, CL = 50 pF, see 图 21
RL = 54 Ω, CL = 50 pF, see 图 21
See 图 23, and 图 24
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
160
200
250
400
See 图 23, and 图 24
(1) Also known as pulse skew.
6.14 Switching Characteristics: Receiver
Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max are over recommended operating conditions unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1Mbps DEVICE
tr, tf Differential output rise time and fall time CL = 15 pF, see 图 25
tPHL, tPLH Propagation delay
2.4
120
5
4
180
20
ns
ns
ns
ns
ns
CL = 15 pF, see 图 25
CL = 15 pF, see 图 25
See 图 26 and 图 27
See 图 26 and 图 27
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
11
7
30
20
(1) Also known as pulse skew.
6.15 Insulation Characteristics Curves
700
1200
1000
800
600
400
200
0
VCC = 1.89 V
VCC = 2.75 V
VCC = 3.6 V
VCC = 5.5 V
600
500
400
300
200
100
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D001
D002
图 1. Thermal Derating Curve for Limiting Current per VDE
图 2. Thermal Derating Curve for Limiting Power per VDE
10
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
6.16 Typical Characteristics
35
30
25
20
15
10
5
80
70
60
50
40
30
20
10
0
ICC1 (VCC1 = 3.3V)
ICC2 (VCC2 = 5V)
ICC1 (VCC1=3.3V)
ICC2 (VCC2=5V)
0
0
100 200 300 400 500 600 700 800 900 1000
Data Rate (kbps)
0
100 200 300 400 500 600 700 800 900 1000
Data rate (kbps)
D001
D002
TA = 25°C
DE = VCC1
RE = GND1
TA = 25°C
DE = VCC1
RE = GND1
Driver load = 54
ohm || 50 pF
Load on R = 15 pF
图 3. Supply Current Vs Data Rate- No Load
图 4. Supply Current Vs Data Rate- with 54 Ω || 50 pf Load
60
50
40
30
20
10
0
4.5
ICC1 (VCC1=3.3V)
ICC2 (VCC2=5V)
4
3.5
3
2.5
2
1.5
1
0.5
0
100 200 300 400 500 600 700 800 900 1000
Data rate (kbps)
0
10
20
30
40
50
60
Driver output current (mA)
70
80
90 100
D003
D005
TA = 25°C
DE = VCC1
RE = GND1
DE = VCC1
VCC2 = 5 V
D = GND1
VCC1 = 3.3 V
Driver load = 120
ohm || 50 pF
Load on R = 15 pF
TA = 25°C
图 6. Driver Differential Output Voltage Vs Driver Output
图 5. Supply Current Vs Data Rate - with 120 Ω || 50 pf Load
Current
版权 © 2018–2019, Texas Instruments Incorporated
11
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Typical Characteristics (接下页)
5
4.5
4
4
3.5
3
VOH
VOL
VOD (5V, 120 W)
VOD (5V, 54 W)
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0
10
20
30
Driver output current (mA)
40
50
60
70
80
90 100
-40
-20
0
20
40
Ambient temp (°C)
60
80
100 120 140
D004
D006
DE = VCC1
VCC2 = 5 V
D = GND1
VCC1 = 3.3 V
TA = 25°C
图 7. Driver Output Voltage Vs Driver Output Current
图 8. Driver Differential Output Voltage Vs Temperature
55
50
45
40
35
30
25
20
15
10
5
230
225
220
215
210
205
200
195
0
0
0.5
1
1.5
2
Supply Voltage VCC2 (V)
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
Ambient Temperature (°C )
100 120 140
D007
D008
TA = 25°C
RL = 54 ohm
DE = D = VCC1
VCC1 = 3.3 V
VCC2 = 5 V
图 9. Driver Output Current Vs Supply Voltage (VCC2
)
图 10. Driver rise/fall time vs Temperature
12
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
Typical Characteristics (接下页)
215
7
6
5
4
3
2
1
0
VOH (1.8V)
VOH (3.3V)
VOH (5V)
210
205
200
195
190
-40
-20
0
20
40
60
80
Ambient Temperature (°C )
100 120 140
-15
-10 -5
High Level Output Current (mA)
0
D009
D010
VCC1 = 3.3 V
VCC2 = 5 V
TA = 25°C
图 11. Driver Propagation Delay vs Temperature
图 12. Receiver Buffer High Level Output Voltage Vs High
Level Output Current
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140
135
130
125
120
115
110
105
Vol (1.8V)
Vol (3.3V)
Vol (5V)
0
5
10
Low Level Output Current (mA)
15
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D013
D014
TA = 25°C
VCC1 = 3.3 V
VCC2 = 5 V
图 13. Receiver Buffer Low Level Output Voltage Vs Low
图 14. Receiver Propagation Delay Vs Temperature
Level Output Current
版权 © 2018–2019, Texas Instruments Incorporated
13
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Typical Characteristics (接下页)
VCC1 = 3.3 V
DE = GND1
VCC2 = 5 V
RE = GND1
TA = 25°C,
VCC1 = 3.3 V
TA = 25°C
VCC2 = 5 V
DE = VCC1
图 16. Receiver Propagation Delay
图 15. Driver Propagation delay
图 18. VCC2 Power Up / Power down- Glitch Free Behavior
图 17. VCC1 Power Up / Power down- Glitch Free Behavior
14
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
7 Parameter Measurement Information
VCC2
375 ꢀ
DE = VCC1
A
VOD
RL
B
D = 0 or
VTEST
VCC1
375 ꢀ
+
œ
GND2
图 19. Driver Voltages
RL(1) / 2
A
0 V or
VCC1
D
A
VA
VB
VOD
RL(1) / 2
B
B
VOC
VOC
GND2
ûVOC(SS)
VOC(PP)
(1) RL = 100 Ω for RS422, RL = 54 Ω for RS-485
图 20. Driver Voltages
VCC1
DE = VCC1
VI
50%
VOD
A
B
(1)
CL
50 pF 20%
RL
54 ꢀ 1%
D
tPHL
tPLH
VOD (H)
Input
Generator
90%
90%
tf
50 ꢀ
VI
0 V
10%
0 V
10%
tr
VOD
VOD (L)
GND1
(1) CL includes fixture and instrumentation capacitance.
图 21. Driver Switching Specifications
VCC1
DE
VCC2
10 µF
VCC1
0.1 µF
10 µF
0.1 µF
GND1
A
B
+
VOH or VOL
D
54 ꢀ
œ
GND1
R
RE
+
VOH or VOL
œ
CL
15 pF(1)
1 kꢀ
GND1
GND2
+ VCM
œ
(1) Includes probe and fixture capacitance.
图 22. Common Mode Transient Immunity (CMTI)—Half Duplex
版权 © 2018–2019, Texas Instruments Incorporated
15
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Parameter Measurement Information (接下页)
A
S1
VCC1
D
VO
50 % 50 %
VI
B
DE
0 V
VOH
(1)
CL
50 pF
RL
110 ꢀ
tPZH
90%
Input
Generator
50 ꢀ
50%
VI
VO
≈ 0 V
tPHZ
GND2
GND1
(1) CL includes fixture and instrumentation capacitance
图 23. Driver Enable and Disable Times
VCC2
RL
110 ꢀ
VCC1
A
50 % 50 %
VI
D
0 V
S1
tPZL
tPLZ
(1)
CL
50 pF
B
DE
VCC2
VO
50%
10%
Input
Generator
VOL
50 ꢀ
VI
GND2
GND1
图 24. Driver Enable and Disable Times
3 V
50 %
50 %
A
VI
R
VO
0 V
VOH
B
Input
Generator
(1)
CL
15 pF
1.5 V
50 ꢀ
tPLH
tPHL
VI
RE
90%
50%
10%
50%
VO
VOL
tr
tf
(1) CL includes fixture and instrumentation capacitance.
图 25. Receiver Switching Specifications
VCC1
50%
VI
0 V
tPZH
tPHZ
VOH
90%
VO
50%
≈ 0 V
VCC1
VOL
tPZL
tPLZ
VO
50%
10%
图 26. Receiver Enable and Disable Times
16
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
Parameter Measurement Information (接下页)
VCC1
0 V
VCC1
VI
50%
A
B
1 kꢀ
0 V or 1.5 V
R
VO
CL
15 pF
S1
tPZH
1.5 V or 0 V
VOH
A at 1.5 V
B at 0 V
S1 to GND
RE
VO
50%
≈ 0 V
VCC1
VOL
Input
Generator
tPZL
VI
50 ꢀ
A at 0 V
B at 1.5 V
S1 to
VO
50%
VCC1
图 27. Receiver Enable and Disable Times
A
A
B
Steady-State
Logic Input
(1 or 0)
Steady State
Logic Input
(1 or 0)
œ7 V ≤ V ≤ 12 V
I(1)
G
G
V
B
C
C
GND
GND
(1) The driver should not sustain any damage with this configuration.
图 28. Short-Circuit Current Limiting
版权 © 2018–2019, Texas Instruments Incorporated
17
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
8 Detailed Description
8.1 Overview
The ISO1500 device is an isolated RS-485/RS-422 transceiver designed to operate in harsh industrial
environments. This device supports data transmissions up to 1 Mbps. The ISO1500 device has a 3-channel
digital isolator and an RS-485 transceiver in an ultra-small SSOP package. The silicon-dioxide based capacitive
isolation barrier supports an isolation withstand voltage of 3 kVRMS and an isolation working voltage of 566 VPK
.
Isolation breaks the ground loop between the communicating nodes and lets data transfer in the presence of
large ground potential differences. The wide logic supply of the device (VCC1) supports interfacing with 1.8-V, 2.5-
V, 3.3-V. and 5-V control logic. Functional Block Diagram shows the functional block diagram of the the half-
duplex device.
8.2 Functional Block Diagram
VCC2
VCC1
VCC2
Rx
VCC
Tx
Tx
Rx
DE
D
Rx
Tx
D
A
B
Half duplex
R
R
RE
GND2
GND1
GND2
8.3 Feature Description
表 1 shows an overview of the device features.
表 1. Device Features
PART NUMBER
ISOLATION
DUPLEX
DATA RATE
1 Mbps
PACKAGE
16-pin SSOP
ISO1500
Basic
Half
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO1500
device has dedicated circuitry to help protect the transceiver from Contact ESD per IEC61000-4-2.
8.3.2 Failsafe Receiver
The differential receiver of the ISO1500 device has failsafe protection from invalid bus states caused by:
•
•
•
Open bus conditions such as a broken cable or a disconnected connector
Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair
Idle bus conditions that occur when no driver on the bus is actively driving
The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line.
The receiver outputs a failsafe logic-high state so that the output of the receiver is not indeterminate.
18
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
The receiver thresholds are offset in the receiver failsafe protection so that the indeterminate range of the input
does not include a 0 V differential. The receiver output must generate a logic high when the differential input (VID)
is greater than 200 mV to comply with the RS-485 standard. The receiver output must also generate a output a
logic low when VID is less than –200 mV to comply with the RS-485 standard. The receiver parameters that
determine the failsafe performance are VTH+, VTH–, and VHYS. Differential signals less than –200 mV always
cause a low receiver output as shown in the Electrical Characteristics table. Differential signals greater than 200
mV always cause a high receiver output. A differential input signal that is near zero is still greater than the VTH+
threshold which makes the receiver output logic high. The receiver output goes to a low state only when the
differential input decreases by VHYS to less than VTH+
.
The internal failsafe biasing feature removes the need for the two external resistors that are typically required
with traditional isolated RS-485 transceivers as shown in 图 29.
Traditional
transceiver
ISO1500
(R1 and R2 not needed)
VCC2
VCC2
VCC1
VCC2
VCC1
VCC2
R1
A
A
RS-485
Bus
RS-485
Bus
RT
RT
B
B
R2
GND2
GND1
GND2
GND1
ISO
Ground
ISO
Ground
Galvanic
Isolation Barrier
Galvanic
Isolation Barrier
图 29. Failsafe Transceiver
8.3.3 Thermal Shutdown
The ISO1500 device has a thermal shutdown circuit to protect against damage when a fault condition occurs. A
driver output short circuit or bus contention condition can cause the driver current to increase significantly which
increases the power dissipation inside the device. An increase in the die temperature is monitored and the device
is disabled when the die temperature becomes 170℃ (typical) which lets the device decrease the temperature.
The device is enabled when the junction temperature becomes 163℃ (typical).
8.3.4 Glitch-Free Power Up and Power Down
Communication on the bus that already exist between a master node and slave node in an RS485 network must
not be disturbed when a new node is swapped in or out of the network. No glitches on the bus occur when the
device is:
•
•
•
Hot plugged into the network in an unpowered state
Hot plugged into the network in a powered state and disabled state
Powered up or powered down in a disabled state when already connected to the bus
The ISO1500 device does not cause any false data toggling on the bus when powered up or powered down in a
disabled state with supply ramp rates from 100 µs to 10 ms.
版权 © 2018–2019, Texas Instruments Incorporated
19
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
8.4 Device Functional Modes
表 2 shows the driver functional modes.
表 2. Driver Functional Table(1)
OUTPUTS
DRIVER ENABLE
DE
VCC1
VCC2
INPUT D
A
H
B
L
H
L
H
H
L
H
PU
PU
X
L
Hi-Z
Hi-Z
H
Hi-Z
Hi-Z
L
X
Open
H
Open
X
PD(2)
X
PU
PD
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
X
(1) PU = Powered Up; PD = Powered Down; H = High Level; L = Low level; X = Irrelevant, Hi-Z = High impedance state
(2) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data
input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the
differential output voltage defined by 公式 1 is positive.
VOD = VA – VB
(1)
A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential
output voltage defined by 公式 1 is negative. A logic low at the DE input causes both outputs to go to the high-
impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin has
an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when the
DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes low
when the D pin is left open while the driver enabled.
表 3 shows the receiver functional modes.
表 3. Receiver Functional Table(1)
VCC1
VCC2
DIFFERENTIAL INPUT
VID = VA – VB
RECEIVER ENABLE RE
OUTPUT R
–0.02 V ≤ VID
L
H
–0.2 V < VID < 0.02 V
L
Indeterminate
V
ID≤ –0.2 V
L
H
L
PU
PU
X
X
Hi-Z
Hi-Z
H
Open
L
Open, Short, Idle
PD(2)
PU
PD(2)
PU
PD
PD
X
X
X
X
Hi-Z
H
L
X
Hi-Z
(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
(2) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
20
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when
the differential input voltage defined by 公式 2 is greater than the positive input threshold, VTH+
.
VID = VA – VB
(2)
The receiver output, R, goes low when the differential input voltage defined by 公式 2 is less than the negative
input threshold, VTH–. If the VID voltage is between the VTH+ and VTH– thresholds, the output is indeterminate. The
receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when the RE pin is logic
high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the
transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or
the bus is not actively driven (idle bus).
8.4.1 Device I/O Schematics
D and RE Inputs
VCC1 VCC1
DE Input
VCC1
VCC1
VCC1
VCC1
VCC1
1.5 Mꢀ
985 ꢀ
985 ꢀ
Input
Input
1.5 Mꢀ
R Output
VCC1
~20 ꢀ
R
图 30. Device I/O Schematics
版权 © 2018–2019, Texas Instruments Incorporated
21
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO1500 device is designed for bidirectional data transfer on multipoint RS-485 networks. The design of
each RS-485 node in the network requires an ISO1500 device and an isolated power supply as shown in 图 32.
An RS-485 bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated
with a termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance,
Z0, of the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable
length.
In half-duplex implementation, as shown in 图 31, the driver and receiver enable pins let any node at any given
moment be configured in either transmit or receive mode which decreases cable requirements.
Integrated isolation barrier allows for communication between
nodes with large ground potential differences
R
R
A
B
A
B
RE
DE
D
RE
DE
D
ISO1500
ISO1500
RT
RT
A
B
A
B
图 31. Half-Duplex Network Circuit
22
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
9.2 Typical Application
图 32 shows the application circuit of the ISO1500 device.
4
8
1
3
5
4
GND
D2
IN
OUT
NC
EN
SN6505
3
2
7
6
3.3 V
TPS76350
EN
VCC
2
GND
1
5
CLK
D1
1
2
10, 16
VCC1
VCC2
0.1 …F
0.1 …F × 2
GND1
R
VDD
3
14
13
GPIO1
NC
B
4
5
MCU
GPIO2
RE
ISO1500
12
DE
A
6
L1 3.3V
NC 11
GPIO3
DGND
D
Optional bus
protection
N
PSU
7
8
NC
0V
PE
9,15
GND1
GND2
Galvanic
Isolation Barrier
Protective Chasis
Ground
Digital
Ground
ISO
Ground
Earth
图 32. Typical Application
9.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1500 device only requires external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface
can be used in a wide range of applications with varying requirements of distance of communication, data rate,
and number of nodes.
9.2.2.1 Data Rate and Bus Length
The RS-485 standard has typical curves similar to those shown in 图 33. These curves show the inverse
relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower,
the cable length between the nodes can be longer.
版权 © 2018–2019, Texas Instruments Incorporated
23
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Typical Application (接下页)
10000
5%, 10%, and 20% Jitter
1000
100
10
Conservative
Characteristics
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
图 33. Cable Length vs Data Rate Characteristics
Applications can increase the cable length at slower data rates compared to what is shown in 图 33 by allowing
for jitter of 5% or higher. Use 图 33 as a guideline for cable selection, data rate, cable length and subsequent
jitter budgeting.
9.2.2.2 Stub Length
In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The
stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of
bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length,
or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline.
Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in 公式 3.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver.
c is the speed of light (3 × 108 m/s).
v is the signal velocity of the cable or trace as a factor of c.
(3)
9.2.2.3 Bus Loading
The current supplied by the driver must supply into a load because the output of the driver depends on this
current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a
hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents
a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs.
The ISO1500 device has 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus.
10 Power Supply Recommendations
To make sure device operation is reliable at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the logic and transceiver supply pins (VCC1 and VCC2). The capacitors should be placed as near
to the supply pins as possible. Side 2 requires one VCC2 decoupling capacitor on each VCC2 pin. If only one
primary-side power supply is available in an application, isolated power can be generated for the secondary-side
with the help of a transformer driver such as TI's SN6505B device. For such applications, detailed power supply
design and transformer selection recommendations are available in the SN6505 Low-Noise 1-A Transformer
Drivers for Isolated Power Supplies data sheet.
24
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
图 35 shows the recommended placement and routing of the device bypass capacitors and optional TVS diodes.
Put the two VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not use vias
to complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal layer is
needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack
mechanically stable and prevents it from warping. Also the power and ground plane of each power system can
be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this space
FR-4
free from planes,
traces, pads, and
vias
40 mils
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 34. Recommended Layer Stack
版权 © 2018–2019, Texas Instruments Incorporated
25
ISO1500
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Layout Example (接下页)
Minimize
distance to
supply pins
VCC1
VCC2
Optional bus
protection
VCC1
VCC2
GND2
NC
0.1 µF
C
C
0.1 µF
GND1
R
MCU
RE
B
D1
RS-485
DE
A
D
NC
NC
VCC2
GND2
0.1 µF
C
GND1
GND1
Plane
GND2
Plane
图 35. Layout Example
26
版权 © 2018–2019, Texas Instruments Incorporated
ISO1500
www.ti.com.cn
ZHCSIV2C –SEPTEMBER 2018–REVISED SEPTEMBER 2019
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
德州仪器 (TI)，《数字隔离器设计指南》
德州仪器 (TI)，《隔离相关术语》
德州仪器 (TI)，《ISO1500 隔离式 RS-485 半双工评估模块》用户指南
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2019, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1500DBQ
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1500
1500
ISO1500DBQR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1500DBQR
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 16
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ISO1500DBQR
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DBQ SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO1500DBQ
16
75
505.46
6.76
3810
4
Pack Materials-Page 3
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明