ISO1540-Q1 [TI]
汽车类 2.5kVrms、隔离式双向时钟、双向 I2C 隔离器;
| 型号： | ISO1540-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 2.5kVrms、隔离式双向时钟、双向 I2C 隔离器 时钟 |
| 文件： | 总36页 (文件大小：1533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO1540-Q1, ISO1541-Q1
ZHCSFS4D –NOVEMBER 2016 –REVISED DECEMBER 2022
ISO154x-Q1 低功耗双向I2C 隔离器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
– 器件温度等级1：–40°C 至+125°C 的工作环
境温度范围
– 器件HBM ESD 分类等级3A
– 器件CDM ESD 分类等级C6
• 提供功能安全
ISO1540-Q1 和 ISO1541-Q1 器件均为兼容 I2C 接口
的低功耗双向隔离器。凭借德州仪器 (TI) 电容隔离技
术使用，这些器件的逻辑输入和输出缓冲器由二氧化硅
(SiO2) 绝缘栅进行隔离。与隔离式电源搭配使用时，这
些器件可阻断高电压、隔离接地并防止噪声电流进入本
地接地端，以至于干扰或损坏敏感电路。
与光电耦合器相比，这项隔离技术在功能、性能、尺
寸、功耗方面具有一定优势。ISO1540-Q1 和
ISO1541-Q1 器件支持将一个完全隔离的 I2C 接口融入
小型封装中。
– 可帮助进行功能安全系统设计的文档：
ISO1540-Q1, ISO1541-Q1
• 隔离式双向I2C 兼容型通信
• 支持高达1MHz 的工作频率
• 3V 至5.5V 电源电压范围
• 开漏输出，1 侧灌电流为3.5mA，而2 侧灌电流为
35mA
ISO1540-Q1 具有两条隔离式双向通道，分别应用于时
钟和数据线，而 ISO1541-Q1 具有一条双向数据通道
和一条单向时钟通道。ISO1541-Q1 在具有一个控制器
的应用中非常实用，ISO1540-Q1 适用于多控制器应
用。对于目标可能需要时钟延展的应用， 应使用
ISO1540-Q1 器件。
• ±50kV/µs 瞬态抗扰度（典型值）
• 安全相关认证：
– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标
准的4242VPK 隔离
– 符合UL 1577 标准且持续时长为1 分钟的
这些器件通过将 1 侧低电平输出电压偏移至高于 1 侧
高电平输入电压的方式实现隔离式双向通信，从而避免
标准数字隔离器发生内部逻辑锁存。
2500VRMS 隔离
– 根据IEC 62368-1 终端设备标准，获得CSA 认
证
– 根据GB4943.1-2011 标准，实现CQC 基本绝
缘
器件信息
封装尺寸（标称值）
器件型号
ISO1540-Q1
封装
SOIC (8)
4.90mm × 3.91mm
ISO1541-Q1
2 应用
VCC1
VCC2
• 电动和混合动力汽车
• 隔离式I2C 总线
• SMBus 和PMBus 接口
• 开漏网络
• 电机控制系统
• 电池管理
• I2C 电平转换
SDA1
or SCL1
SDA2
or SCL2
GND1
GND2
VREF
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEX0
ISO1540-Q1, ISO1541-Q1
ZHCSFS4D –NOVEMBER 2016 –REVISED DECEMBER 2022
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Table of Contents
7.1 Overview...................................................................18
7.2 Functional Block Diagrams....................................... 18
7.3 Feature Description...................................................19
7.4 Isolator Functional Principle......................................19
7.5 Device Functional Modes..........................................20
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Documentation Support.......................................... 27
11.2 Related Links.......................................................... 27
11.3 Receiving Notification of Documentation Updates..27
11.4 Community Resources............................................27
11.5 Trademarks............................................................. 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Power Ratings.............................................................6
6.6 Insulation Specifications............................................. 7
6.7 Safety-Related Certifications...................................... 8
6.8 Safety Limiting Values.................................................8
6.9 Electrical Characteristics.............................................9
6.10 Supply Current Characteristics............................... 10
6.11 Timing Requirements.............................................. 10
6.12 Switching Characteristics........................................11
6.13 Insulation Characteristics Curves........................... 12
6.14 Typical Characteristics............................................13
7 Detailed Description......................................................18
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (November 2021) to Revision D (December 2022)
Page
• 将提到I2C 的旧术语实例通篇更改为控制器和目标。......................................................................................... 1
• 通篇进行了编辑性和修饰性更改......................................................................................................................... 1
• Updated electrical and switching parameters.....................................................................................................5
• Updated 'DIN VDE V 0884-11:2017-01' to 'DIN EN IEC 60747-17 (VDE 0884-17)' and removed references to
'CSA/IEC 60950-1'..............................................................................................................................................8
Changes from Revision B (October 2020) to Revision C (November 2021)
Page
• Changed scaling on mutiple images.................................................................................................................23
Changes from Revision A ( March 2019) to Revision B (October 2020)
Page
• 为“功能安全信息”添加了节1 要点..................................................................................................................1
Changes from Revision * ( November 2016) to Revision A (March 2019)
Page
• 将VDE 标准名称从“DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12”更改为DIN VDE V
0884-11:2017-01（位于节1）............................................................................................................................1
• 将节1 要点从“CSA 元件验收通知5A、IEC 60950-1 和IEC 61010-1 终端设备标准”更改为“根据IEC
60950-1 和IEC 62368-1 终端设备标准，获得CSA 认证”............................................................................... 1
• 删除了节1 要点：通过UL 1577 认证；其他全部认证纳入规划......................................................................... 1
• Updated certifications approval status, numbers, standard names, and details according to the latest agency
certificates in 节6.7 table................................................................................................................................... 8
• Changed both bypass capacitors From: 10 µF To: 0.1 µF in . Even though larger capacitors can be used, 0.1
µF is the minimum recommended bypass capacitor size.................................................................................23
• Changed both bypass capacitors From: 10 µF To: 0.1 µF in . Even though larger capacitors can be used, 0.1
µF is the minimum recommended bypass capacitor size.................................................................................23
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5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
VCC1
SDA1
SCL1
GND1
VCC2
SDA2
SCL2
GND2
Side 2
Side 1
Not to scale
图5-1. ISO1540-Q1 D Package 8-Pin SOIC Top View
表5-1. Pin Functions—ISO1540-Q1
PIN
I/O
DESCRIPTION
NAME
GND1
GND2
SCL1
SCL2
SDA1
SDA2
VCC1
VCC2
NO.
4
Ground, side 1
—
—
5
Ground, side 2
3
I/O
I/O
I/O
I/O
Serial clock input / output, side 1
Serial clock input / output, side 2
Serial data input / output, side 1
Serial data input / output, side 2
Supply voltage, side 1
6
2
7
1
—
—
8
Supply voltage, side 2
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1
2
3
4
8
7
6
5
VCC1
SDA1
SCL1
GND1
VCC2
SDA2
SCL2
GND2
Side 2
Side 1
Not to scale
图5-2. ISO1541-Q1 D Package 8-Pin SOIC Top View
表5-2. Pin Functions—ISO1541-Q1
PIN
I/O
DESCRIPTION
NAME
GND1
GND2
SCL1
SCL2
SDA1
SDA2
VCC1
VCC2
NO.
4
Ground, side 1
—
—
I
5
Ground, side 2
3
Serial clock input, side 1
Serial clock output, side 2
Serial data input / output, side 1
Serial data input / output, side 2
Supply voltage, side 1
Supply voltage, side 2
6
O
2
I/O
I/O
7
1
—
—
8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
–0.5
0
MAX
UNIT
VCC1, VCC2
6
VCC1 + 0.5(3)
VCC2 + 0.5(3)
20
Voltage
SDA1, SCL1
SDA2, SCL2
SDA1, SCL1
SDA2, SCL2
V
IO
Output current
mA
0
100
TJ(MAX)
Tstg
Maximum junction temperature
Storage temperature
150
°C
°C
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values here within are with respect to the local ground pin (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±4000
±8000
±1500
UNIT
All pins except bus pins
Bus pins
Human-body model (HBM), per AEC
Q100-002(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
5.5
UNIT
VCC1, VCC2
Supply voltage
3
V
V
VSDA1, VSCL1
Input and output signal voltages, side 1
Input and output signal voltages, side 2
Low-level input voltage, side 1
High-level input voltage, side 1
Low-level input voltage, side 2
High-level input voltage, side 2
Output current, side 1
0
VCC1
VCC2
0.5
VSDA2, VSCL2
VIL1
VIH1
VIL2
VIH2
IOL1
0
V
0
V
0.7 × VCC1
VCC1
0.3 × VCC2
VCC2
3.5
V
0
0.7 × VCC2
0.5
V
V
mA
mA
pF
pF
MHz
°C
°C
°C
IOL2
Output current, side 2
0.5
35
C1
Capacitive load, side 1
40
C2
Capacitive load, side 2
400
fMAX
TA
Operating frequency(1)
1
Ambient temperature
125
–40
–40
139
TJ
Junction temperature
136
TSD
Thermal shutdown
197
(1) This represents the maximum frequency with the maximum bus load (C) and the maximum current sink (IO). If the system has less bus
capacitance, then higher frequencies can be achieved.
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6.4 Thermal Information
ISO154x-Q1
D (SOIC)
8 PINS
114.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
69.6
55.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
27.2
ψJT
54.7
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
105
37
UNIT
mW
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
VCC1 = VCC2 = 5.5 V, TJ = 150 °C, C1 =
20 pF, C2 = 400 pF; R1 = 1.4 kΩ, R2 = 94
Ω; Input a 1-MHz 50% duty cycle clock
signal
PD1
mW
PD2
Maximum power dissipation (side-2)
68
mW
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6.6 Insulation Specifications
PARAMETER
GENERAL
TEST CONDITIONS
VALUE
UNIT
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
>4
>4
mm
mm
Shortest terminal-to-terminal distance across the
package surface
External creepage(1)
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
0.014
>400
II
mm
V
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
I–IV
I–III
Overvoltage category
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar)
566
VPK
VPK
VTEST = VIOTM
VIOTM
Maximum transient isolation voltage
t = 60 s (qualification)
t = 1 s (100% production)
4242
Method a: After I/O safety test subgroup 2/3, Vini
=
VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 680 VPK, tm
= 10 s
<5
<5
<5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 906
VPK, tm = 10 s
qpd
Apparent charge(3)
pC
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 1062 VPK, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(4)
Isolation resistance, input to output(4)
~1
>1012
>1011
>109
pF
VIO = 0.4 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO = 2500 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
2500
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings
shall be ensured by means of suitable protective circuits.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-terminal device
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Certified according to DIN EN IEC
60747-17 (VDE 0884-17) and DIN
EN 61010-1 (VDE 0411-1)
Recognized under UL 1577
Component Recognition
Program
Certified according to CSA/IEC
62368-1
Certified according to
GB4943.1-2011
Basic Insulation
Maximum Transient Overvoltage,
2.5-kVRMS Insulation Rating;
300 VRMS Basic Insulation
working voltage per CSA
Basic Insulation, Altitude ≤5000
m, Tropical Climate, 250 VRMS
maximum working voltage
4242 VPK
;
Single protection, 2500 VRMS
Maximum Repetitive Peak Voltage, 62368-1-14 and IEC
566 VPK
62368-1:2014
Certificate number:
CQC14001109540
Certificate number: 40047657
Master contract number: 220991 File number: E181974
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
R
θJA = 114.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
198
mA
303
see 图6-1
θJA = 114.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see 图6-1
Safety input, output, or supply
current
IS
R
TS
Safety temperature
150
°C
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the 节 6.4 table is that of a device
installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
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6.9 Electrical Characteristics
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SIDE 1 (ONLY)
Voltage input threshold low, SDA1
and SCL1
VILT1
VIHT1
480
550
660
700
mV
Voltage input threshold high, SDA1
and SCL1
520
40
610
60
mV
mV
mV
VHYST1 Voltage input hysteresis
V
IHT1 –VILT1
Low-level output voltage, SDA1 and
VOL1
570
800
0.5 mA ≤(ISDA1 and ISCL1) ≤3.5 mA
0.5 mA ≤(ISDA1 and ISCL1) ≤3.5 mA
SCL1(1)
Low-level output voltage to high-
level input voltage threshold
50
mV
ΔVOIT1
difference, SDA1 and SCL1(1) (2)
SIDE 2 (ONLY)
Voltage input threshold low, SDA2
VILT2
0.3 × VCC2
0.4 × VCC2
0.5 × VCC2
V
and SCL2
Voltage input threshold high, SDA2
and SCL2
VIHT2
0.4 × VCC2
V
V
V
VHYST2 Voltage input hysteresis
Low-level output voltage, SDA2 and
0.05 × VCC2
V
IHT2 –VILT2
VOL2
0.4
10
0.5 mA ≤(ISDA2 and ISCL2) ≤35 mA
SCL2
BOTH SIDES
Input leakage currents, SDA1,
SCL1, SDA2, and SCL2
VSDA1, VSCL1 = VCC1;
VSDA2, VSCL2 = VCC2
|II|
0.01
µA
Input capacitance to local ground,
SDA1, SCL1, SDA2, and SCL2
CI
7
50
pF
kV/µs
V
VI = 0.4 × sin(2E6πt) + 2.5 V
See 图7-3
CMTI
VCCUV
Common-mode transient immunity
25
VCC undervoltage lockout
threshold(3)
1.7
2.5
2.9
(1) This parameter does not apply to the ISO1541-Q1 SCL1 line as it is unidirectional.
(2) ∆VOIT1 = VOL1 –VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage
Threshold to prevent a permanent latch condition that would otherwise exist with bidirectional communication.
(3) Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages greater than the maximum will
prevent device lockout.
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6.10 Supply Current Characteristics
over recommended operating conditions, unless otherwise noted. For more information, see 图7-1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3 V ≤VCC1, VCC2 ≤3.6 V
VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2;
R1, R2 = Open; C1, C2 = Open
2.4
2.5
2.1
2.3
1.7
1.9
7.1
4
ISO1540-Q1
VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2;
R1, R2 = Open; C1, C2 = Open
ICC1 Supply current, side 1
mA
VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2;
R1, R2 = Open; C1, C2 = Open
6.1
3.6
6.7
3.5
ISO1541-Q1
VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2;
R1, R2 = Open; C1, C2 = Open
VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2;
R1, R2 = Open; C1, C2 = Open
ISO1540-Q1 and
ISO1541-Q1
ICC2 Supply current, side 2
mA
VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2;
R1, R2 = Open; C1, C2 = Open
4.5 V ≤VCC1, VCC2 ≤5.5 V
VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2;
R1,R2 = Open; C1,C2 = Open
3.1
3.1
2.8
2.9
2.3
2.5
7.2
4.7
6.2
4.5
6.8
4
ISO1540-Q1
ISO1541-Q1
VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2;
R1, R2 = Open; C1, C2 = Open
ICC1 Supply current, side 1
mA
mA
VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2;
R1, R2 = Open; C1, C2 = Open
VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2;
R1, R2 = Open; C1, C2 = Open
VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2;
R1, R2 = Open; C1, C2 = Open
ISO1540-Q1 and
ISO1541-Q1
ICC2 Supply current, side 2
VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2;
R1, R2 = Open; C1, C2 = Open
6.11 Timing Requirements
MIN
NOM
MAX UNIT
151 µs
tUVLO
Time to recover from UVLO
30
50
2.7 V to 0.9 V; See 图7-4
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6.12 Switching Characteristics
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
3 V ≤VCC1, VCC2 ≤3.6 V
0.7 × VCC1 to 0.3 × VCC1
0.9 × VCC1 to 900 mV
0.7 × VCC2 to 0.3 × VCC2
0.9 × VCC2 to 400 mV
8
16
14
35
17
29
23
50
29
48
See 图7-1
R1 = 953 Ω,
C1 = 40 pF
Output Signal Fall Time
(SDA1, SCL1)
tf1
ns
ns
47
See 图7-1
R2 = 95.3 Ω,
C2 = 400 pF
Output Signal Fall Time
(SDA2, SCL2)
tf2
100
Low-to-High Propagation
Delay, Side 1 to Side 2
tpLH1-2
tPHL1-2
PWD1-2
0.55 V to 0.7 × VCC2
0.7 V to 0.4 V
33
90
55
47
67
20
65
181
123
68
ns
ns
ns
ns
ns
ns
High-to-Low Propagation
Delay, Side 1 to Side 2
Pulse Width Distortion
See 图7-1
|tpHL1-2 –tpLH1-2
|
R1 = 953 Ω,
R2 = 95.3 Ω,
C1, C2 = 10 pF
Low-to-High Propagation
Delay, Side 2 to Side 1
(1)
tPLH2-1
0.4 × VCC2 to 0.7 × VCC1
0.4 × VCC2 to 0.9 V
High-to-Low Propagation
Delay, Side 2 to Side 1
(1)
tPHL2-1
109
49
Pulse Width Distortion
(1)
PWD2-1
|tpHL2-1 –tpLH2-1
|
See 图7-2;
R1 = 953 Ω, C1 = 40 pF
R2 = 95.3 Ω, C2 = 400 pF
Round-trip propagation
delay on Side 1
(1)
tLOOP1
0.4 V to 0.3 × VCC1
100
165
ns
4.5 V ≤VCC1, VCC2 ≤5.5 V
Output Signal Fall Time
0.7 × VCC1 to 0.3 × VCC1
0.9 × VCC1 to 900 mV
0.7 × VCC2 to 0.3 × VCC2
0.9 × VCC2 to 400 mV
6
13
10
28
11
21
18
41
22
48
35
76
See 图7-1
R1 = 1430 Ω,
C1 = 40 pF
tf1
ns
ns
(SDA1, SCL1)
See 图7-1
R2 = 143 Ω,
C2 = 400 pF
Output Signal Fall Time
(SDA2, SCL2)
tf2
Low-to-High Propagation
Delay, Side 1 to Side 2
tpLH1-2
tPHL1-2
PWD1-2
0.55 V to 0.7 × VCC2
0.7 V to 0.4 V
31
70
38
55
47
8
62
139
80
ns
ns
ns
ns
ns
ns
High-to-Low Propagation
Delay, Side 1 to Side 2
Pulse Width Distortion
See 图7-1
|tpHL1-2 –tpLH1-2
|
R1 = 1430 Ω,
R2 = 143 Ω,
C1,2 = 10 pF
Low-to-high propagation
delay, side 2 to side 1
(1)
tPLH2-1
0.4 × VCC2 to 0.7 × VCC1
0.4 × VCC2 to 0.9 V
80
High-to-low propagation
delay, Side 2 to side 1
(1)
tPHL2-1
85
Pulse Width Distortion
(1)
PWD2-1
34
|tpHL2-1 –tpLH2-1
|
See 图7-2;
R1 = 1430 Ω, C1 = 40 pF
R2 = 143 Ω, C2 = 400 pF
Round-trip propagation
delay on side 1
(1)
tLOOP1
0.4 V to 0.3 × VCC1
110
180
ns
(1) This parameter does not apply to the ISO1541-Q1 SCL1 line as it is unidirectional.
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6.13 Insulation Characteristics Curves
350
300
250
200
150
100
50
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
0
0
50
100
Ambient Temperature (èC)
150
200
图6-1. Thermal Derating Curve for Limiting Current per VDE
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6.14 Typical Characteristics
0.800
0.780
0.760
0.740
0.720
0.700
0.680
0.660
0.640
3.0
I
= 3.5 mA
OL1
I
= 0.5 mA
2.5
2.0
1.5
OL1
1.0
0.5
0.0
-0.5
0.620
0.600
0
0.1 0.2
0.3
0.4
0.5
0.6 0.7
0.8
0.9
−40 −25 −10
5
20 35 50 65 80 95 110 125
Applied Voltage, VSDA1, VSCL1 (V)
Free−Air Temperature (°C)
TA = 25°C
图6-2. Side 1: Output Low Voltage vs Free-Air
图6-3. Side 1: Output Low Current vs SDA1 or SCL1
Temperature
Applied Voltage
20
18
16
14
12
10
8
20
R1 = 1430 W
R1 = 2.2 kW
18
16
14
12
10
8
6
6
4
4
R1= 953 W
R1= 2.2 kW
2
2
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
D001
D002
VCC1 = 3.3 V
C1 = 40 pF
VCC1 = 5 V
C1 = 40 pF
Fall time measured from 70% to 30% VCC1
Fall time measured from 70% to 30% VCC1
图6-4. Side 1: Output Fall Time vs Free-Air
图6-5. Side 1: Output Fall Time vs Free-air
Temperature
Temperature
30
25
20
15
10
30
25
20
15
10
5
5
R2 = 95.3 W
R2 = 2.2 kW
R2 = 143 W
R2 = 2.2 kW
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
D003
D004
VCC2 = 3.3 V
C2 = 400 pF
VCC2 = 5 V
C2 = 400 pF
Fall time measured from 70% to 30% VCC2
Fall time measured from 70% to 30% VCC2
图6-6. Side 2: Output Fall Time vs Free-Air
图6-7. Side 2: Output Fall Time vs Free-Air
Temperature
Temperature
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45
40
35
30
25
20
15
10
120
100
80
60
40
20
0
VCC1 and VCC2 = 3.3 V, R2 = 95.3 W
VCC1 and VCC2 = 3.3 V, R2 = 95.3 W
VCC1 and VCC2 = 5 V, R2 = 143 W
5
0
VCC1 and VCC2 = 5 V, R2 = 143 W
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
D006
D005
C2 = 10 pF
C2 = 10 pF
图6-9. tPHL1-2 Propagation Delay vs Free-Air
图6-8. tPLH1-2 Propagation Delay vs Free-Air
Temperature
Temperature
1050
90
80
70
60
50
40
30
20
VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V
1045
1040
1035
1030
1025
1020
1015
1010
1005
1000
VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V
10
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
D007
D008
C2 = 400 pF
R2 = 2.2 kΩ
C2 = 400 pF
R2 = 2.2 kΩ
图6-10. tPLH1-2 Propagation Delay vs Free-Air
图6-11. tPHL1-2 Propagation Delay vs Free-Air
Temperature
Temperature
70
60
50
40
30
20
80
70
60
50
40
30
20
10
10
VCC1 and VCC2 = 3.3 V, R1 = 953 W
VCC1 and VCC2 = 5 V, R1 = 1430 W
VCC1 and VCC2 = 3.3 V, R1 = 953 W
VCC1 and VCC2 = 5 V, R1 = 1430 W
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
D009
D010
C1 = 10 pF
C1 = 10 pF
图6-12. tPLH2-1 Propagation Delay vs Free-Air
图6-13. tPHL2-1 Propagation Delay vs Free-Air
Temperature
Temperature
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148
146
144
142
140
138
136
134
132
80
70
60
50
40
30
20
10
0
VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V
VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
−40 −25 −10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (°C)
D011
C1 = 40 pF
R1 = 2.2 kΩ
C1 = 40 pF
R1 = 2.2 kΩ
图6-14. tPLH2-1 Propagation Delay vs Free-Air
图6-15. tPHL2-1 Propagation Delay vs Free-Air
Temperature
Temperature
140
120
100
80
600
595
590
585
580
60
40
20
VCC1 and VCC2 = 3.3 V, R1 = 953 W, R2 = 95.3 W
VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V
VCC1 and VCC2 = 5 V, R1 = 1430 W, R2 = 143 W
0
575
-40 -25 -10
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
D013
D014
C1 = 40 pF
C2 = 400 pF
C1 = 40 pF
C2 = 400 pF
R1 = 2.2 kΩ
R2 = 2.2 kΩ
图6-16. tLOOP1 vs Free-Air Temperature
图6-17. tLOOP1 vs Free-Air Temperature
70
60
50
40
30
20
10
0
VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
D015
图6-18. CMTI vs Free-Air Temperature
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Parameter Measurement Information
œ
+
œ
+
VCC2
VCC1
R1
R1
R2
R2
SDA1
SCL1
SDA2
SCL2
ISO1540
ISO1541
C1
C1
C2
C2
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图7-1. Test Diagram
VCC2
VCC1
VCC1
R1
GND1
t
LOOP1
SDA1 or
SCL1
Output
0.3 VCC1
SDA1
SCL1 (ISO1540 Only)
C1
0.4 V
GND1
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图7-2. tLoop1 Setup and Timing Diagram
VCCx
VCCy
2 kꢀ
2 kꢀ
Input
+
Output
œ
GNDx
GNDy
V
CMTI
图7-3. Common-Mode Transient Immunity Test Circuit
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VCCx
VCCy
Side x, Side y VCCx,VCCy
Ry
1, 2
2, 1
3.3 V, 3.3 V 95.3 Ω
3.3 V, 3.3 V 953 Ω
VCCx
Ry
0 V
SDAx or
SCLx
+
Output
-
GNDx
GNDy
or
VCCx
VCCy
VCCy
Ry
SDAx or
SCLx
0 V
+
Output
GNDx
GNDy
VCCx or
VCCy
VCCx (UVLO+)
t
UVLO
0.9 V
Output
图7-4. tUVLO Test Circuit and Timing Diagrams
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7 Detailed Description
7.1 Overview
The I2C bus is used in a wide range of applications because it is simple to use. The bus consists of a two-wire
communication bus that supports bidirectional data transfer between a controller device and several target
devices. The controller, or processor, controls the bus, specifically the serial clock (SCL) line. Data is transferred
between the controller and target through a serial data (SDA) line. This data can be transferred in four speeds:
standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1 Mbps), and high-speed mode
(0 to 3.4 Mbps). The most common speeds are the standard and fast modes.
The I2C bus operates in bidirectional, half-duplex mode, while standard digital isolators are unidirectional
devices. To make efficient use of one technology supporting the other, external circuitry is required that
separates the bidirectional bus into two unidirectional signal paths without introducing significant propagation
delay. These devices have their logic input and output buffers separated by TI's capacitive isolation technology
using a silicon dioxide (SiO2) barrier. When used in conjunction with isolated power supplies, these devices
block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering
with or damaging sensitive circuitry.
7.2 Functional Block Diagrams
VCC1
VCC2
SDA2
SDA1
V
REF
SCL2
SCL1
GND1
GND2
V
REF
图7-1. ISO1540-Q1 Block Diagram
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VCC2
VCC1
SDA1
SDA2
V
REF
SCL1
SCL2
GND1
GND2
图7-2. ISO1541-Q1 Block Diagram
7.3 Feature Description
The device enables a complete isolated I2C interface to be implemented within a small form factor having the
features listed in 表7-1.
表7-1. Features List
PART NUMBER
CHANNEL DIRECTION
RATED ISOLATION(1)
MAXIMUM FREQUENCY
Bidirectional (SCL)
Bidirectional (SDA)
ISO1540-Q1
2500 VRMS
4242 VPK
1 MHz
Unidirectional (SCL)
Bidirectional (SDA)
ISO1541-Q1
(1) See 节6.7 for detailed Isolation specifications.
7.4 Isolator Functional Principle
To isolate a bidirectional signal path (SDA or SCL), the ISO1540-Q1 internally splits a bidirectional line into two
unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output
is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1540-Q1 connects to a
low-capacitance I2C node, while side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF of
capacitance.
VCC1
VCC2
A
VC-out
RPU2
RPU1
B
C
SDA1
SDA2
ISO1540
40 mV
50 mV
Cnode
Cbus
VSDA1
D
VILT1
VIHT1
VOL1
GND1
GND2
VREF
图7-3. SDA Channel Design and Voltage Levels at SDA1
At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up.
However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode
drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The
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comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V
(maximum) driven directly by SDA1 and the buffered output low-level of B.
图 7-4 demonstrate the switching behavior of the I2C isolator, ISO1540-Q1, between a controller node at SDA1
and a heavy loaded bus at SDA2.
VCC2
VCC2
VCC1
VCC1
VOL1
SDA1
50%
SDA2
VIHT1
30%
Receive
Delay
Receive
Delay
Transmit
Delay
Receive
Delay
VCC1
VCC2
VIHT2
VCC1
VCC2
Transmit
Delay
SDA2
50%
SDA1
30%
图7-4. SDA Channel Timing in Receive and Transmit Directions
7.4.1 Receive Direction (Left Diagram of )
When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the
buffered output of VOL1 = 0.75 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum
input-low voltage of VIL = 0.9 V at 3 V supply levels.
When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by
RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the time-
constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2
reaches VCC2 potential.
7.4.2 Transmit Direction (Right Diagram of )
When a controller drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2
turns low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be
observed immediately as it is overwritten by the lower low-level of the controller.
However, when the controller releases SDA1, the voltage potential increases and first must pass the upper input
threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered
output level of VOL1 = 0.75 V, maintained by the receive path. When comparator C turns high, SDA2 is released
after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases
SDA1 to move toward VCC1 potential.
7.5 Device Functional Modes
表7-2 lists the ISO154x-Q1 functional modes.
表7-2. Function Table
POWER STATE
INPUT
OUTPUT
VCC1 or VCC2 < 2.1 V
VCC1 and VCC2 > 2.8 V
VCC1 and VCC2 > 2.8 V
VCC1 and VCC2 > 2.8 V
X
L
Z
L
Z
?
H
Z(1)
(1) Invalid input condition as an I2C system requires that a pullup resistor to VCC is connected.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 I2C Bus Overview
The inter-integrated circuit (I2C) bus is a single-ended, multi-controller, 2-wire bus for efficient inter-IC
communication in half-duplex mode.
I2C uses open-drain technology, requiring two lines, serial data (SDA) and serial clock (SCL), to be connected to
VDD by resistors (see 图 8-1). Pulling the line to ground is considered a logic zero while letting the line float is a
logic one. This logic is used as a channel access method. Transitions of logic states must occur while the SCL
pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply voltages
are 3.3 V and 5 V, although systems with higher or lower voltages are allowed.
V
DD
R
R
PU
R
R
R
R
PU
PU
R
R
PU
PU
PU
PU
PU
SDA
SCL
SDA
SDA
SCL
SDA
SDA
SCL
SCL
SCL
GND
GND
GND
GND
C
ADC
Target
DAC
Target
C
Target
Controller
图8-1. I2C Bus
I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112
nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified,
total bus capacitance of 400 pF, which restricts communication distances to a few meters.
The specified signaling rates for the ISO1540-Q1 and ISO1541-Q1 devices are 100 kbps (standard mode), 400
kbps (fast mode), 1 Mbps (fast mode plus).
The bus has two roles for nodes: controller and target. A controller node issues the clock and target addresses,
and also initiates and ends data transactions. A target node receives the clock and addresses and responds to
requests from the controller. 图8-2 shows a typical data transfer between controller and target.
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7-bit
8-bit
8-bit
ACK /
NACK
R/W
ACK
ACK
SDA
SCL
ADDRESS
DATA
DATA
1 - 7
8
9
1 - 8
9
1 - 8
9
S
P
START
STOP
Condition
condition
图8-2. Timing Diagram of a Complete Data Transfer
The controller initiates a transaction by creating a START condition, following by the 7-bit address of the target it
wishes to communicate with. This is followed by a single read and write (R/W) bit, representing whether the
controller wishes to write to 0, or to read from 1 the target. The controller then releases the SDA line to allow the
target to acknowledge the receipt of data.
The target responds with an acknowledge bit (ACK) by pulling the SDA pin low during the entire high time of the
9th clock pulse on the SCL signal, after which the controller continues in either transmit or receive mode
(according to the R/W bit sent), while the target continues in the complementary mode (receive or transmit,
respectively).
The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a
high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of
SDA while SCL is high.
If the controller writes to a target, it repeatedly sends a byte with the target sending an ACK bit. In this case, the
controller is in controller-transmit mode and the target is in target-receive mode.
If the controller reads from a target, it repeatedly receives a byte from the target, while acknowledging (ACK) the
receipt of every byte but the last one (see 图 8-3). In this situation, the controller is in controller-receive mode
and the target is in target-transmit mode.
The controller ends the transmission with a STOP bit, or may send another START bit to maintain bus control for
further transfers.
A = acknowledge
S Target Address W A
DATA
A
DATA
A P
A P
A = not acknowledge
S = Start
From Controller to Target
From Target to Controller
Controller Transmitter writing to Target Receiver
P = Stop
R = Read
S Target Address R A
DATA
A
DATA
W = Write
Controller Receiver reading from Target Transmitter
图8-3. Transmit or Receive Mode Changes During a Data Transfer
When writing to a target, a controller mainly operates in transmit-mode and only changes to receive-mode when
receiving acknowledgment from the target.
When reading from a target, the controller starts in transmit-mode and then changes to receive-mode after
sending a READ request (R/W bit = 1) to the target. The target continues in the complementary mode until the
end of a transaction.
备注
The controller ends a reading sequence by not acknowledging (NACK) the last byte received. This
procedure resets the target state machine and allows the controller to send the STOP command.
Copyright © 2022 Texas Instruments Incorporated
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ISO1540-Q1, ISO1541-Q1
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8.2 Typical Application
图 8-4 shows isolated I2C data acquisition system built with TI microcontroller, analog-to-digital converter, and
I2C isolator, ISO1541-Q1.
The entire circuit operates from a single 3.3-V supply. A low-power push-pull converter, SN6501-Q1, drives a
center-tapped transformer with an output that is rectified and linearly regulated to provide a stable 5-V supply for
the data converter.
VS
0.1 ꢀF
3.3 V
2
MBR0520L
Vcc
1:2.2
3
1
6,7
13,14
3
5VISO
D2
D1
IN
OUT
TPS76750-Q1
SN6501-Q1
10 ꢀF
0.1 ꢀF
10 ꢀF
5
EN
GND
10 ꢀF
MBR0520L
ISO Barrier
GND
GND
4
5
1.5 kꢁ
1.5 kꢁ
0.1 ꢀF
1.5 kꢁ
0.1 ꢀF
1.5 kꢁ
5VISO
0.1 ꢀF
8
43
VDD
1
8
VDD
4
7
VCC1
VCC2
2
2
7
6
9
AIN0
AIN3
SDA
41
40
SDA
SDA1
SDA2
X1
X2
4 Analog
Inputs
ADS1115-Q1
ISO1541-Q1
3
10
TMS320F28035PAGQ
3
SCL
SCL
SCL1
SCL2
1
ADDR
GND2
5
GND
3
GND1
4
VSS
42
Copyright © 2016, Texas Instruments Incorporated
图8-4. Isolated I2C Data Acquisition System
8.2.1 Design Requirements
The recommended power supply voltages (VCC1 and VCC2) must be from 3 V to 5.5 V. A recommended
decoupling capacitor with a value of 0.1 µF is required between both the VCC1 and GND1 pins, and the VCC2
and GND2 pins to support of power supply voltages transient and to ensure reliable operation at all data rates.
8.2.2 Detailed Design Procedure
The power-supply capacitor with a value of 0.1-µF must be placed as close to the power supply pins as possible.
The recommended placement of the capacitors must be 2-mm maximum from input and output power supply
pins (VCC1 and VCC2).
The maximum load permissible on the input lines, SDA1 and SCL1, is ≤ 40 pF and on the output lines, SDA2
and SCL2, is ≤400 pF.
The minimum pullup resistors on the input lines, SDA1 and SCL1 to VCC1 must be selected in such a way that
input current drawn is ≤ 3.5 mA. The minimum pullup resistors on the input lines, SDA2 and SCL2, to VCC2
must be selected in such a way that output current drawn is ≤ 35 mA. The maximum pullup resistors on the
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ISO1540-Q1, ISO1541-Q1
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www.ti.com.cn
input lines (SDA1 and SCL1) to VCC1 and on output lines (SDA1 and SCL1) to VCC2, depends on the load and
rise time requirements on the respective lines.
ISO1540-Q1
2mm
maximum
2 mm
maximum
VCC1
SDA1
SCL1
VCC2
8
1
0.1 ꢁF
0.1 ꢁF
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
SDA2
2
7
SCL2
3
4
6
5
GND2
GND1
Side 1
Side 2
图8-5. Typical ISO1540-Q1 Circuit Hookup
ISO1541-Q1
2mm
maximum
2 mm
maximum
VCC1
SDA1
SCL1
VCC2
8
1
0.1 ꢁF
0.1 ꢁF
1 kꢀ
1 kꢀ
1 kꢀ
1 kꢀ
SDA2
SCL2
2
7
3
4
6
5
GND1
GND2
Side 1
Side 2
图8-6. Typical ISO1541-Q1 Circuit Hookup
8.2.3 Application Curve
T
= 25oC
A
VCC1 = 3.6 V
900 mV
VOL1
GND1
Time - 50 ns/div
图8-7. Side 1: Low-to-High Transition
Copyright © 2022 Texas Instruments Incorporated
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ISO1540-Q1, ISO1541-Q1
ZHCSFS4D –NOVEMBER 2016 –REVISED DECEMBER 2022
www.ti.com.cn
9 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, TI recommends connecting a 0.1-µF bypass
capacitor at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the
supply pins as possible. If only a single, primary-side power supply is available in an application, isolated power
can be generated for the secondary-side with the help of a transformer driver such as TI's SN6501-Q1 device.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies (SLLSEF3).
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Product Folder Links: ISO1540-Q1 ISO1541-Q1
ISO1540-Q1, ISO1541-Q1
ZHCSFS4D –NOVEMBER 2016 –REVISED DECEMBER 2022
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 10-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide (SLLA284)
10.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
10.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
图10-1. Recommended Layer Stack
Copyright © 2022 Texas Instruments Incorporated
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ISO1540-Q1, ISO1541-Q1
ZHCSFS4D –NOVEMBER 2016 –REVISED DECEMBER 2022
www.ti.com.cn
11 Device and Documentation Support
11.1 Documentation Support
备注
TI is transitioning to use more inclusive terminology. Some language may be different than what you
would expect to see for certain technology areas.
11.1.1 Related Documentation
For related documentation see the following:
• Digital Isolator Design Guide (SLLA284)
• TI Isolation Glossary (SLLA353)
• SN6501-Q1 Transformer Driver for Isolated Power Supplies. (SLLSEF3)
• TPS767xx-Q1 Fast-Transient-Response 1-A Low-Dropout Voltage Regulators (SGLS009)
• ADS1115-Q1 Low-Power, 16-Bit Analog-to-Digital Converter With Internal Reference (SBAS563)
• TMS320F2803x Piccolo™ Microcontrollers (TMS320F2803x Piccolo™ Microcontrollers)
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
ISO1540-Q1
ISO1541-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
11.5 Trademarks
Piccolo™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: ISO1540-Q1 ISO1541-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1540QDQ1
ISO1540QDRQ1
ISO1541QDQ1
ISO1541QDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
I1540Q
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
I1540Q
I1541Q
I1541Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Apr-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO1540-Q1, ISO1541-Q1 :
Catalog : ISO1540, ISO1541
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1540QDRQ1
ISO1540QDRQ1
ISO1541QDRQ1
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
6.4
5.2
5.2
5.2
2.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO1540QDRQ1
ISO1540QDRQ1
ISO1541QDRQ1
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
350.0
356.0
350.0
350.0
356.0
350.0
43.0
35.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO1540QDQ1
ISO1541QDQ1
D
D
SOIC
SOIC
8
8
75
75
505.46
505.46
6.76
6.76
3810
3810
4
4
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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SI9137LG
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SI9122E
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