ISO1640_V01 [TI]
ISO164x Hot-Swappable Bidirectional I2C Isolators with Enhanced EMC and GPIOs;型号: | ISO1640_V01 |
厂家: | TEXAS INSTRUMENTS |
描述: | ISO164x Hot-Swappable Bidirectional I2C Isolators with Enhanced EMC and GPIOs |
文件: | 总45页 (文件大小:3020K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISO1640, ISO1641
SLLSFC2B – FEBRUARY 2020 – REVISED MAY 2021
ISO164x Hot-Swappable Bidirectional I2C Isolators with Enhanced EMC and GPIOs
1 Features
3 Description
•
Reliable Isolated Bidirectional, I2C Compatible,
Communication
– ISO1640: Bidirectional Isolated SDA and SCL
communication
– ISO1641: Bidirectional SDA and unidirectional
SCL communcation
– Hot Swappable SDA and SCL
Bidirectional data transfer up to 1.7 MHz Operation
The ISO1640 and ISO1641 (ISO164x) devices are
hot swappable, low-power, bidirectional isolators that
are compatible with I2C interfaces. The ISO164x
supports UL 1577 isolation ratings of 5000 VRMS
in the 16-DW package, and 3000 VRMS in the 8-D
package. Each isolation channel in this low emissions
device has a logic input and open drain output
separated by a double capacitive silicon dioxide
(SiO2) insulation barrier. This family includes basic
and reinforced insulation ratings devices certified by
VDE, UL, CSA, TUV and CQC. The ISO1640 has
two isolated bidirectional channels for clock and data
lines while the ISO1641 has a bidirectional data
and a unidirectional clock channel. The ISO164x
family integrates logic required to support bidirectional
channels, providing a much simpler design and
smaller footprint when compared to optocoupler-
based solutions.
•
•
•
Robust isolation barrier with enhanced EMC:
– >100-year projected lifetime at 450 VRMS
working voltage (D-8) and 1500 VRMS working
voltage (DW-16)
– Up to 5000 VRMS isolation rating
– Up to 10 kV reinforced surge capability
– ±100 kV/μs typical CMTI
– ±8 kV IEC-ESD 61000-4-2 contact discharge
protection across isolation barrier
– Same side ±8 kV IEC-ESD unpowered contact
discharge on SCL2 and SDA2 (Side 2)
Supply range: 3 V to 5.5 V (Side 1) and 2.25 V to
5.5 V (Side 2)
Open-Drain Outputs With 3.5-mA (Side 1) and 50-
mA (Side 2) Sink Current Capability
Max capacitive load: 80 pF (Side 1) and 400 pF
(Side 2)
Device Information(1)
PART NUMBER
PACKAGE
SOIC (8)
SOIC (16)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
10.30 mm × 7.50 mm
•
•
•
•
ISO1640BD
ISO1641BD
ISO1640DW
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
16-SOIC (DW-16) and 8-SOIC (D-8) Package
Options
–40°C to +125°C Operating Temperature
Safety-Related Certifications (planned):
– UL 1577 Component Recognition Program
– DIN VDE V 0884-11
Isolation Options
PART NUMBER
Protection Level
Surge Test Voltage
Isolation Rating
ISO164xBD
ISO164xDW
Reinforced
10000 VPK
5000 VRMS
•
•
Basic
6500 VPK
3000 VRMS
450 VRMS / 637 1500 VRMS / 2121
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
GB4943.1-2011 certifications
Working Voltage
VPK
VPK
2 Applications
VCC1
VCC2
•
•
•
•
•
Isolated I2C Buses
SMBus and PMBus Interfaces
Power Over Ethernet (PoE)
Motor Control Systems
Battery Management
.
SDA1
or SCL1
SDA2
or SCL2
GND1
GND2
VREF
Simplified Isolated Bidirectional Data Channel
Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1640, ISO1641
SLLSFC2B – FEBRUARY 2020 – REVISED MAY 2021
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5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
VCC1
SDA1
SCL1
GND1
VCC2
SDA2
SCL2
GND2
Side 2
Side 1
Not to scale
Figure 5-1. ISO1640B Package 8-Pin SOIC Top View
1
2
3
4
8
7
6
5
VCC1
SDA1
SCL1
GND1
VCC2
SDA2
SCL2
GND2
Side 2
Side 1
Not to scale
Figure 5-2. ISO1641B Package 8-Pin SOIC Top View
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GND1
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND2
NC
VCC1
NC
VCC2
NC
SDA1
SCL1
GND1
NC
SDA2
SCL2
NC
GND2
Side 1
Not to scale
Side 2
Figure 5-3. ISO1640 Package 16-Pin SOIC Top View
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Table 5-1. Pin Functions — ISO1640 and ISO1641
PIN
8-D
NO.
4
16-DW
NO.
I/O
DESCRIPTION
NAME
GND1
GND2
1, 7
—
—
—
Ground, side 1
Ground, side 2
No Connection
5
9, 16
2, 4, 8, 10,
13, 15
NC
—
3
Serial clock input / output, side 1 (ISO1640 only)
Serial clock input, side 1 (ISO1641 only)
SCL1
6
I/O
I/O
Serial clock input / output, side 2 (ISO1640 only)
Serial clock output, side 2 (ISO1641 only)
SCL2
6
11
SDA1
SDA2
VCC1
VCC2
2
7
1
8
5
12
3
I/O
I/O
—
Serial data input / output, side 1
Serial data input / output, side 2
Supply voltage, side 1
14
—
Supply voltage, side 2
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 5
5 Pin Configuration and Functions...................................2
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................7
6.5 Power Ratings ............................................................7
6.6 Insulation Specifications ............................................ 9
6.7 Safety-Related Certifications ....................................11
6.8 Safety Limiting Values ..............................................11
6.9 Electrical Characteristics ..........................................12
6.10 Supply Current Characteristics .............................. 13
6.11 Timing Requirements ............................................. 14
6.12 I2C Switching Characteristics ................................ 15
6.13 GPIO Switching Characteristics .............................17
6.14 Insulation Characteristics Curves........................... 18
6.15 Typical Characteristics............................................19
7 Parameter Measurement Information..........................22
7.1 Parameter Measurement Information....................... 22
8 Detailed Description......................................................24
8.1 Overview...................................................................24
8.2 Functional Block Diagrams....................................... 24
8.3 Feature Description...................................................25
8.4 Isolator Functional Principle......................................26
8.5 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 29
9.3 Insulation Lifetime ....................................................31
10 Power Supply Recommendations..............................34
11 Layout...........................................................................35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Documentation Support.......................................... 36
12.2 Receiving Notification of Documentation Updates..36
12.3 Support Resources................................................. 36
12.4 Trademarks.............................................................36
12.5 Electrostatic Discharge Caution..............................36
12.6 Glossary..................................................................36
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2020) to Revision B (May 2021)
Page
•
•
•
Added ISO1641B to the datasheet.....................................................................................................................1
Changed minimum input threshold low to 480 mV........................................................................................... 12
Changed tpLH1-2, tpLH2-1, tLOOP1 max to a lower value for all operating voltages.............................................. 15
Changes from Revision * (February 2020) to Revision A (December 2020)
Page
•
Updated device status to Production Data......................................................................................................... 1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
–0.5
-0.5
0
MAX
UNIT
Supply Voltage
VCC1, VCC2
6
VCCX + 0.5(3)
VCCX + 0.5(3)
VCCX + 0.5
20
V
SDA1, SCL1
Input/Output Voltage
SDA2, SCL2
V
INx (ISO1644 only)
SDA1, SCL1
Input/Output Current
Temperature
SDA2, SCL2
0
100
mA
IIO (ISO1644 only)
Maximum junction temperature, TJ
Storage temperature, Tstg
-15
15
150
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to the local ground pin (GND1 or GND2) and are peak voltage values.
(3) During powered off hotswap, the bus pins can go 0 V < SDAx, SCLx < 6 V. Maximum voltage for INx must not exceed 6 V.
6.2 ESD Ratings
VALUE
±6000
±10000
±14000
±8000
±8000
±1500
±8000
UNIT
All pins
V
V
V
V
V
V
V
ISO1640/1: Bus pins (SDA1, SCL1)
ISO1640/1: Bus pins (SDA2, SCL2)
ISO1644: Bus pins (SDA1, SCL1)
ISO1644: Bus pins (SDA2, SCL2)
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(3) (4)
Same side unpowered IEC ESD
contact discharge per IEC 61000-4-2;
Side 2
ISO1640/1: SCL2, SDA2
±8000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
6.3 Recommended Operating Conditions
MIN
NOM
2.7
2.6
2
MAX UNIT
VCC1(UVLO+)
VCC1(UVLO-)
VCC2(UVLO+)
VCC2(UVLO-)
UVLO threshold when supply voltage is rising on Side 1
UVLO threshold when supply voltage is falling on Side 1
UVLO threshold when supply voltage is rising on Side 2
UVLO threshold when supply voltage is falling on Side 2
Supply voltage UVLO hysteresis, Side 1
2.9
V
V
V
V
2.3
2.25
1.7
1.8
VHYS1(UVLO)
VHYS2(UVLO)
100
150
150
mV
mV
Supply voltage UVLO hysteresis, Side 2
100
VCC1
VCC2
Supply voltage, Side 1
Supply voltage, Side 2
3.0
5.5
5.5
V
V
2.25
VSDA1
VSCL1
,
I2C Input and output signal voltages, Side 1
0
VCC1
V
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MIN
NOM
MAX UNIT
VSDA2
VSCL2
,
I2C Input and output signal voltages, Side 2
0
VCC2
V
VIL1
VIH1
VIL2
VIH2
IOL1
IOL2
C1
I2C Low-level input voltage, Side 1
0
0.7 × VCC1
0
480
VCC1
mV
V
I2C High-level input voltage, Side 1
I2C Low-level input voltage, Side 2
0.3 × VCC2
VCC2
V
I2C High-level input voltage, Side 2
0.5 × VCC2
0.5
V
I2C Output current, Side 1
3.5
mA
mA
pF
pF
MHz
V
I2C Output current, Side 2
0.5
50
Capacitive load, Side 1
80
C2
Capacitive load, Side 2
400
fMAX
VILIO
VIHIO
I2C Operating frequency(1)
1.7
Low-level input voltage, GPIO pins (ISO1644 only)
High-level input voltage, GPIO pins (ISO1644 only)
GPIO High-level output current (ISO1644 only), VCCO = 5 V
GPIO High-level output current (ISO1644 only), VCCO = 3.3 V
GPIO High-level output current (ISO1644 only), VCCO = 2.5 V
GPIO Low-level output current (ISO1644 only), VCCO = 5 V
GPIO Low-level output current (ISO1644 only), VCCO = 3.3 V
GPIO Low-level output current (ISO1644 only), VCCO = 2.5 V
GPIO maximum data rate frequency (ISO1644 only)
Ambient temperature
0.7 × VCC1
VCC1
0
-4
-2
-1
0.3 × VCC2
V
mA
mA
mA
mA
mA
mA
IOHIO
4
2
1
IOLIO
fDR
TA
50 Mbps
125 °C
–40
25
(1) Maximum frequency is a function of the RC time constant on the bus. If the system has less bus capacitance, then higher frequencies
can be achieved.
6.4 Thermal Information
ISO1640/1
ISO1644
THERMAL METRIC(1)
D (SOIC) DW (SOIC) DW (SOIC)
UNIT
8 PINS
106.3
38.5
52.5
8.2
16 PINS
62.4
29.5
33.5
11.7
32.4
-
16 PINS
58.3
25.5
29.7
8.9
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
51.8
-
28.5
-
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO1640
Maximum power dissipation (both
sides)
PD
96
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
PD1
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
43
53
mW
mW
PD2
ISO1641
Maximum power dissipation (both
sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
PD
87
40
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
PD1
Maximum power dissipation (side-1)
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
PD2
Maximum power dissipation (side-2)
47
mW
ISO1644
PD
Maximum power dissipation (both
sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
INA = INB = INC = Input at 25-MHz 50% duty cycle square wave,
CL = 15pF
TBD
mW
PD1
PD2
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
TBD
TBD
mW
mW
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6.6 Insulation Specifications
PARAMETER
SPECIFICATIONS
UNIT
TEST CONDITIONS
DW
D
IEC 60664-1
CLR
CPG
External clearance(1)
Side 1 to side 2 distance through air
>8
>8
4
mm
mm
Side 1 to side 2 distance across package
surface
External Creepage(1)
4
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
>17
>600
I
>17
µm
V
>400
II
According to IEC 60664-1
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-IV
I-IV
I-III
I-IV
I-III
n/a
n/a
Overvoltage category
DIN V VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
2121
1500
2121
7071
637
450
637
4242
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test;
VIOWM
Maximum isolation working voltage
Maximum transient isolation voltage
DC voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
VPK
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6,500 VPK
(Basic qualification) Test method per IEC
62368-1, 1.2/50 µs waveform, VTEST = 1.6 ×
VIOSM = 10,000 VPK (Reinforced qualification)
VIOSM
Maximum surge isolation voltage(3)
6250
5000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM
tm = 10 s
,
≤ 5
≤ 5
≤ 5
≤ 5
Method a: After environmental tests subgroup
1, Vini = VIOTM, tini = 60 s;
qpd
Apparent charge(4)
pC
Vpd(m) = 1.6 × VIORM , tm = 10 s
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM
tini = 1 s;
,
≤ 5
≤ 5
Vpd(m) = 1.875 × VIORM , tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
1
1
pF
Ω
> 1012
> 1011
> 109
2
> 1012
> 1011
> 109
2
VIO = 500 V, 100°C ≤ TA ≤ 150°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
40/125/
21
40/125/
21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST
1.2 × VISO , t = 1 s (100% production)
=
VISO
Withstand isolation voltage
5000
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) ISO164xDW is suitable for safe electrical insulation and ISO164xBD is suitable for basic electrical insulation only within the safety
ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
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(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to IEC
61010-1, IEC 62368-1 and Component Recognition
IEC 60601-1
Recognized under UL 1577
Certified according to EN
61010-1:2010/A1:2019, and EN
62368-1:2014
Certified according to DIN
VDE V 0884-11:2017-01
Certified according to
GB4943.1-2011
Program
DW-16: 600 VRMS
5000 VRMS (DW-16) and 3000
DW-16: Reinforced Insulation, VRMS (D-8) Reinforced insulation
Maximum transient isolation
voltage, 7071 VPK (DW-16),
and 4242 VPK (D-8);
Maximum repetitive peak
isolation voltage, 1500 VPK
(DW-16), and 637 VPK (D-8);
Maximum surge isolation
voltage, 6250 VPK (DW-16),
and 5000 VPK (D-8)
reinforced insulation per
CSA 62368-1:19 and IEC
62368-1:2018 , (pollution
degree 2, material group I) 5000 VRMS
D-8: 400 VRMS basic
insulation per CSA
62368-1:19 and IEC
62368-1:2018, (pollution
degree 2, material group III)
Altitude ≤ 5000 m, Tropical
Climate,700 VRMS maximum
working voltage;
per EN 61010- 1:2010/A1:2019 up
to working voltage of 600 VRMS
(DW-16) and 300 VRMS (D-8)
DW-16: Single protection,
;
D-8: Single protection, 3000 D-8: Basic Insulation, Altitude 5000 VRMS (DW-16) and 3000 VRMS
VRMS
≤ 5000 m, Tropical Climate,
250 VRMS maximum working
voltage
(D-8) Reinforced insulation per EN
62368-1:2014 up to working voltage
of 600 VRMS (DW-16) and 400 VRMS
(D-8)
Master contract number
(ISO164xBD): 220991
Certification planned (All
others)
File number (ISO164xBD):
E181974
Certification planned (All
others)
Certification planned
Certification planned
Certification planned
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO1640/1 D-8 PACKAGE
RθJA = 106.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
RθJA = 106.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
214
327
Safety input, output, or supply
IS
mA
current(1)
Safety input, output, or total
power(1)
PS
TS
RθJA = 106.3 °C/W, TJ = 150°C, TA = 25°C
1176
150
mW
°C
Safety temperature(1)
ISO1640/1 DW-16 PACKAGE
RθJA = 62.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
RθJA = 62.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
365
557
Safety input, output, or supply
IS
mA
current(1)
Safety input, output, or total
power(1)
PS
TS
RθJA = 62.4 °C/W, TJ = 150°C, TA = 25°C,
2004
150
mW
°C
Safety temperature(1)
ISO1644 DW-16 Package
Safety input, output, or supply
IS
RθJA = 137.5 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
RθJA = 137.5 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
RθJA = 137.5 °C/W, TJ = 150°C, TA = 25°C
166
253
mA
mA
current(1)
Safety input, output, or supply
current(1)
Safety input, output, or total
power(1)
PS
TS
910
150
mW
°C
Safety temperature(1)
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SIDE 1
Voltage input threshold low
(SDA1 and SCL1)
VILT1
480
560
620
mV
Voltage input threshold high
(SDA1 and SCL1)
VIHT1
VHYST1
VOL1
520
50
mV
mV
mV
Voltage input hysteresis
VIHT1 – VILT1
60
Low-level output voltage(1)
(SDA1 and SCL1)
0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA
570
650
710
Low-level output voltage to highlevel input
voltage threshold difference, SDA1 and
SCL1(2) (3)
ΔVOIT1
0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA
50
mV
SIDE 2
Voltage input threshold low
(SDA2 and SCL2)
VILT2
0.3 × VCC2
0.4 × VCC2
0.5 × VCC2
V
Voltage input threshold high
(SDA2 and SCL2)
VIHT2
VHYST2
VOL2
0.4 × VCC2
V
V
V
Voltage input hysteresis
VIHT2 – VILT2
0.05 × VCC2
Low-level output voltage
(SDA2 and SCL2)
0.5 mA ≤ (ISDA2 and ISCL2) ≤ 50 mA
0.4
10
BOTH SIDES
Input leakage currents
(SDA1, SCL1, SDA2, and SCL2)
VSDA1, VSCL1 = VCC1
VSDA2, VSCL2 = VCC2
,
|II|
0.01
10
µA
pF
Input capacitance to local ground
(SDA1, SCL1, SDA2, and SCL2)
CI
VI = 0.4 × sin(2e6*πt) + VDDx / 2
VCM = 1000 V, see Common-Mode
Transient Immunity Test Circuit
CMTI
Common-mode transient immunity
50
100
kV/µs
GPIO Channels
VCCx = 5 V, IOH = -4 mA; See TBD.
ISO1644 only
VCCO - 0.4
VCCO - 0.3
VCCO - 0.2
V
V
V
V
V
V
VCCx = 3.3 V, IOH = -2 mA; See TBD.
ISO1644 only
VIOOH
High-level output voltage
VCC1 = 2.5 V, IOH = -1 mA; See TBD.
ISO1644 only
VCCx = 5 V, IOH = 4 mA; See TBD. ISO1644
only
0.4
0.3
0.2
VCCx = 3.3 V, IOH = 2 mA; See TBD.
ISO1644 only
VIOOL
Low-level output voltage
VCC1 = 2.5 V, IOH = 1 mA; See TBD.
ISO1644 only
(1)
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
ISO1644 only
0.7 x VCCI
V
V
ISO1644 only
0.3 x VCCI
0.1 x VCCI
ISO1644 only
V
VIH = VCCI (1) at INx ISO1644 only
VIL = 0 V at INx ISO1644 only
10
µA
µA
IIL
Low-level input current
-10
(1) This parameter does not apply to the SCL1 line of the ISO1641 device because it is unidirectional.
(2) ∆VOIT1 = VOL1 – VIHT1. This value represents the minimum difference between a threshold for the low-level output voltage and
a threshold for the high-level input voltage to prevent a permanent latch condition that would otherwise occur with bidirectional
communication.
(3) Any supply voltages on either side that are less than the minimum value make sure that the device does a lockout. Both supply
voltages that are greater than the maximum value keep the device from a lockout.
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6.10 Supply Current Characteristics
over recommended operating conditions, unless otherwise noted. See Test Diagram for more information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.25 V ≤ VCC2 ≤ 2.75 V
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.9
2.7
3.8
2.7
6.6
3.5
5.2
3.5
mA
mA
mA
mA
Supply current,
Side 2
ICC2
ISO1640
ISO1641
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
Supply current,
Side 2
ICC2
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.5
5.6
10
8.7
mA
mA
mA
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
Supply current,
Side 2
ICC2
ISO1644
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.7
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
11.2
3 V ≤ VCC1, VCC2 ≤ 3.6 V
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
5.2
3
7.1
4
mA
mA
mA
mA
Supply current,
Side 1
ICC1
ISO1640
ISO1641
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.6
2.4
6.1
3.2
Supply current,
Side 1
ICC1
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.4
4.6
9.6
9.6
mA
mA
mA
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
Supply current,
Side 1
ICC1
ISO1644
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.6
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
13.1
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.9
2.8
3.9
2.8
6.7
3.5
5.2
3.5
mA
mA
mA
mA
Supply current,
Side 2
ICC2
ISO1640
ISO1641
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
Supply current,
Side 2
ICC2
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
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over recommended operating conditions, unless otherwise noted. See Test Diagram for more information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.5
10
8.4
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
5.6
mA
mA
mA
Supply current,
Side 2
ICC2
ISO1644
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.7
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
11.3
4.5 V ≤ VCC1, VCC2 ≤ 5.5 V
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
5.3
3
7.2
4.1
6.2
3.2
mA
mA
mA
mA
Supply current,
Side 1
ICC1
ISO1640
ISO1641
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.7
2.5
Supply current,
Side 1
ICC1
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
10.4
9.7
mA
mA
mA
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
Supply current,
Side 1
ICC1
ISO1644
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.7
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
13.5
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
5
2.8
3.9
2.8
6.8
3.6
5.3
3.6
mA
mA
mA
mA
Supply current,
Side 2
ICC2
ISO1640
ISO1641
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
Supply current,
Side 2
ICC2
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
9.8
8.5
mA
mA
mA
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
Supply current,
Side 2
ICC2
ISO1644
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.8
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
11.5
6.11 Timing Requirements
MIN
NOM
MAX
UNIT
VCC1 > VCC1(UVLO+) or VCC2 > VCC2(UVLO+), I2C bus Idle.
see tUVLO Test Circuit and Timing Diagrams
tUVLO
Time to recover from UVLO
36
95
151
µs
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6.12 I2C Switching Characteristics
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V
0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 72 Ω,
C2 = 400 pF, see Test Diagram
16
38
26.5
53.3
20
40
78
Output signal fall time
(SDA2 and SCL2)
tf2
ns
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 72Ω,
C2 = 400 pF, see Test Diagram
Low-to-high propagation delay, side 1
to side 2
VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
tpLH1-2
30
ns
ns
ns
ns
ns
ns
ns
High-to-low propagation delay, side 1 to VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1
tpHL1-2
tpLH2-1
tpHL2-1
PWD1-2
PWD2-1
tLOOP1
80
130
48
side 2
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
Low-to-high propagation delay, side 2
to side 1(1)
VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 72 Ω, C1
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
40
High-to-low propagation delay, side 2 to VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 72 Ω, C1
70
100
104
55
side 1(1)
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
Pulse width distortion
R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V
see Test Diagram
60
|tpHL1-2 – tpLH1-2
|
Pulse width distortion(1)
R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V
see Test Diagram
25
|tpHL2-1 – tpLH2-1
|
Round-trip propagation delay on side
1(1)
0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 72 Ω, C2 = 400 pF, see Test Diagram
62
74
3 V ≤ VCC1, VCC2 ≤ 3.6 V
0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram
8
15
14
30
17
25
23
50
21
59
40
70
39
25
65
29
48
Output signal fall time
(SDA1 and SCL1)
tf1
ns
ns
0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 953 Ω,
C1 = 40 pF, see Test Diagram
0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 95.3 Ω,
C2 = 400 pF, see Test Diagram
47
Output signal fall time
(SDA2 and SCL2)
tf2
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 95.3 Ω,
C2 = 400 pF, see Test Diagram
100
29
Low-to-high propagation delay, side 1
to side 2
VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1
and C2 = 10 pF, see Test Diagram
tpLH1-2
tpHL1-2
tpLH2-1
tpHL2-1
PWD1-2
PWD2-1
tLOOP1
ns
ns
ns
ns
ns
ns
ns
High-to-low propagation delay, side 1 to VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1
88
side 2
and C2 = 10 pF, see Test Diagram
Low-to-high propagation delay, side 2
to side 1(1)
VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 95.3 Ω,
C1 and C2 = 10 pF, see Test Diagram
47
High-to-low propagation delay, side 2 to VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 95.3 Ω,
100
61
side 1(1)
C1 and C2 = 10 pF, see Test Diagram
Pulse width distortion
R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF,
see Test Diagram
|tpHL1-2 – tpLH1-2
|
Pulse width distortion(1)
R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF,
see Test Diagram
48
|tpHL2-1 – tpLH2-1
|
Round-trip propagation delay on side
1(1)
0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram
78
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UNIT
SLLSFC2B – FEBRUARY 2020 – REVISED MAY 2021
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.5 V ≤ VCC1, VCC2 ≤ 5.5 V
0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 1430 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram
6
13
10
28
16
32
24
48
21
51
51
60
30
10
84
22
48
30
76
28
70
57
88
45
34
96
Output signal fall time
(SDA1 and SCL1)
tf1
ns
ns
0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 1430 Ω,
C1 = 40 pF, see Test Diagram
0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 143 Ω,
C2 = 400 pF, see Test Diagram
Output signal fall time
(SDA2 and SCL2)
tf2
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 143 Ω,
C2 = 400 pF, see Test Diagram
Low-to-high propagation delay, side 1
to side 2
VI = 535 mV, VO = 0.7 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1
and C2 = 10 pF, see Test Diagram
tpLH1-2
tpHL1-2
tpLH2-1
tpHL2-1
PWD1-2
PWD2-1
tLOOP1
ns
ns
ns
ns
ns
ns
ns
High-to-low propagation delay, side 1 to VI = 550 mV, VO = 0.3 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1
side 2
and C2 = 10 pF, see Test Diagram
Low-to-high propagation delay, side 2
to side 1(1)
VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 1430 Ω, R2 = 143 Ω,
C1 and C2 = 10 pF, see Test Diagram
High-to-low propagation delay, side 2 to VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 1430 Ω, R2 = 143 Ω,
side 1(1)
C1 and C2 = 10 pF, see Test Diagram
Pulse width distortion
R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF,
see Test Diagram
|tpHL1-2 – tpLH1-2
|
Pulse width distortion(1)
R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF,
see Test Diagram
|tpHL2-1 – tpLH2-1
|
Round-trip propagation delay on side
1(1)
0.4 V ≤ VI ≤ 0.3 × VCCI, R1 = 1430 Ω,
C1 = 40 pF, R2 = 143 Ω, C2 = 400 pF, see Test Diagram
(1) This parameter does not apply to the SCL1 line of the ISO1641 device because it is unidirectional.
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6.13 GPIO Switching Characteristics
over recommended operating conditions, unless otherwise noted. ISO1644 only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3 V ≤ VCC1, VCC2 ≤ 3.6 V
tPLH, tPHL
tP(dft)
tUI
Propagation delay time
Propagation delay drift
Minimum pulse width
See TBD
11
20
ns
ps/℃
ns
9.2
See TBD
See TBD
20
PWD
tsk(o)
tsk(p-p)
tr
Pulse width distortion
7
6
ns
Channel to channel output skew time
Part to part skew time
Output signal rise time
Output signal fall time
Same direction channels
ns
6
ns
See TBD
See TBD
6.5
6.5
ns
tf
ns
Default output delay time from input
power loss
tDO
tie
See TBD
0.1
1
0.3
us
ns
Time interval error
4.5 V ≤ VCC1, VCC2 ≤ 5.5 V
tPLH, tPHL
tP(dft)
tUI
Propagation delay time
See TBD
11
8
18
ns
ps/℃
ns
Propagation delay drift
Minimum pulse width
See TBD
20
PWD
tsk(o)
tsk(p-p)
tr
Pulse width distortion
See TBD
7
6
6
6
6
ns
Channel to channel output skew time
Part to part skew time
Output signal rise time
Output signal fall time
Same direction channels
ns
ns
See TBD
See TBD
ns
tf
ns
Default output delay time from input
power loss
tDO
tie
See TBD
0.1
1
0.3
us
ns
Time interval error
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6.14 Insulation Characteristics Curves
350
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 3.3V
VCC1 = VCC2 = 5.5V
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
Ambient Temperature (èC)
Ambient Temperature (èC)
SLLS
SLLS
Figure 6-2. Thermal Derating Curve for Safety
Limiting Power for D-8 Package
Figure 6-1. Thermal Derating Curve for Safety
Limiting Current for D-8 Package
350
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 3.3V
VCC1 = VCC2 = 5.5V
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
Ambient Temperature (èC)
Ambient Temperature (èC)
SLLS
SLLS
Figure 6-4. Thermal Derating Curve for Safety
Limiting Power for DW-16 Package
Figure 6-3. Thermal Derating Curve for Safety
Limiting Current for DW-16 Package
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6.15 Typical Characteristics
0.78
20
18
16
14
12
10
8
VCC1 = 3.3 V, IOL1 = 3.5 mA
VCC1 = 3.3 V, IOL1 = 0.5 mA
VCC1 = 5 V, IOL1 = 3.5 mA
VCC1 = 5 V, IOL1 = 0.5 mA
0.74
0.7
0.66
0.62
0.58
6
C1 = 80 pF, R1 = 1.43 kW
C1 = 80 pF, R1 = 2.2 kW
C1 = 40 pF, R1 = 1.43 kW
C1 = 40 pF, R1 = 2.2 kW
4
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
SLLS
SLLS
TA = 25°C
VCC1 = 5 V
Figure 6-5. Side 1: Output Low Voltage vs Free-Air
Temperature
Figure 6-6. Side 1: Output Fall Time vs Free-Air
Temperature
24
22
20
18
16
14
12
10
8
25
R2 = 143 W
R2 = 2.2 kW
20
15
10
5
C1 - 80 pF, R1 = 953 kW
6
C1 = 80 pF, R1 = 2.2 kW
4
C1 - 40 pF, R1 = 953 kW
C1 = 40 pF, R1 = 2.2 kW
2
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
SLLS
SLLS
VCC1 = 3.3 V
VCC2 = 5 V
C2 = 400 pF
Figure 6-7. Side 1: Output Fall Time vs Free-Air
Temperature
Figure 6-8. Side 2: Output Fall Time vs Free-Air
Temperature
25
30
R2 = 95.3
R2 = 2.2 k
R2 = 71.4 W
R2 = 2.2 kW
25
20
15
10
5
20
15
10
5
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
SLLS
SLLS
VCC2 = 3.3 V
C2 = 400 pF
VCC2 = 2.5 V
C2 = 400 pF
Figure 6-9. Side 2: Output Fall Time vs Free-Air
Temperature
Figure 6-10. Side 2: Output Fall Time vs Free-Air
Temperature
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100
90
80
70
60
50
40
30
20
590
585
580
575
570
565
560
VCC1 and VCC2 = 3.3 V, R1 and R2 = 2.2 kW
VCC1 and VCC2 = 5 V, R1 and R2 = 2.2 kW
VCC1 and VCC2 = 3.3 V, R1 = 953 W, R2 = 95.3 W
VCC1 and VCC2 = 5 V, R1 = 1430 W, R2 = 143 W
10
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
SLLS
SLLS
C1 = 80 pF
C2 = 400 pF
C1 = 80 pF
C2 = 400 pF
Figure 6-11. tLOOP1 vs Free-Air Temperature
Figure 6-12. tLOOP1 vs Free-Air Temperature
30
1200
1180
1160
1140
1120
1100
1080
1060
25
20
15
10
1040
5
VCC1 and VCC2 = 5 V, R2 = 2.2 kW, C2 = 400 pF
VCC1 and VCC2 = 5 V, R2 = 143 W, C2 = 10pF
1020
VCC1 and VCC2 = 3.3 V, R2 = 2.2 kW, C2 = 400 pF
VCC1 and VCC2 = 3.3 V, R2 = 143 W, C2 = 10pF
1000
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
SLLS
SLLS
Figure 6-14. tPLH1-2 Propagation Delay vs Free-Air
Temperature
Figure 6-13. tPLH1-2 Propagation Delay vs Free-Air
Temperature
70
60
50
40
30
20
70
60
50
40
30
20
10
10
VCC1 and VCC2 = 5 V, R2 = 143 W, C2 = 10 pF
VCC1 and VCC2 = 3.3 V, R2 = 143 W, C2 = 10 pF
VCC1 and VCC2 = 5 V, R2 = 2.2 kW, C2 = 400 pF
VCC1 and VCC2 = 3.3 V, R2 = 2.2 kW, C2 = 400 pF
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110120
Free-Air Temperature (èC)
SLLS
SLLS
Figure 6-15. tPHL1-2 Propagation Delay vs Free-Air
Temperature
Figure 6-16. tPHL1-2 Propagation Delay vs Free-Air
Temperature
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70
60
50
40
30
20
10
0
150
140
130
120
110
100
90
VCC1 and VCC2 = 5 V, R1 = 2.2 kW, C1 = 40 pF
VCC1 and VCC2 = 3.3 V, R1 = 2.2 kW, C1 = 40 pF
VCC1 and VCC2 = 5 V, R1 = 143 W, C1 = 10 pF
VCC1 and VCC2 = 3.3 V, R1 = 143 W, C1 = 10 pF
80
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
SLLS
SLLS
Figure 6-18. tPLH2-1 Propagation Delay vs Free-Air
Temperature
Figure 6-17. tPLH2-1 Propagation Delay vs Free-Air
Temperature
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
VCC1 and VCC2 = 5 V, R1 = 143 W, C1 = 10 pF
VCC1 and VCC2 = 3.3 V, R1 = 143 W, C1 = 10 pF
VCC1 and VCC2 = 5 V, R1 = 2.2 kW, C1 = 40 pF
VCC1 and VCC2 = 3.3 V, R1 = 2.2 kW, C1 = 40 pF
10
0
10
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (èC)
SLLS
SLLS
Figure 6-19. tPHL2-1 Propagation Delay vs Free-Air
Temperature
Figure 6-20. tPHL2-1 Propagation Delay vs Free-Air
Temperature
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7 Parameter Measurement Information
7.1 Parameter Measurement Information
œ
+
œ
+
VCC2
VCC1
R1
R1
R2
R2
SDA1
SCL1
SDA2
SCL2
ISO164x
C1
C1
C2
C2
Figure 7-1. Test Diagram
VCC2
VCC1
VCC1
R1
GND1
t
LOOP1
SDA1 or
SCL1
Output
0.3 VCC1
SDA1
SCL1 (ISO1640 only)
C1
0.4 V
GND1
Figure 7-2. tLoop1 Setup and Timing Diagram
VCCx
VCCy
2 kꢀ
2 kꢀ
Input
+
Output
œ
GNDx
GNDy
V
CMTI
Figure 7-3. Common-Mode Transient Immunity Test Circuit
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VCCx
VCCy
Side x, Side y VCCx,VCCy
Ry
3.3 V, 3.3 V 95.3 Ω
3.3 V, 3.3 V 953 Ω
1, 2
2, 1
VCCx
Ry
0 V
SDAx or
SCLx
+
Output
-
GNDx
GNDy
or
VCCx
VCCy
VCCy
Ry
SDAx or
SCLx
0 V
+
Output
GNDx
GNDy
VCCx or
VCCy
VCCx (UVLO+)
t
UVLO
0.9 V
Output
Figure 7-4. tUVLO Test Circuit and Timing Diagrams
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8 Detailed Description
8.1 Overview
The I2C bus consists of a two-wire communication bus that supports bidirectional data transfer between a master
device and several slave devices. The master, or processor, controls the bus, specifically the serial clock (SCL)
line. Data is transferred between the master and slave through a serial data (SDA) line. This data can be
transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1
Mbps), and high-speed mode (0 to 3.4 Mbps).
The I2C bus operates in bidirectional, half-duplex mode, using open collector outputs to allow for multiple
devices to share the bus. When a specific device is ready to communicate on the bus, it can take control pulling
the lines low accordingly in order to transmit data. A standard digital isolator or optocoupler is designed to
transfer data in a single direction. In order to support an I2C bus, external circuitry is required to separates the
bidirectional bus into two unidirectional signal paths. The ISO164x devices internally handle the separation and
partitioning of the transmit and receive signals, integrating the external circuitry needed and provide the open-
collector signals. They provide high electromagnetic immunity and low emissions at low power consumption.
Each isolation channel has a logic input and output buffer separated by TI's double capacitive silicon dioxide
(SiO2) insulation barrier. When used in conjunction with isolated power supplies, these devices block high
voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or
damaging sensitive circuitry.
8.2 Functional Block Diagrams
VCC1
VCC2
SDA2
SDA1
V
REF
SCL2
SCL1
GND1
GND2
V
REF
Figure 8-1. ISO1640 Block Diagram
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VCC2
VCC1
SDA1
SDA2
V
REF
SCL1
SCL2
GND1
GND2
Figure 8-2. ISO1641 Block Diagram
8.3 Feature Description
The device enables a complete isolated I2C interface to be implemented within a small form factor having the
features listed in Table 8-1.
Table 8-1. Features List
PART NUMBER
CHANNEL DIRECTION
RATED ISOLATION(1)
MAXIMUM FREQUENCY
5000 VRMS (16DW) 7071 VPK
(16DW) 3000 VRMS (8D) 4242
VPK (8D)
Bidirectional SCL
Bidirectional SDA
ISO1640
1.7 MHz
Unidirectional (SCL)
Bidirectional (SDA)
ISO1641
3000 VRMS (8D) 4242 VPK (8D)
(1) See for detailed Isolation specifications.
8.3.1 Hot Swap
The ISO164x includes Hot Swap circuitry on Side 2 of the isolator to prevent loading on the I2C bus lines while
VCC2 is either unpowered or in the process of being powered on. While VCC2 is below the UVLO threshold,
the ISO164x bus lines will not load the bus to avoid disrupting or corrupting an active I2C bus. If the isolator
is plugged into a live backplane using a staggered connector, where VCC2 and GND2 make connection first
followed by the bus lines, the SDA and SCL lines are pre-charged to VCC2 / 2 to minimize the current required
to charge the parasitic capacitance of the device. Once the device is fully powered on, the device bus pins
become active providing bidirectional, isolated, SCL and SDA lines.
8.3.2 Protection Features
Features are integrated in the ISO164x to help protect the device from high current events. Enhanced ESD
protection cells are designed on the I2C bus pins to support 10 kV HBM ESD on side 1 and 14 kV HBM ESD on
side 2. The I2C bus pins on side 2 are designed to withstand an unpowered IEC ESD strike of 8kV, improving
robustness and system reliability in hot swap applications. In addition to the improved ESD performance, a short
circuit protection circuit is included on side 2 to protect the bus pins (SDA2 and SCL2) against strong short
circuits of 5 ohms or less to VCC2.
Thermal shutdown is integrated in the ISO164x to protect the device from high current events. If the junction
temperature of the device exceeds the thermal shutdown threshold of 190C (typical), the device turns off,
disabling the I2C circuits and releasing the bus. The shutdown condition is cleared when the junction
temperature drops at least the thermal shutdown hysteresis temperature of 10C (typical) below the thermal
shutdown temperature of the device.
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8.3.3 GPIO Channels
TBD
8.4 Isolator Functional Principle
To isolate a bidirectional signal path (SDA or SCL), the ISO1640 internally splits a bidirectional line into two
unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output
is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1640 connects to a
low-capacitance I2C node (up to 80 pF), while side 2 is designed for connecting to a fully loaded I2C bus with up
to 400 pF of capacitance.
VCC1
VCC2
A
VC-out
RPU2
RPU1
B
C
SDA1
SDA2
ISO164x
40 mV
50 mV
Cnode
Cbus
VSDA1
D
VILT1
VIHT1
VOL1
GND1
GND2
VREF
Figure 8-3. SDA Channel Design and Voltage Levels at SDA1
At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up.
However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode
drop to approximately 0.65 V, and the input buffer (C) that consists of a comparator with defined hysteresis.
The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V
(maximum) driven directly by SDA1 and the buffered output low-level of B.
Figure 8-4 demonstrate the switching behavior of the I2C isolator, ISO164x, between a master node at SDA1
and a heavy loaded bus at SDA2.
VCC2
VCC2
VCC1
VCC1
VOL1
SDA1
50%
SDA2
VIHT1
30%
Receive
Delay
Receive
Delay
Transmit
Delay
Receive
Delay
VCC1
VCC2
VIHT2
VCC1
VCC2
Transmit
Delay
SDA2
50%
SDA1
30%
VOL1
Figure 8-4. SDA Channel Timing in Receive and Transmit Directions
8.4.1 Receive Direction (Left Diagram of Figure 8-4)
When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the
buffered output of VOL1 = 0.65 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum
input-low voltage of VIL = 0.9 V at 3 V supply levels.
When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed
by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the
time-constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before
SDA2 reaches VCC2 potential.
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8.4.2 Transmit Direction (Right Diagram of Figure 8-4)
When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns
low it also causes the output of buffer B to turn low but at a higher 0.65 V level. This level cannot be observed
immediately as it is overwritten by the lower low-level of the master.
However, when the master releases SDA1, the voltage potential increases and first must pass the upper input
threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered
output level of VOL1 = 0.65 V, maintained by the receive path. When comparator C turns high, SDA2 is released
after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases
SDA1 to move toward VCC1 potential.
8.5 Device Functional Modes
Table 8-2 lists the ISO164x functional modes.
Table 8-2. Function Table(1)
POWER STATE
INPUT
OUTPUT
VCC1 < 2.3 V or VCC2 < 1.7 V
X
L
Z
L
VCC1 > 2.9 V and VCC2 > 2.25
V
VCC1 > 2.9 V and VCC2 > 2.25
V
H
Z
VCC1 > 2.9 V and VCC2 > 2.25
V
Z(2)
Undetermined
(1) H = High Level; L = Low Level; Z = High Impedance or Float; X = Irrelevant
(2) Invalid input condition as an I2C system requires that a pullup resistor to VCC is connected.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 I2C Bus Overview
The inter-integrated circuit (I2C) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC
communication in half-duplex mode.
I2C uses open-drain technology, requiring two lines, serial data (SDA) and serial clock (SCL), to be connected
to VDD by resistors (see Figure 9-1). Pulling the line to ground is considered a logic zero while letting the line
float is a logic one. This logic is used as a channel access method. Transitions of logic states must occur while
the SCL pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply
voltages are 3.3 V and 5 V, although systems with higher or lower voltages are allowed.
V
DD
R
R
PU
R
R
R
R
PU
PU
R
R
PU
PU
PU
PU
PU
SDA
SCL
SDA
SDA
SCL
SDA
SDA
SCL
SCL
SCL
GND
GND
GND
GND
ꢀC
Master
ꢀC
Slave
ADC
Slave
DAC
Slave
Figure 9-1. I2C Bus
I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112
nodes can communicate on the same bus. In practice, however, the number of nodes is limited by the specified,
total bus capacitance of 400 pF, which also restricts communication distances to a few meters.
The specified signaling rates for the ISO164x devices are 100 kbps (standard mode), 400 kbps (fast mode), 1.7
Mbps (fast mode plus).
The bus has two roles for nodes: master and slave. A master node issues the clock and slave addresses,
and also initiates and ends data transactions. A slave node receives the clock and addresses and responds to
requests from the master. Figure 9-2 shows a typical data transfer between master and slave.
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7-bit
8-bit
8-bit
ACK /
NACK
R/W
ACK
ACK
SDA
ADDRESS
DATA
DATA
SCL
1 - 7
8
9
1 - 8
9
1 - 8
9
S
P
START
Condition
STOP
condition
Figure 9-2. Timing Diagram of a Complete Data Transfer
The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave
it wishes to communicate with. This is followed by a single read and write (R/W) bit, representing whether the
master wishes to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the
slave to acknowledge the receipt of data.
The slave responds with an acknowledge bit (ACK) by pulling the SDA pin low during the entire high time of the
9th clock pulse on the SCL signal, after which the master continues in either transmit or receive mode (according
to the R/W bit sent), while the slave continues in the complementary mode (receive or transmit, respectively).
The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by
a high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of
SDA while SCL is high.
If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the
master is in master-transmit mode and the slave is in slave-receive mode.
If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the
receipt of every byte but the last one (see Figure 9-3). In this situation, the master is in master-receive mode and
the slave is in slave-transmit mode.
The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for
further transfers.
A = acknowledge
S Slave Address W A
DATA
A
DATA
A P
A P
A = not acknowledge
S = Start
From Master to Slave
From Slave to Master
Master Transmitter writing to Slave Receiver
P = Stop
R = Read
S Slave Address R A
DATA
A
DATA
W = Write
Master Receiver reading from Slave Transmitter
Figure 9-3. Transmit or Receive Mode Changes During a Data Transfer
When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when
receiving acknowledgment from the slave.
When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending
a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a
transaction.
Note
The master ends a reading sequence by not acknowledging (NACK) the last byte received. This
procedure resets the slave state machine and allows the master to send the STOP command.
9.2 Typical Application
In Figure 9-4, the ultra low-power microcontroller, MSP430G2132, controls the I2C data traffic of configuration
data and conversion results for the analog inputs and outputs. Low-power data converters build the analog
interface to sensors and actuators. The ISO164x device provides the required isolation between different ground
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potentials of the system controller, remote sensor, and actuator circuitry to prevent ground loop currents that
otherwise may falsify the acquired data.
The entire circuit operates from a single 3.3-V supply. A low-power push-pull converter, SN6501, drives a
center-tapped transformer with an output that is rectified and linearly regulated to provide a stable 5-V supply for
the data converter.
V
S
0.1 μF
3.3V
2
MBR0520L
1:2.2
5V
ISO
0.1μF
3
1
1
3
5
2
Vcc
D2
IN
OUT
8
10 μF
LP2981-50
VDD
SN6501
10μF 0.1μF
9
10
1
4
SDA
AIN0
ON
GND
4 Analog
Inputs
D1
SCL
GND
4,5
ADS1115
GND RDY
1Ω
10μF
MBR0520L
ADDR
AIN3
7
3
2
5V
ISO
5V
ISO
-
ISO BARRIER
6
2
VIN
REF5040
GND
VOUT
5V
ISO
0.1μF
22 μF
1μF
4
0.1μF
0.1 μF
8
3
15
A2 VDD
SDA
4
12
0.1 μF
H
1.5 kΩ
1.5 kΩ
IOVDD VREF
1.5 kΩ
1.5 kΩ
1
11
10
9
1
2
DVcc
VOUT
A
SCL
LDAC
A1
VCC1
VCC2
4 Analog
Outputs
DAC8574
5
6
9
8
2
3
7
6
XOUT
SDA
SCL
SDA1
SCL1
SDA2
MSP430
G2132
DVss
ISO164x
14
VOUT
D
SCL2
GND2
5
XIN
8
VREF
L
A0 A3 GND
GND1
4
13 16
6
5
4
Figure 9-4. Isolated I2C Data Acquisition System
9.2.1 Design Requirements
The recommended power supply voltages must be from 3 V to 5.5 V for VCC1 and 2.25 V to 5.5 V for VCC2. A
recommended decoupling capacitor with a value of 0.1 µF is required between both the VCC1 and GND1 pins,
and the VCC2 and GND2 pins to support of power supply voltages transient and to ensure reliable operation at
all data rates.
9.2.2 Detailed Design Procedure
Although the ISO1640 features bidirectional data channels, the device performs optimally when side 1 (SDA1
and SCL1) is connected to a single controller or node of an I2C network while side 2 (SDA2 and SCL2) is
connected to the I2C bus.
The power-supply capacitor with a value of 0.1-µF must be placed as close to the power supply pins as possible.
The recommended placement of the capacitors must be 2-mm maximum from input and output power supply
pins (VCC1 and VCC2).
The maximum load permissible on the input lines, SDA1 and SCL1, is ≤ 80 pF and on the output lines, SDA2
and SCL2, is ≤ 400 pF.
The minimum pullup resistors on the input lines, SDA1 and SCL1 to VCC1 must be selected in such a way that
input current drawn is ≤ 3.5 mA. The minimum pullup resistors on the input lines, SDA2 and SCL2, to VCC2
must be selected in such a way that output current drawn is ≤ 50 mA. The maximum pullup resistors on the bus
lines (SDA1 and SCL1) to VCC1 and on bus lines (SDA2 and SCL2) to VCC2, depends on the load and rise
time requirements on the respective lines to comply with I2C protocols. For more information, see .
The output waveforms for SDA1 and SCL1 are captured on the oscilloscope focusing on the low VOL1 voltage
offset offered with the ISO164x. This voltage offset is due to the high output low level on side 1 designed to
prevent a latch-up state mentioned in Section 8.4.
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ISO1640
2 mm
maximum
2 mm
maximum
VCC1
VCC2
8
1
0.01 …F
0.01 …F
3.3 kꢀ
3.3 kꢀ
3.3 kꢀ
3.3 kꢀ
SDA2
SDA1
2
7
SCL1
SCL2
3
4
6
GND1
GND2
5
Side 1
Side 2
Figure 9-5. Typical ISO1640 Circuit Hookup
ISO1641
2 mm
maximum
2 mm
maximum
VCC1
VCC2
8
1
0.01 …F
0.01 …F
3.3 kꢀ
3.3 kꢀ
3.3 kꢀ
3.3 kꢀ
SDA2
SDA1
2
7
SCL1
SCL2
3
6
5
GND1
GND2
4
Side 1
Side 2
Figure 9-6. Typical ISO1641 Circuit Hookup
9.2.3 Application Curve
VOL1 = 650 mV
GND
Figure 9-7. Side 1: Low-to-High Transition
9.3 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
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device and high voltage is applied between the two sides; see Figure 9-8 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For basic insulation,
VDE standard requires the use of a TDDB projection line with failure rate of less than 1000 part per million
(ppm). For reinforced insulation, VDE standard requires the use of a TDDB projection line with failure rate of less
than 1 part per million (ppm).
Even though the expected minimum insulation lifetime is 20 years, at the specified working isolation voltage,
VDE basic and reinforced certifications require additional safety margin of 20% for working voltage. For basic
certification, device lifetime requires a safety margin of 30% translating to a minimum required insulation lifetime
of 26 years at a working voltage that is 20% higher than the specified value. For reinforced insulation, device
lifetime requires a safety margin of 87.5% translating to a minimum required insulation lifetime of 37.5 years at a
working voltage that is 20% higher than the specified value.
Insulation Lifetime Projection Data for ISO164x in 8-D Package and Insulation Lifetime Projection Data for
ISO164x in 16-DW Package show the intrinsic capability of the isolation barrier to withstand high voltage stress
over its lifetime. Based on the TDDB data, the intrinsic capability of the insulation is 450 VRMS with a lifetime
in excess of 100 years in the 8-D package and 1500 VRMS with a lifetime in excess of 135 years in the 16-DW
package. Other factors, such as package size, pollution degree, material group, etc. can further limit the working
voltage of the component. At the lower working voltages, the corresponding insulation lifetime is much longer
than 100 years in the 8-D package and 135 years in the 16-DW package.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 9-8. Test Setup for Insulation Lifetime Measurement
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1.E+11
1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
>>100Yrs
Operating Zone
TDDB Line (< 1000 ppm Fail Rate)
VDE Safety Margin Zone
20%
0
1000
2000
3000
4000
5000
6000
7000
8000
Applied Voltage (VRMS
)
TA upto 150 oC
Operating Life Time = >>100 Years
Stress Voltage Frequency = 60 Hz
Isolation Working Voltage = 450 VRMS
Figure 9-9. Insulation Lifetime Projection Data for ISO164x in 8-D Package
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Figure 9-10. Insulation Lifetime Projection Data for ISO164x in 16-DW Package
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, TI recommends connecting a 1-µF bypass
capacitor at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the
supply pins as possible. If only a single, primary-side power supply is available in an application, isolated power
can be generated for the secondary-side with the help of a transformer driver such as TI's SN6501 device. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 Transformer Driver for Isolated Power Supplies. (SLLSEA0).
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 11-1). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-
frequency signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide (SLLA284)
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
Figure 11-1. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
•
•
Texas Instruments, Isolation Glossary
Texas Instruments, What is EMC? 4 questions about EMI, radiated emissions, ESD and EFT in isolated
systems
•
•
•
•
Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, SN6505x Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, I2C Bus Pullup Resistor Calculation
Texas Instruments, ISO1640DEVM Evaluation Module Users Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1640BDR
ISO1641BDR
XISO1640DWR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
1640B
1641B
NIPDAU
Call TI
DW
16
2000
Non-RoHS &
Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO1640 :
Automotive : ISO1640-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1640BDR
ISO1641BDR
SOIC
SOIC
D
D
8
8
3000
3000
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO1640BDR
ISO1641BDR
SOIC
SOIC
D
D
8
8
3000
3000
853.0
853.0
449.0
449.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
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