ISO518P-U [TI]
SPECIALTY TELECOM CIRCUIT, PDSO24;
| 型号： | ISO518P-U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 电信 光电二极管 电信集成电路 |
| 文件： | 总6页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO518
®
ISO518
ISO518
For most current data sheet and other product
information, visit www.burr-brown.com
Bidirectional
ISOLATED DIGITAL COUPLERS
FEATURES
DESCRIPTION
● LOW POWER CONSUMPTION:
The ISO518 is an 8-channel, isolated, bidirectional
digital coupler based on the Burr-Brown capacitive
barrier technology.
< 12mW per Channel
● 1500Vrms ISOLATION:
100% Tested by Partial Discharge
The ISO518 is designed with input and output buffers
for ease of integration into a µP bus system. All data
pins are I/O under the control of the TX pins. Input
and output buffers are controlled by the latch enable
pins. This feature of the ISO518, which allows mul-
tiple access to a data bus, requires extra circuitry when
using an alternative solution.
● DOUBLE BUFFERED DESIGN FOR
EASY INTEGRATION INTO BUS-BASED
SYSTEMS
● TRI-STATE OUTPUTS
● 24-PIN PDIP OR GULL WING PACKAGES
● 2MWORDS/S TRANSFER RATE
The ISO518 will transfer an 8-bit word at rates up to
2Mwords/s without the skew problems associated in
implementing this function with optocouplers. The
ISO518 is available in 24-pin PDIP or 24-pin Gull
Wing packages. Both are specified for operation from
–40°C to +85°C.
APPLICATIONS
● PARALLEL ADCs/DACs
● DIGITAL INTERFACES
● DIGITAL TRANSMISSION
● GROUND-LOOP ISOLATION
L
A
T
L
A
T
S
H
I
S
H
I
L
A
T
L
A
T
DATA
I/O
DATA
I/O
C
H
C
H
F
T
F
T
C
H
C
H
LEA
LEB
TXB/RXB
TXA/RXA
ISO518 Functional Block Diagram
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
• Tel: (520) 746-1111
Twx: 910-952-1111
•
Internet: http://www.burr-brown.com/
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
•
©1998 Burr-Brown Corporation
PDS-1423B
Printed in U.S.A. June, 1999
SBOS081
SPECIFICATIONS
At TA = +25°C, and VS = +5V, unless otherwise noted.
ISO518P, P-U
TYP
PARAMETER
ISOLATION
CONDITIONS
MIN
MAX
UNITS
Rated Voltage, Continuous
Partial Discharge Voltage
Barrier Impedance
VISO
50Hz, 60Hz
1s, 5 x 5pC/cycle(1)
1500
2500
Vrms
Vrms
Ω/pF
µA
>1014 || 10
1
Leakage Current
240V, 60Hz
2500V, 50Hz
12
1
µA
Creepage Distance
PDIP = “P” and “U” Package
PDIP = “P” and “U” Package
5kV/µs Edge
11
mm
mm
µs
Internal Isolation Distance
Transient Recovery Time
0.1
DC CHARACTERISTICS
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
VIH
VIL
See Note 2
See Note 2
2
V
V
0.8
0.4
IL
5
5
nA
pF
V
CIN
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short-Circuit Current
IOH = 6mA
IOL = 6mA
IS, max
VS –1
V
30
mA
TIMING
LE Width (LOW)
LE Width (HIGH)
Data Set-Up to LEA/B
Data Hold from LEA/B
Propagation Delay
Data Output Delay
Output Rise and Fall Time
Output Enable
tWL
tWH
tSU
tH
100
15
0
ns
ns
LEA/B HIGH to LOW
LEA/B HIGH to LOW
ns
20
ns
tPD
tOD
tRF
tEN
tDIS
LEA/B LOW to Data Out
LEO HIGH to Data Out Channels
10% to 90% Load = 50pF
OE to Data Valid HIGH or LOW
OE to Data HI-Z
520
35
ns
ns
9
5
14
35
ns
ns
Output Disable
35
ns
Max Data Transfer Rate
Skew
2
Mw/s
ns
Between Any Two Channels
POWER
Supply Voltage
Supply Current
V
SA, VSB
Either Side
Transmit Side DC
4.5
5.5
10
15
12
20
V
ISA/B
5
7
mA
mA
mA
mA
Transmit Side DC Max Rate
Receive Side DC
Supply Current
ISB/A
8
Receive Side Max Rate
12
TEMPERATURE RANGE
Operating
–40
–40
+85
°C
°C
Storage
+125
Thermal Resistance, θJA
+75
°C/W
NOTES: (1) All devices receive a 1s test. Failure criterion is > 5pC pulses of ≥ 5pC per cycle. (2) Logic inputs are HCT-type and thresholds are a function of power supply
voltage with approximately 400mV hysteresis.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ISO518
2
PIN CONFIGURATION
FUNCTIONAL DESCRIPTION
NAME
FUNCTION
Top View
DIP
DA (0 - 7)
Data Bus A. The logic levels on these pins are transmitted
to, or received from the corresponding pins on data bus B.
DB (0 -7)
Data Bus B. The logic levels on these pins are transmitted
to, or received from the corresponding pins on data bus A.
VSA
TXA/RXA
DA0
1
2
3
4
5
6
7
8
9
24 GNDB
23 LEB
22 DB0
21 DB1
20 DB2
19 DB3
18 DB4
17 DB5
16 DB6
15 DB7
14 TXB/RXB
13 VSB
LEA(1)
LEB(1)
TX/RXA(2)
TX/RXB(2)
Latch Enable A. Latch enable signal for the A data buffer.
Latch Enable B. Latch enable signal for the B data buffer.
Transmit/Receive Control for Side A.
DA1
Transmit/Receive Control for Side B.
DA2
NOTES: (1) In transmit mode (TX/RX = 1), a logic 0 (LOW) will latch the input
buffer data into the input register and initialize the transmission. A logic 0
(LOW) will latch the internal buffer data into the output register and prevent
any further changes in the output data. A logic 1 (HIGH) will pass the internal
buffer data to the output register and permit each new set of data to appear
as soon as available after transmission. (2) A logic 1 (HIGH) will set that side
to transmit mode and the same side’s data bus to input mode. A logic 0 (LOW)
will set that side to receive mode and the same side’s data bus to output mode.
DA3
ISO518
DA4
DA5
DA6
DA7 10
LEA 11
ELECTROSTATIC
GNDA 12
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage: VSA ............................................................. –0.5V to +6V
VSB ............................................................. –0.5V to +6V
Maximum Input Current, Any Input .................................................. 20mA
Continuous Isolation Voltage ..................................................... 1500Vrms
Storage Temperature ...................................................... –40°C to +125°C
Lead Temperature (soldering, 10s) ................................................. 300°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER(1)
ISO518P
24-Pin Plastic DIP
167
ISO518P-U
24-Pin Gull Wing Surface Mount
167-4
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
ISO518
the input buffer without affecting the transmission. How-
ever, should LEA go LOW again before the barrier transmis-
sion is complete, the barrier transmission will terminate and
restart with the new data (see Figure 2). This will not affect
the output data which only changes at the end of a transmis-
sion or under control of LEB.
OPERATION
Data is transmitted across the barrier under the control of
LEA or LEB; the direction being decided by TXA/RXA and
TXB/RXB.
Assume side A is set to transmit and side B is set to receive.
With LEA LOW, no data is passed to the input buffer and no
barrier transmission takes place. When LEA is HIGH, the
input data is passed to the input buffer ready for transmission
across the barrier on the falling edge of LEA. On the falling
edge of LEA, the data is latched to prevent any subsequent
input data changes interfering with the single barrier trans-
mission. Should LEA go HIGH again before the transmis-
sion is complete, the data in the input pins will be loaded into
If LEB is HIGH, the output data will change at the end of
transmission. If LEB is LOW the output data will change
when LEB next goes HIGH. In both cases, all data bits will
change together, guaranteeing the specified skew perfor-
mance. It should also be noted that LEB may be used to
ignore transmitted data if required.
DATA BUS: A
LEA
n–1
DATA n
ACTIVE
DATA n+1
ACTIVE
BARRIER
LEB
DATA BUS: B
DATA n–1
DATA n
FIGURE 1. Data Transfer.
DATA BUS: A
LEA
n–1
DATA n+1
DATA n+2
ACTIVE
DATA n
BARRIER
LEB
ACTIVE
ACTIVE
DATA BUS: B
DATA n–1
DATA +n
FIGURE 2. Data Transfer—Restart.
®
ISO518
4
tWH
DATA BUS: A
LEA
n+1
DATA n–1
DATA n–2
DATA n
tWL
LEA/B
DATA IN
BARRIER
Transient
ACTIVE
ACTIVE
ACTIVE
DATA OUT
tPD
tH
DATA BUS: B
DATA n+1
Invalid
DATA n-1
tSU
FIGURE 3. Data Corruption.
FIGURE 4. Transmission Timing Diagram.
tOD
LE
DATA OUT
TX/RX
tEN
tDIS
FIGURE 5. Output Data Timing.
VSA
1
VSB
ISO518
13
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
3
4
22
21
20
19
18
17
16
15
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
D
A
T
A
D
A
T
A
L
A
T
L
A
T
L
A
T
S
H
I
S
H
I
L
A
T
5
6
µP
µP
7
C
H
C
H
C
H
F
T
F
T
C
H
B
U
S
B
U
S
8
9
10
I/O
I/O
11
23
A
A
D
D
R
E
S
S
GNDA
GNDB
D
D
R
E
S
S
LEI
LEB
11
2
23
14
TXA/RXA
GNDA
TXB/RXB
GNDB
12
24
FIGURE 6. Burr-Brown I/O System using ISO518.
®
5
ISO518
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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