ISO5500DWR [TI]
2.5 A Isolated IGBT, MOSFET Gate Driver; 2.5 A隔离式IGBT ， MOSFET栅极驱动器
| 型号： | ISO5500DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5 A Isolated IGBT, MOSFET Gate Driver |
| 文件： | 总40页 (文件大小：1308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO5500
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SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
2.5 A Isolated IGBT, MOSFET Gate Driver
Check for Samples: ISO5500
1
FEATURES
•
•
•
•
•
•
•
2.5 A Maximum Peak Output Current
Drives IGBTs up to IC = 150 A, VCE = 1200 V
Capacitive Isolated Fault Feedback
CMOS/TTL Compatible Inputs
•
•
•
•
•
•
•
Wide VCC1 Range: 3 V to 5.5 V
Wide VCC2 Range: 15 V to 30 V
Operating Temperature: –40°C to 125°C
Wide-body SO-16 Package
300 ns Maximum Propagation Delay
Soft IGBT Turn-off
±50 kV/us Transient Immunity Typical
6000 VPeak Isolation
Integrated Fail-safe IGBT Protection
Regulatory Approvals: UL1577 Approved;
CSA, DIN EN 60747-5-2, IEC 60950-1 and
61010-1 Pending
–
–
High VCE (DESAT) Detection
Under-Voltage Lockout (UVLO) Protection
with Hysteresis
APPLICATIONS
•
User Configurable Functions
•
Isolated IGBT and MOSFET Drives in
–
–
–
Inverting, Non-inverting Inputs
Auto-Reset
–
–
–
–
Motor Control
Motion Control
Auto-Shutdown
Industrial Inverters
Switched-Mode Power Supplies
DESCRIPTION
The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to IC = 150 A and
VCE = 1200 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO2),
isolation barrier. When used in conjunction with isolated power supplies, the device blocks high voltage, isolates
ground, and prevents noise currents from entering the local ground and interfering with or damaging sensitive
circuitry.
The device provides over-current protection (DESAT) to an IGBT or MOSFET while an Undervoltage Lockout
circuit (UVLO) monitors the output power supply to ensure sufficient gate drive voltage. If the output supply drops
below 12 V, the UVLO turns the power transistor off by driving the gate drive output to a logic low state.
For a DESAT fault, the ISO5500 initiates a soft shutdown procedure that slowly reduces the IGBT/MOSFET
current to zero while preventing large di/dt induced voltage spikes. A fault signal is then transmitted across the
isolation barrier, actively driving the open-drain FAULT output low and disabling the device inputs. The inputs are
blocked as long as the FAULT-pin is low. FAULT remains low until the inputs are configured for an output low
state, followed by a logic low input on the RESET pin.
The ISO5500 is available in a 16-pin SOIC package and is specified for operating temperatures from –40°C to
125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO5500
SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
VREG
ISO5500
V
CC1
-
V
CC2
UVLO
V
IN+
+
V
C
V
+
-
DESAT
IN-
Gate
Drive
DESAT
12.3V
DELAY
and
7.2V
Q1a
Q1b
Fault
Logic
Q4
V
OUT
FAULT
Q
S
R
V
E
RESET
GND1
Q3
Q2b
Q2a
V
V
EE-P
EE-L
2
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ISO5500
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SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
VIN+
VIN-
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VEE-L
DESAT
VCC2
VC
VCC1
GND1
RESET
FAULT
NC
VOUT
VEE-L
GND1
VEE-P
PIN FUNCTIONS
PIN
DESCRIPTION
NO.
1
NAME
VIN+
Non-inverting gate drive voltage control input
Inverting gate drive voltage control input
Positive input supply (3 V to 5.5 V)
Input ground
2
VIN–
3
VCC1
4,8
5
GND1
RESET
FAULT
NC
FAULT reset input
6
Open-drain output. Connect to 3.3k pull-up resistor
Not connected
7
9
VEE-P
Most negative output-supply potential of the power output. Connect externally to pin 10.
Most negative output-supply potential of the logic circuitry. Pin 10 and 15 are internally connected. Connect at least
pin 10 externally to pin 9. Pin 15 can be floating.
10, 15 VEE-L
11
12
13
14
16
VOUT
VC
Gate drive output voltage
Gate driver supply. Connect to VCC2
.
VCC2
DESAT
VE
Most positive output supply potential
Desaturation voltage input
Gate drive common. Connect to IGBT Emitter.
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ISO5500
SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
Supply voltage, VCC1
–0.5
–0.5
6
V
V
V
Total output supply voltage, VOUT(total)
Positive output supply Voltage, VOUT+
Negative output supply voltage, VOUT-
(VCC2 – VEE-P
)
35
35 –
(VCC2 – VE)
–0.5
(VE – VEE-P
)
(VE – VEE-P
)
–0.5
VE – 0.5
–0.5
VCC2
VCC2
6
V
DESAT
Voltage at
VIN+, VIN–, RESET
Vo(peak)
V
V
Peak gate drive output voltage
Collector voltage, VC
–0.5
VCC2
VCC2
±2.8
±20
±4
–0.5
V
(1)
Output current , IO
A
FAULT output current, IFL
mA
kV
kV
V
Human Body Model
Electrostatic
ESDA / JEDEC JS-001-2012
Discharge,
Charged Device Model JEDEC JESD22-C101E
All pins
±1.5
±200
170
150
ESD
Machine Model
JEDEC JESD22-A115-A
Maximum junction temperature, TJ
Maximum storage temperature, TSTG
°C
°C
-65
(1) Maximum pulse width = 10 μs, maximum duty cycle = 0.2%.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
3
TYP
MAX UNIT
VCC1
Supply voltage
5.5
30
V
V
V
VOUT(total) Total output supply voltage (VCC2 – VEE-P
)
15
30V –
VOUT+
Positive output supply voltage (VCC2 – VE)
15
(VE – VEE-P
)
VOUT–
VC
Negative output supply voltage (VE – VEE-P
)
0
15
V
V
Collector voltage
VEE-P + 8
VCC2
tui
Input pulse width
0.1
0.1
2
μs
μs
V
tuiR
RESET Input pulse width
VIH
High-level input voltage (VIN+, VIN–, RESET)
Low-level input voltage (VIN+, VIN–, RESET)
VCC
0.8
VIL
0
V
fINP
VSUP_SR
TJ
Input frequency
520(1)
kHz
(2)
Supply Slew Rate (VCC1 or VCC2 – VEE-P
)
75 V/ms
Junction temperature
–40
-40
150
125
°C
°C
TA
Ambient temperature
25
(1) If TA = 125°C, VCC1= 5.5 V, VCC2 = 30 V, RG = 10 Ω, CL = 1 nF
(2) If VCC1 skew is faster than 75 V/ms (especially for the falling edge) then VCC2 must be powered up after VCC1 and powered down before
VCC1 to avoid output glitches.
4
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SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS
All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – VE = 30 V, VE – VEE-P = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
5.5
5.7
8.4
9
MAX
8.5
8.7
12
UNIT
Quiescent
300 kHz
VI = VCC1 or 0 V, No load, See Figure 1,
Figure 2, Figure 28, and Figure 29
ICC1
ICC2
ICH
Supply current
mA
Quiescent
300 kHz
VI = VCC1 or 0 V, No load, See Figure 3
through Figure 5, Figure 30, and Figure 31
Supply current
mA
mA
14
IOUT = 0, See Figure 27 and Figure 30
IOUT = –650 μA, See Figure 27 and Figure 30
See Figure 27 and Figure 31
1.3
1.9
0.4
High-level collector current
Low-level collector current
ICL
IEH
IEL
IIH
mA
mA
mA
VE High-level supply current
VE Low-level supply current
High-level input leakage
Low-level input leakage
See Figure 6 and Figure 40
–0.5
–0.8
–0.3
See Figure 6 and Figure 41
–0.53
10
10
IN from 0 to VCC
μA
IIL
–10
–10
VFAULT = VCC1, no pull-up,
See Figure 33
IFH
High-level FAULT pin output current
μA
IFL
Low-level FAULT pin output current
Positive-going UVLO threshold voltage
Negative-going UVLO threshold voltage
VFAULT = 0.4 V, no pull-up, See Figure 34
5
12
12.3
11.1
1.2
mA
VIT+(UVLO)
VIT–(UVLO)
VHYS (UVLO)
11.6
13.5
12.4
See Figure 32
V
A
UVLO Hysteresis voltage (VIT+ – VIT–
)
0.7
–1
VOUT = VCC2 – 4 V(1), See Figure 7 and
Figure 35
VOUT = VCC2 – 15 V(2), See Figure 7 and
Figure 35
VOUT = VEE-P + 2.5 V(1), See Figure 8 and
Figure 36
VOUT = VEE-P + 15 V(2), See Figure 8 and
Figure 36
–1.6
IOH
High-level output current
–2.5
1
1.8
IOL
Low-level output current
Output-low fault current
High-level output voltage
Low-level output voltage
A
mA
V
2.5
VOUT – VEE-P = 14 V, See Figure 9 and
Figure 37
IOF
90
140
VC-0.8
VC-0.05
0.2
230
IOUT = –100 mA, See Figure 10, Figure 11
and Figure 38
VC-1.5
VC-0.15
VOH
IOUT = –650 μA, See Figure 10, Figure 11 and
Figure 38
IOUT = 100 mA, See Figure 12, Figure 13 and
Figure 39
VOL
0.5
V
VDESAT = 0 V to 6 V, See Figure 14 and
Figure 42
ICHG
Blanking capacitor charging current
Blanking capacitor discharge current
DESAT threshold voltage
–180
20
–270
45
–380
μA
mA
V
IDSCHG
VDSTH
VDESAT = 8 V, See Figure 42
(VCC2 – VE) > VTH-(UVLO), See Figure 15 and
Figure 42
6.7
7.2
7.7
VI = VCC1 or 0 V, VCM at 1500 V,
See Figure 43 though Figure 46
CMTI
Common mode transient immunity
25
50
kV/μS
(1) Maximum pulse width is 50 μs, maximum duty cycle is 0.5%
(2) Maximum pulse width is 10 μs, maximum duty cycle is 0.2%
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SWITCHING CHARACTERISTICS
All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – VE = 30 V, VE – VEE-P = 0 V (unless otherwise noted)
PARAMETER
Propagation Delay
TEST CONDITIONS
MIN
TYP
200
1.7
MAX UNIT
tPLH, tPHL
tsk-p
150
300
10
ns
ns
ns
ns
ns
ns
ns
μs
ns
RG = 10 Ω, CG = 10 nF,
50 % duty cycle, 10 kHz input,
VCC2 – VEE = 30 V,
VE – VEE = 0 V, See Figure 16
through Figure 19, Figure 26,
Figure 47, Figure 49, and
Figure 50
Pulse Skew |tPHL – tPLH
Part-to-part skew(1)
Part-to-part skew(2)
Output signal rise time
Output signal fall time
|
tsk-pp
45
tsk2-pp
–50
50
tr
55
10
tf
tDESAT (90%)
tDESAT (10%)
tDESAT (FAULT)
DESAT sense to 90% VOUT delay
DESAT sense to 10% VOUT delay
DESAT sense to FAULT low output delay
300
1.8
290
550
2.3
RG = 10 Ω, CG = 10 nF,
VCC2 – VEE-P = 30 V,
VE – VEE-P = 0 V, See Figure 20
through Figure 25, Figure 48 and
Figure 51
550
DESAT sense to DESAT low propagation
delay
tDESAT (LOW)
180
ns
tRESET (FAULT)
tUVLO (ON)
RESET to high-level FAULT signal delay
UVLO to VOUT high delay
3
8.2
4
13
μs
μs
μs
1ms ramp from 0 V to 30 V
1ms ramp from 30 V to 0 V
tUVLO (OFF)
UVLO to VOUT low delay
6
Failsafe output delay time from input power
loss
tFS
2.8
μs
(1) tsk-pp is the maximum difference in same edge propagation delay times (either VIN+ to VOUT or VIN– to VOUT) between two devices
operating at the same supply voltage, same temperature, and having identical packages and test circuits.
ì
ü
é
ù
tPHL-max
V
CC1,VCC2,TA - t
V
CC1,VCC2,TA
,
(
)
(
)
PHL-min
VCC1,VCC2,TA
PLH-min
ïë
í
û ï
ý
i.e. max
é
ù
tPLH-max
VCC1,VCC2,TA - t
ï
(
)
(
)û ï
ë
î
þ
(2) tsk2-pp is the propagation delay difference in high-to-low to low-to-high transition ( any of the combinations VIN+ to VOUT or VIN– to VOUT
between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits.
)
i.e.
min = tPHL-min
V
CC1,VCC2,TA - t
VCC1,VCC2,TA
(
)
CC1,VCC2,TA - t
(
)
)
PLH-max
max = tPHL-max
V
(
VCC1,VCC2,TA
(
)
PLH-min
6
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TYPICAL CHARACTERISTICS
VCC1 SUPPLY CURRENT vs. TEMPERATURE
VCC1 SUPPLY CURRENT vs. FREQUENCY
8
7
7
6
5
4
3
6
5
4
3
2
1
V
V
V
= 4.5 V
= 5 V
VCC1 = 3 V
CC1
CC1
CC1
2
1
V
V
= 3.3 V
V
V
= 3.3 V
CC1
CC1
CC1
= 5 V
= 5.5 V
= 3.6 V
CC1
0
-40 -20
0
20
40
60
80
100 120 140
0
50
100
150
200
250
300
Ambient Temperature (oC)
Input Frequency (KHz)
Figure 1.
Figure 2.
VCC2 SUPPLY CURRENT vs. TEMPERATURE
VCC2 SUPPLY CURRENT vs. FREQUENCY
12
11
12
No Load
11
10
9
10
9
8
7
8
6
5
V
V
V
= 15 V
= 20 V
= 30 V
V
V
V
= 15 V
= 20 V
= 30 V
CC2
CC2
CC2
CC2
CC2
CC2
7
6
4
-40 -20
0
20
40
60
80
100 120 140
0
50
100
150
200
250
300
Ambient Temperature (oC)
Input Frequency (KHz)
Figure 3.
Figure 4.
VCC2 SUPPLY CURRENT vs. LOAD CAPACITANCE
VE SUPPLY CURRENT vs. TEMPERATURE
70
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
R
f
= 10 W
G
= 20 kHz
60 INP
50
40
30
20
I
I
I
I
, V - V = 0 V
EE
EH
E
, V - V = 15 V
EE
EH
E
10
V
V
= 15 V
= 30 V
CC2
, V - V = 0 V
EE
EL
EL
E
CC2
, V - V = 15 V
EE
E
0
0
20
40
60
80
100
-40 -20
0
20
40
60
80
100 120 140
Ambient Temperature (oC)
Load Capacitance (nF)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT DRIVE CURRENT vs. TEMPERATURE
OUTPUT SINK CURRENT vs. TEMPERATURE
0
8
V
V
= 2.5 V
OUT
OUT
= 15 V
-0.5
-1
7
6
5
-1.5
-2
-2.5
-3
4
3
2
1
0
-3.5
-4
-4.5
-5
V
V
= V - 4 V
C
OUT
= V - 15 V
C
OUT
-40 -20
0
20
40
60
80
100 120 140
-40 -20
0
20
40
60
80
100 120 140
Ambient Temperature (oC)
Ambient Temperature (oC)
Figure 7.
Figure 8.
OUTPUT SINK CURRENT DURING A FAULT CONDITION
vs. OUTPUT VOLTAGE
HIGH OUTPUT VOLTAGE DROP vs. TEMPERATURE
0.1
160
150
-0.1
-0.3
140
130
-0.5
-0.7
-0.9
120
110
100
-1.1
T
T
T
= -40oC
= 25oC
= 125oC
A
A
A
I
I
= -650 mA
90
80
-1.3
-1.5
OUT
= -100 mA
OUT
0
5
10
15
20
25
30
-40 -20
0
20
40
60
80
100 120 140
Output Voltage (V)
Ambient Temperature (oC)
Figure 9.
Figure 10.
HIGH OUTPUT VOLTAGE vs. OUTPUT DRIVE CURRENT
LOW OUTPUT VOLTAGE vs. TEMPERATURE
30
0.35
0.3
T
T
T
= -40oC
= 25oC
= 125oC
A
A
A
I
= 100 mA
OUT
29.5
29
28.5
0.25
28
27.5
27
0.2
0.15
0.1
26.5
26
25.5
25
-40 -20
0
20
40
60
80
100 120 140
0
0.2
0.4
0.6
0.8
1
1.2
1.4 1.5
Ambient Temperature (oC)
Output Drive Current (A)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
BLANKING CAPACITANCE CHARGING CURRENT vs.
LOW OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
6
TEMPERATURE
-0.15
-0.17
-0.19
-0.21
-0.23
-0.25
-0.27
-0.29
-0.31
-0.33
-0.35
5
4
3
2
1
0
T
T
T
= -40oC
= 25oC
= 125oC
A
A
A
0
0.5
1
1.5
2
2.5
-40 -20
0
20
40
60
80
100 120 140
Output Sink Current (A)
Ambient Temperature (oC)
Figure 13.
Figure 14.
DESAT THRESHOLD vs. TEMPERATURE
PROPAGATION DELAY vs. TEMPERATURE
7.9
7.7
7.5
7.3
240
R
= 10 W,
G
L
C
= 10 nF
230
220
210
200
7.1
6.9
6.7
6.5
t
t
t
t
at V
at V
= 3.3 V
= 3.3 V
= 5 V
PLH
PHL
PLH
PHL
CC1
CC1
190
180
at V
at V
CC1
= 5 V
CC1
-40 -20
0
20
40
60
80
100 120 140
-40 -20
0
20
40
60
80
100 120 140
Ambient Temperature (oC)
Ambient Temperature (oC)
Figure 15.
Figure 16.
PROPAGATION DELAY vs. VCC1 SUPPLY VOLTAGE
225
PROPAGATION DELAY vs. VCC2 SUPPLY VOLTAGE
230
R
C
= 10 W,
R
C
= 10 W,
G
L
G
L
225
220
215
210
= 10 nF
= 10 nF
220
215
210
205
200
195
190
t
t
t
t
at V
at V
at V
at V
= 3.3 V
= 3.3 V
= 5 V
PLH
PHL
PLH
PHL
CC1
CC1
CC1
CC1
205
200
t
t
PLH
= 5 V
PHL
3
3.5
4
4.5
5
5.5
14
16
18
20
22
24
26
28
30
VCC1 Supply Voltage (V)
VCC2 Supply Voltage (V)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY vs. LOAD CAPACITANCE
1400
DESAT SENSE to 90% VOUT DELAY vs TEMPERATURE
450
R
= 10 W
R
C
= 10 W,
G
G
L
= 10 nF
1200
400
350
1000
800
300
250
200
150
600
400
t
t
t
t
at V
at V
at V
at V
= 3.3 V
= 3.3 V
= 5 V
PLH
PHL
PLH
PHL
CC1
CC1
CC1
CC1
V
V
= 15 V
= 30 V
200
0
CC2
= 5 V
CC2
0
10
20 30
40
50 60 70
80
90 100
-40 -20
0
20
40
60
80
100 120 140
Load Capacitance (nF)
Ambient Temperature (oC)
Figure 19.
Figure 20.
DESAT SENSE to 90% VOUT DELAY vs LOAD
CAPACITANCE
DESAT SENSE to 10% VOUT DELAY vs TEMPERATURE
2.5
1600
1400
R
= 10 W
R
C
= 10 W,
G
G
L
= 10 nF
2
1200
1000
800
1.5
1
600
400
200
0
0.5
V
V
= 15 V
= 30 V
V
V
= 15 V
= 30 V
CC2
CC2
CC2
CC2
0
0
10
20 30
40
50
60 70
80
90 100
-40 -20
0
20
40
60
80
100 120 140
Load Capacitance (nF)
Ambient Temperature (oC)
Figure 21.
Figure 22.
DESAT SENSE to 10% VOUT DELAY vs LOAD
CAPACITANCE
DESAT SENSE to FAULT LOW DELAY vs TEMPERATURE
450
18
15
14
12
10
8
R
= 10 W
G
400
350
300
250
200
6
4
2
V
V
= 15 V
= 30 V
V
V
= 15 V
= 30 V
CC2
CC2
CC2
CC2
0
150
-40 -20
0
10
20 30
40
50
60 70
80
90 100
0
20
40
60
80
100 120 140
Load Capacitance (nF)
Ambient Temperature (oC)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
RESET to FAULT DELAY vs TEMPERATURE
OUTPUT WAVEFORM
10
9.5
9
V
- V = 30 V
EE
CC2
R
C
= 0 W,
G
L
= 10 nF
8.5
8
7.5
7
VCC1 = 3 V
V
V
V
V
V
= 3.3 V
= 3.6 V
= 4.5 V
= 5 V
CC1
CC1
CC1
CC1
CC1
6.5
6
5.5
5
= 5.5 V
Time 125 ns / div
-40 -20
0
20
40
60
80
100 120 140
Ambient Temperature (oC)
Figure 25.
Figure 26.
VC SUPPLY CURRENT vs. TEMPERATURE
3
2.5
2
1.5
1
I
I
I
I
, I
= -500 mA
= -1 mA
= -1 mA
= -2 mA
CH OUT
, I
CH OUT
, I
CL OUT
0.5
0
, I
CL OUT
-40 -20
0
20
40
60
80
100 120 140
Ambient Temperature (oC)
Figure 27.
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PARAMETER MEASUREMENT INFORMATION
TEST CIRCUITS
SPACER
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
0.1
µF
5.5 V
5.5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
VC
VC
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
GND1
GND1
Figure 28. ICC1H Test Circuit
Figure 29. ICC1L Test Circuit
SPACER
SPACER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
1
2
3
4
5
6
7
8
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
15
14
13
12
11
10
9
5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
ICC2
IC
ICC2
IC
GND1
RESET
FAULT
NC
VC
VC
30 V
0.1
µ F
0.1
µF
30 V
VOUT
VEE-L
VOUT
VEE-L
VEE-P
IOUT
GND1
GND1
VEE-P
Figure 30. ICC2H, ICH Test Circuit
Figure 31. ICC2L, ICL Test Circuit
SPACER
SPACER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
0.1
µF
0.1
µF
5 V
5.5 V
VIN-
VIN-
V1
Sweep
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
0.1
µF
VC
VC
V2
0.1
µF
VOUT
5.5 V
0.1
µF
30 V
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
IFAULT
GND1
GND1
Figure 32. VIT(UVLO) Test Circuit
Figure 33. IFH Test Circuit
SPACER
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PARAMETER MEASUREMENT INFORMATION (continued)
SPACER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
0.1
µF
3 V
5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
VPULSE
VC
VC
0.1 4.7
µF µF
30 V
0.4 V
0.1
µF
30 V
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
IFAULT
IOUT
GND1
GND1
Figure 34. IFL Test Circuit
Figure 35. IOH Test Circuit
SPACER
SPACER
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
0.1
µF
VC
VC
0.1 4.7
µF µF
30 V
30 V
IOUT
VPULSE
IOUT
VOUT
VEE-L
VOUT
VEE-L
VEE-P
14 V
GND1
GND1
VEE-P
Figure 36. IOL Test Circuit
Figure 37. IOF Test Circuit
SPACER
SPACER
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
0.1
µF
2
3
4
5
6
7
8
5 V
5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
0.1
µF
0.1
µF
100
mA
VOUT
VC
VC
30 V
30 V
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
VOUT
IOUT
GND1
GND1
Figure 38. VOH Test Circuit
Figure 39. VOL Test Circuit
SPACER
SPACER
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PARAMETER MEASUREMENT INFORMATION (continued)
IE
IE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
0.1
µF
0.1
µF
0.1
µF
5 V
5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
V1
V1
0.1
µF
0.1
µF
VC
VC
V2
V2
0.1
µF
0.1
µF
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
GND1
GND1
Figure 40. IEH Test Circuit
Figure 41. IEL Test Circuit
SPACER
SPACER
1
16
15
14
13
12
11
10
9
1
16
15
14
13
12
11
10
9
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
SWEEP
0.1
µF
0.1
µF
2
3
4
5
6
7
8
2
3
4
5
6
7
8
0.1
µF
5 V
5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
V1
IDESAT
0.1
µF
GND1
RESET
FAULT
NC
3 k
VC
VC
V2
0.1
µF
0.1 4.7
µF
30 V
µF
SCOPE
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
10 W
100 pF
10
nF
GND1
GND1
VCM
Figure 42. ICHG, IDSCHG, VDSTH Test Circuit
Figure 43. CMTI VFH Test Circuit
SPACER
SPACER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
0.1
µF
5 V
5 V
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
3 k
3 k
SCOPE
VC
VC
0.1 4.7
µF µF
0.1 4.7
µF
30 V
30 V
µF
SCOPE
100 pF
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
100 pF
10 W
10 W
10
nF
10
nF
GND1
GND1
VCM
VCM
Figure 44. CMTI VFL Test Circuit
Figure 45. CMTI VOH Test Circuit
SPACER
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PARAMETER MEASUREMENT INFORMATION (continued)
SPACER
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN
VIN+
VE
VEE-L
DESAT
VCC2
VIN+
VE
VEE-L
DESAT
VCC2
0.1
µF
2
3
4
5
6
7
8
5 V
GND1
VIN-
VIN-
VCC1
VCC1
GND1
RESET
FAULT
NC
GND1
RESET
FAULT
NC
0.1
µF
VOUT
5 V
3 k
SCOPE
VC
0.1 4.7
µF µF
VC
V1
0.1 4.7
µF µF
30 V
3 k
VOUT
VEE-L
VEE-P
VOUT
VEE-L
VEE-P
10 W
10
100 pF
10 W
nF
10
nF
GND1
GND1
VCM
Figure 46. CMTI VOL Test Circuit
Figure 47. tPLH, tPHL, tr, tf Test Circuit
SPACER
1
2
3
4
5
6
7
8
16
VIN+
VE
100
pF
VIN
15
14
13
12
11
10
9
0.1
µF
VIN-
VEE-L
DESAT
VCC2
VCC1
GND1
0.1
V1
µF
DESAT
VOUT
0.1 4.7
µF µF
RESET
FAULT
NC
VC
V2
VOUT
VEE-L
VEE-P
5 V
3 k
10 W
10
0.1
µF
nF
GND1
Figure 48. tDESAT, tRESET Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
V
V
V
0V
IN-
IN-
50 %
50 %
50 %
50 %
V
V
IN+
CC1
IN+
t
t
f
t
t
f
r
r
90%
50%
10%
90%
50%
10%
V
V
OUT
OUT
t
t
t
t
PLH
PHL
PLH
PHL
Figure 49. VOUT Propagation Delay, Non-inverting
Configuration
Figure 50. VOUT Propagation Delay, Inverting
Configuration
t
DESAT (FAULT)
t
DESAT (10%)
t
DESAT (LOW)
7.2V
V
V
DESAT
OUT
50%
t
DESAT (90%)
90%
10%
FAULT
RESET
50 %
50 %
50%
t
RESET (FAULT)
Figure 51. DESAT, VOUT, FAULT, RESET Delays
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PARAMETER MEASUREMENT INFORMATION (continued)
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shortest terminal to terminal distance
through air
L(I01)
L(I02)
Minimum air gap (clearance(1)
Minimum external tracking (creepage(1)
Minimum internal gap (internal clearance)
)
8.3
mm
Shortest terminal to terminal distance
across the package surface
)
8.1
mm
Distance through the insulation
0.012
400
mm
V
CTI
RIO
CIO
Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1
Isolation resistance
Input to output, VIO = 500 V(2)
VIO = 0.4 sin (2πft), f = 1 MHz(2)
>1012
1.25
Ω
Barrier capacitance input-to-output
pF
VI = VCC/2 + 0.4 sin (2π ft), f = 2 MHz,
VCC = 5V
CI
Input capacitance to ground
2
pF
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.space
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the isolation
glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase their specification.
(2) All pins on each side of the barrier tied together creating a two-terminal device
INSULATION CHARACTERISTICS FOR DW-16 PACKAGE
Over recommended operating conditions (unless noted otherwise)
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
Maximum working insulation voltage per DIN
EN 60747-5-2
VIORM
1200/848
After Input/Output safety test subgroup 2/3,
VPR = 1.2 x VIORM, t = 10 sec,
Partial discharge < 5 pC
1440/1018
1920/1358
Method a, After environmental tests subgroup 1,
VPR = 1.6 × VIORM, t = 10 sec (qualification)
Partial discharge < 5pC
Input to output test voltage per DIN EN
60747-5-2
VPR
VPEAK
VRMS
/
Method b1, 100% Production test,
VPR = 1.875 × VIORM, t = 1 sec
Partial discharge < 5pC
2250/1591
6000/4243
VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec
(100% production)
VIOTM Transient overvoltage per DIN EN 60747-5-2
VTEST = VISO, t = 60 sec (qualification)
VTEST = 1.2 × VISO, t = 1 sec (100% production)
VIO = 500 V at TS = 150°C
6000/4243
7200/5092
> 109
VISO
RS
Isolation voltage per UL 1577
Insulation resistance
Pollution degree
Ω
2
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to DIN EN 60747-5-2 and Approved under CSA Component
Recognized under 1577 Component
Recognition Program
EN 61010-1
Acceptance Notice 5A
Basic Insulation
Maximum Transient Overvoltage, 6000 VPK
Maximum Working Voltage, 1200 VPK
Basic and Reinforced Insulation per CSA
60950-1-07 and IEC 60950-1 (2nd Ed)
(1)
Single Protection, 4243 VRMS
File Number: pending
File Number: pending
File Number: E181974
(1) Production tested ≥ 5092 VRMS for 1 second in accordance with UL 1577.
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IEC 60664-1 RATING TABLE
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic Isolation Group
Material Group
Rated Mains Voltage ≤ 300 VRMS
II
I-IV
I-III
I-II
Installation Classification
Rated Mains Voltage ≤ 600 VRMS
Rated Mains Voltage ≤ 848 VRMS
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
530
347
64
UNIT
mA
θJA = 76°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
θJA = 76°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
θJA = 76°C/W, VI = 30 V, TJ = 170°C, TA = 25°C
IS
Safety Limiting Current
Case Temperature
TS
150
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
600
500
VCC1 = 3.6V
400
300
VCC1 = 5.5V
200
VCC2 - VEE-P = 30 V
100
0
0
50
100
150
200
Case Temperature - oC
Figure 52. DW-16 θJC Thermal Derating Curve per IEC 60747-5.2
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THERMAL INFORMATION
ISO5500
UNITS
THERMAL METRIC(1)
DW (16) PIN
θJA
Junction-to-ambient thermal resistance
76
34
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
36
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8
ψJB
35
θJCbot
TSHDN+
TSHDN-
TSHDN-HYS
PD
n/a
185
173
12
°C
°C
Thermal Shutdown
Thermal Shutdown Hysteresis
°C
Power Dissipation See Equation 2 through Equation 6
592
mW
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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BEHAVIORAL MODEL
Figure 53 and Figure 54 show the detailed behavioral model of the ISO5500 for a non-inverting input
configuration and its corresponding timing diagram for normal operation, fault condition, and Reset.
+HV
ISO5500
DESAT 14
+
V
V
IN+
1
2
PWM
C
BLK
-
DIS
ISO
7.2V
270 μA
IN-
V
CC2
13
12
-
UVLO
μC
VREG
DELAY
+
12.3V
V
CC1
3
6
V
C
3.3V
to
5V
15V
Q1a
Q1b
V
OUT
11
16
FAULT
I/P
FAULT
Q
S
R
V
E
RESET
GND1
5
Q3
O/P
Q2b
Q2a
15V
4,8
V
EE-P
VREG
V
CC2
9
V
EE-L
10,15
-HV
Figure 53. ISO5500 Behavioral Model
Normal Operation
Fault Condition
Reset
Normal Operation
5
V
IN+
ISO
4
7.2V
V
V
DESAT
OUT
FAULT
DIS
3
2
1
FAULT
RESET
6
Figure 54. Complete Timing Diagram
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DEVICE INFORMATION
POWER SUPPLIES
VCC1 and GND1 are the power supply input and output for the input side of the ISO5500. The supply voltage at
VCC1 can range from 3 V up to 5.5 V with respect to GND1, thus supporting the direct interface to state-of-the-art
3.3 V low-power controllers as well as legacy 5 V controllers.
VCC2, VEE-P and VEE-L are the power supply input and supply returns for the output side of the ISO5500. VEE-P is
the supply return for the output driver and VEE-L is the return for the logic circuitry. With VEE-P as the main
reference potential, VEE-L should always be directly connected to VEE-P. The supply voltage at VCC2 can range
from 15 V up to 30 V with respect to VEE-P
.
A third voltage input, VE, serves as reference voltage input for the internal UVLO and DESAT comparators. VE
also represents the common return path for the gate voltage of the external power device. The ISO5500 is
designed for driving MOSFETs and IGBTs. Because MOSFETs do not require a negative gate-voltage, the
voltage potential at VE with respect to VEE-P can range from 0 V for MOSFETs and up to 15 V for IGBTs.
ISO5500
ISO5500
V
V
CC2
CC2
+15 V
15V
+15 V
V
V
V
V
C
CC1
C
CC1
15 V-30 V
3 V - 5.5 V
3 V - 5.5 V
Power Device
Common
Power Device
Common
V
V
E
E
0 V-15 V
0-(-15 V)
GND1
GND1
0 V-15 V
-15 V
V
V
EE-P
EE-P
V
V
EE-L
EE-L
Figure 55. Power Supply Configurations
The output supply configuration on the left uses symmetrical ±15 V supplies for VCC2 and VEE-P with respect to
VE. This configuration is mostly applied when deriving the output supply from the input supply via an isolated DC-
DC converter with symmetrical voltage outputs. The configuration on the right, having both supplies referenced to
VEE-P, is found in applications where the device output supply is derived from the high-voltage IGBT supplies.
CONTROL SIGNAL INPUTS
The two digital, TTL control inputs, VIN+ and VIN–, allow for inverting and non-inverting control of the gate driver
output. In the non-inverting configuration VIN+ receives the control input signal and VIN– is connected to GND1. In
the inverting configuration VIN– is the control input while VIN+ is connected to VCC1
.
ISO5500
ISO5500
VIN+
VIN-
VCC1
VCC1
VCC1
VIN+
VIN-
3 V - 5.5 V
PWM
3 V - 5.5 V
GND1
VIN+
VIN-
VIN+
VIN-
PWM
GND1
GND1
VOUT
VOUT
Figure 56. Non-inverting (left) and Inverting (right) Input Configurations
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OUTPUT STAGE
The output stage provides the actual IGBT gate drive by switching the output voltage pin, VOUT, between the
most positive potential, typically VCC2, and the most negative potential, VEE-P
.
V
CC2
ISO5500
V
C
V
IN+
15V
Q1a
Q1b
30V
On
Q3
V
OUT
V
OUT
Q1
Q2
Q1
Gate
Drive
Off
0V
Q2
V
GE
V
E
Q3
+15V
Slow
Off
Q2b
Q2a
15V
V
E
V
E
V
GE
V
EE-P
-15V
V
EE-L
Figure 57. Output Stage Design and Timing
This stage consists of an upper transistor pair (Q1a and Q1b) turning the IGBT on, and a lower transistor pair
(Q2a and Q2b) turning the IGBT off. Each transistor pair possesses a bipolar transistor for high current drive and
a MOSFET for close-to-rail switching capability.
An additional, weak MOSFET (Q3) is used to softly turn-off the IGBT in the event of a short circuit fault to
prevent large di/dt voltage transients which potentially could damage the output circuitry.
The output control signals, On, Off, and Slow-Off are provided by the gate-drive and fault-logic circuit which also
includes a break-before-make function to prevent both transistor pairs from conducting at the same time.
By introducing the reference potential for the IGBT emitter, VE, the final IGBT gate voltage, VGE, assumes
positive and negative values with respect to VE.
A positive VGE of typically 15 V is required to switch the IGBT well into saturation while assuring the survival of
short circuit currents of up to 5–10 times the rated collector current over a time span of up to 10 μs.
Negative values of VE, ranging from a required minimum of –5 V up to a recommended –15 V, are necessary to
keep the IGBT turned off and to prevent it from unintentional conducting due to noise transients, particularly
during short circuit faults. As previously mentioned, MOSFETs do not require a negative gate-voltage and thus
allow the VE-pin to be directly connected to VEE-P
.
The timing diagram in Figure 57 shows that during normal operation VOUT follows the switching sequence of VIN+
(here shown for the non-inverting input configuration), and only the Q1 and Q2 transistor pairs applying VCC2 and
VEE-P potential to the VOUT-pin respectively.
In the event of a short circuit fault, however, while the IGBT is actively driven, the Q1 pair is turned off and Q3
turns on to slowly reduce VOUT in a controlled manner down to a level of approximately 2 V above VEE-P. At this
voltage level, the strong Q2 pair then conducts holding VOUT at VEE-P potential.
UNDER VOLTAGE LOCKOUT (UVLO)
The Under Voltage Lockout feature prevents the application of insufficient gate voltage (VGE-ON) to the power
device by forcing VOUT low (VOUT = VEE-P) during power-up and whenever else VCC2 – VE drops below 12.3 V.
IGBTs and MOSFETs typically require gate voltages of VGE = 15 V to achieve their rated, low saturation voltage,
VCES. At gate voltages below 13 V typically, their VCE-ON increases drastically, especially at higher collector
currents. At even lower voltages, i.e. VGE < 10 V, an IGBT starts operating in the linear region and quickly
overheats. Figure 58 shows the principle operation of the UVLO feature.
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12.3V
2V
V
CC2
V
CC2
-
11.1V
UVLO
On
V
C
+
15V
V
IN+
12.3V
Q1a
Q1b
Gate
Drive
V
OUT
Failsafe
Low
V
GE
Q1
Q2
Q1 Q2
Q1
V
OUT
V
E
0V
Off
R
Q2
PD
V
E
Q2b
Q2a
15V
+15V
V
EE-P
V
E
ISO5500
V
GE
V
EE-L
-15V
Figure 58. Under Voltage Lockout (UVLO) Function
Because VCC2 with respect to VE represents the gate-on voltage, VGE-ON = VCC2 – VE, the UVLO comparator
compares VCC2 to a 12.3 V reference voltage that is also referenced to VE via the connection of the ISO5500 VE-
pin to the emitter potential of the power device.
The comparator hysteresis is 1.2 V typical and the typical values for the positive and negative going input
threshold voltages are VTH+ = 12.3 V and VTH– = 11.1 V.
The timing diagram shows that at VCC2 levels below 2 V VOUT is 0 V. Because none of the internal circuitry
operates at such low supply levels, an internal 100 kΩ pull-down resistor is used to pull VOUT down to VEE-P
potential. This initial weak clamping, known as failsafe-low output, strengthens with rising VCC2. Above 2 V the
Q2-pair starts conducting gradually until VCC2 reaches 12.3 V at which point the logic states of the control inputs
VIN+ and VIN– begin to determine the state of VOUT
.
Another UVLO event takes place should VCC2 drop slightly below 11 V while the IGBT is actively driven. At that
moment the UVLO comparator output causes the gate-drive logic to turn off Q1 and turn on Q2. Now VOUT is
clamped hard to VEE-P. This condition remains until VCC2 returns to above 12.3 V and normal operation
commences.
NOTE
An Under Voltage Lockout does not indicate a Fault condition.
DESATURATION FAULT DETECTION (DESAT)
The DESAT fault detection prevents IGBT destruction due to excessive collector currents during a short circuit
fault. Short circuits caused by user misconnect, bad wiring, or overload conditions induced by the load can cause
a rapid increase in IGBT current, leading to excessive power dissipation and heating. IGBTs become damaged
when the current load approaches the saturation current of the device and the collector-emitter voltage, VCE
,
rises above the saturation voltage level, VCE-sat. The drastically increased power dissipation overheats and
destroys the IGBT.
To prevent damage to IGBT applications, the implemented fault detection slowly reduces the overcurrent in a
controlled manner during the fault condition.
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V
CC2
V
C
15V
ISO5500
DESAT
V
IN+
+
DESAT
-
C
7.2V
BLK
On
V
Q4
DESAT
Gate
Drive
7.2V
Q1a
Q1b
V
OUT
V
CE
Dschg
Q4
V
OUT
V
E
Fault Off
Slow
Off
Q3
Q2b
Q2a
15V
Fault
V
EE-P
V
EE-L
Figure 59. DESAT Fault Detection and Protection
The DESAT fault detection involves a comparator that monitors the IGBT’s VCE and compares it to an internal 7.2
V reference. If VCE exceeds this reference voltage, the comparator causes the gate-drive and fault-logic to initiate
a fault shutdown sequence. This sequence starts with the immediate generation of a fault signal, which is
transmitted across the isolation barrier towards the Fault indicator circuit at the input side of the ISO5500.
At the same time the fault logic turns off the power-pair Q1 and turns on the small discharge MOSFETs, Q3 and
Q4. Q3 slowly discharges the IGBT gate voltage which causes the high short-circuit current through the IGBT to
gradually decrease, thereby preventing large di/dt induced voltage transients. Q4 discharges the blanking
capacitor. Once VOUT is sufficiently close to VEE-P potential (at approximately 2 V), the large Q2-pair turns on in
addition to Q3 to clamp the IGBT gate to VEE-P
.
NOTE
The DESAT detection circuit is only active when the IGBT is turned on. When the IGBT is
turned off, and its VCE is at maximum, the fault detection is simply disabled to prevent
false triggering of fault signals.
DESAT BLANKING TIME
The DESAT fault detection must remain disabled for a short time period following the turn-on of the IGBT to allow
its collector voltage to drop below the 7.2 V DESAT threshold. This time period, called the DESAT blanking time,
tBLK, is controlled by an internal charge current of ICHG = 270 μA, the 7.2 V DESAT threshold, VDSTH, and an
external blanking capacitor, CBLK
.
The nominal blanking time with a recommended capacitor value of CBLK = 100 pF is calculated with:
CBLK ´ VDSTH
100 pF ´ 7.2 V
tBLK
=
=
= 2.7 μs
ICHG
270 μA
(1)
The capacitor value can be scaled slightly to adjust the blanking time. However, because the blanking capacitor
and the DESAT diode capacitance build a voltage divider that attenuates large voltage transients at DESAT,
CBLK values smaller than 100 pF are not recommended. The nominal blanking time also represents the ISO5500
maximum response time to a DESAT fault condition.
If a short circuit condition exists prior to the turn-on of the IGBT, (causing the IGBT switching into a short) the soft
shutdown sequence begins after approximately 3 μs. However, if a short circuit condition occurs while the IGBT
is already on, the response time is significantly shorter due to the parasitic parallel capacitance of the DESAT
diode. The recommended value of 100 pF however, provides sufficient blanking and fault response times for
most applications.
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The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault
condition. The use of VIN+ as control input implies non-inverting input configuration.
During normal operation VDESAT will display a small sawtooth waveform every time VIN+ goes high. The ramp of
the sawtooth is caused by the internal current source charging the blanking capacitor. Once the IGBT collector
has sufficiently dropped below the capacitor voltage, the DESAT diode conducts and discharges CBLK through
the IGBT.
In the event of a short circuit fault; however, high IGBT collector voltage prevents the diode from conducting and
the voltage at the blanking capacitor continues to rise until it reaches the DESAT threshold. When the output of
the DESAT comparator goes high, the gate-drive and fault-logic circuit initiates the soft shutdown sequence and
also produces a Fault signal that is fed back to the input side of the ISO5500.
FAULT ALARM
The Fault alarm unit consists of three circuit elements, a RS flip-flop to store the fault signal received from the
gate-drive and fault-logic, an open-drain MOSFET output signaling the fault condition to the micro controller, and
a delay circuit blocking the control inputs after the soft shutdown sequence of the IGBT has been completed.
Figure 60 shows the ISO5500 in a non-inverting input configuration. Because the FAULT-pin is an open-drain
output, it requires a pull-up resistor, RPU, in the order of 3.3 kΩ to 10 kΩ. The internal signals DIS, ISO, and
FAULT represent the input-disable signal, the isolator output signal, and the fault feedback signal respectively.
V
CC1
“IGBT
On”
ISO5500
5
3.3V
V
IN+
V
V
IN+
IN-
PWM
ISO
FAULT
DIS
DIS
ISO
4
R
PU
µC
3
DELAY
2
1
FAULT
I/P
FAULT
Q
S
R
FAULT
RESET
RESET
GND1
O/P
6
Figure 60. Fault Alarm Circuitry and Timing Sequence
The timing diagram shows that the micro controller initiates an IGBT-on command by taking VIN+ high. After
propagating across the isolation barrier ISO goes high, activating the output stage.
1. Upon a short circuit condition the gate-drive and fault-logic feeds back a fault signal (FAULT = high) which
sets the RS-FF driving the FAULT output active-low.
2. After a delay of approximately 3 μs, the time required to shutdown the IGBT, DIS becomes high and blocks
the control inputs
3. This in turn drives ISO low
4. which, after propagating through the output fault-logic, drives FAULT low.
At this time both flip-flop inputs are low and the fault signal is stored.
5. Once the failure cause has been removed the micro controller must set the control inputs into an "Output-
low" state before applying the Reset pulse.
6. Taking the RESET-input low resets the flip-flop, which removes the fault signal from the controller by pulling
FAULT high and releases the control inputs by driving DIS low
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APPLICATION INFORMATION
TYPICAL APPLICATION
Figure 61 shows the typical application of a three-phase inverter using six ISO5500 isolated gate drivers. Three-
phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for high
power applications such as High-Voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5500
devices that are connected to one of the three load terminals. The operation of the three switches is coordinated
so that one switch operates at each 60 degree point of the fundamental output waveform, thus creating a six-
step line-to-line output waveform. In this type of applications carrier-based PWM techniques are applied to retain
waveform envelope and cancel harmonics.
ISOLATION BARRIER
ISO 5500
ISO 5500
1
2
3
PWM
4
ISO 5500
5
6
3-PHASE
INPUT
µC
M
ISO 5500
ISO 5500
ISO 5500
FAULT
Figure 61. Typical Motor Drive Application
RECOMMENDED ISO5500 APPLICATION CIRCUIT
The ISO5500 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open
drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 62 illustrates
a typical gate drive implementation using the ISO5500.
The four 0.1 μF supply bypass capacitors provide the large transient currents necessary during a switching
transition. Because of the transient nature of the charging currents, low current (20 mA) power supplies for VCC2
and VEE-P suffice. The 100 pF blanking capacitor disables DESAT detection during the off-to-on transition of the
power device. The DESAT diode and its 100 Ω series resistor are important external protection components for
the fault detection circuitry. The 10 Ω gate resistor limits the gate charge current and indirectly controls the IGBT
collector voltage rise and fall times. The open-drain fault output has a passive 3.3 kΩ pull-up resistor and a
330pF filtering capacitor. In this application, the IGBT gate driver will shut down when a fault is detected and will
not resume switching until the micro-controller applies a reset signal.
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ISO5500
VIN+
VE
VEE -L
100 0.1 0.1
pF μF μF
DS (opt.)
VIN-
DDESAT
100 Ω
DESAT
VCC1
-
0.1
μF
+
3.3V
μC
VF
3.3
kΩ
GND1
RESET
FAULT
NC
VCC2
VC
Q1
Q2
+
-
4.7
μF
15V
15V
VCE
Rg
VOUT
VEE -L
VEE-P
0.1
μF
3-PHASE
OUTPUT
330 pF
+
-
GND1
VCE
Figure 62. Recommended Application Circuit
FAULT PIN CIRCUITRY
The FAULT pin is an open-drain output requiring a 3.3 kΩ pull-up resistor to provide logic high when FAULT is
inactive.
Because fast common mode transients can alter the FAULT-pin voltage during high state, a 330 pF capacitor
connected between FAULT and GND1 is recommended to provide sufficient noise margin at the specified CMTI
of 50 kV/μs. The added capacitance does not increase the FAULT response time during a fault condition.
1
ISO5500
VIN+
2
VIN-
3
VCC1
0.1
5 V
µC
µF
4
GND1
RESET
FAULT
NC
3.3
kW
5
6
7
8
330 pF
GND1
Figure 63. FAULT Pin Circuitry for High CMTI
DRIVING THE CONTROL INPUTS
The amount of common-mode transient immunity (CMTI) is primarily determined by the capacitive coupling from
the high-voltage output circuit to the low-voltage input side of the ISO5500. For maximum CMTI performance, the
digital control inputs, VIN+ and VIN–, must be actively driven by standard CMOS or TTL, push-pull drive circuits.
This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the
ISO5500 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain
configurations using pull-up resistors, must be avoided.
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LOCAL SHUTDOWN AND RESET
In applications with local shutdown and reset, the FAULT output of each gate driver is polled separately, and the
individual reset lines are asserted low independently to reset the motor controller after a fault condition.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
ISO5500
ISO5500
VIN+
VIN+
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
µC
µC
RF
RF
GND1
GND1
Figure 64. Local Shutdown and Reset for Non-inverting (left) and Inverting Input Configuration (right)
GLOBAL-SHUTDOWN AND RESET
When configured for inverting operation, the ISO5500 can be configured to shutdown automatically in the event
of a fault condition by tying the FAULT output to VIN+. For high reliability drives, the open drain FAULT outputs of
multiple ISO5500 devices can be wired together forming a single, common fault bus for interfacing directly to the
micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FAULT
output disables all six gate drivers simultaneously; thereby, providing protection against further catastrophic
failures.
1
ISO5500
VIN+
2
VIN-
3
VCC1
µC
4
GND1
5
RESET
6
FAULT
7
NC
8
GND1
to other
RESETs
to other
FAULTs
Figure 65. Global Shutdown with Inverting Input Configuration
AUTO-RESET
Connecting RESET to the active control input (VIN+ for non-inverting, or VIN– for inverting operation) configures
the ISO5500 for automatic reset capability. In this case, the gate control signal at VIN is also applied to the
RESET input to reset the fault latch every switching cycle. During normal IGBT operation, asserting RESET low
has no effect on the output. For a fault condition, however, the gate driver remains in the latched fault state until
the gate control signal changes to the 'gate low' state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch will always be reset before VIN+ goes high
again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next
'on' cycle. When the ISO5500 is configured for Auto Reset, the specified minimum FAULT signal pulse width is
3 μs.
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1
2
3
4
5
6
7
8
1
ISO5500
ISO5500
VIN+
VIN+
2
VIN-
VIN-
3
VCC1
GND1
RESET
FAULT
NC
VCC1
µC
µC
4
GND1
5
RESET
6
FAULT
7
NC
8
GND1
GND1
Figure 66. Auto Reset for Non-inverting and Inverting Input Configuration
RESETTING FOLLOWING A FAULT CONDITION
To resume normal switching operation following a fault condition (FAULT output low), the gate control signal
must be driven into a 'gate low' state before asserting RESET low. This can be accomplished with a micro-
controller, or an additional logic gate that synchronizes the RESET signal with the appropriate input signal.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
ISO5500
ISO5500
VIN+
VIN+
VIN-
VIN-
VCC1
GND1
RESET
FAULT
NC
VCC1
GND1
RESET
FAULT
NC
µC
µC
GND1
GND1
Figure 67. Auto Reset with Prior Gate-low Assertion for Non-inverting and Inverting Input Configuration
DESAT PIN PROTECTION
Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes
of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial
current out of the device. To limit this current below damaging levels, a 100 Ω to 1 kΩ resistor is connected in
series with the DESAT diode. The added resistance neither alters the DESAT threshold nor the DESAT blanking
time.
Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of
the DESAT input to VE potential at low voltage levels.
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16
15
14
13
12
11
10
9
ISO5500
VE
+
100
pF
DS (opt.)
VFW
VEE-L
DESAT
VCC2
DDESAT
RS
-
-
15V
15V
VC
VFW-inst
Rg
+
VOUT
VEE-L
VEE-P
Figure 68. DESAT Pin Protection with Series Resistor and Optional Schottky Diode
DESAT DIODE AND DESAT THRESHOLD
The DESAT diode’s function is to conduct forward current, allowing sensing of the IGBT’s saturated collector-to-
emitter voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the
short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the
IGBT. This results in a charging current ICHARGE = CD-DESAT x dVCE/dt, charging the blanking capacitor.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are
recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector
voltage transients appear at DESAT attenuated by the ratio of 1+ CBLANK / CD-DESAT
.
Table 1 lists a number of fast-recovery diodes suitable for the use as DESAT diodes.
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the
voltage at the DESAT-pin, VF + VCE = VDESAT, the VCE level, which triggers a fault condition, can be modified by
adding multiple DESAT diodes in series: VCE-FAULT(TH) = 7.2 V – n x VF (where n is the number of DESAT
diodes).
When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be
chosen.
Table 1. Recommended DESAT Diodes
PART NUMBER
STTH112
MUR100E
MURS160T3
UF4007
MANUFACTURER
STM
trr (ns)
75
VRRM-max (V)
1200
PACKAGE
SMA, SMB, DO-41
59-04 (axial leaded)
Case 403A (SMD)
Motorola
Motorola
General Semi.
Philips
75
1000
75
600
75
1000
DO-204AL (axial leaded)
SOD64 (axial leaded)
SOD57 (axial leaded)
SOD87 (axial leaded)
BYM26E
75
1000
BYV26E
Philips
75
1000
BYV99
Philips
75
600
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DETERMINING THE MAXIMUM AVAILABLE, DYNAMIC OUTPUT POWER, POD-max
The ISO5500 total power consumption of PD = 592 mW consists of the total input power, PID, the total output
power, POD, and the output power under load, POL
:
PD = PID + POD + POL
(2)
(3)
(4)
(5)
With: PID = VCC1-max × ICC1-max = 5.5 V × 8.5 mA = 47 mW,
and: POD = (VCC2 – VEE-P) x ICC2-q = 30 V × 14 mA = 420 mW,
then: POL = PD – PID – POD = 592 mW – 47 mW – 420 mW = 125 mW.
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety
of parameters:
æ
ç
ö
÷
ron-max
+ RG
roff-max
POL-WC = 0.5 ´ fINP ´ QG
´
V
- VEE-P
´
+
(
)
CC2
r
roff-max + RG ø
è on-max
(6)
Where
fINP = signal frequency at the control input VIN(±)
QG = power device gate charge
VCC2 = positive output supply with respect to VE
VEE-P = negative output supply with respect to VE
ron-max = worst case output resistance in the on-state: 4Ω
roff-max = worst case output resistance in the off-state: 2.5Ω
RG = gate resistor
Once RG is determined, Equation 6 is to be used to verify whether POL-WC < POL. Figure 69 shows a simplified
output stage model for calculating POL-WC
.
ISO5500
VCC2
VC
15 V
r
r
on-max
RG
VOUT
QG
off-max
15 V
VEE-P
Figure 69. Simplified Output Model for Calculating POL-WC
Copyright © 2011–2012, Texas Instruments Incorporated
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ISO5500
SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
www.ti.com
DETERMINING GATE RESISTOR, RG
The value of the gate resistor determines the peak charge and discharge currents, ION-PK and IOFF-PK. Due to the
transient nature of these currents, their peak values only occur during the on-to-off and off-to-on transitions of the
gate voltage. In order to calculate RG for the maximum peak current, ron and roff must be assumed zero. The
resulting charge and discharge models are shown in Figure 70.
ISO5500
ISO5500
VCC2
VC
VCC2
VC
15 V
15 V
VCC2 - VEE-P
VCC2 - VEE-P
I
on
I
off
VOUT
VOUT
RG
RG
CG
CG
VE
VE
15 V
15 V
VEE-P
VEE-P
Figure 70. Simplified Gate Charge and Discharge Model
Off-to-On Transition
In the off-state, the upper plate of the gate capacitance, CG, assumes a steady-state potential of –VEE-P with
respect to VE. When turning on the power device, VCC2 is applied to VOUT and the voltage drop across RG results
in a peak charge current of ION-PK = (VCC2 – VEE-P)/RG. Solving for RG then provides the necessary resistor value
for a desired on-current via:
VCC2 - VEE-P
RG
=
ION-PK
(7)
On-to-Off Transition
When turning the power device off, the current and voltage relations are reversed but the equation for calculating
RG remains the same.
Once RG has been calculated, it is necessary to check whether the resulting, worst-case power consumption,
POD-WC, (derived in Equation 6) is below the calculated maximum, POL = 125 mW (calculated in Equation 5).
Example
The example below considers an IGBT drive with the following parameters:
ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE-P = –5 V
Applying Equation 7, the value of the gate resistor is calculated with
15V - ( - 5V)
RG
=
= 10 Ω
2A
(8)
Then, calculating the worst-case output power consumption as a function of RG, using Equation 6 yields
4 Ω
2.5 Ω
æ
ö
POL-WC = 0.5 ´20 kHz´650 nC´ 15 V - ( - 5V) ´
+
4 Ω + 10Ω 2.5 Ω + 10 Ω
= 63 mW
(
)
ç
è
÷
ø
(9)
=
Because POL-WC = 63 mW is well below the calculated maximum of POL = 125 mW, the resistor value of RG
10Ω is fully suitable for this application.
32
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Product Folder Link(s) :ISO5500
ISO5500
www.ti.com
SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
DETERMINING COLLECTOR RESISTOR, RC
Despite equal charge and discharge currents, many power devices possess longer turn-off propagation and fall
times than turn-on propagation and rise times. In order to compensate for the difference in switching times, it
might be necessary to significantly reduce the charge current, ION-PK, versus the discharge current, IOFF-PK
.
Reducing ION-PK is accomplished by inserting an external resistor, RC, between the VC- pin and the VCC2- pin of
the ISO5500.
ISO5500
ISO5500
VCC2
VC
VCC2
VC
RC
V
C
15 V
C
2
-
V
E
E
15 V
-
P
VCC2 - VEE-P
I
I
off-pk
on-pk
VOUT
VOUT
RG
RG
CG
CG
VE
VE
15 V
15 V
VEE-P
VEE-P
Figure 71. Reducing ION-PK by Inserting Resistor RC
Figure 71 (right) shows that during the on-transition, the (VCC2 – VEE-P) voltage drop occurs across the series
resistance of RC + RG, thus reducing the peak charge current to: ION-PK = (VCC2 – VEE-P) /(RC + RG). Solving for RC
provides:
VCC2 - VEE-P
RC
=
- RG
ION-PK
(10)
(11)
To stay below the maximum output power consumption, RG must be calculated first via:
VCC2 - VEE-P
RG
=
IOFF-PK
and the necessary comparison of POL-WC versus POL must be completed.
Once RG is determined, calculate RC for a desired on-current using Equation 10.
Another method is to insert Equation 11 into Equation 10 and arriving at:
æ
ç
è
ö
IOFF-PK
RC = RG
´
- 1
÷
ION-PK
ø
(12)
(13)
Example
Reducing the peak charge current from the previous example to ION-PK = 1.5 A, requires a RC value of:
2 A
æ
ç
è
ö
RC = 10 Ω ´
- 1 = 3.33 Ω
÷
1.5 A
ø
Copyright © 2011–2012, Texas Instruments Incorporated
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ISO5500
SLLSE64A –SEPTEMBER 2011–REVISED JULY 2012
www.ti.com
HIGHER OUTPUT CURRENT USING AN EXTERNAL CURRENT BUFFER
To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in
Figure 72) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10
pair for up to 15 A maximum.
16
ISO5500
VE
15
100 pF
VEE-L
14
DESAT
13
12
11
10
9
MJD44H11
or
D44VH10
VCC2
VC
15 V
4.5 W
10 W
VOUT
VEE-L
VEE-P
2.5 W
MJD45H11
or
D45VH10
15 V
Figure 72. Current Buffer for Increased Drive Current
REVISION HISTORY
Spacer
Changes from Original (September 2011) to Revision A
Page
•
Changed the device From: Product Preview To: Production ................................................................................................ 1
34
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Product Folder Link(s) :ISO5500
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ISO5500DW
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ISO5500DWR
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO5500DWR
SOIC
DW
16
2000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
ISO5500DWR
2000
Pack Materials-Page 2
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