ISO5851QDWRQ1 [TI]
具有有源保护功能的汽车类 5.7kVrms、2.5A/5A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125;型号: | ISO5851QDWRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有有源保护功能的汽车类 5.7kVrms、2.5A/5A 单通道隔离式栅极驱动器 | DW | 16 | -40 to 125 栅极驱动 双极性晶体管 光电二极管 接口集成电路 驱动器 |
文件: | 总40页 (文件大小:1133K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
ISO5851-Q1 具有有源安全特性的高 CMTI 2.5A/5A 隔离式 IGBT、
MOSFET 栅极
驱动器
1 特性
2 应用
1
•
适用于汽车电子 标准
•
隔离式绝缘栅双极型晶体管 (IGBT) 和金属氧化物
半导体场效应晶体管 (MOSFET) 驱动器:
•
具有符合 AEC-Q100 标准的下列结果:
–
–
–
–
–
混合动力汽车 (HEV) 和电动车 (EV) 电源模块
–
器件温度 1 级:-40°C 至 125°C 的环境运行温
度范围
工业电机控制驱动
工业电源
–
–
器件人体模型 (HBM) 分类等级 3A
器件充电器件模型 (CDM) 分类等级 C6
太阳能逆变器
感应加热
•
在 VCM = 1500V 时,共模瞬态抗扰度 (CMTI) 的最
小值为 100kV/μs
3 说明
•
•
2.5A 峰值拉电流和 5A 峰值灌电流
短暂传播延迟:76ns(典型值),
110ns(最大值)
ISO5851-Q1 是一款用于 IGBT 和 MOSFET 的 5.7
kVRMS 增强型隔离栅极驱动器,具有 2.5A 的拉电流能
力和 5A 的灌电流能力。输入端由 3V 至 5.5V 的单电
源供电运行。输出端允许的电源范围为 15V 至 30V。
两个互补 CMOS 输入控制栅极驱动器的输出状态。
76ns 的短暂传播时间保证了对于输出级的精确控制。
•
•
•
2A 有源米勒钳位
输出短路钳位
在检测到去饱和故障时通过 FLT 发出故障报警,并
通过 RST 复位
•
•
具有就绪 (RDY) 引脚指示的输入和输出欠压锁定
(UVLO)
内置的去饱和 (DESAT) 故障检测功能可识别 IGBT 何
时处于过载状态。当检测到 DESAT 时,栅极驱动器输
出会被拉低为 VEE2 电势,从而将 IGBT 立即关断。
有源输出下拉特性,在低电源或输入悬空的情况下
默认输出低电平
•
•
•
•
•
•
3V 至 5.5V 输入电源电压
当发生去饱和故障时,器件会通过隔离隔栅发送故障信
号,以将输入端的 FLT 输出拉为低电平并阻断隔离器
的输入。FLT 的输出状态将被锁存,可通过 RST 输入
上的低电平有效脉冲复位。
15V 至 30V 输出驱动器电源电压
互补金属氧化物半导体 (CMOS) 兼容输入
抑制短于 20ns 的输入脉冲和瞬态噪声
可承受的浪涌隔离电压达 12800VPK
”
器件信息(1)
安全及管理认证:
器件型号
封装
封装尺寸(标称值)
–
符合 DIN V VDE V 0884-10 (VDE V 0884-
10):2006-12 标准的 8000 VPK VIOTM 和 2121
VPK IORM 增强型隔离
ISO5851-Q1
SOIC (16)
10.30mm x 7.50mm
V
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。
–
–
–
符合 UL 1577 标准且长达 1 分钟的 5700 VRMS
隔离
功能方框图
VCC1
VCC2
CSA 组件验收通知 5A、IEC 60950-1 和 IEC
60601-1 终端设备标准
VCC1
UVLO1
UVLO2
500 µA
DESAT
GND2
INœ
符合 EN 61010-1 和 EN 60950-1 标准的 TUV
认证
Mute
9 V
IN+
–
–
GB4943.1-2011 CQC 认证
VCC1
VCC2
RDY
已通过 UL、VDE、CQC、TUV 认证并规划进
行 CSA 认证
Gate Drive
and
Encoder
Logic
Ready
OUT
VCC1
FLT
Decoder
Q
Q
S
2 V
Fault
CLAMP
VCC1
R
RST
GND1
VEE2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEQ1
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
9
Detailed Description ............................................ 19
9.1 Overview ................................................................. 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 21
应用.......................................................................... 1
说明.......................................................................... 1
修订历史................................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Function........................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Power Rating............................................................. 6
7.6 Insulation Characteristics.......................................... 6
7.7 Safety Limiting Values .............................................. 7
7.8 Safety-Related Certifications..................................... 7
7.9 Electrical Characteristics........................................... 8
7.10 Switching Characteristics........................................ 9
7.11 Safety and Insulation Characteristics Curves ....... 10
7.12 Typical Characteristics.......................................... 11
Parameter Measurement Information ................ 17
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Applications .............................................. 22
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 PCB Material......................................................... 31
12.3 Layout Example .................................................... 31
13 器件和文档支持 ..................................................... 32
13.1 文档支持................................................................ 32
13.2 接收文档更新通知 ................................................. 32
13.3 社区资源................................................................ 32
13.4 商标....................................................................... 32
13.5 静电放电警告......................................................... 32
13.6 Glossary................................................................ 32
14 机械、封装和可订购信息....................................... 33
8
4 修订历史
注:之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 9 月
*
最初发布版本
2
版权 © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
5 说明 (续)
如果在由双极输出电源供电的正常运行期间关断 IGBT,输出电压会被硬钳位为 VEE2。如果输出电源为单极,那么
可采用有源米勒钳位,这种钳位会在一条低阻抗路径上灌入米勒电流,从而防止 IGBT 在高电压瞬态条件下发生动
态导通。
当发生去饱和故障时,器件会通过隔离隔栅发送故障信号,以将输入端的 FLT 输出拉为低电平并阻断隔离器的输
入。FLT 的输出状态将被锁存,可通过 RST 输入上的低电平有效脉冲复位。
如果在由双极输出电源供电的正常运行期间关断 IGBT,输出电压会被硬钳位为 VEE2。如果输出电源为单极,那么
可采用有源米勒钳位,这种钳位会在一条低阻抗路径上灌入米勒电流,从而防止 IGBT 在高电压瞬态条件下发生动
态导通。
栅极驱动器是否准备就绪待运行由两个欠压锁定电路控制,这两个电路会监视输入端和输出端的电源。如果任意一
端电源不足,RDY 输出会变为低电平;否则,该输出为高电平。
ISO5851-Q1 采用 16 引脚小外形尺寸集成电路 (SOIC) 封装。此器件的额定工作环境温度范围为 -40°C 至 125°
C。
Copyright © 2016, Texas Instruments Incorporated
3
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
6 Pin Configuration and Function
DW Package
16-Pin SOIC
Top View
VEE2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
VCC1
DESAT
GND2
NC
RST
FLT
RDY
IN-
VCC2
OUT
CLAMP
VEE2
IN+
GND1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VEE2
DESAT
GND2
NC
NO.
1, 8
2
-
I
Output negative supply. Connect to GND2 for Unipolar supply application.
Desaturation voltage input
3
-
Gate drive common. Connect to IGBT emitter.
Not connected
4
-
VCC2
OUT
CLAMP
GND1
IN+
5
-
Most positive output supply potential.
Gate drive voltage output
6
O
O
-
7
Miller clamp output
9, 16
10
11
12
13
14
15
Input ground
I
Non-inverting gate drive voltage control input
Inverting gate drive voltage control input
Power-good output, active high when both supplies are good.
Fault output, low-active during DESAT condition
Reset input, apply a low pulse to reset fault latch.
Positive input supply (3 V to 5.5 V)
IN-
I
RDY
FLT
O
O
I
RST
VCC1
-
4
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted)
MIN
GND1 - 0.3
–0.3
MAX
UNIT
V
VCC1
Supply voltage input side
6
35
VCC2
Positive supply voltage output side
Negative supply voltage output side
Total supply output voltage
(VCC2 – GND2)
(VEE2 – GND2)
V
VEE2
–17.5
0.3
V
V(SUP2)
VOUT
I(OUTH)
(VCC2 - VEE2
)
–0.3
35
V
Gate driver output voltage
VEE2 - 0.3
VCC2 + 0.3
2.7
V
Gate driver high output current
Gate driver high output current
(max pulse width = 10 μs, max duty
cycle = 0.2%)
A
I(OUTL)
Gate driver low output current
5.5
A
V(LIP)
I(LOP)
Voltage at IN+, IN-,FLT, RDY, RST
Output current of FLT, RDY
GND1 - 0.3
VCC1 + 0.3
10
V
mA
V
V(DESAT) Voltage at DESAT
V(CLAMP) Clamp voltage
GND2 - 0.3
VEE2 - 0.3
–40
VCC2 + 0.3
VCC2 + 0.3
150
V
TJ
Junction temperature
Storage temperature
°C
°C
TSTG
–65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
7.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC1
VCC2
VEE2
V(SUP2)
VIH
Supply voltage input side
3
5.5
V
V
Positive supply voltage output side (VCC2 – GND2)
Negative supply voltage output side (VEE2 – GND2)
15
30
–15
0
30
V
Total supply voltage output side (VCC2 – VEE2
High-level input voltage (IN+, IN-, RST)
Low-level input voltage (IN+, IN-, RST)
)
15
V
0.7 x VCC1
VCC1
V
VIL
0
40
0.3 x VCC1
V
tUI
Pulse width at IN+, IN- for full output (CLOAD = 1nF)
Pulse width at RST for resetting fault latch
Ambient temperature
ns
ns
°C
tRST
TA
800
-40
25
125
7.4 Thermal Information
DW (SOIC)
16 PINS
99.6
THERMAL METRIC(1)
UNIT
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
θJCtop
θJB
48.5
Junction-to-board thermal resistance
56.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.2
ψJB
56.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016, Texas Instruments Incorporated
5
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
7.5 Power Rating
VALUE
1255
175
UNIT
PD
Maximum power dissipation(1)
PID
POD
Maximum input power dissipation
Maximum output power dissipation
mW
1080
(1) Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of
251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design,
while ensuring that Junction temperature does not exceed 150°C.
7.6 Insulation Characteristics
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
8
mm
Shortest terminal-to-terminal distance across the package
surface
External creepage(1)
8
mm
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
21
>600
I
μm
V
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage category per IEC 60664-1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
2121
1500
2121
8000
VPK
VRMS
VDC
AC voltage. Time dependent dielectric breakdown (TDDB)
Test, see Figure 1
VIOWM
Maximum isolation working voltage
DC voltage
VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100%
production)
VIOTM
VIOSM
Maximum Transient isolation voltage
Maximum surge isolation voltage(3)
VPK
Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 x VIOSM = 12800 VPK (qualification)
8000
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.2 × VIORM = 2545 VPK
,
tm = 10 s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
≤5
≤5
qpd
Apparent charge(4)
Vpd(m) = 1.6 × VIORM = 3394 VPK
,
pC
tm = 10 s
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.875× VIORM = 3977 VPK
,
tm = 10 s
> 109
>1012
>1011
1
VIO = 500 V at TS
Ω
Ω
RIO
CIO
Isolation resistance, input to output(5)
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 0.4 x sin (2πft), f = 1 MHz
Ω
Barrier capacitance, input to output(5)
Pollution degree
pF
2
UL 1577
VTEST = VISO, t = 60 sec (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100%
production)
VISO
Withstanding Isolation voltage
5700
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
6
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
7.7 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
349
UNIT
θJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
θJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
θJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C
θJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C
228
Safety input, output or supply
current
IS
mA
84
42
PS
TS
Safety input, output, or total power θJA = 99.6°C/W, TJ = 150°C, TA = 25°C
1255(1)
Maximum ambient safety
temperature
150
°C
(1) Input, output, or the sum of input and output power should not exceed this value
7.8 Safety-Related Certifications
VDE
CSA
UL
CQC
Certified according to GB
TUV
Plan to certify under CSA
Component Acceptance
Notice 5A, IEC 60950-1, and
IEC 60601-1
Certified according to UL
1577 Component Recognition 4943.1-2011
Program
Certified according to
EN 61010-1:2010 (3rd Ed)
and
Certified according to
DIN V VDE V 0884-10 (VDE
V 0884-10):2006-12 and DIN
EN 60950-1 (VDE 0805 Teil
1):2011-01
EN 60950-
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Isolation Rating of 5700 VRMS
;
5700 VRMS Reinforced
insulation per
EN 61010-1:2010 (3rd Ed) up
to working voltage of 600
VRMS
5700 VRMS Reinforced
insulation per
EN 60950-
Reinforced insulation per CSA
60950-1- 07+A1+A2 and IEC
60950-1 (2nd Ed.), 800 VRMS
max working voltage (pollution
degree 2, material group I) ;
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed.
3.1, 250 VRMS (354 VPK) max
working voltage
Reinforced Insulation
Maximum Transient isolation
Reinforced Insulation, Altitude
Single Protection, 5700 VRMS ≤ 5000m, Tropical climate,
voltage, 8000 VPK
Maximum surge isolation
voltage, 8000 VPK
;
(1)
400 VRMS maximum working
voltage
,
Maximum repetitive peak
isolation voltage, 2121 VPK
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to
working voltage of 800 VRMS
Certification completed
Certificate number: 40040142 Certification planned
Certification completed
File number: E181974
Certification completed
Certificate number:
CQC16001141761
Certification completed
Client ID number: 77311
(1) Production tested ≥6840 VRMS for 1 second in accordance with UL 1577.
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
Copyright © 2016, Texas Instruments Incorporated
7
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
7.9 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE SUPPLY
Positive-going UVLO1 threshold voltage
input side (VCC1 – GND1)
VIT+(UVLO1)
VIT-(UVLO1)
VHYS(UVLO1)
VIT+(UVLO2)
VIT-(UVLO2)
VHYS(UVLO2)
2.25
V
V
V
V
V
V
Negative-going UVLO1 threshold voltage
input side (VCC1 – GND1)
1.7
UVLO1 Hysteresis voltage (VIT+ – VIT–
input side
)
0.24
12
11
1
Positive-going UVLO2 threshold voltage
output side (VCC2 – GND2)
13
Negative-going UVLO2 threshold voltage
output side (VCC2 – GND2)
9.5
UVLO2 Hysteresis voltage (VIT+ – VIT–
output side
)
IQ1
Input supply quiescent current
Output supply quiescent current
2.8
3.6
4.5
6
mA
mA
IQ2
LOGIC I/O
Positive-going input threshold voltage (IN+,
IN-, RST)
VIT+(IN,RST)
VIT-(IN,RST)
0.7 x VCC1
V
V
Negative-going input threshold voltage
(IN+, IN-, RST)
0.3 x VCC1
VHYS(IN,RST)
Input hysteresis voltage (IN+, IN-, RST)
High-level input leakage at (IN+)
Low-level input leakage at (IN-, RST)
Pull-up current of FLT, RDY
0.15 x VCC1
100
V
IIH
IN+ = VCC1
µA
µA
µA
V
IIL
IN- = GND1, RST = GND1
V(RDY) = GND1, V(FLT) = GND1
I(FLT) = 5 mA
-100
IPU
VOL
100
Low-level output voltage at FLT, RDY
0.2
2
GATE DRIVER STAGE
V(OUTPD)
V(OUTH)
V(OUTL)
Active output pull-down voltage
IOUT = 200 mA, VCC2 = open
IOUT = –20 mA
V
V
High-level output voltage
Low-level output voltage
VCC2 - 0.5
VCC2 - 0.24
VEE2 + 13
IOUT = 20 mA
VEE2 + 50
mV
IN+ = high, IN- = low,
VOUT = VCC2 - 15 V
I(OUTH)
I(OUTL)
High-level output peak current
Low-level output peak current
1.5
3.4
2.5
5
A
A
IN+ = low, IN- = high,
VOUT = VEE2 + 15 V
ACTIVE MILLER CLAMP
V(CLP) Low-level clamp voltage
I(CLP)
I(CLP) = 20 mA
VEE2 + 0.015
VEE2 + 0.08
2.5
V
A
V
Low-level clamp current
Clamp threshold voltage
V(CLAMP) = VEE2 + 2.5 V
1.6
1.6
2.5
2.1
V(CLTH)
SHORT CIRCUIT CLAMPING
Clamping voltage
V(CLP_OUT)
IN+ = high, IN- = low, tCLP = 10 µs,
I(OUTH) = 500 mA
0.8
1.3
V
(VOUT - VCC2
)
Clamping voltage
(VCLP - VCC2
IN+ = high, IN- = low, tCLP = 10 µs,
I(CLP) = 500 mA
V(CLP_CLAMP)
1.3
0.7
V
V
)
V(CLP_CLAMP)
Clamping voltage at CLAMP
IN+ = High, IN- = Low, I(CLP) = 20 mA
1.1
DESAT PROTECTION
I(CHG)
Blanking capacitor charge current
V(DESAT) - GND2 = 2 V
V(DESAT) - GND2 = 6 V
0.42
9
0.5
14
0.58
mA
mA
I(DCHG)
Blanking capacitor discharge current
DESAT threshold voltage with respect to
GND2
V(DSTH)
V(DSL)
8.3
0.4
9
9.5
1
V
V
DESAT voltage with respect to GND2,
when OUT is driven low
8
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
7.10 Switching Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER
Output signal rise time
Output signal fall time
Propagation Delay
TEST CONDITIONS
MIN
12
TYP
20
MAX UNIT
tr
35
37
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tf
12
20
tPLH, tPHL
tsk-p
76
110
20
CLOAD = 1 nF, see Figure 38,
Figure 39, and Figure 40
Pulse Skew |tPHL – tPLH
|
tsk-pp
Part-to-part skew
30(1)
tGF
Glitch filter on IN+, IN-, RST
DESAT sense to 10% OUT delay
DESAT glitch filter delay
20
30
415
40
tDESAT (10%)
tDESAT (GF)
tDESAT (FLT)
tLEB
300
500
330
DESAT sense to FLT-low delay
Leading edge blanking time
Glitch filter on RST for resetting FLT
see Figure 40
2000
400
2420
500
see Figure 38 and Figure 39
330
300
tGF(RSTFLT)
800
VI = VCC1 /2 + 0.4 x sin (2πft), f = 1
MHz, VCC1 = 5 V
CI
Input capacitance(2)
2
pF
CMTI
Common-mode transient immunity
VCM = 1500 V, see Figure 41
100
120
kV/μs
(1) Measured at same supply voltage and temperature condition
(2) Measured from input pin to ground.
Copyright © 2016, Texas Instruments Incorporated
9
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
7.11 Safety and Insulation Characteristics Curves
1.E+11
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
1.E+2
1.E+1
87.5%
20%
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS
)
TA upto 150°C
Stress-voltage frequency = 60 Hz
Figure 1. Reinforced High-Voltage Capacitor Life Time Projection
400
350
300
250
200
150
100
50
1400
VCC1 = 3.6 V
VCC1 = 5.5 V
VCC2 = 15 V
VCC2 = 30 V
Power
1200
1000
800
600
400
200
0
0
0
50
100
150
200
0
50
100
150
200
Ambient Temperature (èC)
Ambient Temperature (èC)
Figure 2. Thermal Derating Curve for Safety Limiting
Current per VDE
Figure 3. Thermal Derating Curve for Safety Limiting Power
per VDE
10
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
7.12 Typical Characteristics
0.5
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
VCC2 - VOUT = 2.5 V
VCC2 - VOUT = 5 V
VCC2 - VOUT = 10 V
VCC2 - VOUT = 15 V
VCC2 - VOUT = 20 V
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
VOUT - VEE2 = 2.5 V
VOUT - VEE2 = 5 V
VOUT - VEE2 = 10 V
VOUT - VEE2 = 15 V
VOUT - VEE2 = 20 V
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D001
D002
VCC2 = 30 V
VCC2 = 30 V
Figure 4. Output High Drive Current vs Temperature
Figure 5. Output Low Drive Current vs Temperature
7
6
5
4
3
2
1
0
0.0
TA = -40èC
TA = 25èC
TA = 125èC
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
TA = -40èC
TA = 25èC
TA = 125èC
0
5
10
15
20
25
30
0
5
10
15
20
25
30
(VCC2 - VOUT) Voltage (V)
(VOUT - VEE2) Voltage (V)
D003
D004
Figure 6. Output High Drive Current vs Output Voltage
Figure 7. Output Low Drive Current vs Output Voltage
9.5
9.4
9.3
9.2
9.1
9
15 V Unipolar
30 V Unipolar
8.9
8.8
8.7
8.6
8.5
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D005
Unipolar: VCC2 - VEE2 = VCC2 - GND2
Figure 8. DESAT Threshold Voltage vs Temperature
Copyright © 2016, Texas Instruments Incorporated
11
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
Typical Characteristics (continued)
Time - 50 ns/div
Time - 50 ns/div
CL = 1 nF
RG = 10 Ω
CL = 1 nF
RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 10. OUT Transient Waveform
Figure 9. OUT Transient Waveform
Time - 500 ns/div
Time - 500 ns/div
CL = 10 nF
RG = 0 Ω
CL = 10 nF
RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 11. OUT Transient Waveform
Figure 12. OUT Transient Waveform
Time - 2 ms/div
Time - 1 ms/div
CL = 100 nF
RG = 10 Ω
CL = 100 nF
RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 14. OUT Transient Waveform
Figure 13. OUT Transient Waveform
12
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
Typical Characteristics (continued)
3.5
3
CH1: OUT
2.5
2
CH2: DESAT
CH3: FLT
1.5
1
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
0.5
0
Time - 1 ms/div
CL = 100 nF
RG = 10 Ω
-40
-20
0
20
40
60
80
100 120 140
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Ambient Temperature (èC)
D006
IN+ = High
IN- = Low
Figure 15. OUT Transient Waveform DESAT and FLT
Figure 16. ICC1 Supply Current vs Temperature
2
1.8
1.6
1.4
1.2
1
5
4.5
4
3.5
3
2.5
2
0.8
0.6
0.4
0.2
0
1.5
1
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
0.5
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D007
D008
IN+ = Low
IN- = Low
Input Frequency = 1 kHz
Figure 17. ICC1 Supply Current vs Temperature
Figure 18. ICC2 Supply Current vs Temperature
3
2.5
2
5
4.5
4
VCC1 = 3 V
VCC1 = 5.5 V
3.5
3
1.5
1
2.5
2
1.5
1
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
0.5
0
0.5
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Input Frequency (kHz)
Input Frequency (kHz)
D009
D010
no CL
Figure 19. ICC1 Supply Current vs. Input Frequency
Figure 20. ICC2 Supply Current vs Input Frequency
Copyright © 2016, Texas Instruments Incorporated
13
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
Typical Characteristics (continued)
100
90
80
70
60
50
40
30
20
10
0
70
VCC2 = 15 V
VCC2 = 30 V
60
50
40
30
20
10
0
tpLH at VCC2 = 15 V
tpHL at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 30 V
0
10
20
30
40
50
60
70
80
90 100
-40
-20
0
20
40
60
80
100 120 140
Load Capacitance (nF)
Ambient Temperature (èC)
D025
D012
RG = 10 Ω, 20kHz
CL = 1nF
RG = 0 Ω
VCC1 = 5 V
Figure 21. ICC2 Supply Current vs Load Capacitance
Figure 22. VCC1 Propagation Delay vs Temperature
100
90
80
70
60
50
40
30
20
10
0
1200
1000
800
600
400
200
0
tpLH at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 15 V
tpHL at VCC2 = 30 V
tpLH at VCC1 = 3.3 V
tpHL at VCC1 = 3.3 V
tpLH at VCC1 = 5 V
tpHL at VCC1 = 5 V
-40
-20
0
20
40
60
80
100 120 140
0
10
20
30
40
50
60
70
80
90 100
Ambient Temperature (èC)
Load Capacitance (nF)
D013
D024
CL = 1nF
RG = 0 Ω
VCC2 = 15 V
RG = 10 Ω
VCC1 = 5 V
Figure 23. VCC2 Propagation Delay vs Temperature
Figure 24. Propagation Delay vs Load Capacitance
800
700
600
500
400
300
200
100
0
500
450
400
350
300
250
200
150
100
50
VCC2 = 15 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Load Capacitance (nF)
Load Capacitance (nF)
D022
D026
RG = 0 Ω
VCC1 = 5 V
RG = 0 Ω
VCC1 = 5 V
Figure 25. tr Rise Time vs Load Capacitance
Figure 26. tf Fall Time v. Load Capacitance
14
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
Typical Characteristics (continued)
4000
3500
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
VCC2 = 15 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
0
0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Load Capacitance (nF)
Load Capacitance (nF)
D023
D027
RG = 10 Ω
VCC1 = 5 V
RG = 10 Ω
VCC1 = 5 V
Figure 27. tr Rise Time vs Load Capacitance
Figure 28. tf Fall Time vs Load Capacitance
500
480
460
440
420
400
380
360
340
320
300
450
445
440
435
430
425
420
415
410
405
400
VCC2 = 15 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D015
D014
CL = 10 nF
Figure 30. DESAT Sense to VOUT 10% Delay vs Temperature
Figure 29. Leading Edge Blanking Time With Temperature
120
2.1
VCC2 = 15 V
VCC2 = 30 V
100
80
2.05
2
1.95
1.9
60
40
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
1.85
20
VCC1 = 5.5 V
1.8
-40
0
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D016
D017
CL = 1 nF
Figure 31. DESAT Sense to FLT Low Delay vs Temperature
Figure 32. Reset to Fault Delay Across Temperature
Copyright © 2016, Texas Instruments Incorporated
15
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
Typical Characteristics (continued)
5
2
1.8
1.6
1.4
1.2
1
V(CLAMP) = 2 V
V(CLAMP) = 4 V
V(CLAMP) = 6 V
4.5
4
3.5
3
2.5
2
0.8
0.6
0.4
0.2
0
1.5
1
IOUT = 100 mA
IOUT = 200 mA
0.5
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D018
D019
Figure 33. Miller Clamp Current vs Temperature
Figure 34. Active Pull Down Voltage vs Temperature
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.0
1200
1000
800
600
400
200
0
20mA at VCC2 = 15V
20mA at VCC2 = 30V
250mA at VCC2 = 15V
250mA at VCC2 = 30V
500mA at VCC2 = 15V
500mA at VCC2 = 30V
20mA at VCC2 = 15V
20mA at VCC2 = 30V
250mA at VCC2 = 15V
250mA at VCC2 = 30V
500mA at VCC2 = 15V
500mA at VCC2 = 30V
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (Cè)
Ambient Temperature (Cè)
D020
D021
Figure 36. VCLP_CLAMP - Short Circuit Clamp Voltage on OUT
Across Temperature
Figure 35. VCLP_CLAMP - Short Circuit Clamp Voltage on
Clamp Across Temperature
-400
-420
-440
-460
-480
-500
-520
-540
-560
-580
-600
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D011
VCC2 = 15 V
DESAT = 6 V
Figure 37. Blanking Capacitor Charging Current vs Temperature
16
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
8 Parameter Measurement Information
IN-
0V
V
CC1
50 %
50 %
IN+
0V
t
t
f
r
90%
50%
10%
OUT
tPLH
t
PHL
DESAT
t
LEB
Figure 38. OUT Propagation Delay, Non-Inverting Configuration
V
IN-
CC1
0V
50 %
50 %
V
IN+
CC1
t
t
f
r
90%
50%
10%
OUT
t
t
PLH
PHL
DESAT
t
LEB
Figure 39. OUT Propagation Delay, Inverting Configuration
Copyright © 2016, Texas Instruments Incorporated
17
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
Parameter Measurement Information (continued)
tDESAT (10%)
tDESAT (FLT)
9V
tRST
VDESAT
OUT
10%
FLT
50 %
RST
Figure 40. DESAT, OUT, FLT, RST Delay
ISO 5851 œ Q1
15
5
VCC2
VCC1
15 V
1 µF
0. 1 µF
3 V - 5.5 V
9, 16
3
GND 1
GND 2
VEE2
1, 8
6
14
10
RST
IN +
+
-
+
OUT
S1
:
Pass - Fail Criterion
OUT must remain stable
11
13
CL
1 nF
IN -
2
-
FLT
DESAT
12
7
4
CLAMP
NC
RDY
-
+
VCM
Copyright © 2016, Texas Instruments Incorporated
Figure 41. Common-Mode Transient Immunity Test Circuit
18
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
9 Detailed Description
9.1 Overview
The ISO5851-Q1 is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage
are separated by a capacitive, silicon dioxide (SiO2), isolation barrier.
The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET
(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to
supply 2.5-A pull-up and 5-A pull-down currents to drive the capacitive load of the external power transistors, as
well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The
capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and
receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5851-Q1 also contains
under voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pull-down
feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. TheISO5851-
Q1 also has an active Miller clamp function which can be used to prevent parasitic turn-on of the external power
transistor, due to Miller effect, for unipolar supply operation.
9.2 Functional Block Diagram
VCC2
VCC1
VCC1
UVLO1
UVLO2
500 µA
DESAT
GND2
INœ
Mute
9 V
IN+
VCC1
VCC2
RDY
Gate Drive
and
Encoder
Logic
Ready
OUT
VCC1
FLT
Decoder
Q
Q
S
2 V
Fault
CLAMP
VCC1
R
RST
GND1
VEE2
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
19
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
9.3 Feature Description
9.3.1 Supply and active Miller clamp
The ISO5851-Q1 supports both bipolar and unipolar power supply with active Miller clamp.
For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its
emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its
gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the
IGBT gate, but connecting CLAMP output of the gate driver to the IGBT gate is also not an issue. Typical values
of VCC2 and VEE2 for bipolar operation are 15-V and -8-V with respect to GND2.
For operation with unipolar supply, typically, VCC2 is connected to 15-V with respect to GND2, and VEE2 is
connected to GND2. In this use case, the IGBT can turn-on due to additional charge from IGBT Miller
capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the
CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.
Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage
transitions below 2-V the CLAMP current output is activated.
9.3.2 Active Output Pull-down
The Active output pull-down feature ensures that the IGBT gate OUT is clamped to VEE2 to ensure safe IGBT off-
state when the output side is not connected to the power supply.
9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply VCC1
drops below VIT-(UVLO1), irrespective of IN+, IN- and RST input till VCC1 goes above VIT+(UVLO1)
.
In similar manner, the IGBT is turned-off, if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN- and
RST input till VCC2 goes above VIT+(UVLO2)
.
Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection
feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise,
RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for
operation.
9.3.4 Fault (FLT) and Reset (RST)
During IGBT overload condition, to report desaturation error FLT goes low. If RST is held low for the specified
duration, FLT is cleared at rising edge of RST. RST has an internal filter to reject noise and glitches. By asserting
RST for at-least the specified minimum duration, device input logic can be enabled or disabled.
9.3.5 Short Circuit Clamp
Under short circuit events it is possible that currents are induced back into the gate-driver OUT and CLAMP pins
due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes on
OUT and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly higher
than the output side supply.
20
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
9.4 Device Functional Modes
Table 1 lists the functional modes for the ISO5851-Q1 device.
InISO5851-Q1 OUT to follow IN+ in normal functional mode, FLT needs to be in high state.
Table 1. Function Table(1)
VCC1
PU
PD
PU
PU
PU
PU
PU
VCC2
PD
IN+
X
IN-
X
RST
X
RDY
Low
Low
High
Low
High
High
High
OUT
Low
Low
Low
Low
Low
Low
High
PU
X
X
X
PU
X
X
Low
X
Open
PU
X
X
Low
X
X
X
PU
High
Low
X
PU
High
High
(1) PU: Power Up (VCC1 ≥ 2.25-V, VCC2 ≥ 13-V), PD: Power Down (VCC1 ≤ 1.7-V, VCC2 ≤ 9.5-V), X: Irrelevant
Copyright © 2016, Texas Instruments Incorporated
21
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO5851-Q1 is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is
intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In
these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at
the system level eventually may determine, for example, the speed, position, and torque of the motor or the
output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a micro
controller, and are at low voltage levels such as 3.3-V or 5-V. The gate controls required by the MOSFETs and
IGBTs, on the other hand, are in the range of 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output
Supply), and need high current capability to be able to drive the large capacitive loads offered by those power
transistors. Not only that, the gate drive needs to be applied with reference to the Emitter of the IGBT (Source for
MOSFET), and by construction, the Emitter node in a gate drive system may swing between 0 to the DC bus
voltage, that can be several 100s of volts in magnitude.
The ISO5851-Q1 is thus used to level shift the incoming 3.3-V and 5-V control signals from the microcontroller to
the 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output Supply) drive required by the power
transistors while ensuring high-voltage isolation between the driver side and the microcontroller side.
10.2 Typical Applications
Figure 42 shows the typical application of a three-phase inverter using six ISO5851-Q1 isolated gate drivers.
Three-phase inverters are used for variable-frequency drives to control the operating speed and torque of AC
motors and for high power applications such as High-Voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of six power switches, and each switch is driven by one ISO5851-Q1.
The switches are driven on and off at high switching frequency with specific patterns that to converter dc bus
voltage to three-phase AC voltages.
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Typical Motor Drive Application
22
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
Typical Applications (continued)
10.2.1 Design Requirements
Unlike optocoupler based gate drivers which need external current drivers and biasing circuitry to provide the
input control signals, the input control to the ISO5851-Q1 is CMOS and can be directly driven by the
microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a
pullup resistor on the common drain FLT output signal and RST input signal, and a high-voltage protection diode
between the IGBT collector and the DESAT input. Further details are explained in the subsequent sections.
Table 2 shows the allowed range for Input and Output supply voltage, and the typical current output available
from the gate-driver.
Table 2. Design Parameters
PARAMETER
Input supply voltage
VALUE
3-V to 5.5-V
15-V to 30-V
15-V to 30-V
0-V to 15-V
2.5-A
Unipolar output supply voltage (VCC2 - GND2 = VCC2 - VEE2
)
Bipolar output supply voltage (VCC2 - VEE2
)
Bipolar output supply voltage (GND2 - VEE2
Output current
)
10.2.2 Detailed Design Procedure
10.2.2.1 Recommended ISO5851-Q1 Application Circuit
The ISO5851-Q1 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open
drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 43 illustrates
a typical gate driver implementation with Unipolar Output Supply and Figure 44 illustrates a typical gate driver
implementation with Bipolar Output Supply using the ISO5851-Q1.
A 0.1-μF bypass capacitor, recommended at input supply pin VCC1 and 1-μF bypass capacitor, recommended at
output supply pin VCC2, provide the large transient currents necessary during a switching transition to ensure
reliable operation. The 220 pF blanking capacitor disables DESAT detection during the off-to-on transition of the
power device. The DESAT diode (DDST) and its 1-kΩ series resistor are external protection components. The RG
gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times.
The open-drain FLT output and RDY output has a passive 10-kΩ pull-up resistor. In this application, the IGBT
gate driver is disabled when a fault is detected and will not resume switching until the micro-controller applies a
reset signal.
10 R
10
R
15
9, 16
10
5
5
15
9, 16
10
VCC1
VCC1
VCC2
GND 2
VEE2
ISO 5851 œ Q1
VCC2
GND 2
VEE2
ISO 5851 œ Q1
1 µF
1 µF
3
V - 5.5 V
0.1 µF
0.1 µF
3 V - 5.5 V
15 V
15 V
15 V
3
3
GND 1
IN +
GND 1
IN +
1 µF
1
,
8
,
1
8
DDST
DDST
1 kΩ
1 kΩ
10 k
10 k
10 k
10 k
11
12
13
14
2
7
6
4
2
7
6
4
11
12
13
14
IN -
DESAT
CLAMP
OUT
IN -
DESAT
CLAMP
OUT
RDY
FLT
RST
RDY
RG
RG
FLT
NC
NC
RST
220
pf
220
pf
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Unipolar Output Supply
Figure 44. Bipolar Output Supply
Copyright © 2016, Texas Instruments Incorporated
23
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
10.2.2.2 FLT and RDY Pin Circuitry
There is 50k pull-up resistor internally on FLT and RDY pins. The FLT and RDY pin is an open-drain output. A
10-kΩ pull-up resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive,
as shown in Figure 45
Fast common mode transients can inject noise and glitches on FLT and RDY pins due to parasitic coupling. This
is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT
and RDY pins.
ISO 5851 œ Q1
10 R
15
VCC1
0. 1 µF
3V œ 5 V
9, 16
GND 1
10 k
10 k
12
13
RDY
FLT
µC
14
10
RST
IN +
11
IN -
Copyright © 2016, Texas Instruments Incorporated
Figure 45. FLT and RDY Pin Circuitry for High CMTI
10.2.2.3 Driving the Control Inputs
The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the
high-voltage output circuit to the low-voltage input side of the ISO5851-Q1. For maximum CMTI performance, the
digital control inputs, IN+ and IN-, must be actively driven by standard CMOS, push-pull drive circuits. This type
of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5851-Q1
output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain
configurations using pull-up resistors, must be avoided. There is a 20 ns glitch filter which can filter a glitch up to
20 ns on IN+ or IN-.
24
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
10.2.2.4 Local Shutdown and Reset
In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the
individual reset lines are asserted low independently to reset the motor controller after a fault condition.
10 R
ISO 5851 œ Q1
15
ISO 5851 œ Q1
10 R
VCC1
15
VCC1
0.1 µF
3 V - 5 V
0. 1 µF
3 V œ 5 V
9, 16
9, 16
GND 1
GND 1
10 k
10 k
10 k
10 k
12
13
12
13
RDY
FLT
RDY
FLT
µC
µC
14
10
14
10
RST
IN +
RST
IN +
11
IN -
11
IN -
Copyright © 2016, Texas Instruments Incorporated
Figure 46. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)
10.2.2.5 Global-Shutdown and Reset
When configured for inverting operation, the ISO5851-Q1 can be configured to shutdown automatically in the
event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of
multiple ISO5851-Q1 devices can be wired together forming a single, common fault bus for interfacing directly to
the micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FLT
output disables all six gate drivers simultaneously.
10 R
ISO 5851 - Q1
15
VCC1
0. 1 µF
3V œ 5V
9, 16
GND 1
10 k
10 k
12
13
RDY
FLT
µC
14
10
RST
IN +
11
IN -
to other
RSTs
to other
FLTs
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Global Shutdown with Inverting Input Configuration
Copyright © 2016, Texas Instruments Incorporated
25
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
10.2.2.6 Auto-Reset
In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching
cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault
state until the gate control signal changes to the 'gate low' state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch will always be reset before IN+ goes high
again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next
'on' cycle.
ISO 5851 œ Q1
ISO 5851 œ Q1
10 R
10 R
15
15
VCC1
VCC1
0. 1 µF
3 V - 5 V
0.1 µF
3 V - 5 V
9, 16
9, 16
GND 1
GND 1
10 k
10 k
10 k
10 k
12
13
12
13
RDY
FLT
RDY
FLT
µC
µC
14
10
14
10
RST
IN +
RST
IN +
11
11
IN -
IN -
Copyright © 2016, Texas Instruments Incorporated
Figure 48. Auto Reset for Non-inverting and Inverting Input Configuration
26
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
10.2.2.7 DESAT Pin Protection
Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes
of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial
current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in
series with the DESAT diode.
Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of
the DESAT input to GND2 potential at low voltage levels.
ISO 5851 -Q1
5
VCC2
1 µF
15 V
3
GND 2
1 µF
15 V
1, 8
VEE2
DDST
RS
2
DESAT
7
CLAMP
RG
6
OUT
NC
VFW-Inst
4
220 pF
VFW
Copyright © 2016, Texas Instruments Incorporated
Figure 49. DESAT Pin Protection with Series Resistor and Schottky Diode
Copyright © 2016, Texas Instruments Incorporated
27
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
10.2.2.8 DESAT Diode and DESAT Threshold
The DESAT diode’s function is to conduct forward current, allowing sensing of the IGBT’s saturated collector-to-
emitter voltage, V(CESAT), (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the
short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the
IGBT. This results in a charging current I(CHARGE) = C(D-DESAT) x dVCE/dt, charging the blanking capacitor. C(D-DESAT)
is the diode capacitance at DESAT.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are
recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector
voltage transients appear at DESAT attenuated by the ratio of 1+ C(BLANK) / C(D-DESAT)
.
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the
voltage at the DESAT-pin, VF + VCE = V(DESAT), the VCE level, which triggers a fault condition, can be modified by
adding multiple DESAT diodes in series: VCE-FAULT(TH) = 9 V – n x VF (where n is the number of DESAT diodes).
When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be
chosen.
10.2.2.9 Determining the Maximum Available, Dynamic Output Power, POD-max
The ISO5851-Q1 maximum allowed total power consumption of PD = 251 mW consists of the total input power,
PID, the total output power, POD, and the output power under load, POL
:
PD = PID + POD + POL
(1)
(2)
(3)
(4)
With:
PID = VCC1-max × ICC1-max = 5.5 V × 4.5 mA = 24.75 mW
and:
POD = (VCC2 – VEE2) x ICC2-max = (15 V – ( –8 V )) × 6 mA = 138 mW
then:
POL = PD – PID – POD = 251 mW – 24.75 mW – 138 mW = 88.25 mW
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety
of parameters:
æ
ç
è
ö
÷
ø
ron-max
roff-max
POL-WC = 0.5 ´ f
´ QG
´
V
- VEE2
´
+
(
)
INP
CC2
ron-max + RG
roff-max + RG
where
•
•
•
•
•
•
•
fINP = signal frequency at the control input IN+
QG = power device gate charge
VCC2 = positive output supply with respect to GND2
VEE2 = negative output supply with respect to GND2
ron-max = worst case output resistance in the on-state: 4Ω
roff-max = worst case output resistance in the off-state: 2.5Ω
RG = gate resistor
(5)
Once RG is determined, Equation 5 is to be used to verify whether POL-WC < POL. Figure 50 shows a simplified
output stage model for calculating POL-WC
.
28
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
ISO 5851 œ Q1
VCC2
15 V
ron-max
RG
OUT
QG
roff-max
8 V
VEE2
Copyright © 2016, Texas Instruments Incorporated
Figure 50. Simplified Output Model for Calculating POL-WC
10.2.2.10 Example
This examples considers an IGBT drive with the following parameters:
ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE2 = –8 V
(6)
Applying the value of the gate resistor RG = 10 Ω.
Then, calculating the worst-case output power consumption as a function of RG, using Equation 5 ron-max = worst
case output resistance in the on-state: 4 Ω, roff-max = worst case output resistance in the off-state: 2.5 Ω, RG
=
gate resistor yields
4 Ω
2.5 Ω
æ
ö
POL-WC = 0.5´20 kHz´650 nC´ 15 V -( -8 V) ´
+
4 Ω + 10 Ω 2.5 Ω + 10 Ω
= 72.61 mW
(
)
ç
è
÷
ø
(7)
Because POL-WC = 72.61 mW is below the calculated maximum of POL = 88.25 mW, the resistor value of RG = 10
Ω is suitable for this application.
Copyright © 2016, Texas Instruments Incorporated
29
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
10.2.2.11 Higher Output Current Using an External Current Buffer
To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in
Figure 51) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10
pair for up to 15 A maximum.
ISO 5851 - Q1
5
VCC2
1 µF
15 V
3
GND 2
1 µF
15 V
1, 8
VEE2
DDST
1 kΩ
10 Ω
2
7
6
4
DESAT
CLAMP
OUT
rG
NC
220
pf
Copyright © 2016, Texas Instruments Incorporated
Figure 51. Current Buffer for Increased Drive Current
10.2.3 Application Curve
CL = 1 nF
RG = 10 Ω
CL = 1 nF
RG = 10 Ω
GND2 - VEE2 = 8 V
VCC2 - VEE2 = VCC2 - GND2 = 20 V
VCC2 - GND2 = 15 V
(VCC2 - VEE2 = 23 V)
Figure 53. Normal Operation - Unipolar Supply
Figure 52. Normal Operation - Bipolar Supply
30
Copyright © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at
input supply pin VCC1 and 1-μF bypass capacitor is recommended at output supply pin VCC2. The capacitors
should be placed as close to the supply pins as possible. Recommended placement of capacitors needs to be
2-mm maximum from input and output power supply pin (VCC1 and VCC2).
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 54). Layer stacking should
be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and
low-frequency signal layer.
•
Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects between the gate driver and the microcontroller and
power transistors. Gate driver control input, Gate driver output OUT and DESAT should be routed in the top
layer.
•
•
Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for
the return current flow. On the driver side, use GND2 as the ground plane.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2. On the gate-driver VEE2 and VCC2 can be used as power planes. They can share
the same layer on the PCB as long as they are not connected together.
•
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,
routing etc. see Application Note SLLA284, Digital Isolator Design Guide.
12.2 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
12.3 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 54. Recommended Layer Stack
版权 © 2016, Texas Instruments Incorporated
31
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档ꢀ
相关文档如下:
•
•
•
《ISO5851 评估模块 (EVM) 用户指南》,SLLU218
《数字隔离器设计指南》,SLLA284
《隔离相关术语》,SLLA353
13.2 接收文档更新通知
要接收文档更新通知,请访问 www.ti.com.cn 您器件对应的产品文件夹。点击右上角的提醒我 (Alert me) 注册后,
即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档的修订历史记录。
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
版权 © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
33
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.38
0.25
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/A 08/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-013, variation AA.
www.ti.com
34
版权 © 2016, Texas Instruments Incorporated
ISO5851-Q1
www.ti.com.cn
ZHCSFJ4 –SEPTEMBER 2016
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
16X (0.6)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
9
8
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/A 08/2013
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
版权 © 2016, Texas Instruments Incorporated
35
ISO5851-Q1
ZHCSFJ4 –SEPTEMBER 2016
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (0.6)
16X (2)
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/A 08/2013
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
36
版权 © 2016, Texas Instruments Incorporated
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改, 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内,且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定,否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险,
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息,不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可,或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分,仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时,如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分,则会失去相关 TI 组件 或服务的所有明
示或暗示授权,且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意,尽管任何应用相关信息或支持仍可能由 TI 提供,但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意,他们具备制定与实施安全措施所需的全部专业技术和知识,可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中,为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此,此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III(或类似的生命攸关医疗设备)的授权许可,除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意,对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用,其风险由客户单独承担,并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品,这些产品主要用于汽车。在任何情况下,因使用非指定产品而无法达到 ISO/TS16949 要
求,TI不承担任何责任。
产品
应用
www.ti.com.cn/telecom
数字音频
www.ti.com.cn/audio
www.ti.com.cn/amplifiers
www.ti.com.cn/dataconverters
www.dlp.com
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
www.ti.com.cn/computer
www.ti.com/consumer-apps
www.ti.com/energy
www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
视频和影像
www.ti.com.cn/industrial
www.ti.com.cn/medical
www.ti.com.cn/security
www.ti.com.cn/automotive
www.ti.com.cn/video
www.ti.com.cn/clockandtimers
www.ti.com.cn/interface
www.ti.com.cn/logic
逻辑
电源管理
www.ti.com.cn/power
www.ti.com.cn/microcontrollers
www.ti.com.cn/rfidsys
www.ti.com/omap
微控制器 (MCU)
RFID 系统
OMAP应用处理器
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址: 上海市浦东新区世纪大道1568 号,中建大厦32 楼邮政编码: 200122
Copyright © 2016, 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO5851QDWQ1
ISO5851QDWRQ1
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
ISO5851Q
ISO5851Q
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2020 德州仪器半导体技术(上海)有限公司
相关型号:
ISO5852S
High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver with Split Outputs and Active Safety Features
TI
ISO5852SDW
High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver with Split Outputs and Active Safety Features
TI
ISO5852SDWR
High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver with Split Outputs and Active Safety Features
TI
ISO5852S_15
High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver with Split Outputs and Active Safety Features
TI
ISO6720
ISO672x-Q1 General Purpose Reinforced and Basic Dual-Channel Automotive Digital Isolators with Robust EMC
TI
ISO6720-Q1
ISO672x-Q1 General Purpose Reinforced and Basic Dual-Channel Automotive Digital Isolators with Robust EMC
TI
ISO6720-Q1_V01
ISO672x-Q1 General Purpose Reinforced and Basic Dual-Channel Digital Isolators with Robust EMC
TI
©2020 ICPDF网 联系我们和版权申明