ISO5852S-EP_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

ISO5852S-EP 具有分离输出和有源安全保护功能的

高 CMTI 2.5A 和 5A 增强型隔离式 IGBT、MOSFET 栅极驱动器

1 特性

3 说明

1

•

在 V_CM= 1500V 时，共模瞬态抗扰度 (CMTI) 的最

小值为 100kV/μs

ISO5852S-EP 器件是一款用于 IGBT 和 MOSFET 的

5.7 kV_RMS增强型隔离栅极驱动器，具有分离输出

（OUTH 和 OUTL）以及 2.5A 的拉电流能力和 5A 的

灌电流能力。输入端由 2.25V 至 5.5V 的单电源供电运

行。输出端允许的电源范围为 15V 至 30V。两个互补

CMOS 输入控制栅极驱动器的输出状态。76ns 的短暂

传播时间保证了对于输出级的精确控制。

•

分离输出，可提供 2.5A 峰值拉电流和

5A 峰值灌电流

短暂传播延迟：76ns（典型值），

110ns（最大值）

•

2A 有源米勒钳位

输出短路钳位

内置的去饱和 (DESAT) 故障检测功能可识别 IGBT 何

时处于过流状态。检测到 DESAT 时，静音逻辑会立即

阻断隔离器输出，并启动软关断过程以禁用 OUTH 引

脚并将 OUTL 引脚拉至低电平持续 2μs。当 OUTL 引

脚达到 2V 时（相对于最大负电源电势 V_EE2），栅极

驱动器会被“硬”拉至 V_EE2电势，从而立即将 IGBT 关

断。

短路期间的软关断 (STO)

在检测到去饱和故障时通过 FLT 发出故障报警并通

过 RST 复位

•

具有就绪 (RDY) 引脚指示的输入和输出欠压锁定

(UVLO)

有源输出下拉特性，在低电源或输入悬空的情况下

默认输出低电平

•

2.25V 至 5.5V 输入电源电压

当发生去饱和故障时，器件会通过隔离隔栅发送故障信

号，以将输入端的 FLT 输出拉为低电平并阻断隔离器

的输入。静音逻辑在软关断期间激活。FLT 的输出状

态将被锁存，并只能在 RDY 引脚变为高电平后通过

RST 输入上的低电平有效脉冲复位。

15V 至 30V 输出驱动器电源电压

互补金属氧化物半导体 (CMOS) 兼容输入

抑制短于 20ns 的输入脉冲和瞬态噪声

工作环境温度范围：-55°C 至 +125°C

浪涌抗扰度为 12800 V_PK（根据 IEC 61000-4-5）

安全相关认证：

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

–

符合 DIN V VDE V 0884-10 (VDE V 0884-

10):2006-12 标准的 8000 V_PKV_IOTM和 2121

ISO5852S-EP

SOIC (16)

10.30mm x 7.50mm

V_PKV_IORM增强型隔离

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

–

符合 UL 1577 标准且长达 1 分钟的 5700 V_RMS

隔离

功能框图

V_CC1

V_CC2

CSA 组件接受通知 5A，IEC 60950-1、IEC

60601-1 和 IEC 61010-1 终端设备标准

V_CC1

UVLO1

UVLO2

500 µA

DESAT

GND2

INœ

–

符合 GB4943.1-2011 的 CQC 认证

Mute

9 V

已通过 UL、VDE、CQC、TUV 认证并规划进

行 CSA 认证

IN+

V_CC2

V_CC1

RDY

Gate Drive

and

OUTH

OUTL

Ready

2 应用

Encoder

Logic

STO

•

隔离式绝缘栅双极型晶体管 (IGBT) 和金属氧化物

半导体场效应晶体管 (MOSFET) 驱动器

V_CC1

FLT

Decoder

Q

S

R

2 V

Fault

CLAMP

V_CC1

–

工业电机控制驱动器

RST

工业用电源

GND1

V_EE2

太阳能逆变器

混合动力汽车 (HEV) 和电动车 (EV) 电源模块

感应加热

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEW1

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

9

Detailed Description ............................................ 23

9.1 Overview ................................................................. 23

9.2 Functional Block Diagram ....................................... 23

9.3 Feature Description................................................. 24

9.4 Device Functional Modes........................................ 25

应用.......................................................................... 1

说明.......................................................................... 1

修订历史................................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Function........................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Power Ratings........................................................... 6

7.6 Insulation Specifications............................................ 7

7.7 Safety Limiting Values .............................................. 8

7.8 Safety-Related Certifications..................................... 8

7.9 Electrical Characteristics........................................... 9

7.10 Switching Characteristics...................................... 10

7.11 Insulation Characteristics Curves ......................... 11

7.12 Typical Characteristics.......................................... 12

Parameter Measurement Information ................ 19

10 Application and Implementation........................ 26

10.1 Application Information.......................................... 26

10.2 Typical Applications .............................................. 26

11 Power Supply Recommendations ..................... 36

12 Layout................................................................... 36

12.1 Layout Guidelines ................................................. 36

12.2 PCB Material......................................................... 36

12.3 Layout Example .................................................... 36

13 器件和文档支持 ..................................................... 37

13.1 文档支持................................................................ 37

13.2 接收文档更新通知 ................................................. 37

13.3 社区资源................................................................ 37

13.4 商标....................................................................... 37

13.5 静电放电警告......................................................... 37

13.6 Glossary................................................................ 37

14 机械、封装和可订购信息....................................... 37

8

4 修订历史

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

注释

2016 年 12 月

*

最初发布。

2

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

5 说明（续）

如果在由双极输出电源供电的正常运行期间关断 IGBT，输出电压会被硬钳位为 V_EE2。如果输出电源为单极，那么

可采用有源米勒钳位，这种钳位会在一条低阻抗路径上灌入米勒电流，从而防止 IGBT 在高电压瞬态状态下发生动

态导通。

栅极驱动器是否准备就绪待运行由两个欠压锁定电路控制，这两个电路会监视输入端和输出端的电源。如果任意一

端电源不足，RDY 输出会变为低电平，否则该输出为高电平。

ISO5852S-EP 器件采用 16 引脚小外形尺寸集成电路 (SOIC) 封装。此器件的额定工作环境温度范围为 -55°C 至

+125°C。

3

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

6 Pin Configuration and Function

DW Package

16-Pin SOIC

Top View

V_EE2

DESAT

GND2

OUTH

V_CC2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND1

V_CC1

RST

FLT

RDY

INœ

OUTL

CLAMP

V_EE2

IN+

GND1

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

CLAMP

DESAT

FLT

NO.

7

O

I

Miller clamp output

2

Desaturation voltage input

13

9

O

Fault output, active-low during DESAT condition

GND1

—

Input ground

16

3

GND2

IN+

—

I

Gate drive common. Connect to IGBT emitter.

Non-inverting gate drive voltage control input

Inverting gate drive voltage control input

Positive gate drive voltage output

10

11

4

IN–

I

OUTH

OUTL

RDY

RST

O

I

6

Negative gate drive voltage output

12

14

15

5

Power-good output, active high when both supplies are good.

Reset input, apply a low pulse to reset fault latch.

Positive input supply (2.25-V to 5.5-V)

V_CC1

V_CC2

—

Most positive output supply potential.

1

V_EE2

—

Output negative supply. Connect to GND2 for unipolar supply application.

8

4

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

GND1 – 0.3

–0.3

MAX

UNIT

V

V_CC1

Supply-voltage input side

6

35

V_CC2

Positive supply-voltage output side

Negative supply-voltage output side

Total-supply output voltage

(V_CC2– GND2)

(V_EE2– GND2)

V

V_EE2

–17.5

0.3

V

V_(SUP2)

V_(OUTH)

V_(OUTL)

(V_CC2- V_EE2

)

–0.3

35

V

Positive gate-driver output voltage

Negative gate-driver output voltage

V_EE2– 0.3

V_CC2+ 0.3

V

Maximum pulse width = 10 μs, Maximum

duty cycle = 0.2%)

I_(OUTH)

I_(OUTL)

Gate-driver high output current

Gate-driver low output current

2.7

5.5

A

Maximum pulse width = 10 μs, Maximum

duty cycle = 0.2%)

V_(LIP)

I_(LOP)

Voltage at IN+, IN–,FLT, RDY, RST

Output current of FLT, RDY

GND1 – 0.3

V_CC1+ 0.3

10

V

mA

V

V_(DESAT)Voltage at DESAT

V_(CLAMP)Clamp voltage

GND2 – 0.3

V_EE2– 0.3

–55

V_CC2+ 0.3

150

V

T_J

Junction temperature

Storage temperature

°C

T_STG

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V

V_CC1

V_CC2

V_(EE2)

V_(SUP2)

V_(IH)

V_(IL)

t_UI

Supply-voltage input side

2.25

5.5

Positive supply-voltage output side (V_CC2– GND2)

Negative supply-voltage output side (V_EE2– GND2)

15

30

V

–15

0

30

V

Total supply-voltage output side (V_CC2– V_EE2

High-level input voltage (IN+, IN–, RST)

Low-level input voltage (IN+, IN–, RST)

)

15

V

0.7 × V_CC1

V_CC1

V

0

40

0.3 × V_CC1

V

Pulse width at IN+, IN– for full output (C_LOAD= 1 nF)

Pulse width at RST for resetting fault latch

Ambient temperature

ns

°C

t_RST

800

–55

T_A

125

5

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

7.4 Thermal Information

ISO5852S-EP

DW (SOIC)

16 PINS

99.6

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

48.5

56.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

29.2

ψ_JB

56.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Power Ratings

Full-chip power dissipation is derated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a

maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient

temperature and board design, while ensuring that the junction temperature does not exceed 150°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1255

175

UNIT

mW

P_D

Maximum power dissipation (both sides)

Maximum input power dissipation

Maximum output power dissipation

V_CC1= 5.5-V, V_CC2= 30-V, T_A= 25°C

P_D(I)

P_D(O)

1080

6

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

7.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

CPG

DTI

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest terminal-to-terminal distance through air

8

mm

µm

V

Shortest terminal-to-terminal distance across the

package surface

Distance through the insulation

Comparative tracking index

Material group

Minimum internal gap (internal clearance)

21

600

DIN EN 60112 (VDE 0303-11); IEC 60112; Material

Group I according to IEC 60664-1; UL 746A

CTI

I

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage Category

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12⁽²⁾

V_IORMMaximum repetitive peak isolation voltage AC voltage (bipolar)

2121

1500

2121

8000

V_PK

V_RMS

V_DC

AC voltage (sine wave) Time dependent dielectric

breakdown (TDDB) test, see Figure 1

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST= V_IOTM; t = 60 s (qualification); t = 1 s (100%

production)

V_IOTM

V_IOSM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

Test method per IEC 60065, 1.2/50 µs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

8000

V_PK

Method a: After I/O safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s;

≤5

V_pd(m)= 1.2 × V_IORM= 2545 V_PK

t_m= 10 s

,

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

≤5

q_pd

Apparent charge⁽⁴⁾

V_pd(m)= 1.6 × V_IORM= 3394 V_PK

t_m= 10 s

,

pC

Method b1: At routine test (100% production) and

preconditioning (type test)

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.875× V_IORM= 3977 V_PK

t_m= 10 s

,

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Isolation resistance, input to output⁽⁵⁾

Pollution degree

V_IO= 0.4 sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

1

pF

> 10¹²

> 10¹¹

> 10⁹

2

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Ω

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 s (qualification);

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 s (100%

production)

V_ISO

Withstand isolation voltage

5700

VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall

be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

7

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

7.7 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of

the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_θJA= 99.6°C/W, V_I= 2.75 V, T_J= 150°C, T_A= 25°C,

456

see Figure 2

_θJA= 99.6°C/W, V_I= 3.6 V, T_J= 150°C, T_A= 25°C,

see Figure 2

_θJA= 99.6°C/W, V_I= 5.5 V, T_J= 150°C, T_A= 25°C,

see Figure 2

_θJA= 99.6°C/W, V_I= 15 V, T_J= 150°C, T_A= 25°C,

see Figure 2

_θJA= 99.6°C/W, V_I= 30 V, T_J= 150°C, T_A= 25°C,

see Figure 2

R

346

228

84

Safety input, output, or supply

current

R

I_S

mA

R

42

Safety input, output, or total

power

P_S

T_S

R_θJA= 99.6°C/W, T_J= 150°C, T_A= 25°C, see Figure 3

255⁽¹⁾

150

mW

°C

Safety temperature

(1) Input, output, or the sum of input and output power should not exceed this value.

The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines

the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that

of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended

maximum input voltage times the current. The junction temperature is then the ambient temperature plus the

power times the junction-to-air thermal resistance.

7.8 Safety-Related Certifications

VDE

CSA

UL

CQC

TUV

Certified according to DIN V Plan to certify under CSA

Recognized under UL 1577 Certified according to

Certified according to

EN 61010-1:2010 (3rd Ed) and

EN 60950-

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013

VDE V 0884-10

Component Acceptance

Component Recognition

GB4943.1-2011

(VDE V 0884-10):2006-12

and DIN EN 61010-1 (VDE

0411-1):2011-07

Notice 5A, IEC 60950-1, and Program

IEC 60601-1

Reinforced Insulation

Isolation Rating of 5700

Single Protection, 5700

V_RMS

Reinforced Insulation,

Altitude ≤ 5000m, Tropical

climate, 400 V_RMSmaximum working voltage of 600 V_RMS

working voltage

5700 V_RMSReinforced insulation per

EN 61010-1:2010 (3rd Ed) up to

(1)

Maximum Transient isolation V_RMS

voltage, 8000 V_PK

Maximum surge isolation

voltage, 8000 V_PK

;

Reinforced insulation per

CSA 60950-1- 07+A1+A2

and IEC 60950-1 (2nd Ed.),

800 V_RMSmax working

voltage (pollution degree 2,

material group I) ;

5700 V_RMSReinforced insulation per

EN 60950-

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013 up to working

voltage of 800 V_RMS

,

Maximum repetitive peak

isolation voltage, 2121 V_PK

2 MOPP (Means of Patient

Protection) per CSA 60601-

1:14 and IEC 60601-1 Ed.

3.1, 250 V_RMS(354 V_PK

)

max working voltage

Certification completed

Certificate number:

40040142

Certificate planned

Certification completed

File number: E181974

Certification completed

Certificate number:

CQC16001141761

Certification completed

Client ID number: 77311

(1) Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.

8

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V, V_CC2

GND2 = 15 V, GND2 – V_EE2= 8 V

–

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE SUPPLY

Positive-going UVLO1 threshold-voltage

input side

V_IT+(UVLO1)

V_IT-(UVLO1)

V_HYS(UVLO1)

V_IT+(UVLO2)

V_IT–(UVLO2)

V_HYS(UVLO2)

2.25

V

Negative-going UVLO1 threshold-voltage

input side

1.7

UVLO1 Hysteresis voltage (V_IT+– V_IT–

input side

)

0.2

12

11

1

Positive-going UVLO2 threshold-voltage

output side

13

Negative-going UVLO2 threshold-voltage

output side

9.5

UVLO2 hysteresis voltage (V_IT+– V_IT–

output side

)

I_Q1

Input-supply quiescent current

Output-supply quiescent current

2.8

3.6

4.5

6

mA

I_Q2

LOGIC I/O

Positive-going input-threshold voltage (IN+,

IN–, RST)

V_IT+(IN,RST)

V_{IT–(IN,RST)}

0.7 × V_CC1

V

Negative-going input-threshold voltage

(IN+, IN–, RST)

0.3 × V_CC1

V_HYS(IN,RST)

Input hysteresis voltage (IN+, IN–, RST)

High-level input leakage at (IN+)⁽¹⁾

Low-level input leakage at (IN–, RST)⁽²⁾

Pullup current of FLT, RDY

0.15 × V_CC1

100

V

I_IH

IN+ = V_CC1

µA

V

I_IL

IN– = GND1, RST = GND1

V_(RDY)= GND1, V_(FLT)= GND1

I_(FLT)= 5 mA

-100

I_PU

V_(OL)

100

Low-level output voltage at FLT, RDY

0.2

2

GATE DRIVER STAGE

V_(OUTPD)Active output pulldown voltage

V_OUTH

I_(OUTH/L)= 200 mA, V_CC2= open

I_(OUTH)= –20 mA

V

High-level output voltage

Low-level output voltage

V_CC2– 0.5

V_CC2– 0.24

V_EE2+ 13

V_OUTL

I_(OUTL)= 20 mA

V_EE2+ 50

mV

IN+ = high, IN– = low,

V_(OUTH)= V_CC2- 15 V

I_(OUTH)

I_(OUTL)

I_(OLF)

High-level output peak current

Low-level output peak current

1.5

3.4

2.5

5

A

IN+ = low, IN– = high,

V_(OUTL)= V_EE2+ 15 V

Low-level output current during fault

condition

130

mA

ACTIVE MILLER CLAMP

V_(CLP)Low-level clamp voltage

I_(CLP)

I_(CLP)= 20 mA

V_EE2+ 0.015

V_EE2+ 0.08

V

A

V

Low-level clamp current

Clamp threshold voltage

V_(CLAMP)= V_EE2+ 2.5 V

1.6

2.5

2.1

3.3

2.5

V_(CLTH)

SHORT CIRCUIT CLAMPING

Clamping voltage

V_(CLP-OUTH)

IN+ = high, IN– = low, t_CLP= 10 µs,

I_(OUTH)= 500 mA

1.1

1.3

0.7

1.3

1.5

V

(V_OUTH– V_CC2

)

Clamping voltage

(V_OUTL– V_CC2

IN+ = high, IN– = low, t_CLP= 10 µs,

I_(OUTL)= 500 mA

V_(CLP-OUTL)

V_(CLP-CLP)

V_(CLP-CLAMP)

)

Clamping voltage

(V_CLP– V_CC2

IN+ = high, IN– = low, t_CLP= 10 µs,

I_(CLP)= 500 mA

)

IN+ = High, IN– = Low, I_(CLP)= 20

mA

Clamping voltage at CLAMP

Clamping voltage at OUTL

1.1

IN+ = High, IN– = Low, I_(OUTL)= 20

mA

V_(CLP-OUTL)

(V_CLP– V_CC2

)

DESAT PROTECTION

I_(CHG)

Blanking-capacitor charge current

Blanking-capacitor discharge current

V_(DESAT)– GND2 = 2 V

V_(DESAT)– GND2 = 6 V

0.42

9

0.5

14

0.58

mA

I_(DCHG)

(1) I_IHfor IN–, RST pin is zero as they are pulled high internally.

(2) I_ILfor IN+ is zero as it is pulled low internally.

9

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V, V_CC2

GND2 = 15 V, GND2 – V_EE2= 8 V

–

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DESAT threshold voltage with respect to

GND2

V_(DSTH)

V_(DSL)

8.3

9

9.5

V

DESAT voltage with respect to GND2,

when OUTH or OUTL is driven low

0.4

1

V

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V, V_CC2

GND2 = 15 V, GND2 – V_EE2= 8 V

–

PARAMETER

TEST CONDITIONS

C_LOAD= 1 nF

MIN

12

TYP

18

MAX UNIT

t_r

Output-signal rise time at OUTH

Output-signal fall time at OUTL

Propagation Delay

35

37

ns

μs

ns

μs

ns

t_f

C_LOAD= 1 nF

12

20

t_PLH, t_PHL

t_sk-p

76

110

20

Pulse skew |t_PHL– t_PLH

|

See Figure 44, Figure 45,

and Figure 46

t_sk-pp

Part-to-part skew

30⁽¹⁾

t_{GF (IN,/RST)}

t_{DS (90%)}

t_{DS (10%)}

t_{DS (GF)}

t_{DS (FLT)}

t_LEB

Glitch filter on IN+, IN–, RST

20

30

553

2

40

DESAT sense to 90% V_OUTH/Ldelay C_LOAD= 10 nF

DESAT sense to 10% V_OUTH/Ldelay C_LOAD= 10 nF

760

3.5

DESAT-glitch filter delay

C_LOAD= 1 nF

See Figure 46

330

DESAT sense to FLT-low delay

Leading-edge blanking time

Glitch filter on RST for resetting FLT

1.4

480

800

See Figure 44 and Figure 45

310

300

400

t_GF(RSTFLT)

V_I= V_CC1/ 2 + 0.4 × sin (2πft), f = 1 MHz,

V_CC1= 5 V

C_I

Input capacitance⁽²⁾

2

pF

CMTI

Common-mode transient immunity

V_CM= 1500 V, see Figure 47

100

120

kV/μs

(1) Measured at same supply voltage and temperature condition.

(2) Measured from input pin to ground.

10

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

7.11 Insulation Characteristics Curves

500

450

400

350

300

250

200

150

100

50

1.E+11

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

87.5%

V_CC1= 2.75 V

V_CC1= 3.6 V

V_CC1= 5.5 V

V_CC2= 15 V

V_CC2= 30 V

1.E+10

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

20%

1.E+2

0

50

100

150

200

1.E+1

Ambient Temperature (èC)

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

T_Aup to 150°C

Stress-voltage frequency = 60 Hz

Figure 1. Isolation Capacitor Lifetime Projection for Basic

Insulation

Figure 2. Thermal Derating Curve for Safety Limiting

Current per VDE

1400

1200

1000

800

600

400

200

0

Power

0

50

100

Ambient Temperature (èC)

150

200

Figure 3. Thermal Derating Curve for Safety Limiting Power per VDE

11

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

7.12 Typical Characteristics

0

-0.5

-1

0

-0.5

-1

T_A= -40èC

T_A= 25èC

T_A= 125èC

-1.5

-2

-1.5

-2

-2.5

-3

V_CC2- V_OUT= 2.5 V

V_CC2- V_OUT= 5 V

V_CC2- V_OUT= 10 V

V_CC2- V_OUT= 15 V

V_CC2- V_OUT= 20 V

-3.5

-4

-3.5

-4

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

5

10

15

20

25

30

Ambient Temperature (èC)

V_CC2- V_OUTH/LVoltage (V)

D001

D003

Figure 4. Output High Drive Current vs Temperature

Figure 5. Output High Drive Current vs Output Voltage

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

V_OUT- V_EE2= 2.5 V

V_OUT- V_EE2= 5 V

V_OUT- V_EE2= 10 V

V_OUT- V_EE2= 15 V

V_OUT- V_EE2= 20 V

T_A= -40èC

T_A= 25èC

T_A= 125èC

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

5

10

15

20

25

30

Ambient Temperature (èC)

V_OUTH/L- V_EE2Voltage (V)

D002

D004

Figure 6. Output Low Drive Current vs Temperature

Figure 7. Output Low Drive Current vs Output Voltage

9.2

9.1

9

8.9

8.8

8.7

8.6

8.5

15 V Unipolar

30 V Unipolar

-40 -25 -10

5

20 35 50 65 80 95 110 125

Ambient Temperature (èC)

50 ns / Div

D005

C_L= 1 nF

R_GH= 0 Ω

R_GL= 0 Ω

Unipolar: V_CC2– V_EE2= V_CC2– GND2

V_CC2– V_EE2= V_CC2– GND2 = 20 V

Figure 9. Output Transient Waveform

Figure 8. DESAT Threshold Voltage vs Temperature

12

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

Typical Characteristics (continued)

2 ms / Div

500 ns / Div

C_L= 10 nF

R_GH= 0 Ω

R_GL= 0 Ω

C_L= 100 nF

R_GH= 0 Ω

R_GL= 0 Ω

V_CC2– V_EE2= V_CC2– GND2 = 20 V

Figure 10. Output Transient Waveform

Figure 11. Output Transient Waveform

50 ns / Div

500 ns / Div

C_L= 1 nF

R_GH= 10 Ω

R_GL= 5 Ω

C_L= 10 nF

R_GH= 10 Ω

R_GL= 5 Ω

V_CC2– V_EE2= V_CC2– GND2 = 20 V

Figure 12. Output Transient Waveform

Figure 13. Output Transient Waveform

OUT

DESAT

FLT

RDY

1 µs/Div

2 ms / Div

C_L= 10 nF

R_GH= 0 Ω

R_GL= 0 Ω

C_L= 100 nF

R_GH= 10 Ω

R_GL= 5 Ω

V_CC2– V_EE2= V_CC2– GND2 = 15 V

DESAT = 220 pF

V_CC2– V_EE2= V_CC2– GND2 = 20 V

Figure 15. Output Transient Waveform DESAT, RDY, and

FLT

Figure 14. Output Transient Waveform

13

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

Typical Characteristics (continued)

OUT

DESAT

/FLT

DESAT

/FLT

RDY

2 ms / Div

1 ms / Div

C_L= 10 nF

R_GH= 0 Ω

R_GL= 0 Ω

C_L= 10 nF

R_GH= 0 Ω

R_GL= 0 Ω

V_CC2– V_EE2= V_CC2– GND2 = 15 V

DESAT = 220 pF

V_CC2– V_EE2= V_CC2– GND2 = 30 V

DESAT = 220 pF

Figure 16. Output Transient Waveform DESAT, RDY, and

FLT

Figure 17. Output Transient Waveform DESAT, RDY, and

FLT

3.4

3.2

3

OUT

DESAT

/FLT

2.8

2.6

2.4

2.2

2

RDY

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

V_CC1= 5.5 V

2 ms / Div

-55

-35

-15

5

25

45

65

85

105 125

C_L= 10 nF

R_GH= 0 Ω

R_GL= 0 Ω

Ambient Temperature (èC)

D006

V_CC2– V_EE2= V_CC2– GND2 = 30 V

DESAT = 220 pF

IN+ = High

IN– = Low

Figure 18. Output Transient Waveform DESAT, RDY, and

FLT

Figure 19. I_CC1Supply Current vs Temperature

2

1.9

1.8

1.7

1.6

1.5

1.4

3

2.5

2

1.5

1

1.3

V_CC1= 3 V

V_CC1= 3.3 V

1.2

0.5

0

V_CC1= 5 V

V_CC1= 5.5 V

V_CC1= 3 V

V_CC1= 5.5 V

1.1

1

-55

-35

-15

5

25

45

65

85

105 125

0

50

100

150

200

250

300

Ambient Temperature (èC)

Input Frequency - (kHz)

D007

D008

IN+ = Low

IN– = Low

Figure 20. I_CC1Supply Current vs Temperature

Figure 21. >I_CC1Supply Current vs Input Frequency

14

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

Typical Characteristics (continued)

5

5.5

5

4.5

4

4.5

4

3.5

3

3.5

3

V_CC2= 15 V

V_CC2= 20 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 20 V

V_CC2= 30 V

2.5

2

-55

-35

-15

5

25

45

65

85

105 125

0

50

100

150

200

250

300

Ambient Temperature (èC)

Input Frequency - (kHz)

D010

D009

Input frequency = 1 kHz

No C_L

Figure 22. I_CC2Supply Current vs Temperature

Figure 23. I_CC2Supply Current vs Input Frequency

100

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

t_pLHat V_CC2= 15 V

t_pHLat V_CC2= 15 V

t_pLHat V_CC2= 30 V

t_pHLat V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

-55

-35

-15

5

25

45

65

85

105 125

0

10

20

30

40

50

60

70

80

90 100

Ambient Temperature (èC)

Load Capacitance (nF)

D012

D011

C_L= 1 nF

V_CC1= 5 V

R_GH= 0 Ω

R_GL= 0 Ω

R_GH= 10 Ω

R_GL= 5 Ω, 20 kHz

Figure 25. Propagation Delay vs Temperature

Figure 24. I_CC2Supply Current vs Load Capacitance

100

90

80

70

60

50

40

30

20

10

0

1200

1000

800

600

400

200

0

t_pLHat V_CC2= 15 V

t_pLHat V_CC2= 30 V

t_pHLat V_CC2= 15 V

t_pHLat V_CC2= 30 V

t_pLHat V_CC1= 3.3 V

t_pHLat V_CC1= 3.3 V

t_pLHat V_CC1= 5 V

t_pHLat V_CC1= 5 V

-55

-35

-15

5

25

45

65

85

105 125

0

10

20

30

40

50

60

70

80

90 100

Ambient Temperature (èC)

D013

D014

C_L= 1 nF

V_CC2= 15 V

R_GH= 0 Ω

R_GL= 0 Ω

R_GH= 10 Ω

R_GL= 5 Ω

V_CC1= 5 V

Figure 26. Propagation Delay vs Temperature

Figure 27. Propagation Delay vs Load Capacitance

15

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

Typical Characteristics (continued)

1000

600

500

400

300

200

100

0

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

900

800

700

600

500

400

300

200

100

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load Capacitance (nF)

D015

D016

R_GH= 0 Ω

R_GL= 0 Ω

V_CC1= 5 V

R_GH= 0 Ω

R_GL= 0 Ω

V_CC1= 5 V

Figure 28. t_rRise Time vs Load Capacitance

Figure 29. t_fFall Time vs Load Capacitance

6000

5000

4000

3000

2000

1000

0

2000

1800

1600

1400

1200

1000

800

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

600

400

200

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load Capacitance (nF)

D017

D018

R_GH= 10 Ω

R_GL= 5 Ω

V_CC1= 5 V

R_GH= 10 Ω

R_GL= 5 Ω

V_CC1= 5 V

Figure 30. t_rRise Time vs Load Capacitance

Figure 31. t_fFall Time vs Load Capacitance

500

480

460

440

420

400

380

360

340

320

300

4

3.5

3

V_CC2= 15 V

V_CC2= 30 V

2.5

2

V_CC2= 15 V

V_CC2= 30 V

1.5

-55

-35

-15

5

25

45

65

85

105 125

1

-55

Ambient Temperature (èC)

-35

-15

5

25

45

65

85

105 125

D019

Ambient Temperature (èC)

D020

C_L= 10 nF

R_GH= 0 Ω

R_GL= 0 Ω

Figure 33. DESAT Sense to V_OUT10% Delay vs Temperature

Figure 32. Leading Edge Blanking Time With Temperature

16

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

Typical Characteristics (continued)

610

1.25

1.2

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

590

570

550

530

510

490

470

450

1.15

1.1

1.05

-55

-35

-15

5

25

45

65

85

105 125

-55

-35

-15

5

25

45

65

85

105 125

Ambient Temperature (èC)

D021

Ambient Temperature (èC)

D022

C_L= 10 nF

R_GH= 0 Ω

R_GL= 0 Ω

Figure 34. DESAT Sense to V_OUT90% Delay vs Temperature

Figure 35. DESAT Sence to Fault Low Delay vs Temperature

120

5

4.8

4.6

4.4

4.2

4

100

80

60

40

3.8

3.6

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

20

V_CC1= 5.5 V

V_CC1= 5 V, V_CC2= 15 V

3.4

-40 -25 -10

0

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Ambient Temperature (èC)

D024

D023

Figure 36. Fault and RDY Low to RDY High Delay vs

Temperature

Figure 37. Reset to Fault Delay Across Temperature

2

1.8

1.6

1.4

1.2

1

5

4.5

4

3.5

3

2.5

2

0.8

0.6

0.4

0.2

0

1.5

1

V_(CLAMP)= 2 V

V_(CLAMP)= 4 V

V_(CLAMP)= 6 V

I_(OUTH/L)= 100 mA

I_(OUTH/L)= 200 mA

0.5

0

-55

-35

-15

5

25

45

65

85

105 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Ambient Temperature (èC)

D026

D025

Figure 39. Active Pulldown Voltage vs Temperature

Figure 38. Miller Clamp Current vs Temperature

17

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

Typical Characteristics (continued)

1500

1350

1200

1050

900

1400

1200

1000

800

600

400

200

0

20 mA at V_CC2= 15 V

20 mA at V_CC2= 30 V

250 mA at V_CC2= 15 V

250 mA at V_CC2= 30 V

500 mA at V_CC2= 15 V

500 mA at V_CC2= 30 V

750

600

450

300

20 mA at V_CC2= 15 V

20 mA at V_CC2= 30 V

250 mA at V_CC2= 15 V

250 mA at V_CC2= 30 V

500 mA at V_CC2= 15 V

500 mA at V_CC2= 30 V

150

0

-55

-35

-15

5

25

45

65

85

105 125

-55

-35

-15

5

25

45

65

85

105 125

Ambient Temperature (èC)

D029

D027

Figure 40. Short-Circuit Clamp Voltage on Clamp Across

Temperature

Figure 41. Short-Circuit Clamp Voltage on OUTH Across

Temperature

1500

-400

1350

1200

1050

900

750

600

450

300

150

0

-420

-440

-460

-480

-500

-520

-540

-560

-580

-600

20 mA at V_CC2= 15 V

20 mA at V_CC2= 30 V

250 mA at V_CC2= 15 V

250 mA at V_CC2= 30 V

500 mA at V_CC2= 15 V

500 mA at V_CC2= 30 V

V_DESAT= 6 V

85 105 125

-55

-35

-15

5

25

45

65

85

105 125

-55

-35

-15

5

25

45

65

Ambient Temperature (èC)

D028

Ambient Temperature (èC)

D030

V_CC2= 15 V

DESAT = 6 V

Figure 42. Short-Circuit Clamp Voltage on OUTL Across

Temperature

Figure 43. Blanking Capacitor Charging Current vs

Temperature

18

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

8 Parameter Measurement Information

INœ

0 V

50 %

IN+

t_r

t_f

90%

50%

10%

OUTH/L

t_PLH

t_PHL

Figure 44. OUTH and OUTL Propagation Delay, Non-Inverting Configuration

19

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

Parameter Measurement Information (continued)

INœ

50 %

IN+

V_CC1

t_r

t_f

90%

50%

10%

OUTH/L

t_PLH

t_PHL

Figure 45. OUTH and OUTL Propagation Delay, Inverting Configuration

20

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

Parameter Measurement Information (continued)

Inputs

blocked

released

The inputs are muted for 5 µs by internal circuit after

DESAT is detected. RDY is also low until the mute time.

FLT can be reset, only if RDY goes high.

IN+

(INœ = GND1)

90%

V_OUTH/L

t_DS(90%)

10%

t_DS(10%)

V_DSTH

t_LEB

DESAT

FLT

t_DS(FLT)

RDY

RST

t_Mute

RST-rising edge

turns FLT high

t_RST

Figure 46. DESAT, OUTH/L, FLT, RST Delay

21

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

Parameter Measurement Information (continued)

5

15

V_CC2

V_CC1

15V

0.1µF

1µF

2.25 V- 5.5 V

3

9 ,16

14

GND1

GND2

V_EE2

1,8

6

RST

IN+

+

S1

-

10

OUTL

+

Pass œ Fail Criterion :

OUT must remain stable

11

C_L

1nF

IN -

13

12

2

-

FLT

DESAT

7

4

CLAMP

OUTH

RDY

Incorporated

-

+

V_CM

Figure 47. Common-Mode Transient Immunity Test Circuit

22

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

9 Detailed Description

9.1 Overview

The ISO5852S-EP device is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output

power stage are separated by a Silicon dioxide (SiO₂) capacitive isolation.

The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET

(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to

supply 2.5-A pullup and 5-A pulldown currents to drive the capacitive load of the external power transistors, as

well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The

capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and

receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5852S-EP device also

contains undervoltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output

pulldown feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The

ISO5852S-EP device also has an active Miller clamp which can be used to prevent parasitic turnon of the

external power transistor, due to Miller effect, for unipolar supply operation.

9.2 Functional Block Diagram

V_CC2

V_CC1

UVLO1

UVLO2

500 µA

DESAT

GND2

INœ

Mute

9 V

IN+

V_CC2

V_CC1

RDY

Gate Drive

and

OUTH

OUTL

Ready

Encoder

Logic

STO

V_CC1

FLT

Decoder

Q

S

R

2 V

Fault

CLAMP

V_CC1

RST

GND1

V_EE2

23

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

9.3 Feature Description

9.3.1 Supply and Active Miller clamp

The ISO5852S-EP device supports both bipolar and unipolar power supply with active Miller clamp.

For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its

emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its

gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the

IGBT gate. Typical values of V_CC2and V_EE2for bipolar operation are 15-V and -8-V with respect to GND2.

For operation with unipolar supply, typically, V_CC2is connected to 15-V with respect to GND2, and V_EE2is

connected to GND2. In this use case, the IGBT can turn on due to additional charge from IGBT Miller

capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the

CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.

Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage

transitions below 2-V the CLAMP current output is activated.

9.3.2 Active Output Pulldown

The Active output pulldown feature ensures that the IGBT gate OUTH/L is clamped to V_EE2to ensure safe IGBT

off-state, when the output side is not connected to the power supply.

9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output

Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply V_CC1

drops below V_IT-(UVLO1), irrespective of IN+, IN– and RST input till V_CC1goes above V_IT+(UVLO1)

.

In similar manner, the IGBT is turned-off, if the supply V_CC2drops below V_IT-(UVLO2), irrespective of IN+, IN– and

RST input till V_CC2goes above V_IT+(UVLO2)

.

Ready (RDY) pin indicates status of input and output side Undervoltage Lockout (UVLO) internal protection

feature. If either side of device have insufficient supply (V_CC1or V_CC2), the RDY pin output goes low; otherwise,

RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for

operation.

9.3.4 Soft Turnoff, Fault (FLT) and Reset (RST)

During IGBT overcurrent condition, a mute logic initiates a soft-turn-off procedure which disables, OUTH, and

pulls OUTL to low over a time span of 2 μs. When desaturation is active, a fault signal is sent across the isolation

barrier pulling the FLT output at the input side low and blocking the isolator input. mute logic is activated through

the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a

active-low pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for at-

least the specified minimum duration (800 ns), device input logic can be enabled or disabled.

9.3.5 Short Circuit Clamp

Under short circuit events it is possible that currents are induced back into the gate-driver OUTH/L and CLAMP

pins due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes

on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly

higher than the output side supply.

24

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

9.4 Device Functional Modes

In ISO5852S-EP OUTH/L to follow IN+ in normal functional mode, FLT pin must be in the high state. Table 1 lists

the device functions.

Table 1. Function Table⁽¹⁾

V_CC1

PU

PD

PU

V_CC2

PD

IN+

X

IN–

X

RST

X

RDY

Low

High

Low

High

OUTH/L

Low

PU

X

Low

PU

X

Low

X

Low

Open

PU

X

Low

X

Low

PU

High

Low

X

Low

PU

High

(1) PU: Power Up (V_CC1≥ 2.25 V, V_CC2≥ 13 V), PD: Power Down (V_CC1≤ 1.7 V, V_CC2≤ 9.5 V), X: Irrelevant

25

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ISO5852S-EP device is an isolated gate driver for power semiconductor devices such as IGBTs and

MOSFETs. It is intended for use in applications such as motor control, industrial inverters and switched mode

power supplies. In these applications, sophisticated PWM control signals are required to turn the power devices

on and off, which at the system level eventually may determine, for example, the speed, position, and torque of

the motor or the output voltage, frequency and phase of the inverter. These control signals are usually the

outputs of a microcontroller, and are at low voltage levels such as 2.5 V, 3.3 V or 5 V. The gate controls required

by the MOSFETs and IGBTs, however, are in the range of 30-V (using unipolar output supply) to 15-V (using

bipolar output supply), and require high-current capability to drive the large capacitive loads offered by those

power transistors. The gate drive must also be applied with reference to the emitter of the IGBT (source for

MOSFET), and by construction, the emitter node in a gate-drive system swings between 0 to the DC-bus voltage,

which can be several 100s of volts in magnitude.

The ISO5852S-EP device is therefore used to level shift the incoming 2.5-V, 3.3-V, and 5-V control signals from

the microcontroller to the 30-V (using unipolar output supply) to 15-V (using bipolar output supply) drive required

by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller

side.

10.2 Typical Applications

Figure 48 shows the typical application of a three-phase inverter using six ISO5852S-EP isolated gate drivers.

Three-phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for

high-power applications such as high-voltage DC (HVDC) power transmission.

The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5852S-

EP devices that are connected to one of the three load terminals. The operation of the three switches is

coordinated so that one switch operates at each 60 degree point of the fundamental output waveform, therefore

creating a six-step line-to-line output waveform. In this type of applications, carrier-based PWM techniques are

applied to retain waveform envelope and cancel harmonics.

26

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

Typical Applications (continued)

ISO

5852S

1

2

3

4

5

6

PWM

µC

3-Phase

Input

M

FAULT

ISO

5852S

Figure 48. Typical Motor-Drive Application

10.2.1 Design Requirements

Unlike optocoupler-based gate drivers which required external current drivers and biasing circuitry to provide the

input control signals, the input control to the ISO5852S-EP device is CMOS and can be directly driven by the

microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a

pullup resistor on the common-drain FLT output signal, and a high-voltage protection diode between the IGBT

collector and the DESAT input. Additional details are explained in the subsequent sections. Table 2 lists the

allowed range for input and output supply voltage, and the typical current output available from the gate-driver.

Table 2. Design Parameters

PARAMETER

Input supply voltage

VALUE

2.25 V to 5.5 V

15 V to 30 V

0 V to 15 V

2.5 A

Unipolar output-supply voltage (V_CC2– GND2 = V_CC2– V_EE2

)

Bipolar output-supply voltage (V_CC2– V_EE2

)

Bipolar output-supply voltage (GND2 – V_EE2

Output current

)

10.2.2 Detailed Design Procedure

10.2.2.1 Recommended ISO5852S-EP Application Circuit

The ISO5852S-EP device has both, inverting and noninverting gate-control inputs, an active-low reset input, and

an open-drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 49

shows a typical gate-driver implementation with unipolar output supply. Figure 50 shows a typical gate-driver

implementation with bipolar output supply using the ISO5852S-EP device.

27

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

A 0.1-μF bypass capacitor, recommended at the V_CC1input supply pin, and 1-μF bypass capacitor,

recommended at the V_CC2output supply pin, provide the large transient currents required during a switching

transition to ensure reliable operation. The 220-pF blanking capacitor disables DESAT detection during the off-to-

on transition of the power device. The DESAT diode (D_DST) and the 1-kΩ series resistor on the DESAT pin are

external protection components. The R_Ggate resistor limits the gate-charge current and indirectly controls the

rise and fall times of the IGBT collector voltage. The open-drain FLT output and RDY output have a passive 10-

kΩ pullup resistor. In this application, the IGBT gate driver is disabled when a fault is detected and does not

resume switching until the microcontroller applies a reset signal.

10R

ISO5852S

15

5

15

5

V_CC1

GND1

IN+

V_CC2

GND2

V_EE2

V_CC1

GND1

IN+

V_CC2

GND2

V_EE2

+

2.25 to

5 V

2.25 to

5 V

15 V

0.1 µF

œ

3

9

16

9

16

+

0.1 µF

œ

10

1

8

1

8

+

D_DST

1 kꢀ

10 kꢀ

11

12

13

14

2

7

6

4

11

12

13

14

2

7

6

4

œ

INœ

DESAT

CLAMP

OUTL

INœ

DESAT

CLAMP

OUTL

RDY

FLT

RST

RDY

FLT

RST

R_GL

R_GH

R_GL

R_GH

OUTH

220 pF

Figure 49. Unipolar Output Supply

10.2.2.2 FLT and RDY Pin Circuitry

Figure 50. Bipolar Output Supply

A is 50-kΩ pullup resistor exists internally on FLT and RDY pins. The FLT and RDY pins are an open-drain

output. A 10-kΩ pullup resistor can be used to make it faster rise and to provide logic high when FLT and RDY is

inactive, as shown in Figure 51.

Fast common-mode transients can inject noise and glitches on FLT and RDY pins because of parasitic coupling.

The injection of noise and glitches is dependent on board layout. If required, additional capacitance (100 pF to

300 pF) can be included on the FLT and RDY pins.

10R

ISO5852S

15

V_CC1

+

2.25 to 5 V

0.1 µF

œ

9

GND1

16

10 kꢀ

12

13

14

RDY

FLT

µC

RST

10

11

IN+

INœ

Figure 51. FLT and RDY Pin Circuitry for High CMTI

28

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

10.2.2.3 Driving the Control Inputs

The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the

high-voltage output circuit to the low-voltage input side of the ISO5852S-EP device. For maximum CMTI

performance, the digital control inputs, IN+ and IN–, must be actively driven by standard CMOS, push-pull drive

circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching

of the ISO5852S-EP output under extreme common-mode transient conditions. Passive drive circuits, such as

open-drain configurations using pullup resistors, must be avoided. A 20-ns glitch filter exists that can filter a glitch

up to 20 ns on IN+ or IN–.

10.2.2.4 Local Shutdown and Reset

In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the

individual reset lines are independently asserted low to reset the motor controller after a fault condition.

10R

ISO 5852S - EP

V_CC1

ISO 5852S - EP

V_CC1

15

0.1 µF

2.25 V - 5.5 V

9, 16

GND1

10 kꢀ

12

13

12

13

RDY

FLT

RDY

FLT

µC

14

10

14

10

RST

IN+

RST

IN+

11

INœ

Figure 52. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)

29

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

10.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5852S-EP device can be configured to shutdown automatically

in the event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT

outputs of multiple ISO5852S-EP devices can be wired together forming a single, common fault bus for

interfacing directly to the microcontroller. When any of the six gate drivers of a three-phase inverter detects a

fault, the active-low FLT output disables all six gate drivers simultaneously.

10R

ISO5852S

15

V_CC1

+

2.25 to 5 V

0.1 µF

œ

9

GND1

16

10 kꢀ

12

13

14

RDY

FLT

µC

RST

10

11

IN+

INœ

To other

RST pins

To other

FLT pins

Figure 53. Global Shutdown With Inverting Input Configuration

30

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

10.2.2.6 Auto-Reset

In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching

cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault

state until the gate control signal changes to the gate-low state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch is always reset before IN+ goes high again.

This configuration protects the IGBT on a cycle-by-cycle basis and automatically resets before the next on cycle.

10R

ISO 5852S - EP

V_CC1

ISO 5852S - EP

V_CC1

15

2.25 V- 5.5 V

0.1 µF

2.25 V- 5.5 V

9, 16

GND1

10k

12

13

12

13

RDY

FLT

RDY

FLT

µC

14

10

14

10

RST

IN +

IN -

RST

IN +

IN -

11

Figure 54. Auto Reset for Noninverting and Inverting Input Configuration

31

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large, instantaneous forward-voltage transients across the freewheeling diodes

of the IGBTs. These transients result in large negative-voltage spikes on the DESAT pin which draw substantial

current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in

series with the DESAT diode.

Further protection is possible through an optional Schottky diode, whose low-forward voltage assures clamping of

the DESAT input to GND2 potential at low-voltage levels.

ISO5852S

5

3

V_CC2

GND2

V_EE2

+

15 V

1 µF

œ

+

0.1 µF

œ

1

8

D_DST

R_S

2

7

6

DESAT

CLAMP

OUTL

œ

R_GL

R_GH

V_FW-Inst

4

+

OUTH

V_FW

220 pF

Figure 55. DESAT Pin Protection With Series Resistor and Schottky Diode

32

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

10.2.2.8 DESAT Diode and DESAT Threshold

The function of the DESAT diode is to conduct forward current, allowing sensing of the saturated collector-to-

emitter voltage of the IGBT, V_(DESAT), (when the IGBT is on), and to block high voltages (when the IGBT is off).

During the short transition time when the IGBT is switching, a commonly high dV_CE/dt voltage ramp rate occurs

across the IGBT. This ramp rate results in a charging current I_(CHARGE)= C_(D-DESAT)× d_VCE/dt, charging the

blanking capacitor. C_(D-DESAT)is the diode capacitance at DESAT.

To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are

recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector

voltage transients appear at DESAT attenuated by the ratio of 1+ C_(BLANK)/ C_(D-DESAT)

.

Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the

voltage at the DESAT-pin, V_F+ V_CE= V_(DESAT), the V_CElevel, which triggers a fault condition, can be modified by

adding multiple DESAT diodes in series: V_CE-FAULT(TH)= 9 V – n × VF (where n is the number of DESAT diodes).

When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating can be

selected.

10.2.2.9 Determining the Maximum Available, Dynamic Output Power, P_OD-max

The ISO5852S-EP maximum-allowed total power consumption of P_D= 251 mW consists of the total input power,

P_ID, the total output power, P_OD, and the output power under load, P_OL

:

P_D= P_ID+ P_OD+ P_OL

(1)

(2)

(3)

(4)

With:

P_ID= V_CC1-max× I_CC1-max= 5.5 V × 4.5 mA = 24.75 mW

and:

P_OD= (V_CC2– V_EE2) × I_CC2-max= (15 V – [–8 V]) × 6 mA = 138 mW

then:

P_OL= P_D– P_ID– P_OD= 251 mW – 24.75 mW – 138 mW = 88.25 mW

In comparison to P_OL, the actual dynamic output power under worst case condition, P_OL-WC, depends on a variety

of parameters:

æ

ç

è

ö

÷

ø

r_on-max

r_off-max

P_OL-WC= 0.5 ´ f

´ Q_G

´

V

- V_EE2

´

+

(

)

INP

CC2

r_on-max+ R_G

r_off-max+ R_G

where

•

f_INP= signal frequency at the control input IN+

Q_G= power device gate charge

V_CC2= positive output supply with respect to GND2

V_EE2= negative output supply with respect to GND2

r_on-max= worst case output resistance in the on-state: 4 Ω

r_off-max= worst case output resistance in the off-state: 2.5 Ω

R_G= gate resistor

(5)

When R_Gis determined, Equation 5 is to be used to verify whether P_OL-WC< P_OL. Figure 56 shows a simplified

output stage model for calculating P_OL-WC

.

33

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

ISO5852S

V_CC2

+

œ

R_on-max

15 V

R_G

OUTH/L

Q_G

R_off-max

+

8 V

œ

V_EE2

Figure 56. Simplified Output Model for Calculating P_OL-WC

10.2.2.10 Example

This examples considers an IGBT drive with the following parameters:

•

I_ON-PK= 2 A

Q_G= 650 nC

f_INP= 20 kHz

V_CC2= 15 V

V_EE2= –8 V

Applying the value of the gate resistor R_G= 10 Ω.

Then, calculating the worst-case output-power consumption as a function of R_G, using Equation 5 r_on-max= worst

case output resistance in the on-state: 4 Ω, r_off-max= worst case output resistance in the off-state: 2.5 Ω, R_G

=

gate resistor yields

4 Ω

2.5 Ω

æ

ö

P_OL-WC= 0.5´20 kHz´650 nC´ 15 V -( -8 V) ´

+

4 Ω + 10 Ω 2.5 Ω + 10 Ω

= 72.61 mW

(

)

ç

è

÷

ø

(6)

Because P_OL-WC= 72.61 mW is less than the calculated maximum of P_OL= 88.25 mW, the resistor value of R_G=

10 Ω is suitable for this application.

34

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

10.2.2.11 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in

Figure 57) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and

must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10

pair for up to 15 A maximum.

ISO5852S

5

3

V_CC2

GND2

V_EE2

+

15 V

1 µF

œ

+

0.1 µF

œ

1

8

D_DST

1 kꢀ

2

7

6

DESAT

CLAMP

OUTL

R_G

10 ꢀ

4

OUTH

220 pF

Figure 57. Current Buffer for Increased Drive Current

10.2.3 Application Curves

5 µs/Div

C_L= 1 nF

V_CC2– GND2 = 15 V

(V_CC2– V_EE2= 23 V)

R_GH= 10 Ω

R_GL= 10 Ω

C_L= 1 nF

R_GH= 10 Ω

R_GL= 10 Ω

GND2 - V_EE2= 8 V

V_CC2– V_EE2= V_CC2- GND2 = 20 V

Figure 58. Normal Operation - Bipolar Supply

Figure 59. Normal Operation - Unipolar Supply

35

ISO5852S-EP

ZHCSFX1 –DECEMBER 2016

www.ti.com.cn

11 Power Supply Recommendations

To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is

recommended at the V_CC1input supply pin and a 1-μF bypass capacitor is recommended at the V_CC2output

supply pin. The capacitors should be placed as close to the supply pins as possible. The recommended

placement of the capacitors is 2 mm (maximum) from the input and output power supply pins (V_CC1and V_CC2).

12 Layout

12.1 Layout Guidelines

minimum of four layers is required to accomplish a low EMI PCB design (see Figure 60). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

•

Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of

their inductances) and allows for clean interconnects between the gate driver and the microcontroller and

power transistors. Gate driver control input, Gate driver output OUTH/L and DESAT should be routed in the

top layer.

•

Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for

the return current flow. On the driver side, use GND2 as the ground plane.

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/inch². On the gate-driver V_EE2and V_CC2can be used as power planes. They can share

the same layer on the PCB as long as they are not connected together.

•

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,

routing, and other details, see the Digital Isolator Design Guide (SLLA284).

12.2 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace

lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper

alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and

stiffness, and the self-extinguishing flammability-characteristics.

12.3 Layout Example

High-speed traces

10 mils

Ground plane

Yeep this

FR-4

0 ~ 4.5

space free

from planes,

traces, pads,

and vias

40 mils

10 mils

r

Power plane

Low-speed traces

Figure 60. Recommended Layer Stack

36

ISO5852S-EP

www.ti.com.cn

ZHCSFX1 –DECEMBER 2016

13 器件和文档支持

13.1 文档支持

13.1.1 相关文档ꢀ


型号：	ISO5852S-EP
厂家：	TEXAS INSTRUMENTS
描述：	具有分离输出和有源保护功能的 5.7kVrms、2.5A/5A 增强型单通道隔离式栅极驱动器栅极驱动驱动器
文件：	总45页 (文件大小：1966K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISO5852S-EP [TI]

相关型号：

ISO5852S-Q1

ISO5852SDW

ISO5852SDWR

ISO5852SMDWREP

ISO5852SQDWQ1

ISO5852SQDWRQ1

ISO5852S_15

ISO6720

ISO6720-Q1

ISO6720-Q1_V01

ISO6720-Q1_V02

ISO6720-Q1_V03