ISO6720-Q1_V02 [TI]
ISO672x-Q1 General Purpose Reinforced and Basic Dual-Channel Digital Isolators with Robust EMC;型号: | ISO6720-Q1_V02 |
厂家: | TEXAS INSTRUMENTS |
描述: | ISO672x-Q1 General Purpose Reinforced and Basic Dual-Channel Digital Isolators with Robust EMC |
文件: | 总54页 (文件大小:4358K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISO6720-Q1, ISO6721-Q1
SLLSFF5C – JANUARY 2020 – REVISED MARCH 2021
ISO672x-Q1 General Purpose Reinforced and Basic Dual-Channel Digital Isolators
with Robust EMC
1 Features
3 Description
•
•
50-Mbps data rate
Robust isolation barrier:
The ISO672x-Q1 devices are high-performance, dual-
channel digital isolators ideal for cost sensitive
applications requiring up to 5000 VRMS (DWV
package) and 3000 VRMS (D package) isolation
ratings per UL 1577. These devices are also certified
by VDE, TUV, CSA, and CQC.
– High lifetime at 1060 VRMS working voltage
– Up to 5000 VRMS isolation rating
– ±75 kV/μs typical CMTI
Wide supply range: 1.71 V to 1.89 V and 2.25 V to
5.5 V
•
The
ISO672x-Q1
devices
provide
high
electromagnetic immunity and low emissions at
low power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by TI's double
capacitive silicon dioxide (SiO2) insulation barrier. The
ISO6720-Q1 device has 2 isolation channels with
both channels in the same direction. The ISO6721-Q1
device has 2 isolation channels with 1 channel in
each direction. In the event of input power or signal
loss, the default output is high for devices without
suffix F and low for devices with suffix F. See Device
Functional Modes section for further details.
•
•
1.71-V to 5.5-V level translation
Default output High (ISO672x-Q1) and Low
(ISO672xF-Q1) Options
•
•
•
1.8 mA per channel typical at 1 Mbps
Low propagation delay: 11 ns typical
AEC-Q100 qualified with the following results:
– Device temperature Grade 1: –40°C to +125°C
ambient operating temperature range
Meets VDA320 isolation requirements
Robust electromagnetic compatibility (EMC)
– System-Level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Low emissions
Narrow-SOIC (D-8) and Wide-SOIC (DWV-8)
package
Safety-Related Certifications (pending):
– DIN VDE V 0884-11:2017-01
– UL 1577 component recognition program
(completed)
•
•
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
ISO6720B-Q1, ISO6720B-Q1
ISO6721B-Q1, ISO6721B-Q1
ISO6720-Q1, ISO6720F-Q1
ISO6721-Q1, ISO6721F-Q1
D (8)
4.90 mm x 3.91 mm
•
•
DWV (8)
5.85 mm x 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
GB 4943.1-2011 certifications
VCCO
VCCI
Series Isolation
Capacitors
2 Applications
INx
OUTx
•
Hybrid, electric and power train system (EV/HEV)
– Battery management system (BMS)
– On-board charger
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
– Traction inverter
– DC/DC converter
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
– Inverter and motor control
Power supplies
Grid, Electricity meter
Simplified Schematic
•
•
•
Appliances
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO6720-Q1, ISO6721-Q1
SLLSFF5C – JANUARY 2020 – REVISED MARCH 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Power Ratings ............................................................7
7.6 Insulation Specifications ............................................ 8
7.7 Safety-Related Certifications ................................... 10
7.8 Safety Limiting Values ..............................................10
7.9 Electrical Characteristics—5-V Supply .................... 12
7.10 Supply Current Characteristics—5-V Supply .........12
7.11 Electrical Characteristics—3.3-V Supply ................13
7.12 Supply Current Characteristics—3.3-V Supply ......13
7.13 Electrical Characteristics—2.5-V Supply .............. 14
7.14 Supply Current Characteristics—2.5-V Supply ......14
7.15 Electrical Characteristics—1.8-V Supply ............... 15
7.16 Supply Current Characteristics—1.8-V Supply ......15
7.17 Switching Characteristics—5-V Supply ..................16
7.18 Switching Characteristics—3.3-V Supply ...............16
7.19 Switching Characteristics—2.5-V Supply ...............17
7.20 Switching Characteristics—1.8-V Supply ...............17
7.21 Insulation Characteristics Curves........................... 18
7.22 Typical Characteristics............................................19
8 Parameter Measurement Information..........................21
9 Detailed Description......................................................22
9.1 Overview...................................................................22
9.2 Functional Block Diagram.........................................22
9.3 Feature Description...................................................23
9.4 Device Functional Modes..........................................24
10 Application and Implementation................................25
10.1 Application Information........................................... 25
10.2 Typical Application.................................................. 26
11 Power Supply Recommendations..............................30
12 Layout...........................................................................31
12.1 Layout Guidelines................................................... 31
12.2 Layout Example...................................................... 32
13 Device and Documentation Support..........................33
13.1 Device Support....................................................... 33
13.2 Documentation Support.......................................... 33
13.3 Receiving Notification of Documentation Updates..33
13.4 Support Resources................................................. 33
13.6 Electrostatic Discharge Caution..............................33
13.7 Glossary..................................................................33
14 Mechanical, Packaging, and Orderable
Information.................................................................... 34
14.1 Package Option Addendum....................................41
14.2 Tape and Reel Information......................................42
4 Revision History
Changes from Revision B (January 2021) to Revision C (March 2021)
Page
•
Added the Device Support section................................................................................................................... 33
Changes from Revision A (December 2020) to Revision B (January 2021)
Page
•
•
Changed device status to Production Data........................................................................................................ 1
Switched the labels for VCC1 falling and VCC2 rising in the graph legend of Power Supply Undervoltage
Threshold vs Free-Air Temperature .................................................................................................................19
Added the Receiving Notification of Documentation Updates section..............................................................33
Changed the Electrostatic Discharge Caution statement ................................................................................ 33
•
•
Changes from Revision * (July 2020) to Revision A (December 2020)
Page
•
Pre-RTM updates................................................................................................................................................1
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5 Description (continued)
Used in conjunction with isolated power supplies, these devices help prevent noise currents on data buses, such
as CAN and LIN from damaging sensitive circuitry. Through innovative chip design and layout techniques, the
electromagnetic compatibility of the ISO672x-Q1 devices has been significantly enhanced to ease system-level
ESD, EFT, surge, and emissions compliance. The ISO672x-Q1 family of devices is available in a 8-pin SOIC
wide-body (DWV) package and 8-pin SOIC narrow-body (D) package and is a pin-to-pin upgrade to the older
generations.
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6 Pin Configuration and Functions
VCC1
INA
1
2
3
4
8
7
6
5
VCC2
OUTA
OUTB
GND2
INB
GND1
Not to scale
Figure 6-1. ISO6720-Q1 D and DWV Package 8-Pin SOIC Top View
VCC1
OUTA
INB
1
2
3
4
8
7
6
5
VCC2
INA
OUTB
GND2
GND1
Not to scale
Figure 6-2. ISO6721-Q1 D and DWV Package 8-Pin SOIC Top View
Table 6-1. Pin Functions
PIN
D and DWV PACKAGE
ISO6720-Q1 ISO6721-Q1
I/O
DESCRIPTION
NAME
GND1
GND2
INA
4
4
—
—
I
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
5
2
3
7
6
1
8
5
7
3
2
6
1
8
INB
I
Input, channel B
OUTA
OUTB
VCC1
VCC2
O
O
—
—
Output, channel A
Output, channel B
Power supply, VCC1
Power supply, VCC2
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7 Specifications
7.1 Absolute Maximum Ratings
See(1)
MIN
-0.5
-0.5
-0.5
-0.5
-15
MAX
UNIT
VCC1 to GND1
Supply Voltage (2)
6
V
VCC2 to GND2
6
VCCX + 0.5 (3)
VCCX + 0.5 (3)
15
INx to GNDx
Input/Output
V
Voltage
OUTx to GNDx
Output Current
Io
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
150
Temperature
-65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
(3) Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±6000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
V(ESD)
Electrostatic discharge
±1500
±8000
V
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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7.3 Recommended Operating Conditions
MIN
1.71
2.25
1.71
2.25
NOM
MAX
1.89
5.5
UNIT
(1)
VCC1
VCC1
VCC2
VCC2
VCC
Supply Voltage Side 1
Supply Voltage Side 1
Supply Voltage Side 2
Supply Voltage Side 2
VCC = 1.8 V
V
V
V
V
(1)
(1)
(1)
VCC = 2.5 V to 5 V
VCC = 1.8 V
1.89
5.5
VCC = 2.5 V to 5 V
UVLO threshold when supply voltage is rising
UVLO threshold when supply voltage is falling
Supply voltage UVLO hysteresis
1.53
1.41
0.13
1.71
V
V
V
V
(UVLO+)
VCC
1.1
(UVLO-)
Vhys
0.08
(UVLO)
0.7 x VCC(2I)
VIH
VIL
High level Input voltage
VCCI
Low level Input voltage
0
-4
-2
-1
-1
0.3 x VCCI
V
mA
mA
mA
mA
mA
mA
mA
mA
Mbps
°C
(2)
VCCO
= 5 V
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 1.8 V
VCCO = 5 V
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 1.8 V
IOH
High level output current
Low level output current
4
2
IOL
1
1
DR
TA
Data Rate
0
50
125
Ambient temperature
-40
25
(1) VCC1 and VCC2 can be set independent of one another
(2) VCCI = Input-side VCC; VCCO = Output-side VCC
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7.4 Thermal Information
ISO672x
DWV (SOIC)
8 PINS
84.3
ISO672xB
THERMAL METRIC (1)
D (SOIC)
8 PINS
104.6
48.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
36.3
47.0
52.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.4
7.9
ψJB
45.1
52.1
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO6720
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
71.2
19.3
51.9
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
15 pF, Input a 25-MHz 50% duty cycle
square wave
PD1
PD2
ISO6721
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
72.7
36.35
36.35
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
15 pF, Input a 25-MHz 50% duty cycle
square wave
PD1
PD2
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UNIT
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7.6 Insulation Specifications
PARAMETER
VALUE
8-DWV
VALUE
8-D
TEST CONDITIONS
IEC 60664-1
CLR
CPG
External clearance(1)
Side 1 to side 2 distance through air
>8.5
>8.5
4
4
mm
mm
Side 1 to side 2 distance across
package surface
External creepage(1)
Minimum internal gap (internal
clearance)
DTI
CTI
Distance through the insulation
>17
>17
µm
V
>600
Comparative tracking index
Material Group
IEC 60112; UL 746A
>400
According to IEC 60664-1
I
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I–IV
I–IV
I–IV
I-III
I-IV
I-III
n/a
n/a
Overvoltage category
DIN VDE V 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM
AC voltage (bipolar)
1500
637
VPK
voltage
AC voltage (sine wave); time-
dependent dielectric breakdown
(TDDB) test
1060
1500
7071
450
VRMS
VDC
VPK
VIOWM
Maximum isolation working voltage
DC voltage
637
VTEST = VIOTM , t = 60 s (qualification);
VTEST = 1.2 × VIOTM, t = 1 s (100%
production)
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
4242
Test method per IEC 62368-1, 1.2/50
µs waveform, VTEST = 1.6 × VIOSM
10,000 VPK (qualification)
VIOSM
=
6250
≤ 5
5000
≤ 5
VPK
Method a: After I/O safety test
subgroup 2/3, Vini = VIOTM, tini = 60
s; Vpd(m) = 1.2 × VIORM , tm = 10 s
Method a: After environmental tests
subgroup 1, Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM , tm = 10 s
≤ 5
≤ 5
qpd
Apparent charge(4)
pC
Method b: At routine test (100%
production) and preconditioning (type
test), Vini = VIOTM, tini = 1 s;
≤ 5
≤ 5
Vpd(m) = 1.5 × VIORM , tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1 MHz
~0.5
~0.5
pF
Ω
VIO = 500 V, TA = 25°C
> 1012
> 1011
> 109
2
> 1012
> 1011
> 109
2
Insulation resistance, input to output(5) VIO = 500 V, 100°C ≤ TA ≤ 150°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
40/125/21
40/125/21
UL 1577
VTEST = VISO , t = 60 s (qualification);
VISO
Withstand isolation voltage
VTEST = 1.2 × VISO , t = 1 s (100%
production)
5000
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
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in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation (ISO672x) and basic electrical insulation (ISO672xB) only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Plan to certify
according to EN
61010-1:2010/A1:2019,
EN 60950-1:2006/A2:2013
and EN 62368-1:2014
Plan to certify according to Plan to certify according to Certified according to
DIN VDE V 0884-11:2017- IEC 62368-1, IEC 61010-1 UL 1577 Component
Plan to certify according to
GB4943.1-2011
01
and IEC 60601
Recognition Program
D-8: 400 VRMS basic
insulation per CSA
5000 VRMS (DW-16)
Maximum transient
isolation voltage, 7071
62368-1:19 and IEC
62368-1:2018 , (pollution
degree 2, material group
Reinforced insulation per
EN 61010-1:2010/A1:2019
up to working voltage of
VPK
Maximum repetitive peak III)
isolation voltage, 1500 DWV-8: 600
VPK VRMS reinforced insulation
Maximum surge isolation per CSA 62368-1:19
;
Reinforced insulation,
Altitude ≤ 5000 m, Tropical 600 VRMS (DW-16)
Single protection,
5000 VRMS
Climate,
700 VRMS maximum
working voltage
5000 VRMS (DW-16)
;
Reinforced insulation per
EN 60950-1:2006/A2:2013
and EN 62368-1:2014 up
to working voltage of 600
VRMS (DW-16)
voltage,
6250 VPK
and IEC 62368-1:2018 ,
(pollution degree 2,
material group I)
Master contract number:
220991
Certificate planned
File number: E181974
Certificate planned
Certificate planned
7.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
D-8 PACKAGE
RθJA =104.6°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
See Figure 7-1
217.2
332
mA
mA
mA
mA
RθJA = 104.6°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
See Figure 7-1
IS
Safety input, output, or supply current (1)
RθJA = 104.6°C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C
See Figure 7-1
434.5
628.9
RθJA = 104.6°C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C
See Figure 7-1
RθJA = 104.6°C/W, TJ = 150°C, TA = 25°C
See Figure 7-2
PS
TS
Safety input, output, or total power (1)
Maximum safety temperature (1)
1195
150
mW
°C
DWV-8 PACKAGE
RθJA =84.3°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
See Figure 7-3
IS
270
412
539
mA
mA
mA
RθJA = 84.3.6°C/W, VI = 3.6 V, TJ =
150°C, TA = 25°C
See Figure 7-3
IS
Safety input, output, or supply current (1)
RθJA = 84.3°C/W, VI = 2.75 V, TJ = 150°C,
TA = 25°C
IS
See Figure 7-3
RθJA = 84.3°C/W, VI = 1.89 V, TJ = 150°C,
TA = 25°C
IS
790
mA
See Figure 7-3
RθJA = 84.3°C/W, TJ = 150°C, TA = 25°C
See Figure 7-3
PS
Safety input, output, or total power (1)
1483
mW
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Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TS
Maximum safety temperature (1)
150
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -4 mA; See Figure 8-1
IOL = 4 mA; See Figure 8-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
VCCO - 0.4
V
VOL
0.4
V
V
(1)
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
V
V
VIH = VCCI (1) at INx
10
µA
µA
kV/us
IIL
Low-level input current
VIL = 0 V at INx
-10
50
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200 V
75
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 5 V ; See Figure 8-3
Ci
Input Capacitance (2)
2.8
pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
7.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.1
1.3
3.2
1.4
2.1
1.5
2.2
2.7
2.5
7.9
1.7
2.1
4.6
2.3
VI = VCCI (ISO6720), VI = 0 V (ISO6720 with F suffix)
VI = 0V (ISO6720), VI = VCC1 (ISO6720 with F suffix)
1 Mbps
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
Supply current - AC signal
3.1
mA
2.3
3.2
3.6
3.6
9.5
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
50 Mbps
ISO6721
VI = VCCI (ISO6721); VI = 0 V (ISO6721 with F suffix)
VI = 0 V (ISO6721); VI = VCCI (ISO6721 with F suffix)
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.2
2.3
1.9
2.5
5.2
2.1
3.5
Supply current - DC signal
2.9
3.6
6.7
mA
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
50 Mbps
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -2mA ; See Figure 8-1
IOL = 2mA ; See Figure 8-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.2
V
VOL
0.2
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
µA
µA
-10
50
Common mode transient
immunity
CMTI
Ci
VI = VCC or 0 V, VCM = 1200 V
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 3.3 V ; See Figure
8-3
Input Capacitance(2)
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
7.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.1
1.3
3.2
1.4
2.1
1.4
2.2
2.3
2.4
6
1.6
2
Supply current - DC signal VI = VCCI (ISO6720), VI = 0 V (ISO6720 with F suffix)
Supply current - DC signal VI = 0V (ISO6720), VI = VCC1 (ISO6720 with F suffix)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
4.5
2.2
3.1
mA
2.2
1 Mbps
3.1
3.2
3.4
7.3
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
50 Mbps
ISO6721
Supply current - DC signal VI = VCCI (ISO6721); VI = 0 V (ISO6721 with F suffix) ICC1, ICC2
VI = 0 V (ISO6721);
1.2
2.3
2.1
3.5
Supply current - DC signal
ICC1, ICC2
VI = VCCI (ISO6721 with F suffix)
mA
2.8
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.8
2.3
4.2
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
50 Mbps
3.3
5.5
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7.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA ; See Figure 8-1
IOL = 1mA ; See Figure 8-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.1
V
VOL
0.1
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
µA
µA
-10
50
Common mode transient
immunity
CMTI
Ci
VI = VCC or 0 V, VCM = 1200 V
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 2.5 V ; See Figure
8-3
Input Capacitance(2)
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
7.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.1
1.3
3.1
1.4
2.1
1.4
2.1
2
1.6
2
Supply current - DC signal VI = VCCI (ISO6720), VI = 0 V (ISO6720 with F suffix)
Supply current - DC signal VI = 0V (ISO6720), VI = VCC1 (ISO6720 with F suffix)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
4.5
2.2
1 Mbps
1 Mbps
3.1
mA
2.2
10 Mbps
10 Mbps
50 Mbps
50 Mbps
3.1
2.9
3.3
6
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
2.3
4.8
ISO6721
Supply current - DC signal VI = VCCI (ISO6721); VI = 0 V (ISO6721 with F suffix) ICC1, ICC2
Supply current - DC signal VI = 0 V (ISO6721); VI = VCCI (ISO6721 with F suffix) ICC1, ICC2
1.2
2.3
1.8
2.1
3.6
2.1
3.5
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
2.8
3.2
4.9
mA
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
50 Mbps
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7.15 Electrical Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA ; See Figure 8-1
IOL = 1mA ; See Figure 8-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
VCCO - 0.1
V
VOL
0.1
V
V
(1)
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
V
V
VIH = VCCI (1) at INx
10
µA
µA
kV/us
IIL
Low-level input current
VIL = 0 V at INx
-10
50
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200 V
75
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 1.8 V ; See Figure
8-3
Ci
Input Capacitance(2)
2.8
pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
7.16 Supply Current Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.8
1.2
2.8
1.3
1.8
1.3
1.8
1.8
2
1.5
2.1
4.3
2.2
VI = VCCI (ISO6720), VI = 0 V (ISO6720 with F suffix)
VI = 0V (ISO6720), VI = VCC1 (ISO6720 with F suffix)
1 Mbps
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
Supply current - AC signal
2.9
mA
2.2
2.9
2.7
3.1
4.9
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
50 Mbps
3.8
ISO6721
VI = VCCI (ISO6721); VI = 0 V (ISO6721 with F suffix) ICC1, ICC2
VI = 0 V (ISO6721); VI = VCCI (ISO6721 with F suffix) ICC1, ICC2
1.1
2.1
1.6
1.9
3
2
Supply current - DC signal
3.4
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
2.7
3
mA
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
50 Mbps
4.2
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7.17 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 8-1
18
8
ps/℃
ns
tUI
See Figure 8-1
See Figure 8-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.2
7
6
ns
Channel-to-channel output skew time
tsk(o)
Same direction channels
ns
(2)
tsk(p-p)
Part-to-part skew time (3)
Output signal rise time
Output signal fall time
6
4.5
4.5
ns
ns
ns
tr
tf
2.6
2.6
See Figure 8-1
See Figure 8-2
Default output delay time from input
power loss
tDO
0.1
0.3
us
tPU
tie
Time from UVLO to valid output data
Time interval error
300
us
ns
1
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.18 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 8-1
18
9.2
ps/℃
ns
tUI
See Figure 8-1
See Figure 8-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.5
7
6
ns
Channel-to-channel output skew time
tsk(o)
Same direction channels
ns
(2)
tsk(p-p)
Part-to-part skew time (3)
Output signal rise time
Output signal fall time
6
3.2
3.2
ns
ns
ns
tr
tf
1.6
1.6
See Figure 8-1
See Figure 8-2
Default output delay time from input
power loss
tDO
0.1
0.3
us
tPU
tie
Time from UVLO to valid output data
Time interval error
300
us
ns
1
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.19 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
12
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 8-1
20.5
14.3
ps/℃
ns
tUI
See Figure 8-1
See Figure 8-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.6
7.1
6
ns
Channel-to-channel output skew
time(2)
tsk(o)
Same direction channels
ns
tsk(p-p)
Part-to-part skew time(3)
Output signal rise time
Output signal fall time
6.1
4
ns
ns
ns
tr
tf
2
2
See Figure 8-1
See Figure 8-2
4
Default output delay time from input
power loss
tDO
0.1
0.3
us
tPU
tie
Time from UVLO to valid output data
Time interval error
300
us
ns
1
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.20 Switching Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
15
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 8-1
24
15.2
ps/℃
ns
tUI
See Figure 8-1
See Figure 8-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.7
8.2
6
ns
Channel-to-channel output skew
time(2)
tsk(o)
Same direction channels
ns
tsk(p-p)
Part-to-part skew time(3)
Output signal rise time
Output signal fall time
8.8
5.3
5.3
ns
ns
ns
tr
tf
2.7
2.7
See Figure 8-1
See Figure 8-2
Default output delay time from input
power loss
tDO
0.1
0.3
us
tPU
tie
Time from UVLO to valid output data
Time interval error
300
us
ns
1
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.21 Insulation Characteristics Curves
650
600
550
500
450
400
350
300
250
200
150
100
50
Vcc = 5.5 V
Vcc = 3.6 V
Vcc = 2.75 V
Vcc = 1.89 V
0
0
20
40
60
80
100
120
140
160
Ambient Temperature (ꢀC)
Figure 7-1. Thermal Derating Curve for Safety Limiting Current for D-8 Package
Figure 7-2. Thermal Derating Curve for Safety Limiting Power for D-8 Package
1000
Vcc = 5.5 V
Vcc = 3.6 V
Vcc = 2.75 V
Vcc = 1.89 V
800
600
400
200
0
0
20
40
60
80
100
120
140
160
Ambient Temperature (ꢀC)
Figure 7-3. Thermal Derating Curve for Safety Limiting Current for DWV-8 Package
1600
1400
1200
1000
800
600
400
200
0
0
20
40
60
80
100
120
140
160
Ambient Temperature (ꢀC)
Figure 7-4. Thermal Derating Curve for Safety Limiting Power for DWV-8 Package
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7.22 Typical Characteristics
7.5
4
3.5
3
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
6
4.5
3
ICC2 at 5 V
ICC2 at 5 V
2.5
2
1.5
0
1.5
1
0
10
20
30
40
50
0
10
20
30
40
50
Data Rate (Mbps)
Data Rate (Mbps)
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 7-5. ISO6720 Supply Current vs Data Rate
(With 15-pF Load)
Figure 7-6. ISO6720 Supply Current vs Data Rate
(With No Load)
4.8
3
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
4
3.2
2.4
1.6
0.8
2.7
2.4
2.1
1.8
1.5
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC2 at 5 V
0
10
20
30
40
50
0
10
20
30
40
50
Data Rate (Mbps)
Data Rate (Mbps)
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 7-7. ISO6721 Supply Current vs Data Rate
(With 15-pF Load)
Figure 7-8. ISO6721 Supply Current vs Data Rate
(With No Load)
1
1
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 1.8 V
VCC2 at 2.5 V
0.9
0.9
VCC1 at 3.3 V
VCC2 at 5 V
0.7
VCC1 at 3.3 V
VCC2 at 5 V
0.7
0.8
0.8
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
15
0
5
10
15
Low-Level Output Current (mA)
Low-Level Output Current (mA)
TA = 25°C
TA = 25°C
Figure 7-9. High-Level Output Voltage vs High-level
Output Current
Figure 7-10. Low-Level Output Voltage vs Low-
Level Output Current
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1.6
1.575
1.55
15
14
13
12
11
10
9
1.525
1.5
1.475
1.45
1.425
VCC1
VCC1
VCC2
VCC2
+
-
+
-
1.4
1.375
1.35
tPHL at 1.8 V
tPLH at 1.8 V
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
tPHL at 5 V
tPLH at 5V
8
-55
-5
45
95
125
-55
-5
45
95
125
Free-Air Temperature (ꢀC)
Free-Air Temperature (ꢀC)
Figure 7-11. Power Supply Undervoltage Threshold Figure 7-12. Propagation Delay Time vs Free-Air
vs Free-Air Temperature
Temperature
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8 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO
50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
=
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
See Note B
V
CC
V
CC
V
1.4 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
Figure 8-2. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
V
OH
or V
OL
C
L
œ
See Note A
GNDI
GNDO
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-3. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISO672x-Q1family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices
also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 9-1, shows a functional block diagram of a typical channel.
9.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Figure 9-1. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 9-2 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 9-2. On-Off Keying (OOK) Based Modulation Scheme
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9.3 Feature Description
The ISO672x-Q1 family of devices is available in two channel configurations and default output state options to
enable a variety of application uses. Table 9-1 lists the device features of the ISO672x-Q1 devices.
Table 9-1. Device Features
MAXIMUM DATA
RATE
DEFAULT OUTPUT
STATE
PART NUMBER
CHANNEL DIRECTION
PACKAGE
RATED ISOLATION(1)
ISO6720B-Q1
ISO6720FB-Q1
ISO6721B-Q1
ISO6721FB-Q1
ISO6720-Q1
50 Mbps
50 Mbps
50 Mbps
50 Mbps
50 Mbps
50 Mbps
50 Mbps
50 Mbps
2 Forward, 0 Reverse
2 Forward, 0 Reverse
1 Forward, 1 Reverse
1 Forward, 1 Reverse
2 Forward, 0 Reverse
2 Forward, 0 Reverse
1 Forward, 1 Reverse
1 Forward, 1 Reverse
High
Low
High
Low
High
Low
High
Low
D-8
D-8
3000 VRMS / 4242 VPK
3000 VRMS / 4242 VPK
3000 VRMS / 4242 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 7071 VPK
5000 VRMS / 7071 VPK
5000 VRMS / 7071 VPK
5000 VRMS / 7071 VPK
D-8
D-8
DWV-8
DWV-8
DWV-8
DWV-8
ISO6720F-Q1
ISO6721-Q1
ISO6721F-Q1
(1) See Safety-Related Certifications for detailed isolation ratings.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 25 . Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO672x-
Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.4 Device Functional Modes
Table 9-2 lists the functional modes for the ISO672x-Q1 devices.
Table 9-2. Function Table
INPUT
(INx)(2)
OUTPUT
(OUTx)
(1)
VCCI
VCCO
COMMENTS
H
L
H
L
Normal Operation: A channel output assumes the logic state of the input.
PU
PU
Default mode: When INx is open, the corresponding channel output goes
to the default logic state. The default is High for ISO672x-Q1 and Low for
ISO672x-Q1 with F suffix.
Open
Default
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for ISO672x-Q1
and Low for ISO672x-Q1 with F suffix.
PD
X
PU
PD
X
X
Default
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(3)
.
Undetermined
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.71V); PD = Powered down (VCC ≤ 1.05 V); X = Irrelevant;
H = High level; L = Low level
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V and 1.05 V < VCCI, VCCO < 1.71 V
9.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
V
V
V
CCI
V
CCI
CCI
CCI
V
V
V
CCI
CCI
CCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
Output
V
CCO
~20 ꢀ
OUTx
Figure 9-3. Device I/O Schematics
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant the accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The ISO672x-Q1 devices are high-performance, dual-channel digital isolators. The devices use single-ended
CMOS-logic switching technology. The supply voltage range is from 1.71 V to 5.5 V for both supplies, VCC1
and VCC2. Since an isolation barrier separates the two sides, each side can be sourced independently with any
voltage within recommended operating conditions. As an example, it is possible to supply ISO672x-Q1 VCC1 with
3.3 V (which is within 1.71 V to 1.89 V and 2.25 V to 5 V) and VCC2 with 5 V (which is also within 1.71 V to
1.89 V and 2.25 V to 5 V). You can use the digital isolator as a logic-level translator in addition to providing
isolation. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
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10.2 Typical Application
For automotive applications, the ISO672x-Q1 device can also be used with Texas Instruments' Piccolo™
microcontroller, CAN transceiver, transformer driver, and voltage regulator to create an isolated CAN interface.
V
S
0.1 ꢀF
3.3 V
2
MBR0520L
1:1.33
3.3VISO
10 ꢀF
3
1
1
3
5
2
V
CC
D2
IN
OUT
TPS76333-Q1
SN6501-Q1
10 ꢀF 0.1 ꢀF
EN
GND
D1
GND
4, 5
10 ꢀF
MBR0520L
ISO Barrier
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
1
8
3
29,57
V
V
CC1
CC2
VCC
RS
8
V
DDIO
10 ꢁ (optional)
10 ꢁ (optional)
4
7
26
25
2
R
D
CANH
INA
CANRXA
OUTA
INB
7
6
5
TMS320F28035PAGQ
ISO6721-Q1
6
3
TCAN1044-Q1
OUTB
GND2
5
CANTXA
1
CANL
Vref
GND1
V
SS
GND
2
4
6,28
SM712
4.7 nF /
2 kV
Figure 10-1. Typical Isolated CAN Application Circuit
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10.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 10-1.
Table 10-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
1.71 V to 1.89 V and 2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
0.1 µF
10.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO672x-Q1 devices only require two external bypass capacitors to operate.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
VCC2
VCC1
GND1
GND2
1
8
0.1uF
0.1 µF
2
3
7
6
INA
OUTA
INB
OUTB
GND2
GND1
5
4
Figure 10-2. Typical ISO672x-Q1 Circuit Hook-up
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10.2.3 Application Curve
The following typical eye diagrams of the ISO672x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 50 Mbps.
Time = 5 ns / div
Time = 5 ns / div
Figure 10-4. Eye Diagram at 50 Mbps PRBS 216 – 1,
3.3 V and 25°C
Figure 10-3. Eye Diagram at 50 Mbps PRBS 216 – 1,
5 V and 25°C
Time = 5 ns / div
Time = 5 ns / div
Figure 10-5. Eye Diagram at 50 Mbps PRBS 216 – 1,
2.5 V and 25°C
Figure 10-6. Eye Diagram at 50 Mbps PRBS 216 – 1,
1.8 V and 25°C
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 10-7 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For basic insulation,
VDE standard requires the use of TDDB projection line with failure rate of less than 1000 part per million (ppm).
For reinforced insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1
part per million (ppm).
Even though the expected minimum insulation lifetime is 20 years, at the specified working isolation voltage,
VDE basic and reinforced certifications require additional safety margin of 20% for working voltage. For basic
certification, device lifetime requires a safety margin of 30% translating to a minimum required insulation lifetime
of 26 years at a working voltage that is 20% higher than the specified value. For reinforced insulation, device
lifetime requires a safety margin of 87.5% translating to a minimum required insulation lifetime of 37.5 years at a
working voltage that is 20% higher than the specified value.
Figure 10-8 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1060 VRMS with a lifetime of 220 years in the
8-DWV package and 450 VRMS with a lifetime of >100 years in the 8D package. Other factors, such as package
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size, pollution degree, material group, etc. can further limit the working voltage of the component. At the lower
working voltages, the corresponding insulation lifetime is 220 years in the 8-DWV package and much longer than
100 years in the 8-D package.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 10-7. Test Setup for Insulation Lifetime Measurement
Figure 10-8. Insulation Lifetime Projection Data
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11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply
pins as possible. If only a single primary-side power supply is available in an application, isolated power can
be generated for the secondary-side with the help of a transformer driver. For automotive applications, please
use SN6501-Q1 or SN6505A-Q1. For such applications, detailed power supply design and transformer selection
recommendations are available in SN6501-Q1 Transformer Driver for Isolated Power Supplies or SN6505A-Q1
Low-Noise 1-A Transformer Drivers for Isolated Power Supplies.
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12 Layout
12.1 Layout Guidelines
A minimum of two layers is required to accomplish a cost optimized and low EMI PCB design. To further improve
EMI, a four layer board can be used (see Section 12.2). Layer stacking for a four layer board should be in the
following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal
layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
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12.2 Layout Example
Solid supply islands reduce
inductance because large peak
currents flow into the VCC pin
2 mm
maximum
from VCC1
2 mm
maximum
from VCC2
VCC1
VCC2
1
8
2
3
4
7
6
5
0.1 …F
0.1 …F
GND2
GND1
Solid ground islands help
dissipate heat through PCB
Figure 12-1. Layout Example
High-speed traces
Ground plane
10 mils
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
r
Power plane
10 mils
Low-speed traces
Figure 12-2. Four Layer Board Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For development support, refer to:
•
•
•
•
Isolated CAN Flexible Data (FD) Rate Repeater Reference Design
Isolated 16-Channel AC Analog Input Module Reference Design Using Dual Simultaneously Sampled ADCs
Polyphase Shunt Metrology with Isolated AFE Reference Design
Reference Design for Power-Isolated Ultra-Compact Analog Output Module
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
•
•
•
•
•
•
Texas Instruments, Isolation Glossary
Texas Instruments, Enabling high voltage signal isolation quality and reliability
Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, SN65HVD231Q 3.3-V CAN Transceivers data sheet
Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet
Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
Piccolo™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
0.25
8X
7.6
7.4
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
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EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: ISO6720-Q1 ISO6721-Q1
ISO6720-Q1, ISO6721-Q1
SLLSFF5C – JANUARY 2020 – REVISED MARCH 2021
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: ISO6720-Q1 ISO6721-Q1
ISO6720-Q1, ISO6721-Q1
SLLSFF5C – JANUARY 2020 – REVISED MARCH 2021
www.ti.com
14.1 Package Option Addendum
Packaging Information
Orderable
Device
Status(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan(2)
Lead/Ball
Finish(6)
MSL Peak
Op Temp (°C) Device
Marking(4) (5)
Temp(3)
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
X6720Q
X6720FQ
X6721Q
X6721FQ
XISO6720QDW ACTIVE
VRQ1
SOIC
SOIC
SOIC
SOIC
DWV
DWV
DWV
DWV
8
1000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
XISO6720FQD ACTIVE
WVRQ1
8
8
8
1000
1000
1000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
XISO6721QDW ACTIVE
VRQ1
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
XISO6721FQD ACTIVE
WVRQ1
XISO6720BQD
RQ1
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
X20BQ
X20FBQ
X21A0
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
3000
3000
XISO6720FBQ
DRQ1
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
XISO6721BQD
RQ1
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
3000
3000
XISO6721FBQ
DRQ1
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
X21FA0
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Product Folder Links: ISO6720-Q1 ISO6721-Q1
ISO6720-Q1, ISO6721-Q1
SLLSFF5C – JANUARY 2020 – REVISED MARCH 2021
www.ti.com
14.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
P1 Pitch between successive cavity centers
W
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
XISO6720QDWVRQ1
XISO6720FQDWVRQ1
XISO6721QDWVRQ1
XISO6721FQDWVRQ1
XISO6720BQDRQ1
XISO6720FBQDRQ1
XISO6721BQDRQ1
XISO6721FBQDRQ1
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DWV
DWV
DWV
DWV
D
8
8
8
8
8
8
8
8
1000
1000
1000
1000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
12.4
12.4
12.4
12.4
12.05
12.05
12.05
12.05
6.4
6.15
6.15
6.15
6.15
5.2
3.3
3.3
3.3
3.3
2.1
2.1
2.1
2.1
16.0
16.0
16.0
16.0
8.0
16.0
16.0
16.0
16.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
3000
3000
D
6.4
5.2
8.0
D
3000
3000
6.4
5.2
8.0
D
6.4
5.2
8.0
Copyright © 2021 Texas Instruments Incorporated
42
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Product Folder Links: ISO6720-Q1 ISO6721-Q1
ISO6720-Q1, ISO6721-Q1
SLLSFF5C – JANUARY 2020 – REVISED MARCH 2021
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
Length (mm) Width (mm)
Height (mm)
XISO6720QDWVRQ1
XISO6720FQDWVRQ1
XISO6721QDWVRQ1
XISO6721FQDWVRQ1
XISO6720BQDRQ1
XISO6720FBQDRQ1
XISO6721BQDRQ1
XISO6721FBQDRQ1
350.0
350.0
350.0
350.0
367.0
367.0
367.0
367.0
350.0
350.0
350.0
350.0
367.0
367.0
367.0
367.0
43.0
SOIC
DWV
DWV
DWV
DWV
D
8
8
8
8
8
8
8
8
1000
43.0
43.0
43.0
35.0
35.0
35.0
35.0
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
1000
1000
1000
3000
D
3000
3000
D
D
3000
Copyright © 2021 Texas Instruments Incorporated
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43
Product Folder Links: ISO6720-Q1 ISO6721-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO6720FQDWVRQ1
ISO6720QDWVRQ1
ISO6721BQDRQ1
PREVIEW
PREVIEW
ACTIVE
SOIC
SOIC
SOIC
DWV
DWV
D
8
8
8
1000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
6720F
6720
6721B
ISO6721FBQDRQ1
ACTIVE
SOIC
D
8
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6721FB
ISO6721FQDWVRQ1
ISO6721QDWVRQ1
XISO6720BQDRQ1
PREVIEW
PREVIEW
ACTIVE
SOIC
SOIC
SOIC
DWV
DWV
D
8
8
8
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
6721F
6721
2500
2500
1000
1000
1000
1000
Non-RoHS &
Non-Green
XISO6720FBQDRQ1
XISO6720FQDWVRQ1
XISO6720QDWVRQ1
XISO6721FQDWVRQ1
XISO6721QDWVRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
D
8
8
8
8
8
Non-RoHS &
Non-Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DWV
DWV
DWV
DWV
Non-RoHS &
Non-Green
Non-RoHS &
Non-Green
Non-RoHS &
Non-Green
Non-RoHS &
Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2021
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO6720-Q1, ISO6721-Q1 :
Catalog : ISO6720, ISO6721
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO6721BQDRQ1
ISO6721FBQDRQ1
SOIC
SOIC
D
D
8
8
3000
3000
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO6721BQDRQ1
ISO6721FBQDRQ1
SOIC
SOIC
D
D
8
8
3000
3000
853.0
853.0
449.0
449.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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