ISO6721B [TI]
ISO672x General Purpose Basic Dual-Channel Digital Isolators with Robust EMC;
| 型号： | ISO6721B |
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| 描述： | ISO672x General Purpose Basic Dual-Channel Digital Isolators with Robust EMC |
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ISO6720, ISO6721
SLLSFJ0C – JANUARY 2020 – REVISED MAY 2021
ISO672x General Purpose Basic Dual-Channel Digital Isolators with Robust EMC
1 Features
3 Description
•
Functional Safety-Capable
The ISO672xB devices are high-performance, dual-
channel digital isolators ideal for cost sensitive
applications requiring up to 3000 VRMS (D package)
isolation ratings per UL 1577. These devices are also
certified by VDE, TUV, CSA, and CQC.
– Documentation available to aid functional safety
system design: ISO6720, ISO6721
50-Mbps data rate
•
•
Robust isolation barrier:
– High lifetime at 450 VRMS working voltage
– Up to 3000 VRMS isolation rating
– ±75 kV/μs typical CMTI
Wide supply range: 1.71 V to 1.89 V and 2.25 V to
5.5 V
1.71-V to 5.5-V level translation
Default output High (ISO672xB) and Low
(ISO672xFB) Options
Wide temperature range: –40°C to +125°C
1.8 mA per channel typical at 1 Mbps
Low propagation delay: 11 ns typical
Robust electromagnetic compatibility (EMC)
– System-Level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Low emissions
The ISO672xB devices provide high electromagnetic
immunity and low emissions at low power
consumption, while isolating CMOS or LVCMOS
digital I/Os. Each isolation channel has a logic
input and output buffer separated by TI's double
capacitive silicon dioxide (SiO2) insulation barrier.
The ISO6720B device has 2 isolation channels with
both channels in the same direction. The ISO6721B
device has 2 isolation channels with 1 channel in
each direction. In the event of input power or signal
loss, the default output is high for devices without
suffix F and low for devices with suffix F. See Device
Functional Modes section for further details.
•
•
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•
•
•
•
Used in conjunction with isolated power supplies,
these devices help prevent noise currents on data
buses, such as UART, SPI, RS-485, RS-232, and
CAN from damaging sensitive circuitry. Through
innovative chip design and layout techniques,
the electromagnetic compatibility of the ISO672xB
devices has been significantly enhanced to ease
system-level ESD, EFT, surge, and emissions
compliance. The ISO672xB family of devices is
available in a 8-pin SOIC narrow-body (D) package
and is a pin-to-pin upgrade to the older generations.
For reinforced isolation requirements, refer to the
ISO672x-Q1.
•
•
Narrow-SOIC (D-8) package
Safety-Related Certifications:
– DIN VDE V 0884-11:2017-01
– UL 1577 component recognition program
– IEC 62368-1, IEC 61010-1, IEC 60601-1
– GB 4943.1-2011 (pending)
2 Applications
•
•
•
•
•
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•
Power supplies
Grid, Electricity meter
Motor drives
Factory automation
Building automation
Lighting
Table 3-1. Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
ISO6720B,
ISO6720FB
Appliances
D (8)
4.90 mm x 3.91 mm
ISO6721B,
ISO6721FB
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO6720, ISO6721
SLLSFJ0C – JANUARY 2020 – REVISED MAY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Power Ratings ............................................................6
6.6 Insulation Specifications ............................................ 7
6.7 Safety-Related Certifications ..................................... 8
6.8 Safety Limiting Values ................................................8
6.9 Electrical Characteristics—5-V Supply ...................... 9
6.10 Supply Current Characteristics—5-V Supply ...........9
6.11 Electrical Characteristics—3.3-V Supply ................10
6.12 Supply Current Characteristics—3.3-V Supply ......10
6.13 Electrical Characteristics—2.5-V Supply ...............11
6.14 Supply Current Characteristics—2.5-V Supply ...... 11
6.15 Electrical Characteristics—1.8-V Supply ............... 12
6.16 Supply Current Characteristics—1.8-V Supply ......12
6.17 Switching Characteristics—5-V Supply ..................13
6.18 Switching Characteristics—3.3-V Supply ...............13
6.19 Switching Characteristics—2.5-V Supply ...............14
6.20 Switching Characteristics—1.8-V Supply ...............14
6.21 Insulation Characteristics Curves........................... 15
6.22 Typical Characteristics............................................16
7 Parameter Measurement Information..........................17
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................26
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 Device Support....................................................... 29
12.2 Documentation Support.......................................... 29
12.3 Receiving Notification of Documentation Updates..29
12.4 Support Resources................................................. 29
12.5 Trademarks.............................................................29
12.6 Electrostatic Discharge Caution..............................29
12.7 Glossary..................................................................29
13 Mechanical, Packaging, and Orderable
Information.................................................................... 29
13.1 Package Option Addendum....................................33
13.2 Tape and Reel Information......................................34
4 Revision History
Changes from Revision B (March 2021) to Revision C (May 2021)
Page
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•
•
•
•
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Updated Safety-Related Certifications table.......................................................................................................8
Updated test conditions in all Switching Characteristics tables........................................................................13
Updated CISPR 22 to CISPR 32...................................................................................................................... 19
Updated Insulation Lifetime Projection Data image..........................................................................................24
Updated Power Supply Recommendations document references................................................................... 26
Added the Device Support section................................................................................................................... 29
Changes from Revision A (December 2020) to Revision B (March 2021)
Page
•
•
Switched the line colors for VCC at 2.5 V and VCC at 3.3 V in ..........................................................................16
Switched the labels for VCC1 falling and VCC2 rising in the graph legend of Power Supply Undervoltage
Threshold vs Free-Air Temperature .................................................................................................................16
Changes from Revision * (July 2020) to Revision A (December 2020)
Page
•
Changed device status to Production Data........................................................................................................ 1
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5 Pin Configuration and Functions
VCC1
INA
1
2
3
4
8
7
6
5
VCC2
OUTA
OUTB
GND2
INB
GND1
Not to scale
Figure 5-1. ISO6720B D Package 8-Pin SOIC Top View
VCC1
OUTA
INB
1
2
3
4
8
7
6
5
VCC2
INA
OUTB
GND2
GND1
Not to scale
Figure 5-2. ISO6721B D Package 8-Pin SOIC Top View
Table 5-1. Pin Functions
PIN
D PACKAGE
I/O
DESCRIPTION
NAME
ISO6720B
ISO6721B
GND1
GND2
INA
4
5
2
3
7
6
1
8
4
5
7
3
2
6
1
8
—
—
I
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
INB
I
Input, channel B
OUTA
OUTB
VCC1
VCC2
O
O
—
—
Output, channel A
Output, channel B
Power supply, VCC1
Power supply, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
See(1)
MIN
-0.5
-0.5
-0.5
-0.5
-15
MAX
UNIT
VCC1 to GND1
Supply Voltage (2)
6
V
V
VCC2 to GND2
6
VCCX + 0.5 (3)
VCCX + 0.5 (3)
15
INx to GNDx
Input/Output
Voltage
OUTx to GNDx
Output Current
Io
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
150
Temperature
-65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±6000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
V(ESD)
Electrostatic discharge
±1500
±8000
V
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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6.3 Recommended Operating Conditions
MIN
1.71
2.25
1.71
2.25
NOM
MAX
1.89
5.5
UNIT
(1)
VCC1
VCC1
VCC2
VCC2
VCC
Supply Voltage Side 1
Supply Voltage Side 1
Supply Voltage Side 2
Supply Voltage Side 2
VCC = 1.8 V (3)
V
V
V
V
(1)
(1)
(1)
VCC = 2.5 V to 5 V (3)
VCC = 1.8 V (3)
1.89
5.5
VCC = 2.5 V to 5 V (3)
UVLO threshold when supply voltage is rising
UVLO threshold when supply voltage is falling
Supply voltage UVLO hysteresis
1.53
1.41
0.13
1.71
V
V
V
V
(UVLO+)
VCC
1.1
(UVLO-)
Vhys
0.08
(UVLO)
0.7 x VCC(2I)
VIH
VIL
High level Input voltage
VCCI
Low level Input voltage
0
-4
-2
-1
-1
0.3 x VCCI
V
mA
mA
mA
mA
mA
mA
mA
mA
Mbps
°C
(2)
VCCO
= 5 V
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 1.8 V
VCCO = 5 V
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 1.8 V
IOH
High level output current
Low level output current
4
2
IOL
1
1
DR
TA
Data Rate
0
50
125
Ambient temperature
-40
25
(1) VCC1 and VCC2 can be set independent of one another
(2) VCCI = Input-side VCC; VCCO = Output-side VCC
(3) The channel outputs are in undetermined state when 1.89 V < VCC1, VCC2 < 2.25 V and 1.05 V < VCC1, VCC2 < 1.71 V
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UNIT
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6.4 Thermal Information
ISO672xB
D (SOIC)
8 PINS
104.6
48.9
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
52.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.9
ψJB
52.1
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO6720B
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
71.2
19.3
51.9
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
15 pF, Input a 25-MHz 50% duty cycle
square wave
PD1
PD2
ISO6721B
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
72.7
36.35
36.35
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
15 pF, Input a 25-MHz 50% duty cycle
square wave
PD1
PD2
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6.6 Insulation Specifications
PARAMETER
VALUE
UNIT
8-D
TEST CONDITIONS
IEC 60664-1
CLR
CPG
External clearance(1)
Side 1 to side 2 distance through air
4
4
mm
mm
Side 1 to side 2 distance across package
surface
External creepage(1)
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
>17
>400
II
µm
V
According to IEC 60664-1
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I-IV
I-III
Overvoltage category
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
637
VPK
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test. See Figure 450
9-8
VRMS
VIOWM
Maximum isolation working voltage
DC voltage
637
VDC
VPK
VTEST = VIOTM , t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
4242
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6500 VPK
(qualification)
VIOSM
5000
≤ 5
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM
tm = 10 s
,
Method a: After environmental tests subgroup
1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 ×
VIORM , tm = 10 s
qpd
Apparent charge(4)
≤ 5
pC
Method b: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM
,
≤ 5
tini = 1 s; Vpd(m) = 1.5 × VIORM , tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~0.5
pF
Ω
> 1012
> 1011
> 109
2
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
40/125/21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST
1.2 × VISO , t = 1 s (100% production)
=
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) ISO672x is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to IEC Certified according to
62368-1, IEC 61010-1 and UL 1577 Component
Certified according to
EN 61010-1:2010/A1:2019
and EN 62368-1:2014
Certified according to DIN
VDE V 0884-11:2017- 01
Plan to certify according to
GB4943.1-2011
IEC 60601
Recognition Program
3000 VRMS (D-8) basic
insulation per EN
61010-1:2010/A1:2019 up
Maximum transient
isolation voltage, 4242
400 VRMS basic insulation
per CSA 62368-1:19
Basic insulation, Altitude ≤ to working voltage of 300
5000 m, Tropical Climate, VRMS (D-8)
VPK
;
Single protection,
3000 VRMS
Maximum repetitive peak and IEC 62368-1:2018,
isolation voltage, 637 VPK (pollution degree 2,
Maximum surge isolation material group III)
voltage, 5000 VPK
250 VRMS maximum
working voltage
3000 VRMS (D-8) basic
insulation per EN
62368-1:2014 up to
working voltage of 400
VRMS (D-8)
;
Certificate number:
40047657
Master contract number:
220991
File number: E181974
Certificate planned
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
D-8 PACKAGE
RθJA =104.6°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
See Figure 6-1
217.2
332
mA
mA
mA
mA
RθJA = 104.6°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
See Figure 6-1
IS
Safety input, output, or supply current (1)
RθJA = 104.6°C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C
See Figure 6-1
434.5
628.9
RθJA = 104.6°C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C
See Figure 6-1
RθJA = 104.6°C/W, TJ = 150°C, TA = 25°C
See Figure 6-2
PS
TS
Safety input, output, or total power (1)
Maximum safety temperature (1)
1195
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -4 mA; See Figure 7-1
IOL = 4 mA; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
VCCO - 0.4
V
VOL
0.4
V
V
(1)
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
V
V
VIH = VCCI (1) at INx
10
µA
µA
kV/us
IIL
Low-level input current
VIL = 0 V at INx
-10
50
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200 V
75
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 5 V ; See Figure 7-3
Ci
Input Capacitance (2)
2.8
pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720B
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.1
1.3
3.2
1.4
2.1
1.5
2.2
2.7
2.5
7.9
1.7
2.1
4.6
2.3
VI = VCCI (ISO6720B), VI = 0 V (ISO6720B with F
suffix)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
Supply current - AC signal
VI = 0V (ISO6720B), VI = VCC1 (ISO6720B with F
suffix)
3.1
mA
2.3
1 Mbps
3.2
3.6
3.6
9.5
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
50 Mbps
ISO6721B
VI = VCCI (ISO6721B); VI = 0 V (ISO6721B with F
suffix)
ICC1, ICC2
ICC1, ICC2
1.2
2.3
2.1
Supply current - DC signal
VI = 0 V (ISO6721B); VI = VCCI (ISO6721B with F
suffix)
3.5
mA
2.9
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.9
2.5
5.2
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
3.6
6.7
50 Mbps
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -2mA ; See Figure 7-1
IOL = 2mA ; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.2
V
VOL
0.2
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
µA
µA
-10
50
Common mode transient
immunity
CMTI
Ci
VI = VCC or 0 V, VCM = 1200 V
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 3.3 V ; See Figure
7-3
Input Capacitance(2)
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720B
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.1
1.3
3.2
1.4
2.1
1.4
2.2
2.3
2.4
6
1.6
2
VI = VCCI (ISO6720B), VI = 0 V (ISO6720B with F
suffix)
Supply current - DC signal
Supply current - DC signal
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
4.5
2.2
VI = 0V (ISO6720B), VI = VCC1 (ISO6720B with F
suffix)
3.1
mA
2.2
1 Mbps
3.1
3.2
3.4
7.3
All channels switching with square
10 Mbps
Supply current - AC signal
wave clock input; CL = 15 pF
50 Mbps
ISO6721B
VI = VCCI (ISO6721B); VI = 0 V (ISO6721B with F
suffix)
Supply current - DC signal
ICC1, ICC2
ICC1, ICC2
1.2
2.3
2.1
VI = 0 V (ISO6721B);
VI = VCCI (ISO6721B with F suffix)
Supply current - DC signal
Supply current - AC signal
3.5
mA
2.8
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.8
2.3
4.2
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
3.3
5.5
50 Mbps
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA ; See Figure 7-1
IOL = 1mA ; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.1
V
VOL
0.1
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
µA
µA
-10
50
Common mode transient
immunity
CMTI
Ci
VI = VCC or 0 V, VCM = 1200 V
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 2.5 V ; See Figure
7-3
Input Capacitance(2)
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720B
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.1
1.3
3.1
1.4
2.1
1.4
2.1
2
1.6
2
VI = VCCI (ISO6720B), VI = 0 V (ISO6720B with F
suffix)
Supply current - DC signal
Supply current - DC signal
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
4.5
2.2
VI = 0V (ISO6720B), VI = VCC1 (ISO6720B with F
suffix)
1 Mbps
1 Mbps
3.1
mA
2.2
10 Mbps
10 Mbps
50 Mbps
50 Mbps
3.1
2.9
3.3
6
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
2.3
4.8
ISO6721B
VI = VCCI (ISO6721B); VI = 0 V (ISO6721B with F
suffix)
Supply current - DC signal
ICC1, ICC2
ICC1, ICC2
1.2
2.3
2.1
VI = 0 V (ISO6721B); VI = VCCI (ISO6721B with F
suffix)
Supply current - DC signal
Supply current - AC signal
3.5
mA
2.8
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.8
2.1
3.6
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
3.2
4.9
50 Mbps
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6.15 Electrical Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA ; See Figure 7-1
IOL = 1mA ; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
VCCO - 0.1
V
VOL
0.1
V
V
(1)
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
V
V
VIH = VCCI (1) at INx
10
µA
µA
kV/us
IIL
Low-level input current
VIL = 0 V at INx
-10
50
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200 V
75
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 1.8 V ; See Figure
7-3
Ci
Input Capacitance(2)
2.8
pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.16 Supply Current Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6720B
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.8
1.2
2.8
1.3
1.8
1.3
1.8
1.8
2
1.5
2.1
4.3
2.2
VI = VCCI (ISO6720B), VI = 0 V (ISO6720B with F
suffix)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
Supply current - AC signal
VI = 0V (ISO6720B), VI = VCC1 (ISO6720B with F
suffix)
2.9
mA
2.2
1 Mbps
2.9
2.7
3.1
4.9
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
50 Mbps
3.8
ISO6721B
VI = VCCI (ISO6721B); VI = 0 V (ISO6721B with F
suffix)
ICC1, ICC2
ICC1, ICC2
1.1
2.1
2
Supply current - DC signal
VI = 0 V (ISO6721B); VI = VCCI (ISO6721B with F
suffix)
3.4
mA
2.7
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.6
1.9
3
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
3
50 Mbps
4.2
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6.17 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 7-1
18
8
ps/℃
ns
tUI
See Figure 7-1
See Figure 7-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.2
7
6
ns
Channel-to-channel output skew time
tsk(o)
Same direction channels
ns
(2)
tsk(p-p)
Part-to-part skew time (3)
Output signal rise time
6
4.5
ns
ns
ns
us
tr
2.6
2.6
See Figure 7-1
tf
Output signal fall time
4.5
tPU
Time from UVLO to valid output data
300
Default output delay time from input
power loss
Measured from the time VCC goes
below 1.2V. See Figure 7-2
tDO
tie
0.1
1
0.3
us
ns
Time interval error
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.18 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 7-1
18
9.2
ps/℃
ns
tUI
See Figure 7-1
See Figure 7-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.5
7
6
ns
Channel-to-channel output skew time
tsk(o)
Same direction channels
ns
(2)
tsk(p-p)
Part-to-part skew time (3)
Output signal rise time
6
3.2
ns
ns
ns
us
tr
1.6
1.6
See Figure 7-1
tf
Output signal fall time
3.2
tPU
Time from UVLO to valid output data
300
Default output delay time from input
power loss
Measured from the time VCC goes
below 1.2V. See Figure 7-2
tDO
tie
0.1
1
0.3
us
ns
Time interval error
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.19 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
12
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 7-1
20.5
14.3
ps/℃
ns
tUI
See Figure 7-1
See Figure 7-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.6
7.1
6
ns
Channel-to-channel output skew
time(2)
tsk(o)
Same direction channels
ns
tsk(p-p)
Part-to-part skew time(3)
Output signal rise time
Output signal fall time
6.1
4
ns
ns
ns
us
tr
2
2
See Figure 7-1
tf
4
tPU
Time from UVLO to valid output data
300
Default output delay time from input
power loss
Measured from the time VCC goes
below 1.2V. See Figure 7-2
tDO
tie
0.1
1
0.3
us
ns
Time interval error
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.20 Switching Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
15
MAX
UNIT
ns
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
See Figure 7-1
24
15.2
ps/℃
ns
tUI
See Figure 7-1
See Figure 7-1
20
PWD
Pulse width distortion(1) |tPHL – tPLH
|
0.7
8.2
6
ns
Channel-to-channel output skew
time(2)
tsk(o)
Same direction channels
ns
tsk(p-p)
Part-to-part skew time(3)
Output signal rise time
Output signal fall time
8.8
5.3
ns
ns
ns
us
tr
2.7
2.7
See Figure 7-1
tf
5.3
tPU
Time from UVLO to valid output data
300
Default output delay time from input
power loss
Measured from the time VCC goes
below 1.2V. See Figure 7-2
tDO
tie
0.1
1
0.3
us
ns
Time interval error
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.21 Insulation Characteristics Curves
650
Vcc = 5.5 V
Vcc = 3.6 V
Vcc = 2.75 V
600
550
500
450
400
350
300
250
200
150
100
50
Vcc = 1.89 V
0
0
20
40
60
80
100
120
140
160
Ambient Temperature (ꢀC)
Figure 6-1. Thermal Derating Curve for Safety
Limiting Current for D-8 Package
Figure 6-2. Thermal Derating Curve for Safety
Limiting Power for D-8 Package
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6.22 Typical Characteristics
7.5
4
3.5
3
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
6
4.5
3
ICC2 at 5 V
ICC2 at 5 V
2.5
2
1.5
0
1.5
1
0
10
20
30
40
50
0
10
20
30
40
50
Data Rate (Mbps)
Data Rate (Mbps)
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 6-3. ISO6720B Supply Current vs Data Rate Figure 6-4. ISO6720B Supply Current vs Data Rate
(With 15-pF Load)
(With No Load)
4.8
4
3
2.7
2.4
2.1
1.8
1.5
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
3.2
2.4
1.6
0.8
ICC2 at 5 V
ICC2 at 5 V
0
10
20
30
40
50
0
10
20
30
40
50
Data Rate (Mbps)
Data Rate (Mbps)
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 6-5. ISO6721B Supply Current vs Data Rate Figure 6-6. ISO6721B Supply Current vs Data Rate
(With 15-pF Load)
(With No Load)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
0
5
10
15
0
5
10
15
Low-Level Output Current (mA)
Low-Level Output Current (mA)
TA = 25°C
TA = 25°C
Figure 6-7. High-Level Output Voltage vs High-level Figure 6-8. Low-Level Output Voltage vs Low-Level
Output Current Output Current
1.6
1.575
1.55
15
14
13
12
11
10
9
1.525
1.5
1.475
1.45
1.425
1.4
VCC1
+
-
+
-
VCC1
VCC2
VCC2
tPHL at 1.8 V
tPLH at 1.8 V
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
tPHL at 5 V
tPLH at 5V
1.375
1.35
8
-55
-5
45
95
125
-55
-5
45
95
125
Free-Air Temperature (ꢀC)
Free-Air Temperature (ꢀC)
Figure 6-9. Power Supply Undervoltage Threshold
vs Free-Air Temperature
Figure 6-10. Propagation Delay Time vs Free-Air
Temperature
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7 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO
50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
=
Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
See Note B
V
CC
V
CC
V
1.4 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
Figure 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
V
OH
or V
OL
C
L
œ
See Note A
GNDI
GNDO
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-3. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO672xB family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices
also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 8-1, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 8-2 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
The ISO672xB family of devices is available in two channel configurations and default output state options to
enable a variety of application uses. Table 8-1 lists the device features of the ISO672xB devices.
Table 8-1. Device Features
MAXIMUM DATA
RATE
DEFAULT OUTPUT
STATE
PART NUMBER
CHANNEL DIRECTION
PACKAGE
RATED ISOLATION(1)
ISO6720B
ISO6720FB
ISO6721B
ISO6721FB
50 Mbps
50 Mbps
50 Mbps
50 Mbps
2 Forward, 0 Reverse
2 Forward, 0 Reverse
1 Forward, 1 Reverse
1 Forward, 1 Reverse
High
Low
High
Low
D-8
D-8
D-8
D-8
3000 VRMS / 4242 VPK
3000 VRMS / 4242 VPK
3000 VRMS / 4242 VPK
3000 VRMS / 4242 VPK
(1) See Safety-Related Certifications for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO672xB
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 8-2 lists the functional modes for the ISO672xB devices.
Table 8-2. Function Table
INPUT
(INx)(2)
OUTPUT
(OUTx)
(1)
VCCI
VCCO
COMMENTS
H
L
H
L
Normal Operation: A channel output assumes the logic state of the input.
PU
PU
Default mode: When INx is open, the corresponding channel output goes
to the default logic state. The default is High for ISO672xB and Low for
ISO672xB with F suffix.
Open
Default
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for ISO672xB
and Low for ISO672xB with F suffix.
PD
X
PU
PD
X
X
Default
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(3)
.
Undetermined
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.71V); PD = Powered down (VCC ≤ 1.05 V); X = Irrelevant;
H = High level; L = Low level
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.89 V < VCCI, VCCO < 2.25 V and 1.05 V < VCCI, VCCO < 1.71 V
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
V
V
V
CCI
V
CCI
CCI
CCI
V
V
V
CCI
CCI
CCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
Output
V
CCO
~20 ꢀ
OUTx
Figure 8-3. Device I/O Schematics
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant the accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO672xB devices are high-performance, dual-channel digital isolators. The devices use single-ended
CMOS-logic switching technology. The supply voltage range is from 1.71 V to 5.5 V for both supplies, VCC1
and VCC2. Since an isolation barrier separates the two sides, each side can be sourced independently with any
voltage within recommended operating conditions. As an example, it is possible to supply ISO672xB VCC1 with
3.3 V (which is within 1.71 V to 1.89 V and 2.25 V to 5 V) and VCC2 with 5 V (which is also within 1.71 V to
1.89 V and 2.25 V to 5 V). You can use the digital isolator as a logic-level translator in addition to providing
isolation. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, MCU or
FPGA), and a data converter or a line transceiver, regardless of the interface type or standard.
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9.2 Typical Application
For industrial applications, the ISO672xB device can be used with Texas Instruments' mixed signal
microcontroller, digital-to-analog converter, transformer driver, and voltage regulator to create an isolated 4-mA
to 20-mA current loop.
V
S
0.1 ꢀF
3.3 V
2
MBR0520L
1:1.33
3.3VISO
3
1
1
3
5
2
V
CC
D2
D1
IN
OUT
GND
10 ꢀF
TPS76333
SN6501
10 ꢀF 0.1 ꢀF
EN
GND
4, 5
10 ꢀF
MBR0520L
ISO Barrier
0.1 ꢀF
0.1 ꢀF
20 ꢁ
LOOP+
15
VA
3
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
VD
10
16
LOW
BASE
OUT
0.1 ꢀF 1 ꢀF
1
8
8
2
ERRLVL
V
V
CC1
CC2
DAC161P997
DV
CC
5
4
5
6
22 ꢁ
7
6
INA
OUTB
DBACK
DIN
11
12
2
3
XOUT
XIN
P3.0
P3.1
OUTA
INB
9
ISO6721B
MSP430G2132
LOOPœ
C1 C2 C3 COMA COMD
GND1
GND2
5
14 13 12
1
2
DV
SS
3 × 2.2 nF
4
4
Figure 9-1. Isolated 4-mA to 20-mA Current Loop
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
1.71 V to 1.89 V and 2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO672xB devices only require two external bypass capacitors to operate.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
VCC2
VCC1
GND1
GND2
1
8
0.1uF
0.1 µF
2
3
7
6
INA
OUTA
INB
OUTB
GND2
GND1
5
4
Figure 9-2. Typical ISO672xB Circuit Hook-up
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9.2.3 Application Curve
The following typical eye diagrams of the ISO672xB family of devices indicate low jitter and wide open eye at the
maximum data rate of 50 Mbps.
Time = 5 ns / div
Figure 9-4. Eye Diagram at 50 Mbps PRBS 216 – 1,
3.3 V and 25°C
Time = 5 ns / div
Figure 9-3. Eye Diagram at 50 Mbps PRBS 216 – 1,
5 V and 25°C
Time = 5 ns / div
Figure 9-5. Eye Diagram at 50 Mbps PRBS 216 – 1,
2.5 V and 25°C
Time = 5 ns / div
Figure 9-6. Eye Diagram at 50 Mbps PRBS 216 – 1,
1.8 V and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 9-7 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For basic insulation,
VDE standard requires the use of TDDB projection line with failure rate of less than 1000 part per million (ppm).
For reinforced insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1
part per million (ppm).
Even though the expected minimum insulation lifetime is 20 years, at the specified working isolation voltage,
VDE basic and reinforced certifications require additional safety margin of 20% for working voltage. For basic
certification, device lifetime requires a safety margin of 30% translating to a minimum required insulation lifetime
of 26 years at a working voltage that is 20% higher than the specified value.
Figure 9-8 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 450 VRMS with a lifetime of >100 years in
the 8D package . Other factors, such as package size, pollution degree, material group, etc. can further limit the
working voltage of the component. At the lower working voltages, the corresponding insulation lifetime is much
longer than 100 years in the 8-D package.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 9-7. Test Setup for Insulation Lifetime Measurement
87.5 %
1.E+11
>>100Yrs
1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
Operating Zone
TDDB Line (< 1000 ppm Fail Rate)
VDE Safety Margin Zone
20%
0
1000
2000
3000
4000
5000
6000
7000
8000
Applied Voltage (VRMS
)
TA upto 150 oC
Operating Life Time = >>100 Years
Stress Voltage Frequency = 60 Hz
Isolation Working Voltage = 450 VRMS
Figure 9-8. Insulation Lifetime Projection Data
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10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply
pins as possible. If only a single primary-side power supply is available in an application, isolated power
can be generated for the secondary-side with the help of a transformer driver. For industrial applications,
please use Texas Instruments' SN6501 or SN6505B. For such applications, detailed power supply design
and transformer selection recommendations are available in SN6501 Transformer Drivers for Isolated Power
Supplies or SN6505B-Q1 Low-noise, 1-A Transformer Drivers for Isolated Power Supplies.
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11 Layout
11.1 Layout Guidelines
A minimum of two layers is required to accomplish a cost optimized and low EMI PCB design. To further improve
EMI, a four layer board can be used (see Section 11.2). Layer stacking for a four layer board should be in the
following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal
layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
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11.2 Layout Example
Solid supply islands reduce
inductance because large peak
currents flow into the VCC pin
2 mm
maximum
from VCC1
2 mm
maximum
from VCC2
VCC1
VCC2
1
8
2
3
4
7
6
5
0.1 …F
0.1 …F
GND2
GND1
Solid ground islands help
dissipate heat through PCB
Figure 11-1. Layout Example
High-speed traces
Ground plane
10 mils
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
r
Power plane
10 mils
Low-speed traces
Figure 11-2. Four Layer Board Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, refer to:
•
•
•
•
Isolated CAN Flexible Data (FD) Rate Repeater Reference Design
Isolated 16-Channel AC Analog Input Module Reference Design Using Dual Simultaneously Sampled ADCs
Polyphase Shunt Metrology with Isolated AFE Reference Design
Reference Design for Power-Isolated Ultra-Compact Analog Output Module
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
•
•
•
•
•
•
Texas Instruments, Isolation Glossary
Texas Instruments, Enabling high voltage signal isolation quality and reliability
Texas Instruments, DAC161P997 Single-Wire 16-bit DAC for 4- to 20-mA Loops data sheet
Texas Instruments, MSP430G2132 Mixed Signal Microcontroller data sheet
Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, TPS76333 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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13.1 Package Option Addendum
Packaging Information
Orderable
Device
Status(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan(2)
Lead/Ball
Finish(6)
MSL Peak
Op Temp (°C) Device
Marking(4) (5)
Temp(3)
ACTIVE
SOIC
D
8
3000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
6720B
ISO6720BDR
ISO6720FBDR
NIPDAU
Level-2-260C-1 -40 to 125
YEAR
6720FB
ACTIVE
SOIC
D
8
3000
Green (RoHS &
no Sb/Br)
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
3000
3000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
6721B
ISO6721BDR
ISO6721FBDR
NIPDAU
Level-2-260C-1 -40 to 125
YEAR
6721FB
Green (RoHS &
no Sb/Br)
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13.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
P1 Pitch between successive cavity centers
W
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
ISO6720BDR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
3000
3000
3000
3000
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
ISO6720FBDR
ISO6721BDR
ISO6721FBDR
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
Length (mm) Width (mm)
Height (mm)
43.0
ISO6720BDR
SOIC
D
D
D
D
8
8
8
8
3000
350.0
350.0
350.0
350.0
ISO6720FBDR
43.0
SOIC
SOIC
SOIC
3000
3000
3000
ISO6721BDR
350.0
350.0
350.0
350.0
43.0
43.0
ISO6721FBDR
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PACKAGE OPTION ADDENDUM
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11-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO6720BDR
ISO6720FBDR
ISO6721BDR
ISO6721FBDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
6720B
NIPDAU
NIPDAU
NIPDAU
6720FB
6721B
6721FB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Jul-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO6720, ISO6721 :
Automotive : ISO6720-Q1, ISO6721-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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12-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO6720BDR
ISO6720FBDR
ISO6721BDR
ISO6721FBDR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
3000
3000
3000
3000
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO6720BDR
ISO6720FBDR
ISO6721BDR
ISO6721FBDR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
3000
3000
3000
3000
853.0
853.0
853.0
853.0
449.0
449.0
449.0
449.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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