ISO6742FQDWRQ1 [TI]
ISO674x-Q1 General-Purpose Reinforced Quad-Channel Automotive Digital Isolators with Robust EMC;
| 型号： | ISO6742FQDWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ISO674x-Q1 General-Purpose Reinforced Quad-Channel Automotive Digital Isolators with Robust EMC |
| 文件： | 总46页 (文件大小：3358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO6740-Q1, ISO6741-Q1, ISO6742-Q1
SLLSFG4A – AUGUST 2020 – REVISED JANUARY 2021
ISO674x-Q1 General-Purpose Reinforced Quad-Channel Automotive Digital Isolators
with Robust EMC
1 Features
3 Description
•
AEC-Q100 qualified with the following results:
– Device temperature Grade 1: –40°C to +125°C
ambient operating temperature range
Meets VDA320 isolation requirements
50 Mbps data rate
The ISO674x-Q1 devices are high-performance,
quad-channel digital isolators ideal for cost-sensitive
applications requiring up to 5000 VRMS isolation
ratings per UL 1577. These devices are also certified
by VDE, TUV, CSA, and CQC.
•
•
•
Robust isolation barrier:
The
ISO674x-Q1
devices
provide
high
electromagnetic immunity and low emissions at low
power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by TI's double
capacitive silicon dioxide (SiO2) insulation barrier.
These devices come with enable pins which can be
used to put the respective outputs in high impedance
for multi-master driving applications. The ISO6741-Q1
device has three forward and one reverse-direction
channels. In the event of input power or signal loss,
the default output is high for devices without suffix F
and low for devices with suffix F. See Device
Functional Modes section for further details.
– High lifetime at 1060 VRMS working voltage
– Up to 5000 VRMS isolation rating
– Up to 10 kV surge capability
– ±75 kV/μs typical CMTI
Wide supply range: 1.71 V to 1.89 V and 2.25 V to
5.5 V
1.71 V to 5.5 V level translation
Default output high (ISO674x-Q1) and low
(ISO674xF-Q1) options
1.6 mA per channel typical at 1 Mbps
Low propagation delay: 11 ns typical
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Low emissions
•
•
•
•
•
•
Used in conjunction with isolated power supplies,
these devices help prevent noise currents on data
buses, such as CAN and LIN from damaging sensitive
circuitry. Through innovative chip design and layout
techniques, the electromagnetic compatibility of the
ISO674x-Q1 devices has been significantly enhanced
to ease system-level ESD, EFT, surge, and emissions
compliance. The ISO674x-Q1 family of devices is
available in a 16-pin SOIC wide-body (DW) package
and is a pin-to-pin upgrade to the older generations.
•
•
Wide-SOIC (DW-16) Package
Safety-Related Certifications (pending):
– DIN V VDE 0884-11:2017-01
– UL 1577 component recognition program
– IEC 60950-1, IEC 62368-1, IEC 61010-1,
IEC60601-1 and GB 4943.1-2011 certifications
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
2 Applications
ISO6740-Q1, ISO6740F-Q1 SOIC (DW)
ISO6741-Q1, ISO6741F-Q1
ISO6742-Q1, ISO6742F-Q1
10.30 mm × 7.50 mm
•
Hybrid, electric and power train system (EV/HEV)
– Battery management system (BMS)
– On-board charger
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Traction inverter
– DC/DC converter
– Inverter and motor control
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
ISO6740-Q1, ISO6741-Q1, ISO6742-Q1
SLLSFG4A – AUGUST 2020 – REVISED JANUARY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................7
6.5 Power Ratings ............................................................7
6.6 Insulation Specifications ............................................ 8
6.7 Safety-Related Certifications ..................................... 9
6.8 Safety Limiting Values ................................................9
6.9 Electrical Characteristics—5-V Supply .................... 10
6.10 Supply Current Characteristics—5-V Supply .........10
6.11 Electrical Characteristics—3.3-V Supply ................12
6.12 Supply Current Characteristics—3.3-V Supply ......12
6.13 Electrical Characteristics—2.5-V Supply .............. 14
6.14 Supply Current Characteristics—2.5-V Supply ......14
6.15 Electrical Characteristics—1.8-V Supply ............... 16
6.16 Supply Current Characteristics—1.8-V Supply ......16
6.17 Switching Characteristics—5-V Supply ..................18
6.18 Switching Characteristics—3.3-V Supply ...............19
6.19 Switching Characteristics—2.5-V Supply ...............20
6.20 Switching Characteristics—1.8-V Supply ...............21
6.21 Insulation Characteristics Curves........................... 22
6.22 Typical Characteristics............................................23
7 Parameter Measurement Information..........................24
8 Detailed Description......................................................26
8.1 Overview...................................................................26
8.2 Functional Block Diagram.........................................26
8.3 Feature Description...................................................27
8.4 Device Functional Modes..........................................28
9 Application and Implementation..................................29
9.1 Application Information............................................. 29
9.2 Typical Application.................................................... 29
10 Power Supply Recommendations..............................33
11 Layout...........................................................................34
11.1 Layout Guidelines................................................... 34
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Documentation Support.......................................... 36
12.2 Receiving Notification of Documentation Updates..36
12.3 Support Resources................................................. 36
12.4 Trademarks.............................................................36
12.5 Electrostatic Discharge Caution..............................36
12.6 Glossary..................................................................36
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
13.1 Package Option Addendum....................................37
13.2 Tape and Reel Information......................................38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 2020) to Revision A (January 2021)
Page
•
Added ISO674x-Q1 to APL data sheet. .............................................................................................................1
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5 Pin Configuration and Functions
VCC1
GND1
INA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
OUTD
EN2
INB
INC
IND
NC
GND1
GND2
Not to scale
Figure 5-1. ISO6740-Q1 DW Package 16-Pin SOIC-WB Top View
VCC1
GND1
INA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
IND
INB
INC
OUTD
EN1
EN2
GND1
GND2
Not to scale
Figure 5-2. ISO6741-Q1 DW Package 16-Pin SOIC-WB Top View
VCC1
GND1
INA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
INB
OUTC
OUTD
EN1
IND
EN2
GND1
GND2
Not to scale
Figure 5-3. ISO6742-Q1 DW Package 16-Pin SOIC-WB Top View
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Pin Functions
PIN
I/O
DESCRIPTION
NAME
ISO6740-Q1
ISO6741-Q1
ISO6742-Q1
Output enable 1. Output pins on side 1 are enabled when EN1
is high or open and in high-impedance state when EN1 is low.
For ISO6740, this pin needs to be floating.
EN1
-
7
7
I
I
Output enable 2. Output pins on side 2 are enabled when EN2
is high or open and in high-impedance state when EN2 is low.
EN2
10
10
10
GND1
GND2
INA
2, 8
9, 15
3
2,8
9,15
3
2,8
9,15
3
—
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
—
I
I
I
I
INB
4
4
4
Input, channel B
INC
5
5
12
11
-
Input, channel C
IND
6
11
-
Input, channel D
NC
7
Not connected
OUTA
OUTB
OUTC
OUTD
VCC1
VCC2
14
13
12
11
1
14
13
12
6
14
13
5
O
O
Output, channel A
Output, channel B
Output, channel C
Output, channel D
Power supply, side 1
Power supply, side 2
O
6
O
1
1
—
—
16
16
16
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6 Specifications
6.1 Absolute Maximum Ratings
See(1)
MIN
MAX
UNIT
Supply voltage (2) VCC1, VCC2
-0.5
6
V
Voltage at INx,
V
-0.5
-15
VCCX + 0.5 (3)
V
OUTx, ENx
Output current
Temperature
Io
15
150
150
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
-65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±6000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
V(ESD)
Electrostatic discharge
±1500
±8000
V
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
2.25
1.71
2.25
NOM
MAX
1.89
5.5
UNIT
(1)
VCC1
VCC1
VCC2
VCC2
Supply Voltage Side 1
Supply Voltage Side 1
Supply Voltage Side 2
Supply Voltage Side 2
VCC = 1.8 V
V
V
V
V
(1)
(1)
(1)
VCC = 2.5 V to 5 V
VCC = 1.8 V
1.89
5.5
VCC = 2.5 V to 5 V
Vcc (UVLO
+)
UVLO threshold when supply voltage is rising
UVLO threshold when supply voltage is falling
Supply voltage UVLO hysteresis
1.53
1.41
0.13
1.71
V
V
V
V
Vcc
(UVLO-)
1.1
Vhys
(UVLO)
0.08
0.7 x VCC(2I)
VIH
VIL
High level Input voltage
VCCI
Low level Input voltage
VCCO = 5 V (2)
0
-4
-2
-1
-1
0.3 x VCCI
V
mA
mA
mA
mA
mA
mA
mA
mA
Mbps
°C
VCCO = 3.3 V
High level output current
IOH
VCCO = 2.5 V
VCCO = 1.8 V
VCCO = 5 V
4
2
VCCO = 3.3 V
Low level output current
IOL
VCCO = 2.5 V
1
VCCO = 1.8 V
1
DR
TA
Data Rate
0
50
125
Ambient temperature
-40
25
(1) VCC1 and VCC2 can be set independent of one another
(2) VCCI = Input-side VCC; VCCO = Output-side VCC
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6.4 Thermal Information
ISO674x
THERMAL METRIC(1)
DW (SOIC)
16 PINS
73
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
36.1
40.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17
ψJB
39.9
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO6740
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
130.9
33
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
PD1
PD2
97.9
ISO6741
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
134.9
50.8
84.1
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
PD1
PD2
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UNIT
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6.6 Insulation Specifications
VALUE
DW-16
PARAMETER
TEST CONDITIONS
CLR
CPG
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
>8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
>8
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
>17
>600
I
um
V
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage category per IEC 60664-1
DIN VDE V 0884-11:2017-01 (2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
1060
1500
VPK
VRMS
VDC
AC voltage; Time dependent dielectric breakdown
(TDDB) Test; See Figure 9-8
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM
t = 60 s (qualification);
VTEST = 1.2 x VIOTM
,
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
7071
VPK
,
t= 1 s (100% production)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM (qualification)
VIOSM
6250
≤5
VPK
Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 x VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 x VIORM, tm = 10 s
≤5
≤5
qpd
Apparent charge(4)
pC
Method b; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 x VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance(5)
VIO = 0.4 x sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~1
pF
Ω
>1012
>1011
>109
2
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
40/125/21
UL 1577
VISO
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 x VISO , t = 1 s (100% production)
Maximum withstanding isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Plan to certify according to
EN 61010-1:2010/
A1:2019, EN
60950-1:2006/A2:2013
and EN 62368-1:2014
Plan to certify according to Plan to certify according to Plan to certify according to
Plan to certify according to
GB4943.1-2011
DIN VDE V 0884-11:2017- IEC 60950-1 and IEC
UL 1577 Component
Recognition Program
01
62368-1
5000 VRMS insulation per
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Maximum transient
isolation voltage,
5000 VRMS insulation per
EN 61010-1:2010 (3rd Ed)
up to working voltage of
600 VRMS
5000 VRMS insulation per
EN 60950- 1:2006/
7071 VPK
;
Reinforced insulation,
Altitude ≤ 5000 m, Tropical
Climate,
700 VRMS maximum
working voltage
Ed.+A1+A2, CSA
Maximum repetitive peak
isolation voltage, 1500
62368-1- 14 and IEC
62368-1:2014 800 VRMS
(DW-16) maximum
working voltage (pollution
degree 2, material group I)
Single protection,
5000 VRMS
VPK
;
Maximum surge isolation
voltage,
6250 VPK
A2:2013 up to working
voltage of 800 VRMS
Certificate planned
Certificate planned
Certificate planned
Certificate planned
Certificate planned
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW-16 PACKAGE
RθJA =73°C/W, VI = 5.5 V, TJ = 150°C, TA
= 25°C
311.4
475.7
622
mA
RθJA = 73°C/W, VI = 3.6 V, TJ = 150°C, TA
= 25°C
IS
Safety input, output, or supply current
mA
RθJA = 73°C/W, VI = 2.75 V, TJ = 150°C,
TA = 25°C
RθJA = 73°C/W, VI = 1.89 V, TJ = 150°C,
TA = 25°C
905.1
mA
PS
TS
Safety input, output, or total power
Maximum safety temperature
RθJA = 73°C/W, TJ = 150°C, TA = 25°C
1712.4
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -4 mA; See Figure 7-1
IOL = 4 mA; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
VCCO - 0.4 (1)
V
0.4
V
V
(1)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
V
V
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
28
µA
µA
uA
uA
IIL
Low-level input current
-10
IIH
High-level input current
VIH = VCCI (1) at ENx
IIL
Low-level input current
VIL = 0 V at ENx
-28
50
VI = VCC or 0 V, VCM = 1200 V;
See Figure 7-4
CMTI
Ci
Common mode transient immunity
Input Capacitance (2)
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 5 V
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6740
TEST CONDITIONS
MIN
TYP
MAX UNIT
VI = VCC1 (1)(ISO6740); VI = 0 V (ISO6740 with F
suffix)
ICC1
1.6
2.1
5.8
2.3
3.7
2.4
3.8
4.8
4.4
15
2.2
3.4
8
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
(2)
VI = 0 V (ISO6740); VI = VCC1 (ISO6740 with F suffix)
1 Mbps
3.7
5.1
mA
3.8
5.3
6.4
6
Supply current - AC signal All channels switching with square
10 Mbps
50 Mbps
(3)
wave clock input; CL = 15 pF
17.8
ISO6741
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.9
2.2
5.1
3.4
3.6
3
2.8
3.5
7.2
5.1
VI = VCCI (1)(ISO6741); VI = 0 V (ISO6741 with F suffix)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
Supply current - DC signal
(2)
5.1
mA
4.5
4.2
4.8
7.3
12.6
5.8
6.5
Supply current - AC signal All channels switching with square
10 Mbps
50 Mbps
(3)
wave clock input; CL = 15 pF
9.3
15.3
(1) VCCI = Input-side VCC
(2) Supply current valid for ENx = VCCx and ENx = 0V
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(3) Supply current valid for ENx = VCCx
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -2mA; See Figure 7-1
IOL = 2mA; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.2 (1)
V
VOL
0.2
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
IIH
IIL
High-level input current
Low-level input current
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
30
µA
µA
uA
uA
-10
VIH = VCCI (1) at ENx
VIL = 0 V at ENx
-30
50
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; See Figure 7-4
CMTI
Ci
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 3.3 V
Input Capacitance (2)
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6740
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.6
2.1
5.7
2.3
3.7
2.4
3.8
4
2.2
3.3
8
EN2 = VCC2; VI = VCC1 (ISO6740); VI = 0 V (ISO6740
with F suffix)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO6740); VI = VCC1 (ISO6740
with F suffix)
3.6
5.1
mA
3.7
1 Mbps
10 Mbps
10 Mbps
50 Mbps
50 Mbps
5.2
5.6
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
4.2
11.2
5.7
13.8
ISO6741
VI = VCCI (1)(ISO6741); VI = 0 V (ISO6741 with F
suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.9
2.2
5
2.7
3.4
7.1
5.1
Supply current - DC signal
(2)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
3.4
3.5
2.9
4
5
mA
4.4
5.5
5.8
8
Supply current - AC signal All channels switching with square
10 Mbps
50 Mbps
(3)
wave clock input; CL = 15 pF
4.2
6.1
9.7
12.1
(1) VCCI = Input-side VCC
(2) Supply current valid for ENx = VCCx and ENx = 0V
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(3) Supply current valid for ENx = VCCx
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA; See Figure 7-1
IOL = 1mA; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
VCCO - 0.1 (1)
V
VOL
0.1
V
V
V
(1)
VIT+(IN)
VIT-(IN)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
Input threshold voltage
hysteresis
VI(HYS)
V
IIH
IIL
IIH
IIL
High-level input current
Low-level input current
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
30
µA
µA
uA
uA
-10
VIH = VCCI (1) at ENx
VIL = 0 V at ENx
-30
50
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; See Figure 7-4
CMTI
Ci
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 2.5 V
Input Capacitance (2)
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6740
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.6
2.1
5.7
2.3
3.7
2.3
3.7
3.5
4.1
9
2.2
3.3
7.9
3.6
EN2 = VCC2; VI = VCC1 (ISO6740); VI = 0 V (ISO6740
with F suffix)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO6740); VI = VCC1 (ISO6740
with F suffix)
5.1
mA
3.6
1 Mbps
10 Mbps
10 Mbps
50 Mbps
50 Mbps
5.1
5.1
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
5.6
11.2
ISO6741
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.9
2.2
5
2.7
3.4
7.1
5.1
VI = VCCI (1)(ISO6741); VI = 0 V (ISO6741 with F suffix)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
Supply current - DC signal
(2)
3.4
3.5
2.9
3.9
3.8
5.5
8.1
5
mA
4.4
5.4
5.4
Supply current - AC signal All channels switching with square
10 Mbps
50 Mbps
(3)
wave clock input; CL = 15 pF
7.2
10.2
(1) VCCI = Input-side VCC
(2) Supply current valid for ENx = VCCx and ENx = 0V
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(3) Supply current valid for ENx = VCCx
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6.15 Electrical Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA; See Figure 7-1
IOL = 1mA; See Figure 7-1
MIN
TYP
MAX UNIT
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
High-level output voltage
Low-level output voltage
Rising input switching threshold
Falling input switching threshold
Input threshold voltage hysteresis
High-level input current
VCCO - 0.1 (1)
V
0.1
V
V
(1)
0.7 x VCCI
0.3 x VCCI
0.1 x VCCI
V
V
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
30
µA
µA
µA
µA
IIL
Low-level input current
-10
IIH
High-level input current
VIH = VCCI (1) at ENx
IIL
Low-level input current
VIL = 0 V at ENx
-30
50
VI = VCC or 0 V, VCM = 1200 V;
See Figure 7-4
CMTI
Ci
Common mode transient immunity
Input Capacitance (2)
75
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 1.8 V
2.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.16 Supply Current Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO6740
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.2
2
1.8
3.4
7.6
3.7
EN2 = VCC2; VI = VCC1 (ISO6740); VI = 0 V (ISO6740
with F suffix)
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
5.1
2.2
3.1
2.2
3.2
3.1
3.4
7
EN2 = VCC2; VI = 0 V (ISO6740); VI = VCC1 (ISO6740
with F suffix)
4.7
mA
3.7
1 Mbps
10 Mbps
10 Mbps
50 Mbps
50 Mbps
4.8
4.6
5.1
8.9
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
ISO6741
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.5
2
2.4
3.4
6.9
5
VI = VCCI (1)(ISO6741); VI = 0 V (ISO6741 with F suffix)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
Supply current - DC signal
(2)
4.5
3.2
3.1
2.7
3.3
3.4
4.5
6.4
4.7
mA
4.3
5
5
Supply current - AC signal All channels switching with square
10 Mbps
50 Mbps
(3)
wave clock input; CL = 15 pF
6.3
8.3
(1) VCCI = Input-side VCC
(2) Supply current valid for ENx = VCCx and ENx = 0V
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(3) Supply current valid for ENx = VCCx
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6.17 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
11
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
18
7
ns
ns
ns
ns
ns
ns
@100kbps
See Figure 7-1
|
0.2
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
6
6
Output signal rise time
2.6
2.6
4.5
4.5
See Figure 7-1
See Figure 7-2
tf
Output signal fall time
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
tPZH
tPZL
18.6
18.6
14.2
14.2
25.8
25.8
21.1
ns
ns
ns
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output for ISO674x
Enable propagation delay, high impedance-to-low
output for ISO674x
21.1
300
0.3
ns
us
us
ns
Time from UVLO to valid output data
Default output delay time from input power loss
Time interval error
tPU
Measured from the time VCC goes
below 1.2V. See Figure 7-3
tDO
0.1
1
tie
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
11
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
18
7
ns
ns
ns
ns
ns
ns
@100kbps
See Figure 7-1
|
0.5
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
6
7
Output signal rise time
1.6
1.6
3.2
3.2
See Figure 7-1
See Figure 7-2
tf
Output signal fall time
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
tPZH
tPZL
23.2
23.2
16.6
16.6
34.4
34.4
23
ns
ns
ns
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output for ISO674x
Enable propagation delay, high impedance-to-low
output for ISO674x
23
300
0.3
ns
us
us
ns
Time from UVLO to valid output data
Default output delay time from input power loss
Time interval error
tPU
Measured from the time VCC goes
below 1.2V. See Figure 7-3
tDO
0.1
1
tie
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.19 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
12
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
20.5
7.1
6
ns
ns
ns
ns
ns
ns
@100kbps
See Figure 7-1
|
0.6
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
7
Output signal rise time
2
2
4
See Figure 7-1
See Figure 7-2
tf
Output signal fall time
4
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
tPZH
tPZL
28.1
28.1
20.4
20.4
43
43
ns
ns
ns
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output for ISO674x
36.3
Enable propagation delay, high impedance-to-low
output for ISO674x
36.3
300
0.3
ns
us
us
ns
Time from UVLO to valid output data
Default output delay time from input power loss
Time interval error
tPU
Measured from the time VCC goes
below 1.2V. See Figure 7-3
tDO
0.1
1
tie
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.20 Switching Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
15
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
24
8.2
6
ns
ns
ns
ns
ns
ns
@100kbps
See Figure 7-1
|
0.7
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
8.8
5.3
5.3
Output signal rise time
2.7
2.7
See Figure 7-1
See Figure 7-2
tf
Output signal fall time
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
tPZH
tPZL
40.3
40.3
30
63
63
ns
ns
ns
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output for ISO674x
51.4
Enable propagation delay, high impedance-to-low
output for ISO674x
30
51.4
300
0.3
ns
us
us
ns
Time from UVLO to valid output data
Default output delay time from input power loss
Time interval error
tPU
Measured from the time VCC goes
below 1.2V. See Figure 7-3
tDO
0.1
1
tie
216 – 1 PRBS data at 50 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.21 Insulation Characteristics Curves
1000
1800
1600
1400
1200
1000
800
600
400
200
0
Vcc = 5.5 V
Vcc = 3.6 V
Vcc = 2.75 V
Vcc = 1.89 V
800
600
400
200
0
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
Ambient Temperature (ꢀC)
Ambient Temperature (ꢀC)
Figure 6-1. Thermal Derating Curve for Safety
Limiting Current for DW-16 Package
Figure 6-2. Thermal Derating Curve for Safety
Limiting Power for DW-16 Package
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6.22 Typical Characteristics
10.5
9
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
7.5
6
ICC2 at 5 V
4.5
3
1.5
0
10
20
30
40
50
Data Rate (Mbps)
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 6-3. ISO6741-Q1 Supply Current vs Data
Rate (With 15-pF Load)
Figure 6-4. ISO6741-Q1 Supply Current vs Data
Rate (With No Load)
8
0.8
VCC1 at 1.8 V
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
7
6
5
4
3
2
1
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-15
-10
-5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
TA = 25°C
TA = 25°C
Figure 6-5. High-Level Output Voltage vs High-level Figure 6-6. Low-Level Output Voltage vs Low-Level
Output Current Output Current
1.625
1.6
17
16
15
14
13
12
11
10
9
1.575
1.55
1.525
1.5
1.475
1.45
1.425
1.4
1.375
1.35
1.325
1.3
VCC1 +
VCC1 -
VCC2 +
VCC2 -
tPHL at 1.8 V
tPLH at 1.8 V
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
tPHL at 5 V
tPLH at 5 V
8
1.275
7
-55
-5
45
95
125
-55
-5
45
95
125
Free-Air Temperature (ꢀC)
Free-Air Temperature (ꢀC)
Figure 6-7. Power Supply Undervoltage Threshold
vs Free-Air Temperature
Figure 6-8. Propagation Delay Time vs Free-Air
Temperature
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7 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input
Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50
Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
CCO
V
CC
R
L
= 1 kꢀ 1%
V
/ 2
CC
V
/ 2
CC
V
I
IN
OUT
0 V
V
0 V
O
t
t
PLZ
PZL
V
OH
EN
0.5 V
V
V
O
50%
C
L
OL
See Note B
Input
Generator
(See Note A)
V
I
50 ꢀ
V
CC
V
O
IN
OUT
3 V
V / 2
CC
V
/ 2
CC
V
I
0 V
t
PZH
EN
See Note B
R
L
= 1 kꢀ 1%
V
OH
C
L
50%
Input
Generator
(See Note A)
0.5 V
V
O
V
I
0 V
t
50 ꢀ
PHZ
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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V
I
See Note B
V
CC
V
CC
V
1.4 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
Figure 7-3. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
C
L
V
or V
OL
OH
See Note A
œ
GNDO
GNDI
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-4. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO674x-Q1 family of devices have an ON-OFF keying (OOK) modulation scheme to transmit the digital
data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the
barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the
ENx pin is low then the output goes to high impedance. The ISO674x-Q1 devices also incorporate advanced
circuit techniques to maximize the CMTI performance and minimize the radiated emissions due to the high
frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure
8-1, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 8-2 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
Table 8-1 provides an overview of the device features.
Table 8-1. Device Features
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PART NUMBER
ISO6740-Q1
ISO6740F-Q1
ISO6741-Q1
ISO6741F-Q1
ISO6742-Q1
ISO6742F-Q1
CHANNEL DIRECTION
PACKAGE
DW-16
DW-16
DW-16
DW-16
DW-16
DW-16
RATED ISOLATION(1)
5000 VRMS / 8000 VPK
5000 VRMS / 8000 VPK
5000 VRMS / 8000 VPK
5000 VRMS / 8000 VPK
5000 VRMS / 8000 VPK
5000 VRMS / 8000 VPK
4 Forward,
0 Reverse
50 Mbps
50 Mbps
50 Mbps
50 Mbps
50 Mbps
50 Mbps
High
Low
High
Low
High
Low
4 Forward,
0 Reverse
3 Forward,
1 Reverse
3 Forward,
1 Reverse
2 Forward,
2 Reverse
2 Forward,
2 Reverse
(1) See for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 25. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO674x-
Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 8-2 lists the functional modes for the ISO674x-Q1 devices.
Table 8-2. Function Table
OUTPUT
ENABLE
(ENx)
INPUT
OUTPUT
(OUTx)
(1)
VCCI
VCCO
COMMENTS
(INx) (3)
H
L
H or open
H or open
H
L
Normal Operation: A channel output assumes the logic state of its
input.
PU
X
PU
PU
PU
Default mode: When INx is open, the corresponding channel output
goes to its default logic state. Default is High for ISO674x-Q1 and
Low for ISO674x-Q1 with F suffix.
Open
X
H or open
L
Default
Z
A low value of output enable causes the outputs to be high-
impedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is High
for ISO674x-Q1 and Low for ISO674x-Q1 with F suffix. When VCCI
transitions from unpowered to powered-up, a channel output assumes
the logic state of the input. When VCCI transitions from powered-up to
unpowered, channel output assumes the selected default state.
PD
X
X
H or open
Default
When VCCO is unpowered, a channel output is undetermined(2). When
Undetermined VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
X
PD
X
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.71 V); PD = Powered down (VCC ≤ 1.05 V); X = Irrelevant;
H = High level; L = Low level ; Z = High Impedance
(2) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V and 1.05 V < VCCI, VCCO < 1.71 V
(3) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
V
V
V
CCI
V
CCI
CCI
CCI
V
V
V
CCI
CCI
CCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
Output
Enable
V
CCO
V
V
V
CCI
V
CCI
CCI
CCI
550 kꢀ
~20 ꢀ
20 kꢀ
985 ꢀ
OUTx
INx
Figure 8-3. Device I/O Schematics
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO674x-Q1 devices are high-performance, quad-channel digital isolators. These devices come with enable
pins on each side which can be used to put the respective outputs in high impedance for multi master driving
applications. The ISO674x-Q1 devices use single-ended CMOS-logic switching technology. The supply voltage
range is from 1.71 V to 5.5 V for both supplies, VCC1 and VCC2. Since an isolation barrier separates the two
sides, each side can be sourced independently with any voltage within recommended operating conditions. As
an example, it is possible to supply ISO674x-Q1 VCC1 with 3.3 V (which is within 1.71 V to 5.5 V) and VCC2 with
5V (which is also within 1.71 V to 5.5 V). You can use the digital isolator as a logic-level translator in addition to
providing isolation. When designing with digital isolators, keep in mind that because of the single-ended design
structure, digital isolators do not conform to any specific interface standard and are only intended for isolating
single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that
is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
Figure 9-1 shows ISO6741-Q1 in a belt starter generator application.
48 V Side
12 V Side
WAKE
nSTB
MCU
TMS570
EN TCAN1043
ISO6741-Q1
CANH
CANL
TXD
RXD
Figure 9-1. Belt Starter Generator Application
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
1.71 V to 1.89 V and 2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO674x-Q1 family of devices only require two external bypass capacitors to operate.
2 mm maximum
from VCC1
2 mm maximum
from VCC2
0.1 µF
0.1 µF
VCC2
VCC1
1
16
GND1
GND2
2
3
15
14
INA
INB
INC
OUTA
OUTB
OUTC
13
4
12
11
10
9
5
6
7
8
IND
OUTD
EN2
EN1
GND2
GND1
Figure 9-2. Typical ISO674x-Q1 Circuit Hook-up
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9.2.3 Application Curve
The following typical eye diagrams of the ISO674x-Q1 family of devices indicates low jitter and wide open eye at
the maximum data rate of 50 Mbps.
Time = 5 ns / div
Time = 5 ns / div
Figure 9-4. Eye Diagram at 50 Mbps PRBS 216 – 1,
3.3 V and 25°C
Figure 9-3. Eye Diagram at 50 Mbps PRBS 216 – 1,
5 V and 25°C
Time = 5 ns / div
Time = 5 ns / div
Figure 9-5. Eye Diagram at 50 Mbps PRBS 216 – 1, Figure 9-6. Eye Diagram at 50 Mbps PRBS 216 – 1,
2.5 V and 25°C 1.8 V and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 9-7 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 9-8 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1060 VRMS with a lifetime of 220 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1060 VRMS. At the lower working voltages,
the corresponding insulation lifetime is much longer than 220 years.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 9-7. Test Setup for Insulation Lifetime Measurement
Figure 9-8. Insulation Lifetime Projection Data
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10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver. For automotive applications, please use
SN6501-Q1 or SN6505A-Q1. For such applications, detailed power supply design and transformer selection
recommendations are available in SN6501-Q1 Transformer Driver for Isolated Power Supplies or SN6505A-Q1
Low-Noise 1-A Transformer Drivers for Isolated Power Supplies.
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11 Layout
11.1 Layout Guidelines
A minimum of two layers is required to accomplish a cost optimized and low EMI PCB design. To further improve
EMI, a four layer board can be used (see Figure 11-2). Layer stacking for a four layer board should be in the
following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal
layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
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11.2 Layout Example
Solid supply islands reduce
inductance because large peak
currents flow into the VCC pin
2 mm
maximum
from VCC1
2 mm
maximum
from VCC2
VCC1
VCC2
1
16
0.1 …F
GND2
0.1 …F
GND1
2
3
15
14
4
13
5
6
12
11
EN1
EN2
7
8
10
9
GND2
GND1
Solid ground islands help
dissipate heat through PCB
Figure 11-1. Layout Example
High-speed traces
Ground plane
10 mils
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
r
Power plane
10 mils
Low-speed traces
Figure 11-2. Layout Example Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, ADS79xx 12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial
Interface ADCs data sheet
•
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, Isolation Glossary
Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
•
•
•
•
Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, SN65HVD231Q 3.3-V CAN Transceivers data sheet
Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet
Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
Packaging Information
Orderable
Device
Status(1)
Package Type Package
Drawing
Pins
16
Package Qty
2000
Eco Plan(2)
Lead/Ball
Finish(6)
MSL Peak
Temp(3)
Op Temp (°C) Device
Marking(4) (5)
ISO6740QDWR ACTIVE
Q1
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6740
ISO6740FQDW ACTIVE
RQ1
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6740F
ISO6741
ISO6741F
ISO6742
ISO6742F
ISO6741QDWR ACTIVE
Q1
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6741FQDW ACTIVE
RQ1
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6742QDWR ACTIVE
Q1
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6742FQDW ACTIVE
RQ1
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
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13.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
P1 Pitch between successive cavity centers
W
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
ISO6740QDWRQ1
ISO6740FQDWRQ1
ISO6741QDWRQ1
ISO6741FQDWRQ1
ISO6742QDWRQ1
ISO6742FQDWRQ1
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
24.4
24.4
10.9
10.9
10.9
10.9
10.9
10.9
10.7
10.7
10.7
10.7
10.7
10.7
2.7
2.7
2.7
2.7
2.7
2.7
12.0
12.0
12.0
12.0
12.0
12.0
24.4
24.4
24.4
24.4
24.4
24.4
Q1
Q1
Q1
Q1
Q1
Q1
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: ISO6740-Q1 ISO6741-Q1 ISO6742-Q1
ISO6740-Q1, ISO6741-Q1, ISO6742-Q1
SLLSFG4A – AUGUST 2020 – REVISED JANUARY 2021
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
SOIC
Package Drawing Pins
SPQ
2000
2000
2000
2000
2000
2000
Length (mm) Width (mm)
Height (mm)
45.0
ISO6740QDWRQ1
ISO6740FQDWRQ1
ISO6741QDWRQ1
ISO6741FQDWRQ1
ISO6742QDWRQ1
ISO6742FQDWRQ1
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
SOIC
45.0
SOIC
45.0
SOIC
45.0
SOIC
45.0
SOIC
45.0
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: ISO6740-Q1 ISO6741-Q1 ISO6742-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO6740FQDWRQ1
ISO6740QDWRQ1
PREVIEW
SOIC
SOIC
DW
16
16
2000 RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
PREVIEW
DW
2000 RoHS (In work)
& Non-Green
Call TI
ISO6741FQDWRQ1
ISO6741QDWRQ1
ISO6742FQDWRQ1
PREVIEW
PREVIEW
PREVIEW
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
ISO6741F
ISO6741
2000 RoHS (In work)
& Non-Green
ISO6742QDWRQ1
XISO6740FQDWRQ1
XISO6740QDWRQ1
XISO6741FQDWRQ1
XISO6741QDWRQ1
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
16
16
16
16
16
2000 RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2000 RoHS (In work)
& Non-Green
2000 RoHS (In work)
& Non-Green
2000 RoHS (In work)
& Non-Green
2000 RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2021
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO6740-Q1, ISO6741-Q1, ISO6742-Q1 :
Catalog: ISO6740, ISO6741, ISO6742
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
9
8
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
8
9
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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