ISO6763F-Q1 [TI]

ISO676x-Q1 General-Purpose Six-Channel Automotive Reinforced Digital Isolators with Robust EMC;


型号：	ISO6763F-Q1
厂家：	TEXAS INSTRUMENTS
描述：	ISO676x-Q1 General-Purpose Six-Channel Automotive Reinforced Digital Isolators with Robust EMC
文件：	总37页 (文件大小：1874K)
中文：	中文翻译
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ISO6763-Q1

SLLSFK2 – AUGUST 2021

ISO676x-Q1 General-Purpose Six-Channel Automotive Reinforced Digital Isolators

with Robust EMC

1 Features

3 Description

•

AEC-Q100 qualified with the following results:

– Device temperature Grade 1: –40°C to +125°C

ambient operating temperature range

Meets VDA320 isolation requirements

50 Mbps data rate

The ISO676x-Q1 devices are high-performance,

six-channel digital isolators ideal for cost-sensitive

applications requiring up to 5000 V_RMSisolation

ratings per UL 1577. These devices are also certified

by VDE, TUV, CSA, and CQC.

•

Robust isolation barrier:

The

ISO676x-Q1

devices

provide

high

– High lifetime at 1500 V_RMSworking voltage

– Up to 5000 V_RMSisolation rating

– Up to 10 kV surge capability

– ±75 kV/μs typical CMTI

Wide supply range: 1.71 V to 1.89 V and 2.25 V to

5.5 V

1.71 V to 5.5 V level translation

Default output high (ISO676x-Q1) and low

(ISO676xF-Q1) options

1.6 mA per channel typical at 1 Mbps

Low propagation delay: 11 ns typical

Robust electromagnetic compatibility (EMC)

– System-level ESD, EFT, and surge immunity

– Low emissions

electromagnetic immunity and low emissions at

low power consumption, while isolating CMOS or

LVCMOS digital I/Os. Each isolation channel has a

logic input and output buffer separated by TI's double

capacitive silicon dioxide (SiO₂) insulation barrier. The

ISO676x family of devices is available in all possible

pin configurations such that all six channels are in the

same direction, or one, two, or three channels are in

reverse direction while the remaining channels are in

forward direction. In the event of input power or signal

loss, the default output is high for devices without

suffix F and low for devices with suffix F. See Device

Functional Modes section for further details.

•

Used in conjunction with isolated power supplies,

these devices help prevent noise currents on data

buses, such as CAN and LIN from damaging sensitive

circuitry. Through innovative chip design and layout

techniques, the electromagnetic compatibility of the

ISO6763-Q1 devices has been significantly enhanced

to ease system-level ESD, EFT, surge, and emissions

compliance. The ISO676x-Q1 family of devices is

available in a 16-pin SOIC wide-body (DW) package

and is a pin-to-pin upgrade to the older generations.

•

Wide-SOIC (DW-16) Package

Safety-Related Certifications (pending):

– DIN V VDE 0884-11:2017-01

– UL 1577 component recognition program

– IEC 60950-1, IEC 62368-1, IEC 61010-1,

IEC60601-1 and GB 4943.1-2011 certifications

2 Applications

•

Hybrid, electric and power train system (EV/HEV)

– Battery management system (BMS)

– On-board charger

Device Description

– DC/DC converter

– Inverter and motor control

Part Number

ISO6763-Q1,

Package

Body Size

10.30 mm × 7.50

SOIC (DW)

ISO6763F-Q1

V_CCO

V_CCI

Series Isolation

Capacitors

INx

OUTx

GNDI

GNDO

V_CCI=Input supply, V_CCO=Output supply

GNDI=Input ground, GNDO=Output ground

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

without notice.

ISO6763-Q1

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................6

6.5 Power Ratings ............................................................6

6.6 Insulation Specifications ............................................ 7

6.7 Safety-Related Certifications ..................................... 8

6.8 Safety Limiting Values ................................................8

6.9 Electrical Characteristics—5-V Supply ...................... 9

6.10 Supply Current Characteristics—5-V Supply ...........9

6.11 Electrical Characteristics—3.3-V Supply ................10

6.12 Supply Current Characteristics—3.3-V Supply ......10

6.13 Electrical Characteristics—2.5-V Supply ...............11

6.14 Supply Current Characteristics—2.5-V Supply ...... 11

6.15 Electrical Characteristics—1.8-V Supply ............... 12

6.16 Supply Current Characteristics—1.8-V Supply ......12

6.17 Switching Characteristics—5-V Supply ..................13

6.18 Switching Characteristics—3.3-V Supply ...............14

6.19 Switching Characteristics—2.5-V Supply ...............15

6.20 Switching Characteristics—1.8-V Supply ...............16

7 Parameter Measurement Information..........................17

8 Detailed Description......................................................18

8.1 Overview...................................................................18

8.2 Functional Block Diagram.........................................18

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................20

9 Layout.............................................................................26

9.1 Layout Guidelines..................................................... 26

9.2 Layout Example........................................................ 27

10 Device and Documentation Support..........................28

10.1 Documentation Support.......................................... 28

10.2 Receiving Notification of Documentation Updates..28

10.3 Support Resources................................................. 28

10.4 Trademarks.............................................................28

10.5 Electrostatic Discharge Caution..............................28

10.6 Glossary..................................................................28

11 Mechanical, Packaging, and Orderable

Information.................................................................... 28

11.1 Package Option Addendum.................................... 31

11.2 Tape and Reel Information......................................32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Date

Revision

Notes

August 2021

Initial Release

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5 Pin Configuration and Functions

VCC1

INA

VCC2

OUTA

OUTB

OUTC

IND

INB

INC

OUTD

OUTE

INE

INF

OUTF

GND1

GND2

Not to scale

Figure 5-1. ISO6763-Q1 DW Package 16-Pin SOIC-WB Top View

Table 5-1. Pin Functions

I/O

DESCRIPTION

NAME

GND1

GND2

INA

ISO6763-Q1

—

Ground connection for V_CC1

Ground connection for V_CC2

Input, channel A

—

INB

Input, channel B

INC

Input, channel C

IND

Input, channel D

INE

INF

Input, channel E

Input, channel F

OUTA

OUTB

OUTC

Output, channel A

Output, channel B

Output, channel C

Output, channel D

OUTD

OUTE

OUTF

Output, channel E

—

Output, channel F

V_CC1

V_CC2

Power supply, side 1

Power supply, side 2

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6 Specifications

6.1 Absolute Maximum Ratings

See⁽¹⁾

MIN

-0.5

-15

MAX

UNIT

V_CC1to GND1

Supply Voltage ⁽²⁾

V_CC2to GND2

V_CCX+ 0.5 ⁽³⁾

INx to GNDx

Input/Output

Voltage

OUTx to GNDx

Output Current

°C

Operating junction temperature, T_J

Storage temperature, T_stg

150

Temperature

-65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak

voltage values

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

(1) (2)

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

±6000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

MIN

1.71

2.25

1.71

2.25

NOM

MAX

1.89

5.5

UNIT

(1)

V_CC1

V_CC2

Vcc

Supply Voltage Side 1 ⁽³⁾

Supply Voltage Side 2 ⁽³⁾

(1)

1.89

5.5

UVLO threshold when supply voltage is rising

UVLO threshold when supply voltage is falling

Supply voltage UVLO hysteresis

1.53

1.41

0.13

1.71

(UVLO+)

Vcc

1.1

(UVLO-)

Vhys

0.08

(UVLO)

0.7 x V_CC₍₂_I₎

V_IH

V_IL

High level Input voltage

V_CCI

Low level Input voltage

-4

-2

-1

0.3 x V_CCI

Mbps

°C

(2)

V_CCO

= 5 V

V_CCO= 3.3 V

V_CCO= 2.5 V

V_CCO= 1.8 V

V_CCO= 5 V

V_CCO= 3.3 V

V_CCO= 2.5 V

V_CCO= 1.8 V

I_OH

High level output current

Low level output current

I_OL

T_A

Data Rate

125

Ambient temperature

-40

(1) V_CC1and V_CC2can be set independent of one another

(2) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(3) The channel outputs are in undetermined state when 1.89 V < V_CC1, V_CC2< 2.25 V and 1.05 V < V_CC1, V_CC2< 1.71 V

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UNIT

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6.4 Thermal Information

ISO676x

DW (SOIC)

16 PINS

68.8

THERMAL METRIC ⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

31.8

32.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

13.5

ψ_JB

32.1

R_θJC(bot)

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ISO6763

V_CC1= V_CC2= 5.5 V, T_J= 150°C, C_L=

Maximum power dissipation (both sides) 15 pF, Input a 25-MHz 50% duty cycle

square wave

P_D

196

V_CC1= V_CC2= 5.5 V, T_J= 150°C, C_L=

P_D1

Maximum power dissipation (side-1)

Maximum power dissipation (side-2)

15 pF, Input a 25-MHz 50% duty cycle

square wave

V_CC1= V_CC2= 5.5 V, T_J= 150°C, C_L=

15 pF, Input a 25-MHz 50% duty cycle

square wave

P_D2

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6.6 Insulation Specifications

VALUE

UNIT

DW-16

PARAMETER

TEST CONDITIONS

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest terminal-to-terminal distance through air

Shortest terminal-to-terminal distance across the

package surface

DTI

CTI

Distance through the insulation

Comparative tracking index

Material group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

>17

>600

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category per IEC 60664-1

DIN VDE V 0884-11:2017-01⁽²⁾

V_IORMMaximum repetitive peak isolation voltage

AC voltage (bipolar)

2121

1500

2121

V_PK

V_RMS

V_DC

AC voltage; Time dependent dielectric breakdown

(TDDB) Test;

See Figure 9-4

V_IOWM

Maximum working isolation voltage

DC voltage

V_TEST= V_IOTM

t = 60 s (qualification);

V_TEST= 1.2 x V_IOTM

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

7071

V_PK

t= 1 s (100% production)

Test method per IEC 62368-1, 1.2/50 µs waveform,

V_TEST= 1.6 x V_IOSM= 10,000 V_PK(qualification)

V_IOSM

6250

≤5

V_PK

Method a, After Input-output safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.2 x V_IORM, t_m= 10 s

Method a, After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.6 x V_IORM, t_m= 10 s

≤5

q_pd

Apparent charge⁽⁴⁾

Method b1; At routine test (100% production) and

preconditioning (type test)

V_ini= 1.2 x V_IOTM, t_ini= 1 s;

V_pd(m)= 1.875 x V_IORM, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Isolation resistance⁽⁵⁾

V_IO= 0.4 x sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

>10¹²

>10¹¹

>10⁹

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO, t = 60 s (qualification),

V_TEST= 1.2 x V_ISO, t = 1 s (100% production)

V_ISO

Maximum withstanding isolation voltage

5000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of

the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become

equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

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6.7 Safety-Related Certifications

VDE

CSA

CQC

TUV

Plan to certify according

Plan to certify according to to EN 61010-1:2010/

Plan to certify according to Plan to certify according to Plan to certify according

DIN VDE V 0884-11:2017- IEC 62368-1, IEC 61010-1 to UL 1577 Component

GB4943.1-2011

A1:2019 and EN

62368-1:2014

and IEC 60601

Recognition Program

5000 V_RMSinsulation

per CSA 62368-1:19,

IEC 62368-1:2018, CSA

61010-1-12+A1 and IEC

61010-1 3rd Ed., 1000

V_RMSbasic and 600

Maximum transient

isolation

5000 V_RMSreinforced

insulation per EN

61010-1:2010/A1:2019

and EN 62368-1:2014 up

to working voltage of 600

V_RMS

Reinforced insulation,

Altitude ≤ 5000 m, Tropical

Climate,

700 V_RMS

maximum working voltage

voltage, 7071 V_PK

;

Maximum repetitive peak V_RMSreinforced working

Single protection,

5000 V_RMS

isolation

voltage (pollution degree

2, material group I);

Maximum surge isolation 5000 V_RMSinsulation per

voltage, 2121 V_PK

;

voltage, 6250 V_PK

CSA 60601-1-14 and

IEC 60601-1 Ed.3+A1, 2

MOPP for 250 V_RMS

Certificate planned

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DW-16 PACKAGE

R_θJA=68.8°C/W, V_I= 5.5 V, T_J= 150°C,

T_A= 25°C

330

504

660

956

R_θJA= 68.8°C/W, V_I= 3.6 V, T_J= 150°C,

T_A= 25°C

I_S

Safety input, output, or supply current ⁽¹⁾

R_θJA= 68.8°C/W, V_I= 2.75 V, T_J= 150°C,

T_A= 25°C

R_θJA= 68.8°C/W, V_I= 1.89 V, T_J= 150°C,

T_A= 25°C

P_S

T_S

Safety input, output, or total power ⁽¹⁾

Maximum safety temperature ⁽¹⁾

R_θJA= 68.8°C/W, T_J= 150°C, T_A= 25°C

1820

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The

I_Sand P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the table is that of a device installed on a high-K test board for leaded surface-mount

packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

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6.9 Electrical Characteristics—5-V Supply

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OH

High-level output voltage

Low-level output voltage

I_OH= -4 mA; See Figure 7-1

I_OL= 4 mA; See Figure 7-1

V_CCO- 0.4

V_OL

0.4

(1)

V_IT+(IN)

V_IT-(IN)

V_I(HYS)

I_IH

Rising input switching threshold

Falling input switching threshold

Input threshold voltage hysteresis

High-level input current

0.7 x V_CCI

0.3 x V_CCI

0.1 x V_CCI

V_IH= V_CCI⁽¹⁾at INx

µA

kV/us

I_IL

Low-level input current

V_IL= 0 V at INx

-10

CMTI

Common mode transient immunity

V_I= V_CCor 0 V, V_CM= 1200 V

V_I= V_CC/ 2 + 0.4×sin(2πft), f = 2

MHz, V_CC= 5 V ; See Figure 7-3

C_i

Input Capacitance ⁽²⁾

2.8

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.10 Supply Current Characteristics—5-V Supply

V_CC1= V_CC2= 5 V ±10% (over recommended operating conditions unless otherwise noted).

SUPPLY

CURRENT

PARAMETER

ISO6763

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_I= V_CCI(ISO6763); V_I= 0 V (ISO6763 with F suffix)

V_I= 0 V (ISO6763); V_I= V_CCI(ISO6763 with F suffix)

1 Mbps

I_CC1,I_CC2

6.3

4.7

Supply current - DC signal

4.8

All channels switching with square

wave clock input; C_L= 15 pF

Supply current - AC signal

10 Mbps

6.6

50 Mbps

14.4

17.8

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6.11 Electrical Characteristics—3.3-V Supply

V_CC1= V_CC2= 3.3 V ±10% (over recommended operating conditions unless otherwise noted).

PARAMETER

TEST CONDITIONS

I_OH= -2mA ; See Figure 7-1

I_OL= 2mA ; See Figure 7-1

MIN

TYP

MAX UNIT

V_OH

High-level output voltage

Low-level output voltage

Rising input switching threshold

Falling input switching threshold

V_CCO- 0.2

V_OL

0.2

(1)

V_IT+(IN)

V_IT-(IN)

0.7 x V_CCI

0.3 x V_CCI

0.1 x V_CCI

Input threshold voltage

hysteresis

V_I(HYS)

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CCI⁽¹⁾at INx

V_IL= 0 V at INx

µA

-10

Common mode transient

immunity

CMTI

C_i

V_I= V_CCor 0 V, V_CM= 1200 V

kV/us

V_I= V_CC/ 2 + 0.4×sin(2πft), f =

2 MHz, V_CC= 3.3 V ; See Figure

7-3

Input Capacitance⁽²⁾

2.8

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.12 Supply Current Characteristics—3.3-V Supply

V_CC1= V_CC2= 3.3 V ±10% (over recommended operating conditions unless otherwise noted).

SUPPLY

CURRENT

PARAMETER

ISO6763

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_I= V_CCI(ISO6763); V_I= 0 V (ISO6763 with F suffix)

V_I= 0 V (ISO6763); V_I= V_CCI(ISO6763 with F suffix)

1 Mbps

I_CC1,I_CC2

6.2

4.8

4.6

8.9

Supply current - DC signal

6.9

8.4

All channels switching with square

wave clock input; C_L= 15 pF

Supply current - AC signal

10 Mbps

50 Mbps

11.6

14.7

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6.13 Electrical Characteristics—2.5-V Supply

V_CC1= V_CC2= 2.5 V ±10% (over recommended operating conditions unless otherwise noted).

PARAMETER

TEST CONDITIONS

I_OH= -1mA ; See Figure 7-1

I_OL= 1mA ; See Figure 7-1

MIN

TYP

MAX UNIT

V_OH

High-level output voltage

Low-level output voltage

Rising input switching threshold

Falling input switching threshold

V_CCO- 0.1

V_OL

0.1

(1)

V_IT+(IN)

V_IT-(IN)

0.7 x V_CCI

0.3 x V_CCI

0.1 x V_CCI

Input threshold voltage

hysteresis

V_I(HYS)

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CCI⁽¹⁾at INx

V_IL= 0 V at INx

µA

-10

Common mode transient

immunity

CMTI

C_i

V_I= V_CCor 0 V, V_CM= 1200 V

kV/us

V_I= V_CC/ 2 + 0.4×sin(2πft), f =

2 MHz, V_CC= 2.5 V ; See Figure

7-3

Input Capacitance⁽²⁾

2.8

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.14 Supply Current Characteristics—2.5-V Supply

V_CC1= V_CC2= 2.5 V ±10% (over recommended operating conditions unless otherwise noted).

SUPPLY

CURRENT

PARAMETER

ISO6763

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_I= V_CCI(ISO6763); V_I= 0 V (ISO6763 with F suffix)

V_I= 0 V (ISO6763); V_I= V_CCI(ISO6763 with F suffix)

1 Mbps

I_CC1,I_CC2

6.2

4.7

5.6

9.8

4.6

8.9

Supply current - DC signal

6.9

7.9

All channels switching with square

wave clock input; C_L= 15 pF

Supply current - AC signal

10 Mbps

50 Mbps

12.7

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6.15 Electrical Characteristics—1.8-V Supply

V_CC1= V_CC2= 1.8 V ±10% (over recommended operating conditions unless otherwise noted).

PARAMETER

TEST CONDITIONS

I_OH= -1mA ; See Figure 7-1

I_OL= 1mA ; See Figure 7-1

MIN

TYP

MAX UNIT

V_OH

High-level output voltage

Low-level output voltage

V_CCO- 0.1

V_OL

0.1

(1)

V_IT+(IN)

V_IT-(IN)

V_I(HYS)

I_IH

Rising input switching threshold

Falling input switching threshold

Input threshold voltage hysteresis

High-level input current

0.7 x V_CCI

0.3 x V_CCI

0.1 x V_CCI

V_IH= V_CCI⁽¹⁾at INx

µA

kV/us

I_IL

Low-level input current

V_IL= 0 V at INx

-10

CMTI

Common mode transient immunity

V_I= V_CCor 0 V, V_CM= 1200 V

V_I= V_CC/ 2 + 0.4×sin(2πft), f =

2 MHz, V_CC= 1.8 V ; See Figure

7-3

C_i

Input Capacitance⁽²⁾

2.8

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.16 Supply Current Characteristics—1.8-V Supply

V_CC1= V_CC2= 1.8 V ±10% (over recommended operating conditions unless otherwise noted).

SUPPLY

CURRENT

PARAMETER

ISO6763

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_I= V_CCI(ISO6763); V_I= 0 V (ISO6763 with F suffix)

V_I= 0 V (ISO6763); V_I= V_CCI(ISO6763 with F suffix)

1 Mbps

I_CC1,I_CC2

2.6

5.7

4.2

4.9

7.9

4.3

8.6

Supply current - DC signal

6.5

7.3

All channels switching with square

wave clock input; C_L= 15 pF

Supply current - AC signal

10 Mbps

50 Mbps

10.5

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6.17 Switching Characteristics—5-V Supply

V_CC1= V_CC2= 5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ISO676x

Propagation delay

time

t_PLH, t_PHL

Propagation delay time

See TBD

Pulse width

PWD

t_sk(o)

Pulse width distortion⁽¹⁾|t_PHL– t_PLH

distortion⁽¹⁾|t_PHL

–

t_PLH

Channel-to-

Channel-to-channel output skew time⁽²⁾channel output

skew time⁽²⁾

Same-direction channels

Part-to-part skew

time⁽³⁾

t_sk(pp)

Part-to-part skew time⁽³⁾

Output signal rise time

4.5

300

Output signal rise

time

t_r

t_f

See TBD

Output signal fall

time

Output signal fall time

Time from UVLO to

valid output data

Time from UVLO to valid output data

tPU

Default output

delay time from

input power loss

Default output delay time from input

power loss

Measured from the time VCC goes

below 1.2V. See TBD

t_DO

t_ie

0.1

0.3

Time interval error

Time interval error 2¹⁶– 1 PRBS data at 50 Mbps

(1) Also known as pulse skew.

(2) t_sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

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6.18 Switching Characteristics—3.3-V Supply

V_CC1= V_CC2= 3.3 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

ISO676x

Propagation delay

time

t_PLH, t_PHL

Propagation delay time

See TBD

Pulse width

PWD

t_sk(o)

Pulse width distortion⁽¹⁾|t_PHL– t_PLH

distortion⁽¹⁾|t_PHL

–

t_PLH

Channel-to-

Channel-to-channel output skew time⁽²⁾channel output

skew time⁽²⁾

Same-direction channels

Part-to-part skew

time⁽³⁾

t_sk(pp)

Part-to-part skew time⁽³⁾

Output signal rise time

3.2

300

Output signal rise

time

t_r

t_f

See TBD

Output signal fall

time

Output signal fall time

Time from UVLO to

valid output data

Time from UVLO to valid output data

tPU

Default output

delay time from

input power loss

Default output delay time from input

power loss

Measured from the time VCC goes

below 1.2V. See TBD

t_DO

t_ie

0.1

0.3

Time interval error

Time interval error 2¹⁶– 1 PRBS data at 50 Mbps

(1) Also known as pulse skew.

(2) t_sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

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6.19 Switching Characteristics—2.5-V Supply

V_CC1= V_CC2= 2.5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ISO676x

Propagation delay

time

t_PLH, t_PHL

Propagation delay time

See TBD

20.5

7.1

Pulse width

PWD

t_sk(o)

Pulse width distortion⁽¹⁾|t_PHL– t_PLH

distortion⁽¹⁾|t_PHL

–

t_PLH

Channel-to-

Channel-to-channel output skew time⁽²⁾channel output

skew time⁽²⁾

Same-direction channels

Part-to-part skew

time⁽³⁾

t_sk(pp)

Part-to-part skew time⁽³⁾

Output signal rise time

Output signal rise

time

t_r

t_f

See TBD

Output signal fall

time

Output signal fall time

Time from UVLO to

valid output data

Time from UVLO to valid output data

300

tPU

Default output

delay time from

input power loss

Default output delay time from input

power loss

Measured from the time VCC goes

below 1.2V. See TBD

t_DO

t_ie

0.1

0.3

Time interval error

Time interval error 2¹⁶– 1 PRBS data at 50 Mbps

(1) Also known as pulse skew.

(2) t_sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

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6.20 Switching Characteristics—1.8-V Supply

V_CC1= V_CC2= 1.8 V ±5% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

ISO676x

Propagation delay

time

t_PLH, t_PHL

Propagation delay time

See TBD

Pulse width

PWD

t_sk(o)

Pulse width distortion |t_PHL– t_PLH

distortion |t_PHL

t_PLH

–

8.2

Channel-to-

Channel-to-channel output skew time⁽¹⁾channel output

skew time⁽¹⁾

Same-direction channels

Part-to-part skew

time⁽²⁾

t_sk(pp)

Part-to-part skew time⁽²⁾

Output signal rise time

8.8

4.7

300

Output signal rise

time

t_r

t_f

See TBD

Output signal fall

time

Output signal fall time

Time from UVLO to

valid output data

Time from UVLO to valid output data

tPU

Default output

delay time from

input power loss

Default output delay time from input

power loss

Measured from the time VCC goes

below 1.2V. See TBD

t_DO

t_ie

0.1

0.3

Time interval error

Time interval error 2¹⁶– 1 PRBS data at 50 Mbps

(1) t_sk(o)is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(2) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

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7 Parameter Measurement Information

CCI

50%

OUT

0 V

PHL

PLH

Input

Generator

(See Note A)

50 ꢀ

See Note B

90%

10%

50%

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, t_r≤ 3 ns, t_f≤ 3ns, Z_O

50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.

B. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms

See Note B

1.4 V

0 V

default high

OUT

IN = 0 V (Devices without suffix F)

IN = V (Devices with suffix F)

50%

See Note A

default low

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

B. Power Supply Ramp Rate = 10 mV/ns

Figure 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms

CCO

CCI

Pass-fail criteria:

The output must

remain stable.

OUT

or V

See Note A

GNDO

GNDI

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

B. For optimized CMTI performance, a 0.1 μF + 1 μF decoupling capacitor should be placed close to V_CC1and V_CC2. Please see Section

9.2 for capacitor placement details. A recommended 0.1μF capacitor is LLL185R71A104MA11L (CAP CER 0.1UF 10V X7R 0306 - LW

Reversed Low ESL Chip Ceramic Capacitors) or equivalent.

Figure 7-3. Common-Mode Transient Immunity Test Circuit

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8 Detailed Description

8.1 Overview

The ISO676x-Q1 family of devices have an ON-OFF keying (OOK) modulation scheme to transmit the digital

data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across

the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver

demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the

ENx pin is low then the output goes to high impedance. The ISO676x-Q1 devices also incorporate advanced

circuit techniques to maximize the CMTI performance and minimize the radiated emissions due to the high

frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure

8-1, shows a functional block diagram of a typical channel.

8.2 Functional Block Diagram

Transmitter

Receiver

OOK

Modulation

TX IN

SiO based

RX OUT

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

Capacitive

Isolation

Barrier

Emissions

Reduction

Techniques

Oscillator

Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 8-2 shows a conceptual detail of how the ON-OFF keying scheme works.

TX IN

Carrier signal through

isolation barrier

RX OUT

Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme

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8.3 Feature Description

Table 8-1 provides an overview of the device features.

Table 8-1. Device Features

MAXIMUM DATA

RATE

DEFAULT

OUTPUT

PART NUMBER

ISO6763-Q1

CHANNEL DIRECTION

PACKAGE

DW-16

RATED ISOLATION⁽¹⁾

5000 V_RMS/ 8000 V_PK

3 Forward,

3 Reverse

50 Mbps

High

Low

3 Forward,

3 Reverse

ISO6763F-Q1

DW-16

(1) See for detailed isolation ratings.

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 25. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO676x-

Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of

these improvements include:

•

Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

Low-resistance connectivity of ESD cells to supply and ground pins.

Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

•

PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

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8.4 Device Functional Modes

Table 8-2 lists the functional modes for the ISO676x-Q1 devices.

Table 8-2. Function Table

INPUT

OUTPUT

(OUTx)

(1)

V_CCI

V_CCO

COMMENTS

(INx) ⁽³⁾

Normal Operation: A channel output assumes the logic state of its input.

Default mode: When INx is open, the corresponding channel output goes to its

default logic state. Default is High for ISO676x-Q1 and Low for ISO676x-Q1

with F suffix.

Open

Default

Default mode: When V_CCIis unpowered, a channel output assumes the logic

state based on the selected default option. Default is High for ISO676x-Q1

and Low for ISO676x-Q1 with F suffix. When V_CCItransitions from unpowered

to powered-up, a channel output assumes the logic state of the input. When

V_CCItransitions from powered-up to unpowered, channel output assumes the

selected default state.

Default

When V_CCOis unpowered, a channel output is undetermined⁽²⁾. When V_CCO

transitions from unpowered to powered-up, a channel output assumes the

logic state of the input.

Undetermined

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC; PU = Powered up (V_CC≥ 1.71 V); PD = Powered down (V_CC≤ 1.05 V); X = Irrelevant;

H = High level; L = Low level ; Z = High Impedance

(2) The outputs are in undetermined state when 1.7 V < V_CCI, V_CCO< 2.25 V and 1.05 V < V_CCI, V_CCO< 1.71 V

(3) A strongly driven input signal can weakly power the floating V_CCthrough an internal protection diode and cause undetermined output

8.4.1 Device I/O Schematics

Input (Devices with F suffix)

Input (Devices without F suffix)

CCI

1.5 Mꢀ

985 ꢀ

INx

1.5 Mꢀ

Output

CCO

~20 ꢀ

OUTx

Figure 8-3. Device I/O Schematics

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Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The ISO676x-Q1 devices are high-performance, quad-channel digital isolators. The ISO676x-Q1 devices use

single-ended CMOS-logic switching technology. The supply voltage range is from 1.71 V to 5.5 V for both

supplies, V_CC1and V_CC2. Since an isolation barrier separates the two sides, each side can be sourced

independently with any voltage within recommended operating conditions. As an example, it is possible to

supply ISO676x-Q1 V_CC1with 3.3 V (which is within 1.71 V to 5.5 V) and V_CC2with 5V (which is also within 1.71

V to 5.5 V). You can use the digital isolator as a logic-level translator in addition to providing isolation. When

designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators

do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL

digital signal lines. The isolator is typically placed between the data controller (that is, MCU or FPGA), and a

data converter or a line transceiver, regardless of the interface type or standard.

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9.2 Typical Application

Figure 9-1 shows the isolated serial-peripheral interface (SPI) and controller-area network (CAN) interface

implementation.

V_S

10 ꢀF

3.3 V

MBR0520L

Vcc

1:1.33

ISO 3.3V

OUT

10 ꢀF

TPS76333-Q1

SN6501-Q1

V_IN

V_OUT

0.1 ꢀF

10 ꢀF

GND

1 µF

REF5025A-Q1

GND

22 µF

MBR0520L

GND

ISO Barrier

0.1 ꢀF

0.1 µF

0.1 ꢀF

AINP MXO +VBD +VA REFP

V_CC2

V_CC1

CH0

SCLK

SDI

16 Analog

Inputs

INA

OUTA

OUTB

29, 57

ADS7953-Q1

INB

SPICLKA

V_DDIO

SDO

CH15

BDGND AGND

27 1, 22

REFM

ISO6762-Q1

INC

SPISIMOA

SPISOMIA

OUTC

INE

OUTE

TMS320F28035Q

CANRXA

CANTXA

INF

OUTF

IND

0.1 ꢀF

OUTD

V_SS

V_CC

R_S

GND1

GND2

10 ꢁ (optional)

6, 28

CANH

CAN Bus

SN65HVD231Q-Q1

CANL

Vref

10 ꢁ (optional)

GND

SM712

4.7 nF /

2 kV

Figure 9-1. Isolated SPI and CAN Interface

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9.2.1 Design Requirements

To design with these devices, use the parameters listed in Table 9-1.

Table 9-1. Design Parameters

PARAMETER

VALUE

Supply voltage, V_CC1and V_CC2

1.71 V to 1.89 V and 2.25 V to 5.5 V

Decoupling capacitor between V_CC1and GND1

Decoupling capacitor from V_CC2and GND2

0.1 µF

9.2.2 Detailed Design Procedure

Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,

the ISO676x-Q1 family of devices only require two external bypass capacitors to operate.

0.1 µF

V_CC1

V_CC2

INA

INB

OUTA

OUTB

OUTC

INC

OUTD

OUTE

IND

INE

OUTF

INF

GND1

GND2

Figure 9-2. Typical ISO676x-Q1 Circuit Hook-up

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9.2.3 Application Curve

9.2.3.1 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown

(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal

device and high voltage applied between the two sides; See Figure 9-3 for TDDB test setup. The insulation

breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced

insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million

(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation

voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for

lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%

higher than the specified value.

Figure 9-4 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.

Based on the TDDB data, the intrinsic capability of the insulation is 1500 V_RMSwith a lifetime of 220 years. Other

factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the

component. The working voltage of DW-16 package is specified upto 1500 V_RMS. At the lower working voltages,

the corresponding insulation lifetime is much longer than 220 years.

Vcc 1

Vcc 2

Time Counter

> 1 mA

DUT

GND 1

GND 2

Oven at 150 °C

Figure 9-3. Test Setup for Insulation Lifetime Measurement

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Figure 9-4. Insulation Lifetime Projection Data

Power Supply Recommendations

To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended

at the input and output supply pins (V_CC1and V_CC2). The capacitors should be placed as close to the supply

pins as possible. If only a single primary-side power supply is available in an application, isolated power can

be generated for the secondary-side with the help of a transformer driver. For automotive applications, please

use SN6501-Q1 or SN6505B-Q1. For such applications, detailed power supply design and transformer selection

recommendations are available in SN6501-Q1 Transformer Driver for Isolated Power Supplies or SN6505B-Q1

Automotive, low-noise, 1-A, 420-kHz transformer driver with soft start for isolated power supplies.

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9 Layout

9.1 Layout Guidelines

A minimum of two layers is required to accomplish a low EMI PCB design. To further improve EMI, a four layer

board can be used (see Figure 9-2). Layer stacking for a four layer board should be in the following order

(top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

•

Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/inch².

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system

to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.

Also the power and ground plane of each power system can be placed closer together, thus increasing the

high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to the Digital Isolator Design Guide.

9.1.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths

of up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper

alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and

stiffness, and self-extinguishing flammability-characteristics.

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9.2 Layout Example

Solid supply islands reduce

inductance because large peak

currents flow into the V_CCpin

0.5 mm

maximum

from V_CC1

0.5 mm

maximum

from V_CC2

V_CC1

V_CC2

0.1 …F

I/O pins

routed

through

alternate

layer with

vias

GND2

GND1

Solid ground islands help

dissipate heat through PCB

Figure 9-1. Layout Example

High-speed traces

10 mils

Ground plane

Keep this

FR-4

space free

from planes,

40 mils

0 ~ 4.5

traces, pads,

and vias

Power plane

10 mils

Low-speed traces

Figure 9-2. Four Layer Board Layout Example

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

•

Texas Instruments, Digital Isolator Design Guide

Texas Instruments, Isolation Glossary

Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems

application report

•

Texas Instruments, SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies

Texas Instruments, TCAN1044-Q1 Automotive Fault-Protected CAN FD Transceiver

Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet

Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

DW0016A

SOIC - 2.65 mm max height

SOIC

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

14X 1.27

10.5

10.1

NOTE 3

8.89

0.51

0.31

16X

7.6

7.4

2.65 MAX

0.25

C A B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4220721/A 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead ﬂash. Interlead ﬂash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016A

SOIC - 2.65 mm max height

SOIC

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Product Folder Links: ISO6763-Q1

16X (2)

SEE

DETAILS

SYMM

ISO6763-Q1

SLLSFK2 – AUGUST 2021

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EXAMPLE STENCIL DESIGN

DW0016A

SOIC - 2.65 mm max height

SOIC

16X (2)

SYMM

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:7X

4220721/A 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have diﬀerent recommendations for stencil design.

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ISO6763-Q1

SLLSFK2 – AUGUST 2021

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11.1 Package Option Addendum

Packaging Information

Orderable

Device

Status⁽¹⁾

Package Type Package

Drawing

Pins

Package Qty

2000

Eco Plan⁽²⁾

Lead/Ball

Finish⁽⁶⁾

MSL Peak

Temp⁽³⁾

Op Temp (°C) Device

Marking^{(4) (5)}

XISO6763QDW ACTIVE

RQ1

SOIC

Green (RoHS & NIPDAU

no Sb/Br)

Level-2-260C-1 --40 to 125

YEAR

XISO6763

XISO6763FQD

WRQ1

Green (RoHS & NIPDAU

no Sb/Br)

Level-2-260C-1 --40 to 125

YEAR

XISO6763

ACTIVE

SOIC

2000

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SLLSFK2 – AUGUST 2021

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11.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

XISO6763QDWRQ1

XISO6763FQDWRQ1

SOIC

2000

330.0

24.4

10.9

10.7

2.7

12.0

24.0

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SLLSFK2 – AUGUST 2021

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

SOIC

Package Drawing Pins

SPQ

Length (mm) Width (mm)

Height (mm)

XISO6763QDWRQ1

XISO6763FQDWRQ1

2000

367.0

45.0

SOIC

2000

45.0

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PACKAGE OPTION ADDENDUM

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7-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

XISO6763FQDWRQ1

XISO6763QDWRQ1

ACTIVE

SOIC

2000

TBD

Call TI

-40 to 125

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

OTHER QUALIFIED VERSIONS OF ISO6763-Q1 :

Catalog : ISO6763

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ISO6763F-Q1 [TI]

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