ISO7041 [TI]

经 ATEX/IECEx 认证的超低功耗四通道数字隔离器;


型号：	ISO7041
厂家：	TEXAS INSTRUMENTS
描述：	经 ATEX/IECEx 认证的超低功耗四通道数字隔离器
文件：	总35页 (文件大小：3450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

ISO7041 超低功耗四通道数字隔离器

1 特性

2 应用

•

超低功率耗散

•

4mA 至 20mA 环路供电式现场发送器

工厂自动化、工艺自动化

–

每通道静态电流为 3.5μA (3.3V)

低功耗 GPIO、UART 和 SPI 隔离

100kbps 时的每通道电流为 15μA (3.3V)

1Mbps 时的每通道电流为 116μA (3.3V)

3 说明

•

稳健可靠的隔离栅

ISO7041 器件是一种可用于隔离 CMOS 或 LVCMOS

数字 I/O 的超低功耗多通道数字隔离器。每条隔离通道

的逻辑输入和输出缓冲器均由双电容二氧化硅 (SiO₂)

绝缘栅相隔离。基于边缘的创新架构与开关键控调制方

案相结合，使这些隔离器具有非常低的功耗，同时符合

UL1577 规定的 3000V_RMS隔离额定值。该器件的每通

道动态电流消耗低于 120μA/Mbps，并且 3.3V 时每通

道静态电流消耗为 3.5μA，从而允许在功耗和热性能受

限的系统设计中使用 ISO7041。

–

预计寿命超过 100 年

隔离额定值为 3000V_RMS

CMTI 典型值为 ±100kV/μs

•

宽电源电压范围：2.25V 至 5.5V

宽温度范围：

–

2.25V 至 3.6V：-55°C 至 +125°C

3.6V 至 5.5V：-40°C 至 +125°C

•

小型 16-QSOP 封装 (16-DBQ)

信号传输速率：高达 2Mbps

默认输出高电平 (ISO7041) 和低电平 (ISO7041F)

选项

该器件可在低至 2.25V 和高达 5.5V，并可在隔离栅的

每一侧采用不同电源电压的情况下实现完整功能。四通

道隔离器采用 16-QSOP 封装，具有三个正向通道和一

个反向通道。该器件具有默认输出高电平和低电平选

项。如果输入功率或信号出现损失，不具有 F 后缀的

ISO7041 器件默认输出高电平，具有 F 后缀的

ISO7041F 器件默认输出低电平。有关更多信息，请参

阅器件功能模式部分。

•

优异的电磁兼容性 (EMC)

–

系统级 ESD、EFT 和浪涌抗扰性

±8kV IEC 61000-4-2 跨隔离栅接触放电保护

极低辐射

•

安全相关认证（计划）：

–

UL 1577 组件认证计划

DIN V VDE V 0884-11

CQC、TUV 和 CSA 认证

器件信息⁽¹⁾

器件型号

ISO7041

封装

QSOP (16)

封装尺寸（标称值）

IECEx（IEC 60079-0 和 IEC 60079-11）和

ATEX (EN 60079-11)

4.90mm × 3.90mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化应用电路原理图

电压为 3.3V 时的数据速率与功耗间的关系

200

100

V_CC2

V_CC1

V_CC2

V_DD

ISO7041

MCU

ADC

DGND

GND2

GND1

Galvanic

Isolation Barrier

Digital

Ground

ISO

Ground

100

Data Rate (Kbps)

1000 2000

D001

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSF54

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

8.16 Insulation Characteristics Curves ......................... 14

8.17 Typical Characteristics.......................................... 15

Parameter Measurement Information ................ 16

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

8.1 Absolute Maximum Ratings ...................................... 5

8.2 ESD Ratings.............................................................. 5

8.3 Recommended Operating Conditions....................... 5

8.4 Thermal Information.................................................. 6

8.5 Power Ratings........................................................... 6

8.6 Insulation Specifications............................................ 7

8.7 Safety-Related Certifications..................................... 8

8.8 Safety Limiting Values .............................................. 8

8.9 Electrical Characteristics 5V Supply ......................... 9

8.10 Supply Current Characteristics 5V Supply.............. 9

8.11 Electrical Characteristics 3.3V Supply .................. 11

8.12 Supply Current Characteristics 3.3V Supply......... 11

8.13 Electrical Characteristics 2.5V Supply .................. 13

8.14 Supply Current Characteristics 2.5V Supply......... 13

8.15 Switching Characteristics...................................... 14

10 Detailed Description ........................................... 17

10.1 Overview ............................................................... 17

10.2 Functional Block Diagram ..................................... 17

10.3 Feature Description............................................... 17

10.4 Device Functional Modes...................................... 19

11 Application and Implementation........................ 21

11.1 Application Information.......................................... 21

11.2 Typical Application ................................................ 22

12 Power Supply Recommendations ..................... 24

13 Layout................................................................... 25

13.1 Layout Guidelines ................................................. 25

13.2 Layout Example .................................................... 25

14 器件和文档支持 ..................................................... 26

14.1 文档支持................................................................ 26

14.2 接收文档更新通知 ................................................. 26

14.3 社区资源................................................................ 26

14.4 商标....................................................................... 26

14.5 静电放电警告......................................................... 26

14.6 Glossary................................................................ 26

15 机械、封装和可订购信息....................................... 26

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (October 2017) to Revision A

Page

•

已更改将器件状态更改为“生产数据” ...................................................................................................................................... 1

5 修订历史记录

Changes from Revision A (December 2018) to Revision B

Page

•

更新首页通道静态电流以匹配表中数据................................................................................................................................... 1

扩大电源电压范围，以支持特性中高达 5.5V 的电压 ............................................................................................................ 1

分割温度范围，以便支持特性中 -40°C 的温度（电压范围 3.6V 至 5.5V）.......................................................................... 1

在特性中添加了“±8kV IEC 61000-4-2 跨隔离栅接触放电保护” ............................................................................................. 1

的电压下工作在说明中将电源电压范围提升至 5.5V .............................................................................................................. 1

Added ±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier.............................................................. 5

Added 5 V support to Recommended Operating Conditions ................................................................................................ 5

Added temperature range for 3.6 V to 5.5 V supply range in Recommended Operating Conditions.................................. 5

Added power dissipation maximum numbers to support 5.5 V in Power Ratings................................................................. 6

Added 5.5 V support in Safety Limiting Values..................................................................................................................... 8

Added 5 V Electrical Characteristics section.......................................................................................................................... 9

Added 5 V Supply Current Characteristics section ................................................................................................................ 9

Added 5.5 V support to Thermal Derating Curves in Insulation Characteristics Curves ..................................................... 14

Added 5 V Supply Current Curves to Typical Characteristics ............................................................................................. 15

Updated Device I/O schematics removing (F version) only text in 图 13 ............................................................................ 20

Extended power supply range to 5.5 V in Application Information ...................................................................................... 21

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

6 Device Comparison Table

Table 1. Device Features

MAXIMUM DATA

RATE

DEFAULT

OUTPUT

PART NUMBER

CHANNEL DIRECTION

PACKAGE

DBQ-16

RATED ISOLATION⁽¹⁾

3000 V_RMS/ 4242 V_PK

3 Forward,

1 Reverse

ISO7041

2 Mbps

High

Low

ISO7041 with F

suffix

3 Forward,

1 Reverse

DBQ-16

(1) See for detailed isolation ratings.

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

7 Pin Configuration and Functions

ISO7041 DBQ Package

16-Pin QSOP

Top View

VCC1

GND1

INA

VCC2

GND2

OUTA

OUTB

OUTC

IND

INB

INC

OUTD

EN1

EN2

GND1

GND2

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Refresh enable 1. Refresh is enabled when the EN1 pin is connected to GND1. Disable

refresh by connecting the EN1 pin high to V_CC1. EN1 and EN2 must be connected to the

same logic state to enable or disable refresh.

EN1

Refresh enable 2. Refresh is enabled when the EN2 pin is connected to GND2. Disable

refresh by connecting the EN2 pin high to V_CC2. EN1 and EN2 must be connected to the

same logic state to enable or disable refresh.

EN2

GND1

GND2

—

Ground connection for V_CC1

Ground connection for V_CC2

INA

Input, channel A

INB

Input, channel B

INC

Input, channel C

Input, channel D

Output, channel A

Output, channel B

Output, channel C

Output, channel D

Power supply, side 1

Power supply, side 2

IND

OUTA

OUTB

OUTC

OUTD

V_CC1

V_CC2

—

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)

MIN

-0.5

-15

MAX

UNIT

V_CC1to GND1

Supply Voltage

V_CC2to GND2

INx to GNDx

Input/Output

OUTx to GNDx

Voltage

V_CCX+ 0.5

ENx to GNDx

Output Current

Temperature

°C

Operating junction temperature, T_J

Storage temperature, T_stg

150

-65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak

voltage values

(3) Maximum voltage must not exceed 6 V.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±6000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

V_(ESD)

Electrostatic discharge

±1500

±8000

Contact discharge per IEC 61000-4-2;

Isolation barrier withstand test⁽³⁾⁽⁴⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.

(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

5.5

UNIT

(1)

V_CC1

V_CC2

V_IH

Supply Voltage Side 1

Supply Voltage Side 2

High level Input voltage

Low level Input voltage

2.25

5.5

0.7 x V_CCI

V_CCI

V_IL

-4

-2

-1

0.3 x V_CCI

V_CCO= 5 V

Mbps

°C

I_OH

High level output current

Low level output current

V_CCO= 3.3 V

V_CCO= 2.5 V

V_CCO= 5 V

I_OL

V_CCO= 3.3 V

V_CCO= 2.5 V

T_A

Data Rate

-55

-40

V_CC1, V_CC2= 2.25 V to 3.6 V

V_CC1, V_CC2= 3.6 V to 5.5 V

125

Ambient temperature

°C

(1) V_CC1and V_CC2can be set independent of one another

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

8.4 Thermal Information

ISO7041

DBQ (SOIC)

16 PINS

87.0

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

33.3

49.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

8.4

ψ_JB

48.5

R_θJC(bot)

—

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

7.82

4.46

3.36

UNIT

P_D

Maximum power dissipation (both sides)

Maximum power dissipation (side-1)

Maximum power dissipation (side-2)

V_CC1= V_CC2= 5.5 V, T_J= 150°C, C_L

15 pF, Input a 1-MHz 50% duty cycle

square wave

P_D1

P_D2

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

8.6 Insulation Specifications

PARAMETER

SPECIFICATIONS

UNIT

TEST CONDITIONS

QSOP-16

IEC 60664-1

CLR

External clearance⁽¹⁾

Side 1 to side 2 distance through air

>3.7

Side 1 to side 2 distance across package

surface

CPG

External Creepage⁽¹⁾

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

IEC 60112; UL 746A

µm

>600

According to IEC 60664-1

Overvoltage category per IEC 60664-1

Rated mains voltage ≤ 300 V_RMS

I-III

DIN V VDE V 0884-11:2017-01⁽²⁾

V_IORMMaximum repetitive peak isolation voltage

AC voltage (bipolar)

566

400

566

4242

V_PK

V_RMS

V_DC

AC voltage (sine wave); time-dependent

dielectric breakdown (TDDB) test; See 图 15

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST= V_IOTM, t = 60 s (qualification); V_TEST

= 1.2 × V_IOTM, t = 1 s (100% production)

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

Test method per IEC 62368-1, 1.2/50 µs

waveform, V_TEST= 1.6 × V_IOSM= 6400 V_PK

(qualification)

V_IOSM

4000

≤ 5

V_PK

Method a: After I/O safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM

t_m= 10 s

Method a: After environmental tests

subgroup 1, V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.6 × V_IORM, t_m= 10 s

≤ 5

q_pd

Apparent charge⁽⁴⁾

Method b1: At routine test (100% production)

and preconditioning (type test), V_ini= V_IOTM

t_ini= 1 s;

≤ 5

V_pd(m)= 1.875 × V_IORM, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

V_IO= 0.4 × sin (2 πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

~1.5

> 10¹²

> 10¹¹

> 10⁹

V_IO= 500 V, 100°C ≤ T_A≤ 150°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

55/125/21

UL 1577

V_TEST= V_ISO, t = 60 s (qualification); V_TEST

1.2 × V_ISO, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

3000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

CSA/Sira

8.7 Safety-Related Certifications

VDE

CSA

CQC

TUV

Plan to certify

Plan to certify for use

in intrinsic safety (IS)

to IS applications

under ATEX and

IECEx

Plan to certify

according to DIN V

VDE V 0884-

11:2017- 01

Plan to certify

according to UL 1577

Component

Certified according to

IEC 60950-1 and IEC

62368-1

Plan to certify

according to

GB4943.1-2011

according to EN

61010-1:2010 (3rd

Ed) and EN 60950-

1:2006/A2:2013

Recognition Program

3000 V_RMSinsulation

per CSA 60950-1-

07+A1+A2, IEC

60950-1 2nd

Ed.+A1+A2, CSA

62368-1- 14 and IEC

62368-1:2014 370

V_RMS(DBQ-16)

maximum working

voltage (pollution

degree 2, material

group I)

3000 V_RMSinsulation

per EN 61010-1:2010

(3rd Ed) up to

working voltage of

300 V_RMS

3000 V_RMSinsulation

per EN 60950-

1:2006/A2:2013 up to

working voltage of

370 V_RMS

Maximum transient

isolation voltage,

ATEX: EN 60079-

0:2012+A11:2013

and EN 60079-

11:2012

IECEx:IEC 60079-

0:2011 (6th Ed) and

IEC60079-11:2011

(6th Ed)

4242 V_PK

;

Basic insulation,

Altitude ≤ 5000 m,

Tropical Climate,

250 V_RMSmaximum

working voltage

Maximum repetitive

peak isolation

Single protection,

3000 V_RMS

voltage, 566 V_PK

;

Maximum surge

isolation voltage,

4000 V_PK

II 1G Ex ia IIC Ga

Certificate planned

8.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

16-QSOP PACKAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

_θJA= 87°C/W, V_I= 5.5 V, T_J= 150°C,

261

399

522

T_A= 25°C

_θJA= 87°C/W, V_I= 3.6 V, T_J= 150°C,

T_A= 25°C

_θJA= 87°C/W, V_I= 2.75 V, T_J= 150°C,

T_A= 25°C

_θJA= 87°C/W, T_J= 150°C, T_A= 25°C

I_S

Safety input, output, or supply current

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

1435

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the table is that of a device installed on a high-K test board for leaded surface-mount

packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

8.9 Electrical Characteristics 5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

V_IT+(IN)

V_IT-(IN)

V_OH

Rising input switching threshold

Falling input switching threshold

High-level output voltage

Low-level output voltage

0.7 x V_CCI

0.3 x V_CCI

V_CCO- 0.4

I_OH= -4 mA

V_OL

I_OL= 4 mA

0.4

Input threshold voltage

hysteresis

V_I(HYS)

0.1 x V_CCI

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CCI⁽¹⁾at INx

V_IL= 0 V at INx

µA

-1

Common mode transient

immunity

CMTI

C_i

V_I= V_CCor 0 V, V_CM= 1200 V

100

kV/us

V_I= V_CC/ 2 + 0.4×sin(2πft), f = 1

MHz, V_CC= 5 V

(2)

Input Capacitance

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

8.10 Supply Current Characteristics 5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

ISO7041

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

I_CC1

I_CC2

I_CC1

6.2

10.1

8.2

14.3

18.5

16.7

µA

Refresh disable

Refresh enable

Supply current - DC

signal

V_I= V_CC1(ISO7041);

V_I= 0 V (ISO7041 with F suffix)

I_CC2

I_CC1

I_CC2

10.8

9.5

18.5

19.9

19.5

µA

Refresh enable

V_I= 0 V (ISO7041);

V_I= V_CC1(ISO7041 with F suffix)

11.3

I_CC1

6.7

11.8

37.1

25.8

340.5

167.0

10.6

11.9

37.1

25.8

338.3

166.0

4.1

19.7

20.6

57.4

37.7

436.1

211.1

20.8

20.4

57.4

37.7

436.1

211.1

7.4

µA

Refresh disable

10 kbps, No Load

I_CC2

I_CC1

Refresh disable

100 kbps, No Load

I_CC2

I_CC1

Refresh disable

1 Mbps, No Load

I_CC2

Supply current - AC

signal

I_CC1

Refresh enable

10 kbps, No Load

I_CC2

I_CC1

Refresh enable

100 kbps, No Load

I_CC2

I_CC1

Refresh enable

1 Mbps, No Load

I_CC2

DC Signal

I_CC1(ch)+ I_CC2(ch)

Total Supply Current

Per Channel,

Refresh Disabled

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

5.9

10.7

23.4

164.5

17.4

137.0

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Supply Current Characteristics 5V Supply (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

V_I= V_CC1(ISO7041);

V_I= 0 V (ISO7041 with F suffix)

I_CC1(ch)+ I_CC2(ch)

4.8

8.5

µA

V_I= 0 V (ISO7041);

V_I= V_CC1(ISO7041 with F suffix)

Total Supply Current

Per Channel,

I_CC1(ch)+ I_CC2(ch)

5.3

9.6

µA

Refresh Enabled

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

I_CC1(ch)+ I_CC2(ch)

5.7

16.4

10.4

22.3

µA

125.9

154.0

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

8.11 Electrical Characteristics 3.3V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

V_IT+(IN)

V_IT-(IN)

V_OH

Rising input switching threshold

Falling input switching threshold

High-level output voltage

Low-level output voltage

0.7 x V_CCI

0.3 x V_CCI

V_CCO- 0.3

I_OH= -2mA

V_CCO- 0.2

0.2

V_OL

I_OL= 2mA

0.3

Input threshold voltage

hysteresis

V_I(HYS)

0.1 x V_CCI

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CCI⁽¹⁾at INx

V_IL= 0 V at INx

µA

-1

Common mode transient

immunity

CMTI

C_i

V_I= V_CCor 0 V, V_CM= 1200 V

100

kV/us

V_I= V_CC/ 2 + 0.4×sin(2πft), f = 1

MHz, V_CC= 3.6 V

Input Capacitance⁽²⁾

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

8.12 Supply Current Characteristics 3.3V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

ISO7041

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

I_CC1

I_CC2

I_CC1

5.1

8.9

6.8

8.8

14.0

12.2

µA

Refresh disable

Refresh enable

Supply current - DC

signal

V_I= V_CC1(ISO7041);

V_I= 0 V (ISO7041 with F suffix)

I_CC2

I_CC1

I_CC2

9.6

8.1

14.0

14.8

15.6

µA

Refresh enable

V_I= 0 V (ISO7041);

V_I= V_CC1(ISO7041 with F suffix)

10.0

I_CC1

7.9

10.4

35.9

22.7

316.4

147.2

9.8

13.7

15.9

48.3

31.4

395.7

188.2

16.4

16.2

48.3

31.4

395.7

188.2

5.7

µA

Refresh disable

10 kbps, No Load

I_CC2

I_CC1

Refresh disable

100 kbps, No Load

I_CC2

I_CC1

Refresh disable

1 Mbps, No Load

I_CC2

Supply current - AC

signal

I_CC1

Refresh enable

10 kbps, No Load

I_CC2

10.5

35.9

22.7

315.3

146.2

3.5

I_CC1

Refresh enable

100 kbps, No Load

I_CC2

I_CC1

Refresh enable

1 Mbps, No Load

I_CC2

DC Signal

I_CC1(ch)+ I_CC2(ch)

Total Supply Current

Per Channel,

Refresh Disabled

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

5.2

8.2

14.8

115.7

19.2

138.7

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Supply Current Characteristics 3.3V Supply (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

V_I= V_CC1(ISO7041);

V_I= 0 V (ISO7041 with F suffix)

I_CC1(ch)+ I_CC2(ch)

4.2

6.8

µA

V_I= 0 V (ISO7041);

V_I= V_CC1(ISO7041 with F suffix)

Total Supply Current

Per Channel,

I_CC1(ch)+ I_CC2(ch)

4.6

7.7

µA

Refresh Enabled

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

I_CC1(ch)+ I_CC2(ch)

5.2

14.8

8.2

19.2

µA

115.7

138.7

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

8.13 Electrical Characteristics 2.5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

V_IT+(IN)

V_IT-(IN)

V_OH

Rising input switching threshold

Falling input switching threshold

High-level output voltage

Low-level output voltage

0.7 x V_CCI

0.3 x V_CCI

V_CCO- 0.2

I_OH= -1mA

V_OL

I_OL= 1mA

0.2

Input threshold voltage

hysteresis

V_I(HYS)

0.1 x V_CCI

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CCI⁽¹⁾at INx

V_IL= 0 V at INx

µA

-1

Common mode transient

immunity

CMTI

V_I= V_CCor 0 V, V_CM= 1200 V

100

kV/us

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

8.14 Supply Current Characteristics 2.5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

ISO7041

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

I_CC1

I_CC2

I_CC1

4.7

8.6

6.4

8.2

13.0

10.9

µA

Refresh disable

Refresh enable

Supply current - DC

signal

V_I= V_CC1(ISO7041);

V_I= 0 V (ISO7041 with F suffix)

I_CC2

I_CC1

I_CC2

9.2

7.6

9.6

13.0

13.2

14.6

µA

Refresh enable

V_I= 0 V (ISO7041);

V_I= V_CC1(ISO7041 with F suffix)

I_CC1

8.2

10.0

34.7

21.3

301.5

137.0

9.9

12.2

14.8

44.5

29.0

367.4

173.3

14.6

15.9

44.5

29.0

367.4

173.3

5.3

µA

Refresh disable

10 kbps, No Load

I_CC2

I_CC1

Refresh disable

100 kbps, No Load

I_CC2

I_CC1

Refresh disable

1 Mbps, No Load

I_CC2

Supply current - AC

signal

I_CC1

Refresh enable

10 kbps, No Load

I_CC2

10.0

34.7

21.3

304.8

136.0

3.3

I_CC1

Refresh enable

100 kbps, No Load

I_CC2

I_CC1

Refresh enable

1 Mbps, No Load

I_CC2

DC Signal

I_CC1(ch)+ I_CC2(ch)

Total Supply Current

Per Channel,

Refresh Disabled

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

5.0

7.5

14.0

110.0

17.6

127.1

V_I= V_CC1(ISO7041);

V_I= 0 V (ISO7041 with F suffix)

I_CC1(ch)+ I_CC2(ch)

4.0

4.4

6.2

7.0

µA

V_I= 0 V (ISO7041);

V_I= V_CC1(ISO7041 with F suffix)

Total Supply Current

Per Channel,

Refresh Enabled

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

I_CC1(ch)+ I_CC2(ch)

5.0

14.0

110

7.5

17.6

µA

127.1

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

8.15 Switching Characteristics

V_CC1, V_CC2= 2.25 V to 5.5 V (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

140

MAX

UNIT

t_PLH, t_PHL

t_P(dft)

Propagation delay time

Propagation delay drift

Minimum pulse width

Pulse width distortion

See 图 9

165

ps/℃

t_UI

500

PWD

Same-direction channels

t_sk(o)

Channel to channel output skew time

Opposite-direction channels

t_sk(p-p)

Part to part skew time

Output signal rise time

Output signal fall time

t_r

t_f

See 图 9

Default output delay time from input

power loss

t_DO

Refresh enabled, See 图 10

400

750

t_PU

F_R

Time from UVLO to valid output data

Refresh rate

kbps

8.16 Insulation Characteristics Curves

1600

600

V_CC= 3.6 V

V_CC= 2.75 V

V_CC= 5.5 V

500

400

300

200

100

1200

800

400

120

160

200

120

160

200

Ambient Temperature (èC)

SLLS

Ambient Temperature (èC)

SLLS

图 2. Thermal Derating Curve for Limiting Power per

图 1. Thermal Derating Curve for Limiting Current per

VDE

200

300

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

8.17 Typical Characteristics

200

300

100

Refresh Enabled

Refresh Disabled

Refresh Enabled

Refresh Disabled

100

Data Rate (kbps)

1000 2000

100

Data Rate (kbps)

1000 2000

SLLS

T_A= 25°C

C_L= 0 pF

T_A= 25°C

C_L= 15 pF

图 3. ISO7041 Supply Current vs Data Rate at 2.5 V

图 4. ISO7041 Supply Current vs Data Rate at 2.5 V

(With No Load)

(With 15-pF Load)

Refresh Enabled

Refresh Disabled

Refresh Enabled

Refresh Disabled

100

Data Rate (Kbps)

1000 2000

100

Data Rate (kbps)

1000 2000

SLLS

T_A= 25°C

C_L= 0 pF

T_A= 25°C

C_L= 15 pF

图 5. ISO7041 Supply Current vs Data Rate at 3.3 V

图 6. ISO7041 Supply Current vs Data Rate at 3.3 V

(With No Load)

(With 15-pF Load)

300

Refresh Enabled

Refresh Disabled

Refresh Enabled

Refresh Disabled

100

Data Rate (kbps)

1000 2000

100

Data Rate (kbps)

1000 2000

SLLS

T_A= 25°C

C_L= 0 pF

T_A= 25°C

C_L= 15 pF

图 7. ISO7041 Supply Current vs Data Rate at 5 V

图 8. ISO7041 Supply Current vs Data Rate at 5 V

(With No Load)

(With 15-pF Load)

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

9 Parameter Measurement Information

CCI

50%

OUT

0 V

PHL

PLH

Input

Generator

(See Note A)

See Note B

90%

10%

50%

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, t_r≤ 3

ns, t_f≤ 3ns, Z_O= 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in

actual application.

B. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图 9. Switching Characteristics Test Circuit and Voltage Waveforms

1.7 V

0 V

OUT

IN = 0 V (Devices without suffix F)

IN = V (Devices with suffix F)

default high

50%

See Note A

default low

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

B. Power Supply Ramp Rate = 10 mV/ns

图 10. Default Output Delay Time Test Circuit and Voltage Waveforms

CCO

CCI

C = 0.1 µF 1%

Pass-fail criteria:

The output must

remain stable.

OUT

or V

See Note A

GNDI

GNDO

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图 11. Common-Mode Transient Immunity Test Circuit

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

10 Detailed Description

10.1 Overview

The ISO7041 device uses edge encoding of data with an ON-OFF keying (OOK) modulation scheme to transmit

the digital data across a silicon dioxide isolation barrier. The transmitter uses a high frequency carrier signal to

pass data across the barrier representing a signal edge transition. Using this method achieves very low power

consumption and high immunity. The receiver demodulates the carrier signal after advanced signal conditioning

and produces the output through a buffer stage. For low data rates, a refresh logic option is available to make

sure the output state matches the input state. The ENx pins of side A and side B must be tied low to enable

refresh or high to disable refresh. Advanced circuit techniques are used to maximize the CMTI performance and

minimize the radiated emissions due the high frequency carrier and IO buffer switching. The conceptual block

diagram of a digital capacitive isolator, 图 12, shows a functional block diagram of a typical channel.

10.2 Functional Block Diagram

Transmitter

Receiver

OOK

Modulation

SiO based

RX OUT

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

TX IN

Edge

Encoding

Capacitive

Isolation

Barrier

EN1

Refresh

Logic

Watch Dog

Timer

EN2

Oscillator

图 12. Conceptual Block Diagram of a Digital Capacitive Isolator

10.3 Feature Description

10.3.1 Refresh Enable

The ISO7041 uses an edge based encoding scheme to transfer an input signal change across the isolation

barrier versus sending across the DC state. consistently validates that the DC output state of each isolator

channel matches the DC input state. An internal watchdog timer monitors for activity on the individual inputs and

transmits the logic state when there is no input signal transition for more than 100 µs. This ensures that the input

and output state of the isolator always match. Tie both EN1 and EN2 to their respective grounds to enable

refresh.

Disable refresh by tying both EN1 and EN2 to their respective VCC power supplies. Disabling refresh will further

decrease the power consumption of the device but the DC state is not guaranteed at startup. System level

solutions can be implemented to ensure the isolator channel output matches the input at startup. For example, at

start up, an immediate full transition of the input signals from high to low and low to high on the individual isolator

lines would allow the states of the outputs to properly track the inputs.

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Feature Description (接下页)

10.3.2 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO70xx

family of devices incorporates many chip-level design improvements for overall system robustness. Some of

these improvements include:

•

Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

Low-resistance connectivity of ESD cells to supply and ground pins.

Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

•

PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

The device has no issue being able to meet either CISPR 22 Class A and CISPR22 Class B standards in an

unshielded environment.

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

10.4 Device Functional Modes

表 2 shows the functional modes for the device.

表 2. Function Table⁽¹⁾

REFRESH

ENABLE

(ENx)

INPUT

(INx)⁽²⁾

OUTPUT

(OUTx)

V_CCI

V_CCO

COMMENTS

Normal Operation:

A channel output assumes the logic state of its input.

The device needs an input signal transition to validate the output

Undetermined tracks the input state. Without a signal edge transition, the output will

be in an undetermined state.

When V_CCIis unpowered, a channel output assumes the logic state

based on the selected default option. Default is High for the device

without the F suffix and Low for device with the F suffix.

Default

When V_CCItransitions from unpowered to powered-up, a channel

output assumes the logic state of the input.

When V_CCItransitions from powered-up to unpowered, channel output

assumes the selected default state.

When V_CCIis unpowered, a channel output assumes the logic state

based on the previous state of the output before V_CCIpowered down.

Undetermined

When V_CCOis unpowered, a channel output is undetermined⁽³⁾

Undetermined When V_CCOtransitions from unpowered to powered-up, a channel

output assumes the logic state of the input.

When V_CCOis unpowered, a channel output is undetermined⁽³⁾

Undetermined When V_CCOtransitions from unpowered to powered-up, a channel

output assumes the selected default option.

When ENx is unconnected or open, the device output will be in an

Undetermined undetermined and unknown state. ENx must be connected high or

low for the device to behave correctly.

Open

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC; PU = Powered up (V_CC≥ 2.25 V); PD = Powered down (V_CC≤ 1.54); X = Irrelevant; H =

High level; L = Low level ; Z = High Impedance

(2) A strongly driven input signal can weakly power the floating V_CCthrough an internal protection diode and cause undetermined output.

(3) The outputs are in undetermined state when 2.25 V < V_CCI, V_CCO< 2.25 V.

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

10.4.1 Device I/O Schematics

Refresh Enable

Input

CCI

985 ꢀ

1970 ꢀ

INx

ENx

Output

CCO

~20 ꢀ

OUTx

图 13. Device I/O Schematics

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

11 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Application Information

The ISO7041 device is an ultra-low power digital isolator. The device uses single-ended CMOS-logic switching

technology. The voltage range is from 2.25 V to 5.5 V for both supplies, V_CC1and V_CC2, and can be set

irrespective of one another. When designing with digital isolators, keep in mind that because of the single-ended

design structure, digital isolators do not conform to any specific interface standard and are only intended for

isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data

controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or

standard. See Isolated power and data interface for low-power applications reference design TI Design for

detailed information on designing the ISO70xx in low-power applications.

11.1.1 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown

(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal

device and high voltage applied between the two sides; see 图 14 for TDDB test setup. The insulation

breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced

insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million

(ppm) and a minimum insulation lifetime of 20 years. VDE standard also requires additional safety margin of 20%

for working voltage and 87.5% for insulation lifetime which translates into minimum required life time of 37.5

years.

图 15 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime. Based

on the TDDB data, the intrinsic capability of these devices is 400 VRMS with a lifetime of >100 years. Other

factors, such as package size, pollution degree, material group, and so forth can further limit the working voltage

of the component. The working voltage of the DBQ-16 package specified up to 400 VRMS. At the lower working

voltages, the corresponding insulation barrier life time is much longer.

Vcc 1

Vcc 2

Time Counter

> 1 mA

DUT

GND

GND 2

Oven at 150 °C

图 14. Test Setup for Insulation Lifetime Measurement

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Application Information (接下页)

图 15. Insulation Lifetime Projection Data

11.2 Typical Application

图 16 shows the isolated serial peripheral interface (SPI).

Isolation Barrier

VCC1

0.1 ꢀF

VCC2

0.1 …F

0.1 ꢀF

1 kΩ

0.27 …F

4.7 …F

V_CC1

INA

V_CC2

DVDD AVDD

ADS1220

AVcc DVcc

AIN0

AIN1

AIN2

AIN3

OUTA

OUTB

P1.4

SCLK

DIN

INB

INC

SCLK

Thermocouple

0.27 …F

MSP430FR2355

ISO7041

OUTC

SDO

SDI

DOUT/DRDY

DGND CLK AVSS

OUTD

EN1

IND

AVss DVss

EN2

GND1

GND2

图 16. Isolated SPI for a Temperature Field Transmitter

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

Typical Application (接下页)

11.2.1 Design Requirements

To design with these devices, use the parameters listed in 表 3.

表 3. Design Parameters

PARAMETER

VALUE

2.25 V to 5.5 V

0.1 µF

Supply voltage, V_CC1and V_CC2

Decoupling capacitor between V_CC1and GND1

Decoupling capacitor from V_CC2and GND2

0.1 µF

11.2.2 Detailed Design Procedure

Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,

the device only require two external bypass capacitors to operate.

2 mm maximum

from V_CC2

2 mm maximum

from V_CC1

V_CC2

V_CC1

0.1 µF

GND1

GND2

INA

INB

INC

OUTA

OUTB

OUTC

IND

OUTD

EN2

EN1

GND2

GND1

图 17. Typical ISO7041 Circuit Hook-up

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

11.2.3 Application Curves

The following typical eye diagrams of the device indicates wide open eye at the maximum data rate of 2 Mbps.

图 18. Eye Diagram at 2 Mbps PRBS 2¹⁶– 1, 3.3 V and 25°C

图 19. Eye Diagram at 2 Mbps PRBS 2¹⁶– 1, 2.5 V and 25°C

12 Power Supply Recommendations

Put a 0.1-μF bypass capacitor at the input and output supply pins (V_CC1and V_CC2) to make sure that operation is

reliable at data rates and supply voltage. Put the capacitors as near to the supply pins as possible. If only one

primary-side power supply is available in an application, use a transformer driver to help generate the isolated

power for the secondary-side. Texas Instruments recommends the SN6501 device or SN6505A device. Refer to

the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505 Low-Noise 1-A Transformer

Drivers for Isolated Power Supplies data sheet for detailed power supply design and transformer selection

recommendations.

ISO7041

www.ti.com.cn

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

13 Layout

13.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

•

Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in².

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to

the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be placed closer together, thus increasing the high-frequency

bypass capacitance significantly.

Refer to the Digital Isolator Design Guide for detailed layout recommendations,.

13.1.1 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace

lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper

alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and

stiffness, and the self-extinguishing flammability-characteristics.

13.2 Layout Example

High-speed traces

10 mils

Ground plane

Keep this space

FR-4

free from planes,

traces, pads, and

vias

40 mils

0_r~ 4.5

Power plane

10 mils

Low-speed traces

Figure 20. Recommended Layer Stack

ISO7041

ZHCSJ22B –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

14 器件和文档支持

14.1 文档支持

14.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《数字隔离器设计指南》

德州仪器 (TI)，《隔离相关术语》

德州仪器 (TI)，《具有集成 PGA 和基准的 ADS1220 4 通道 2kSPS 低功耗 24 位 ADC》数据表

德州仪器 (TI)，《具有 UART 接口的 ADS122U04 24 位 4 通道 2kSPS Δ-Σ ADC》数据表

德州仪器 (TI)，《具有 PGA 和电压基准的 ADS124S0x 低功耗、低噪声、高集成度、6 通道和 12 通道 4kSPS

24 位 Δ-Σ ADC》数据表

•

德州仪器 (TI)，《用于超低功耗和低功耗应用的独特高效率隔离式直流/直流转换器》TI 设计

德州仪器 (TI)，《SN6501 用于隔离式电源的变压器驱动器》数据表

德州仪器 (TI)，《SN6505A 用于隔离式电源的低噪声 1A 变压器驱动器》数据表

德州仪器 (TI)，《适用于低功耗应用的隔离式电源和数据接口参考设计》 TI 设计

14.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

14.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.4 商标

E2E is a trademark of Texas Instruments.

14.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

14.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

15 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ISO7041DBQ

ISO7041DBQR

ISO7041FDBQ

ISO7041FDBQR

ACTIVE

SSOP

DBQ

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-55 to 125

7041

2500 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

NIPDAU

7041F

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ISO7041DBQR

ISO7041FDBQR

SSOP

DBQ

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ISO7041DBQR

ISO7041FDBQR

SSOP

DBQ

2500

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ISO7041DBQ

ISO7041FDBQ

DBQ

SSOP

505.46

6.76

3810

Pack Materials-Page 3

PACKAGE OUTLINE

DBQ0016A

SSOP - 1.75 mm max height

SCALE 2.800

SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

14X .0250

[0.635]

.189-.197

[4.81-5.00]

NOTE 3

.175

[4.45]

16X .008-.012

[0.21-0.30]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.007 [0.17]

C A

.005-.010 TYP

[0.13-0.25]

SEE DETAIL A

.010

[0.25]

GAGE PLANE

.004-.010

[0.11-0.25]

0 - 8

.016-.035

[0.41-0.88]

DETAIL A

TYPICAL

(.041 )

[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 inch, per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MO-137, variation AB.

www.ti.com

EXAMPLE BOARD LAYOUT

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SEE

DETAILS

SYMM

16X (.016 )

[0.41]

14X (.0250 )

[0.635]

(.213)

[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

.002 MAX

[0.05]

ALL AROUND

.002 MIN

[0.05]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SYMM

16X (.016 )

[0.41]

SYMM

14X (.0250 )

[0.635]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL

SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ISO7041 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E