ISO7142CC-Q1 [TI]
汽车类四通道、2/2、50Mbps 数字隔离器;
| 型号： | ISO7142CC-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类四通道、2/2、50Mbps 数字隔离器 |
| 文件： | 总27页 (文件大小：926K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
ISO7142CC-Q1 4242 VPK 小型封装低功耗四通道数字隔离器
1 特性
2 应用
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
•
•
•
•
通用隔离
工业自动化
电机控制
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
太阳能逆变器
–
–
器件人体模型 (HBM) 分类等级 3A
3 说明
器件充电器件模型 (CDM) 分类等级 C6
ISO7142CC-Q1 器件可提供符合 UL 1577 标准的长达
1 分钟且高达 2500 VRMS 的电流隔离，以及符合 VDE
V 0884-10 标准的 4242 VPK隔离。
•
•
•
最大信号传输速率：50Mbps（5V 电源供电）
具有集成噪声滤波器的稳健设计
低功耗，每通道 ICC 典型值（3.3V 电源）：
ISO7142CC-Q1 是一款四通道隔离器，此隔离器具有
两个正向和两个反向通道。此器件在由 5V 电源供电时
的最大数据传输速率为 50Mbps，而在由 3.3V 或 2.7V
电源供电时的最大数据传输速率为 40Mbps。
ISO7142CC-Q1 器件的输入端集成有滤波器，适用于
易受噪声干扰的应用。
–
1Mbps 时为 1.3mA，25Mbps 时为 2.5mA
•
•
•
•
•
•
典型值为 50kV/µs 的瞬态抗扰度
使用 SiO2 绝缘隔栅实现长使用寿命
可由 2.7V、3.3V 和 5V 电源供电
2.7V 和 5V 电平转换
小型四分之一尺寸小外形封装 (QSOP)-16 封装
安全及管理批准
每个隔离通道都有一个由二氧化硅 (SiO2) 绝缘隔栅分
开的逻辑输入和输出缓冲器。与隔离式电源一起使用，
这个器件可防止数据总线或者其它电路上的噪音电流进
入本地接地和干扰或损坏敏感电路。该器件具有晶体管
晶体管逻辑电路 (TTL) 输入阈值，并且可由 2.7V、
3.3V 和 5V 电压供电运行。
–
–
–
–
符合 UL 1577 标准且长达 1 分钟的 2500 VRMS
隔离
符合 DIN V VDE V 0884-10 (VDE V 0884-
10):2006-12 标准的 4242 VPK 隔离
CSA 组件验收通知 5A，IEC 60950-1 和 IEC
61010-1 终端设备标准
器件信息(1)
已通过符合 GB4943.1-2011 的 CQC 认证
器件型号
封装
SSOP (16)
封装尺寸（标称值）
ISO7142CC-Q1
4.90mm × 3.90mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
V
CCO
V
CCI
Isolation
Capacitor
INx
OUTx
ENx
GNDI
GNDO
V
CCI 和 GNDI 分别是输入通道的电源和接地连接。
CCO 和 GNDO 分别是输出通道的电源和接地连接。
V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSER5
ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
7
8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics—5-V Supply ..................... 5
6.6 Supply Current Characteristics—5-V Supply............ 5
6.7 Electrical Characteristics—3.3-V Supply .................. 5
6.8 Supply Current Characteristics—3.3-V Supply......... 6
6.9 Electrical Characteristics—2.7-V Supply .................. 6
6.10 Supply Current Characteristics—2.7-V Supply....... 6
6.11 Power Dissipation Characteristics .......................... 6
6.12 Switching Characteristics—5-V Supply................... 7
6.13 Switching Characteristics—3.3-V Supply................ 7
6.14 Switching Characteristics—2.7-V Supply................ 8
6.15 Typical Characteristics............................................ 8
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 文档支持................................................................ 20
12.2 社区资源................................................................ 20
12.3 商标....................................................................... 20
12.4 静电放电警告......................................................... 20
12.5 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 12 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
ISO7142CC-Q1
www.ti.com.cn
ZHCSEG9 –DECEMBER 2015
5 Pin Configuration and Functions
DBQ Package
16-Pin SSOP
Top View
VCC1
VCC2
1
2
16
GND2
OUTA
OUTB
INC
15
GND1
INA
3
4
5
6
7
8
14
13
12
11
10
9
INB
OUTC
OUTD
EN1
IND
EN2
GND1
GND2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-
impedance state when EN1 is low.
EN1
7
I
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-
impedance state when EN2 is low.
EN2
10
2
8
GND1
—
—
Ground connection for VCC1
Ground connection for VCC2
9
GND2
15
3
INA
I
I
Input, channel A
Input, channel B
Input, channel C
Input, channel D
Output, channel A
Output, channel B
Output, channel C
Output, channel D
Power supply, VCC1
Power supply, VCC2
INB
4
INC
12
11
14
13
5
I
IND
I
OUTA
OUTB
OUTC
OUTD
VCC1
VCC2
O
O
O
O
—
—
6
1
16
Copyright © 2015, Texas Instruments Incorporated
3
ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–15
MAX
UNIT
Supply voltage(2)
Voltage
VCC1, VCC2
6
V
INx, OUTx, ENx
VCC + 0.5(3)
V
IO
Output current
15
mA
°C
°C
TJ
Maximum junction temperature
Storage temperature
150
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
2.7
–4
NOM
MAX
UNIT
VCC1, VCC2
IOH
Supply voltage
5.5
V
V
CC ≥ 3 V
High-level output current
mA
VCC < 3 V
–2
IOL
VIH
VIL
Low-level output current
High-level input voltage
Low-level input voltage
4
5.5
0.8
mA
V
2
0
V
V
CC ≥ 4.5 V
VCC < 4.5 V
CC ≥ 4.5 V
VCC < 4.5 V
20
25
0
tui
Input pulse duration
Signaling rate
ns
V
50
40
1 / tui
Mbps
0
TJ
Junction temperature
Ambient temperature
136
125
°C
°C
TA
–55
25
6.4 Thermal Information
ISO7142CC-Q1
DBQ (SSOP)
16 PINS
104.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
57.8
Junction-to-board thermal resistance
46.8
ψJT
Junction-to-top characterization parameter
18.3
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
46.4
RθJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
ISO7142CC-Q1
www.ti.com.cn
ZHCSEG9 –DECEMBER 2015
6.5 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 8
MIN
VCCO (1) – 0.5
VCCO – 0.1
TYP
MAX UNIT
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 8
IOL = 4 mA; see Figure 8
IOL = 20 μA; see Figure 8
0.4
V
VOL
Low-level output voltage
0.1
Input threshold voltage
hysteresis
VI(HYS)
480
70
mV
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
–10
25
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V; see Figure 11
kV/μs
(1) VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
6.6 Supply Current Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Disable
EN1 = EN2 = 0 V
ICC1, ICC2
0.8
1.6
5
DC signal: VI = VCCI or 0 V,
DC to 1 Mbps AC signal: All channels switching with ICC1 , ICC2
square wave clock input; CL = 15 pF
3.3
All channels switching with square
wave clock input; CL = 15 pF
Supply current for VCC1 and VCC2
10 Mbps
25 Mbps
50 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
4.9
7.3
7
10
mA
All channels switching with square
wave clock input; CL = 15 pF
All channels switching with square
wave clock input; CL = 15 pF
11.1
14.5
6.7 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 8
MIN
VCCO (1) – 0.5
TYP
MAX UNIT
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 8
IOL = 4 mA; see Figure 8
IOL = 20 μA; see Figure 8
VCCO – 0.1
0.4
V
VOL
Low-level output voltage
0.1
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
460
50
mV
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
IIL
Low-level input current
–10
25
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V; see Figure 11
kV/μs
(1) VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
Copyright © 2015, Texas Instruments Incorporated
5
ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
www.ti.com.cn
6.8 Supply Current Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Disable
EN1 = EN2 = 0 V
ICC1, ICC2
0.5
2.5
1
4
DC signal: VI = VCCI or 0 V
DC to 1 Mbps AC signal: All channels switching with
square-wave clock input; CL = 15 pF
ICC1, ICC2
All channels switching with square
10 Mbps
Supply current for VCC1 and VCC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
3.5
5
5
7
mA
wave clock input; CL = 15 pF
All channels switching with square
25 Mbps
wave clock input; CL = 15 pF
All channels switching with square
40 Mbps
6.5
10
wave clock input; CL = 15 pF
6.9 Electrical Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –2 mA; see Figure 8
MIN
VCCO (1) – 0.3
TYP
MAX UNIT
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 8
IOL = 4 mA; see Figure 8
IOL = 20 μA; see Figure 8
VCCO – 0.1
0.4
V
VOL
Low-level output voltage
0.1
Input threshold voltage
hysteresis
VI(HYS)
360
45
mV
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
–10
25
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V; see Figure 11
kV/μs
(1) VCCI= Supply voltage for the input channel; VCCO = Supply voltage for the output channel
6.10 Supply Current Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Disable
EN1 = EN2 = 0 V
ICC1, ICC2
0.4
0.8
3.5
DC signal: VI = VCCI or 0 V
DC to 1 Mbps AC signal: All channels switching with
square-wave clock input; CL = 15 pF
ICC1, ICC2
2.2
All channels switching with square
10 Mbps
Supply current for VCC1 and VCC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
3
4.2
5.4
4.2
5.5
7.5
mA
wave clock input; CL = 15 pF
All channels switching with square
25 Mbps
wave clock input; CL = 15 pF
All channels switching with square
40 Mbps
wave clock input; CL = 15 pF
6.11 Power Dissipation Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
170
UNIT
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF
Input a 25-MHz, 50% duty cycle square wave
PD
Device power dissipation
6
Copyright © 2015, Texas Instruments Incorporated
ISO7142CC-Q1
www.ti.com.cn
ZHCSEG9 –DECEMBER 2015
6.12 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
See Figure 8
MIN
TYP
MAX UNIT
38 ns
tPLH, tPHL
PWD(1)
Propagation delay time
Pulse width distortion |tPHL – tPLH
15
21
|
See Figure 8
3.5 ns
Same-direction channels
Opposite-direction channels
1.5
ns
Channel-to-channel output skew
time
(2)
tsk(o)
6.5
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
14 ns
ns
tr
tf
See Figure 8
See Figure 8
2.5
2.1
ns
Disable propagation delay,
high/low-to-high impedance
output
tPHZ, tPLZ
See Figure 9
7
12 ns
Enable propagation delay, high
impedance-to-high output
tPZH
tPZL
See Figure 9
See Figure 9
See Figure 10
6
12 ns
23 us
Enable propagation delay, high
impedance-to-low output
12
Fail-safe output delay time from
input data or power loss
tfs
8
μs
tGR
Input glitch rejection time
9.5
ns
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
6.13 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
Pulse width distortion |tPHL
See Figure 8
See Figure 8
16
25
46
ns
–
3
ns
tPLH
|
Same-direction Channels
2
6.5
21
Channel-to-channel output
skew time
(2)
tsk(o)
ns
Opposite-direction Channels
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
ns
ns
ns
tr
tf
See Figure 8
See Figure 8
3
2.5
Disable propagation delay, from
high/low to high-impedance
output
tPHZ, tPLZ
See Figure 9
9
14
ns
Enable propagation delay, from
high-impedance to high output
tPZH
tPZL
See Figure 9
See Figure 9
See Figure 10
9
17
24
ns
us
Enable propagation delay, from
high-impedance to low output
12
Fail-safe output delay time from
input data or power loss
tfs
7
μs
tGR
Input glitch rejection time
11
ns
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2015, Texas Instruments Incorporated
7
ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
www.ti.com.cn
6.14 Switching Characteristics—2.7-V Supply
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
Pulse width distortion |tPHL
See Figure 8
See Figure 8
18
28
50 ns
–
3
3
ns
ns
tPLH
|
Same-direction Channels
Channel-to-channel output
skew time
(2)
tsk(o)
Opposite-direction Channels
8.5 ns
24 ns
ns
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
tr
tf
See Figure 8
See Figure 8
3.5
2.8
ns
Disable propagation delay, from
high/low to high-impedance
output
tPHZ, tPLZ
See Figure 9
10
15 ns
Enable propagation delay, from
high-impedance to high output
tPZH
tPZL
See Figure 9
See Figure 9
See Figure 10
10
12
19 ns
23 us
Enable propagation delay, from
high-impedance to low output
Fail-safe output delay time from
input data or power loss
tfs
7
μs
tGR
Input glitch rejection time
12
ns
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
6.15 Typical Characteristics
12
10
8
6
5
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
4
3
6
2
4
1
VCC at 3.3 V
2
0
V
at 5 V
CC
œ1
0
œ15
œ10
œ5
0
C002
0
10
20
30
40
50
60
C001
High-Level Output Current (mA)
Data Rate (Mbps)
TA = 25°C
CL = 15 pF
TA = 25°C
Figure 1. ISO7142CC-Q1 Supply Current for All Channels vs
Data Rate
Figure 2. High-Level Output Voltage
vs High-Level Output Current
8
Copyright © 2015, Texas Instruments Incorporated
ISO7142CC-Q1
www.ti.com.cn
ZHCSEG9 –DECEMBER 2015
Typical Characteristics (continued)
1.2
2.50
2.48
2.46
2.44
2.42
2.40
2.38
2.36
2.34
VCC at 3.3 V
V
at 5 V
CC
0.8
0.4
0.0
VCC Rising
VCC Falling
0
5
10
15
œ55
œ25
5
35
65
95
125
C003
Low-Level Output Current (mA)
Free-Air Temperature (oC)
C004
TA = 25°C
Figure 3. Low-Level Output Voltage
vs Low-Level Output Current
Figure 4. VCC Undervoltage Threshold
vs Free-Air Temperature
30
25
20
15
10
5
14
12
10
8
6
4
tpLH at 3.3 V
t at 3.3 V
pHL
tGR at 3.3 V
2
tpLH at 5 V
tGR at 2.7 V
t at 5 V
pHL
tGR at 5 V
0
0
œ55
œ25
5
35
65
95
125
C005
œ55
œ25
5
35
65
95
125
C006
Free-Air Temperature (oC)
Free-Air Temperature (oC)
Figure 5. Propagation Delay Time
vs Free-Air Temperature
Figure 6. Input Glitch Rejection Time
vs Free-Air Temperature
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Output jitter at 2.7 V
Output jitter at 3.3 V
Output Jitter at 5 V
0.0
0
20
40
60
C007
Data Rate (Mbps)
TA = 25°C
Figure 7. Peak-Peak Output Jitter vs Data Rate
Copyright © 2015, Texas Instruments Incorporated
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7 Parameter Measurement Information
VCCI
VI
50%
50%
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator
Note A
50 W
VI
CL
VOH
VOL
90%
10%
Note B
50%
50%
VO
tr
tf
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the input-generator signal. It is not
needed in an actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Switching-Characteristics Test Circuit and Voltage Waveforms
V
CC
VCC
VCC / 2
VCC / 2
RL = 1 kΩ 1%
OUT
VI
0 V
IN
tPLZ
tPZL
VO
0 V
VCC
0.5 V
VO
50%
EN
CL
V
OL
See Note B
Input
Generator
V
I
50 Ω
See Note A
VCC
VO
VCC / 2
VCC / 2
IN
OUT
VI
3 V
0 V
tPZH
EN
CL
See Note B
VOH
RL = 1 kΩ 1%
Input
50%
0.5 V
VO
Generator
See Note A
V
I
50 W
0 V
tPHZ
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Enable/Disable Propagation Delay-Time Test Circuit and Waveform
10
Copyright © 2015, Texas Instruments Incorporated
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ZHCSEG9 –DECEMBER 2015
Parameter Measurement Information (continued)
V
I
V
V
CC
CC
2.7 V
V
I
0 V
IN
OUT
t
V
fs
VIN = 0 V
O
V
OH
50%
V
O
C
L
See Note A
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Failsafe Delay-Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 μF 1ꢀ
C = 0.1 μF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL
Note A
VOH or VOL
–
GNDI
GNDO
–
+
VCM
A. CL = 15pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
Copyright © 2015, Texas Instruments Incorporated
11
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8 Detailed Description
8.1 Overview
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
50 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-
ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input.
The following capacitor-resistor networks differentiate the signal into transients, which then are converted into
differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an
output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between
signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case
of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency
channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
Lsolation .arrier
OSC
LPF
[owtCrequency
/hannel
PWM
VREF
(5/ꢀꢀꢀ100 kbps)
0
1
OUT
{
IN
DCL
IightCrequency
/hannel
VREF
(100 kbpsꢀꢀꢀꢁ0 ꢂbps)
Figure 12. Conceptual Block Diagram of a Digital Capacitive Isolator
12
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8.3 Feature Description
8.3.1 Insulation and Safety-Related Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DTI
Distance through the insulation
Input capacitance
Minimum internal gap (internal clearance)
0.014
mm
pF
(1)
CI
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
2
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIOTM Maximum transient isolation voltage
VIORM Maximum working isolation voltage
4242
566
VPK
VPK
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
679
906
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
VPR
Input-to-output test voltage
VPK
Partial discharge < 5 pC
Method b1, 100% production test,
VPR = VIORM x 1.875, t = 1 s,
Partial discharge < 5 pC
1061
L(I01) Minimum air gap (clearance)
Shortest terminal to terminal distance through air
3.7
3.7
mm
mm
Minimum external tracking
Shortest terminal to terminal distance across the
package surface
L(I02)
(creepage)
Pollution degree
2
Tracking resistance (comparative
tracking index)
CTI
DIN EN 60112 (VDE 0303-11); IEC 60112
VIO = 500 V, TA = 25oC
≥400
V
>1012
>1011
>109
2.4
Isolation resistance, input to output VIO = 500 V, 100oC ≤ TA ≤ 125oC
Ω
(2)
RIO
CIO
VIO = 500 V, TS = 150oC
(2)
Barrier capacitance, input to output VI = 0.4 sin (2πft), f = 1 MHz
pF
UL 1577
Withstanding Isolation voltage
VTEST = VISO= 2500 VRMS, 60 sec (qualification);
VISO
VTEST = 1.2 * VISO= 3000 VRMS, 1 sec (100%
production)
2500 VRMS
(1) Measured from input data pin to ground.
(2) All pins on each side of the barrier tied together creating a two-terminal device.
spacer
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
Table 1. IEC 60664-1 Ratings Table
PARAMETER
Material Group
TEST CONDITIONS
SPECIFICATION
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Installation classification / Overvoltage
Category for Basic Insulation
Copyright © 2015, Texas Instruments Incorporated
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ISO7142CC-Q1
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8.3.2 Regulatory Information
VDE
UL
CSA
CQC
Certified according to DIN V
VDE V 0884-10 (VDE V 0884-
10):2006-12 and DIN EN
Certified under UL 1577
Component Recognition
Program
Approved under CSA Component
Acceptance Notice 5A, IEC 60950-1
and IEC 61010-1
Plan to certify according to GB
4943.1-2011
61010-1 (VDE 0411-1):2011-07
3000 VRMS Isolation rating;
185 VRMS Reinforced Insulation and
370 VRMS Basic Insulation per CSA
60950-1-07+A1+A2 and IEC 60950-1
2nd Ed.+A1+A2;
150 VRMS Reinforced Insulation and
300 VRMS Basic Insulation per CSA
61010-1-12 and IEC 61010-1 3rd Ed.
Basic Insulation;
Maximum transient Isolation
IsolatiIsolationvoltage, 4242 VPK Single protection, 2500 VRMS
Maximum working isolation
voltage, 566 VPK
Basic Insulation, Altitude ≤
5000m, Tropical climate, 250
VRMS maximum working
voltage.
(1)
File number: 40016131
File number: E181974
Master contract number: 220991
Certification Planned
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
8.3.3 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output
circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting,
dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary
system failures.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
θJA = 104.5°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
DBQ-16 θJA = 104.5°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
θJA = 104.5°C/W, VI = 2.7 V, TJ = 150°C, TA = 25°C
217
Safety input, output, or supply
current
IS
332
443
150
mA
°C
TS Maximum safety temperature
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the
ambient temperature plus the power times the junction-to-air thermal resistance.
500
VCC1 = VCC2 = 2.7 V
VCC1 = VCC2 = 3.6 V
450
VCC1 = VCC2 = 5.5 V
400
350
300
250
200
150
100
50
0
0
50
100
150
200
Ambient Temperature (èC)
D001
Figure 13. Thermal Derating Curve for Safety Limiting Current per VDE
14
Copyright © 2015, Texas Instruments Incorporated
ISO7142CC-Q1
www.ti.com.cn
ZHCSEG9 –DECEMBER 2015
8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7142CC-Q1.
Table 2. Function Table(1)
INPUT
(INx)
OUTPUT ENABLE
(ENx)
OUTPUT
(OUTx)
VCCI
VCCO
H
L
H or open
H
H or open
L
PU
PU
X
L
Z
Open
X
H or open
H
PD
PD
X
PU
PU
PD
H or open
H
X
L
Z
X
X
Undetermined
(1) VCCI = Input-side Supply Voltage; VCCO = Output-side Supply Voltage; PU = Powered Up (VCC ≥ 2.7
V); PD = Powered Down (VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L = Low Level; Z = High
Impedance
8.4.1 Device I/O Schematics
Output
Input
V
V
CCO
V
V
V
CCI
CCI
CCI
CCI
5 mA
500 W
40 W
INx
OUTx
Enable
V
V
V
V
CCO
CCO
CCO
CCO
5 mA
500 W
ENx
Figure 14. Device I/O Schematics
Copyright © 2015, Texas Instruments Incorporated
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ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7142CC-Q1 device uses single-ended TTL-logic switching technology. The supply voltage range is from
2.7 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because
of the single-ended design structure the single-ended design structure, digital isolators do not conform to any
specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The
isolator is typically placed between the data controller (that is, µC or UART), and a data converter or a line
transceiver, regardless of the interface type or standard.
9.2 Typical Application
Figure 15 shows the typical isolated CAN interface implementation.
VS
10 ꢀF
3.3 V
2
MBR0520L
Vcc
1:1.33
ISO 3.3V
3
1
1
5
2
D2
D1
IN
OUT
TPS76333-Q1
SN6501-Q1
10 ꢀF
0.1 ꢀF
10 ꢀF
3
EN
GND
MBR0520L
GND
GND
4
5
ISO Barrier
0.1 ꢀF
0.1 ꢀF
VCC2
0.1 ꢀF
0.1 ꢀF
29,57
3
VCC1
V
VCC
DDIO
8
RS
1
5
16
10 ꢁ (optional)
10 ꢁ (optional)
26
25
CANRXA
CANTXA
CANH
OUTC
INA
INC
R
7
6
TMS320F28
035PAGQ
4
12
14
SN65HVD231Q
D
OUTA
CANL
Vref
1
3
5
GND
SM712
V
SS
6,28
2
ISO7142CC-Q1
0.1 ꢀF
3
4.7 nF / 2 kV
0.1 ꢀF
OUTD
INB
VCC
8
RS
29,57
10 ꢁ (optional)
IND
6
4
11
CANH
V
7
6
DDIO
R
4
OUTB
10 ꢁ (optional)
26
25
SN65HVD231Q
13
CANRXA
CANTXA
CANL
Vref
D
1
TMS320F28
035PAGQ
GND1
GND2
2,8
9,15
5
GND
2
SM712
V
SS
6,28
4.7 nF / 2 kV
Figure 15. Typical Isolated CAN Application Circuit for ISO7142CC-Q1
9.2.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7142CC-Q1 device only requires two external bypass capacitors to operate.
16
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ISO7142CC-Q1
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ZHCSEG9 –DECEMBER 2015
Typical Application (continued)
9.2.2 Detailed Design Procedure
Figure 16 shows the hookup of a typical ISO7142CC-Q1 circuit. The only external components are two bypass
capacitors.
V
V
CC1
CC2
ISO7142CC
0.1 µF
0.1 µF
V
V
CC2
CC1
1
2
3
4
16
GND1
GND2
15
14
INA
OUTA
OUTB
INC
13
INB
OUTC
12
11
10
9
5
6
7
8
IND
OUTD
EN2
EN1
GND1
GND2
Figure 16. Typical ISO7142CC-Q1 Circuit Hook-up
9.2.3 Application Curves
Figure 17. Typical Eye Diagram at 40 Mbps,
PRBS 216 - 1, 2.7-V Operation
Figure 18. Typical Eye Diagram at 40 Mbps,
PRBS 216 - 1, 3.3-V Operation
Copyright © 2015, Texas Instruments Incorporated
17
ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
www.ti.com.cn
Typical Application (continued)
Figure 19. Typical Eye Diagram at 50 Mbps,
PRBS 216 - 1, 5-V Operation
10 Power Supply Recommendations
To help ensure reliable operation supply voltages, a 0.1-µF bypass capacitor is recommended at the input and
output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If
only a single primary-side power supply is available in an application, isolated power can be generated for the
secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501-
Q1 datasheet (SLLSEF3).
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide, SLLA284.
18
Copyright © 2015, Texas Instruments Incorporated
ISO7142CC-Q1
www.ti.com.cn
ZHCSEG9 –DECEMBER 2015
Layout Guidelines (continued)
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL 94 V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 20. Recommended Layer Stack
版权 © 2015, Texas Instruments Incorporated
19
ISO7142CC-Q1
ZHCSEG9 –DECEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
•
•
《数字隔离器设计指南》，SLLA284
《隔离相关术语》，SLLA353
《ISO71xx EVM 用户指南》，SLLU179
《SN6501-Q1 用于隔离电源的变压器驱动器》，SLLSEF3
《SN65HVD231Q-Q1 3.3V CAN 收发器》，SGLS398
《TMS320F28035 Piccolo™ 微控制器》，SPRS584
《TPS76333-Q1 低功耗 150mA 低压降线性稳压器》，SGLS247
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
20
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Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7142CCQDBQQ1
ISO7142CCQDBQRQ1
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
7142Q
7142Q
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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