ISO721M-EP [TI]
3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS; 3.3 V / 5 V高速数字隔离器
| 型号： | ISO721M-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS |
| 文件： | 总24页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO721M-EP
www.ti.com ....................................................................................................................................................................................................... SLLS882–JUNE 2008
3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS
1
FEATURES
•
Signaling Rate 0 Mbps to 150 Mbps
23
•
Controlled Baseline
–
–
Low Propagation Delay
–
–
–
One Assembly Site
One Test Site
Low Pulse Skew (Pulse-Width Distortion)
•
•
•
•
•
Low-Power Sleep Mode
High Electromagnetic Immunity
Low Input Current Requirement
Failsafe Output
One Fabrication Site
•
•
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Drop-In Replacement for Most Opto and
Magnetic Isolators
•
•
•
Enhanced Product-Change Notification
APPLICATIONS
(1)
•
Industrial Fieldbus
Qualification Pedigree
–
–
–
–
Modbus
Profibus
4000-V(peak) Isolation
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1
DeviceNet™ Data Buses
Smart Distributed Systems (SDS™)
–
50-kV/µs Transient Immunity Typical
•
•
•
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDER INFORMATION
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated
by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits
from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed
to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ISO721M-EP
SLLS882–JUNE 2008....................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
Isolation Barrier
DC Channel
+
_
Filter
Pulse Width
Demodulation
OSC
+
PWM
V
ref
_
+
Carrier Detect
POR
POR
BIAS
ISO722
Only
+
_
Data MUX
AC Detect
3-State
EN
Input
+
Filter
IN
V
ref
_
+
OUT
Output Buffer
AC Channel
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching,
and allows fast transient voltage changes between the input and output grounds without corrupting the output.
The small capacitance and resulting time constant provide for fast operation with signaling rates(2) from 0 Mbps
(dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
The ISO721 has TTL input thresholds and a noise-filter at the input that prevents transient pulses of up to 2 ns in
duration from being passed to the output of the device.
The ISO721M has CMOS VCC/2 input thresholds, but do not have the noise filter and the additional propagation
delay. These features of the ISO721M also provide for reduced jitter operation.
The ISO721M is characterized for operation over the ambient temperature range of –55°C to 125°C.
(2) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
2
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Product Folder Link(s): ISO721M-EP
ISO721M-EP
www.ti.com ....................................................................................................................................................................................................... SLLS882–JUNE 2008
D PACKAGE
ISO721, ISO721M
(TOP VIEW)
D PACKAGE
ISO722, ISO722M
(TOP VIEW)
V
V
V
CC2
V
V
V
CC2
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC1
IN
CC1
IN
GND2
OUT
EN
CC1
OUT
GND2
CC1
GND1
GND2
GND1
AVAILABLE OPTIONS(1)
OUTPUT
ENABLED
INPUT
THRESHOLDS
NOISE
TOP-SIDE
MARKING
PRODUCT(2)
PACKAGE
FILTER
ORDERING NUMBER
GREEN
ISO721(3)
ISO721M
ISO722(3)
ISO722M(3)
NO
NO
TTL
YES
NO
SOIC-8
SOIC-8
SOIC-8
SOIC-8
-
-
CMOS
TTL
721MEP
ISO721MMDREP (reel)
Pb Free
Sb/Br Free
YES
YES
YES
NO
-
-
-
-
CMOS
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Product Preview
REGULATORY INFORMATION
VDE
CSA
UL
Approved under CSA Component
Acceptance Notice: CA-5A
Recognized under 1577
Certified according to IEC 60747-5-2
File Number: 40014131
Component Recognition Program(1)
File Number: 1698195
File Number: E181974
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
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ABSOLUTE MAXIMUM RATINGS(1)
UNIT
VCC
VI
Supply voltage(2), VCC1, VCC2
Voltage at IN, OUT, or EN terminal
Output Current
–0.5 V to 6 V
–0.5 V to 6 V
±15 mA
IO
Human-Body Model
Charged-Device Model
JEDEC Standard 22, Test Method A114-C.01
JEDEC Standard 22, Test Method C101
±2 kV
Electrostatic
discharge
ESD
TJ
All pins
±1 kV
Maximum junction temperature
170°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms
values are not listed in this publication.
RECOMMENDED OPERATING CONDITIONS
MIN TYP
MAX
5.5
3.6
4
UNIT
V
4.5
3
VCC
Supply voltage, VCC1, VCC2
IOH
IOL
High-level output current
Low-level output current
mA
-4
10
6.67
2
ISO72x
tui
Input pulse width
ns
V
ISO72xM
VIH
VIL
VIH
VIL
TJ
High-level input voltage (IN, EN)
Low-level input voltage (IN, EN)
High-level input voltage (IN, EN)
Low-level input voltage (IN, EN)
Junction temperature
VCC
0.8
ISO72x
0
0.7 VCC
VCC
IOS72xM
V
0
0.3 VCC
150
See the Thermal Characteristics table
°C
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9
certification
H
1000
A/m
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATIONS
UNIT
VIORM
Maximum working insulation voltage
560
V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
896
V
V
V
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
VPR
Input to output test voltage
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
VIOTM
RS
Transient overvoltage
Insulation resistance
Pollution degree
t = 60 s
4000
>109
2
V
VIO = 500 V at TS
Ω
(1) Climatic Classification 40/125/21
4
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Quiescent
0.5
2
1
ICC1
ICC2
VOH
VOL
VCC1 supply current
VI = VCC or 0 V, No load
mA
4
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, No load
VI = VCC or 0 V, No load
IOH = -4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
8
12
VCC2 supply current
mA
14
10
VCC – 0.8
4.6
5
High-level output voltage
Low-level output voltage
V
VCC – 0.1
0.2
0
0.4
V
0.1
VI(HYS) Input voltage hysteresis
150
mV
IIH
IIL
High-level input current
Low-level input current
IN at 2 V
10
µA
IN at 0.8 V
–10
25
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
1
µA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
50
kV/µs
SWITCHING CHARACTERISTICS: VCC1 and VCC2 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
17
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
ISO72x
17
ns
Pulse skew |tPHL – tPLH
|
0.5
10
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
2
2
16
16
1
ISO721M
10
Pulse skew |tPHL – tPLH
|
0.5
(1)
Part-to-part skew
3
ns
ns
Output signal rise time
Output signal fall time
1
1
EN at 0 V,
See Figure 1
tf
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
8
4
8
5
ns
µs
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
µs
µs
Failsafe output delay time from input power loss
3
2
100 Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100 Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150 Mbps NRZ data input, See Figure 6
150 Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Quiescent
0.5
2
1
ICC1
ICC2
VOH
VOL
VCC1 supply current
VI = VCC or 0 V, No load
mA
4
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, No load
VI = VCC or 0 V, No load
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
4
6.5
mA
7.5
VCC2 supply current
5
VCC – 0.4
3
3.3
0.2
0
High-level output voltage
Low-level output voltage
V
VCC – 0.1
0.4
V
0.1
VI(HYS) Input voltage hysteresis
150
mV
IIH
IIL
High-level input current
Low-level input current
IN at 2 V
10
µA
IN at 0.8 V
–10
25
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
1
µA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
40
kV/µs
SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
19
19
ISO72x
ns
Pulse skew |tPHL – tPLH
|
0.5
12
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
3
3
20
20
1
ISO721M
12
Pulse skew |tPHL – tPLH
|
0.5
(1)
Part-to-part skew
5
ns
ns
Output signal rise time
Output signal fall time
2
2
EN at 0 V,
See Figure 1
tf
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
11
6
ns
µs
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
13
6
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
µs
µs
Failsafe output delay time from input power loss
3
2
100 Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100 Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150 Mbps NRZ data input, See Figure 6
150 Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Quiescent
0.3
1
0.5
mA
2
ICC1
ICC2
VOH
VOL
VCC1 supply current
VI = VCC or 0 V, No load
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, No load
VI = VCC or 0 V, No load
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
8
12
VCC2 supply current
mA
14
10
VCC – 0.8
VCC – 0.1
4.6
5
High-level output voltage
Low-level output voltage
V
0.2
0
0.4
V
0.1
VI(HYS) Input voltage hysteresis
150
mV
IIH
IIL
High-level input current
Low-level input current
IN at 2 V
10
µA
IN at 0.8 V
–10
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
1
µA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
25
40
kV/µs
SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
17
17
0.5
12
12
0.5
0
ISO72x
ns
Pulse skew |tPHL – tPLH
|
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
3
3
21
21
1
ISO721M
Pulse skew |tPHL – tPLH
|
(1)
Part-to-part skew
5
ns
ns
Output signal rise time
Output signal fall time
1
EN at 0 V,
See Figure 1
tf
1
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
9
5
9
5
ns
µs
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
µs
µs
Failsafe output delay time from input power loss
3
2
100 Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100 Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150 Mbps NRZ data input, See Figure 6
150 Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.3
1
MAX
0.5
2
UNIT
Quiescent
ICC1
ICC2
VOH
VOL
VCC1 supply current
VI = VCC or 0 V, No load
mA
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, No load
VI = VCC or 0 V, No load
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
4
6.5
7.5
VCC2 supply current
mA
V
5
VCC – 0.4
VCC – 0.1
3
High-level output voltage
Low-level output voltage
3.3
0.2
0
0.4
0.1
V
VI(HYS) Input voltage hysteresis
150
mV
µA
IIH
IIL
High-level input current
Low-level input current
IN at 2 V
10
IN at 0.8 V
–10
25
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
1
µA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
40
kV/µs
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
20
20
ISO72x
ns
Pulse skew |tPHL – tPLH
|
0.5
12
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
3
3
25
25
1
ISO721M
12
Pulse skew |tPHL – tPLH
|
0.5
(1)
Part-to-part skew
5
ns
ns
Output signal rise time
Output signal fall time
2
2
EN at 0 V,
See Figure 1
tf
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
13
6
ns
µs
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
13
6
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
µs
µs
Failsafe output delay time from input power loss
3
2
100 Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100 Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150 Mbps NRZ data input, See Figure 6
150 Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
8
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PARAMETER MEASUREMENT INFORMATION
V
CC1
V
/2
V
/2
CC1
I
OUT
V
CC1
O
I
IN
0 V
t
t
+
Input
PHL
V
PLH
+
C
Generator
OH
OL
V
L
V
ISO722
and
ISO722M
90%
10%
O
I
50 W
50%
50%
Note B
V
-
EN
-
O
NOTE A
V
t
t
f
r
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
V
O
V
CC2
IN
V
OUT
C
I
V
/2
3 V
V
/2
CC2
CC2
0 V
V
EN
t
R
= 1 kW ±1 %
PZH
L
L
OH
NOTE B
+
50%
Input
Generator
NOTE A
0.5 V
V
O
V
I
50 W
0 V
t
PHZ
-
Figure 2. ISO722 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
V
CC2
R
= 1 kW ±1%
L
V
CC2
V
I
V
/2
CC2
V
/2
CC2
IN
OUT
V
0 V
0 V
O
t
t
PZL
PLZ
V
CC2
0.5 V
EN
V
C
L
O
50%
NOTE B
+
V
Input
Generator
NOTE A
OL
50 W
V
I
-
A. The input pulse is supplied by a generator having the following characteristics:
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. ISO722 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
CC1
V
CC1
V
2.7 V
I
IN
0 V
V
OUT
V
0 V
t
fs
O
OH
50%
V
O
C
EN
ISO722
and
L
V
OL
15 pF
±20%
ISO722M
NOTE: VI transition time is 100 ns
Figure 4. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
V
CC2
CC1
OUT
C
IN
V
L
CC
V
15 pF
±20%
O
or
0 V
C = 0.1 mF,
I
GND1
GND2
±1%
V
CM
NOTE: Pass/Fail criteria is no change in VO.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
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PARAMETER MEASUREMENT INFORMATION (continued)
Tektronix
Tektronix
HFS9009
784D
PATTERN
GENERATOR
V
CC1
In p u t
0 V
O u tp u t
V
CC2/2
J itte r
NOTE: Bit pattern run length is 216 – 1. Transition Time is 800 ps. NRZ data input has no more than five consecutive
ones or zeros.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
4.8
TYP
MAX UNIT
(1)
L(101) Minimum air gap (Clearance)
Shortest terminal to terminal distance through air
mm
Shortest terminal to terminal distance across the
package surface
L(102) Minimum external tracking (Creepage)
4.3
mm
Tracking resistance (comparative tracking
index)
CTI
DIN IEC 60112/VDE 0303 Part 1
Distance through insulation
≥ 175
V
Minimum internal gap (internal clearance)
0.008
mm
Input to output, VIO = 500 V, all pins on each side
of the barrier tied together creating a two-terminal
device, TA < 100 °C
>1012
>1011
Ω
Ω
RIO
Isolation resistance
Input to output, VIO = 500 V,
100°C ≤ TA< TA max.
Barrier capacitance
Input-to-output
CIO
CI
VI = 0.4 sin (4E6πt)
VI = 0.4 sin (4E6πt)
1
1
pF
pF
Input capacitance to ground
(1) Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Care should
be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
Basic isolation group
TEST CONDITIONS
SPECIFICATION
Material group
IIIa
I-IV
I-III
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Installation classification
DEVICE I/O SCHEMATIC
Equivalent Input and Output Schematic Diagrams
Enable
Input
Output
V
CC2
V
V
V
CC1
CC2
V
CC1
V
CC1
CC2
8 W
1 MW
OUT
500 W
500 W
EN
IN
13 W
1 MW
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IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply, and without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
100
153
150
UNIT
θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
IS
Safety input, output, or supply current
Maximum case temperature
mA
TS
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal
Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board
for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K Thermal Resistance(1)
High-K Thermal Resistance(1)
MIN
TYP
263
125
MAX
UNIT
°C/W
°C/W
θJA
Junction-to-Air
Junction-to-Board Thermal
Resistance
θJB
θJC
44
75
°C/W
°C/W
Junction-to-Case Thermal
Resistance
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, Input a 100 Mbps 50% duty
cycle square wave
ISO72x
159
195
PD
Device Power Dissipation
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
ISO72xM CL = 15 pF, Input a 150 Mbps 50% duty
cycle square wave
(1) Tested in accordance with the Low-K or High-K thermal metric definition of EIA/JESD51-3 for leaded surface mount packages.
200
175
V
, V
= 3.6 V
CC1 CC2
150
125
100
75
50
25
0
V
, V
= 5.5 V
CC1 CC2
0
50
100
Case Temperature
150
200
−
oC
Figure 7. θJC THERMAL DERATING CURVE per IEC 60747-5-2
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FUNCTION TABLE
ISO721(1)
VCC1
VCC2
INPUT
(IN)
OUTPUT
(OUT)
H
L
H
L
PU
PD
PU
PU
Open
X
H
H
(1) PU = powered up (VCC ≥ 3 V); PD = powered down (VCC ≤ 2.5 V), X = irrelevant, H = high Level; L =
low level
ISO722(1)
VCC1
VCC2
INPUT
(IN)
ISO722/ISO722M
OUTPUT ENABLE (EN)
OUTPUT
(OUT)
H
L
L or Open
L or Open
H
H
L
PU
PU
X
Z
H
H
Z
Open
X
L or Open
L or Open
H
PD
PD
PU
PU
X
(1) PU = powered up (VCC ≥ 3 V); PD = powered down (VCC ≤ 2.5 V), X = irrelevant, H = high Level; L = low level
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TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT vs SIGNALING RATE
RMS SUPPLY CURRENT vs SIGNALING RATE
10
9
15
14
13
12
V
V
T
= 3.3 V,
= 3.3 V,
= 25oC,
V
V
T
= 5 V,
= 5 V,
= 25oC,
CC1
CC2
CC1
CC2
8
7
6
5
A
A
I
CC2
C
= 15 pF
C
= 15 pF
L
L
11
10
9
8
7
6
I
CC2
I
4
3
2
CC1
5
4
3
2
1
0
I
CC1
1
0
0
25
50
75
100
0
25
50
75
100
Signaling Rate (Mbps)
Signaling Rate (Mbps)
Figure 8.
Figure 9.
PROPAGATION DELAY vs FREE-AIR TEMPERATURE
30
PROPAGATION DELAY vs FREE-AIR TEMPERATURE
20
t
PLH
18
16
t
PLH
25
ISO72x
t
PHL
t
ISO72x
PHL
14
12
10
20
15
t
PLH
t
PLH
t
PHL
t
PHL
ISO72xM
ISO72xM
8
6
4
10
V
V
C
= 3.3 V,
= 3.3 V,
CC1
V
= 5 V,
= 5 V,
CC1
CC2
CC2
V
C
5
0
= 15 pF,
L
= 15 pF,
L
Air Flow at 7 cf/m
2
0
Air Flow at 7 cf/m
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
T
− Free-Air Temperature − o
C
T
− Free-Air Temperature − o
C
A
A
Figure 10.
Figure 11.
ISO72x INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
ISO72xM INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
1.4
1.35
1.3
2.5
5-V (V
)
IT+
2.4
2.3
5-V (V
)
IT+
2.2
2.1
5-V (V
)
3.3-V (V
)
IT-
IT+
1.25
1.2
2
Air Flow at 7 cf/m
1.9
Air Flow at 7 cf/m
1.15
1.1
1.05
1
1.8
1.7
1.6
5-V (V
)
IT-
3.3-V (V
)
IT+
3.3-V (V
)
IT-
3.3-V (V
)
1.5
1.4
IT-
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
T
− Free-Air Temperature − o
C
T
− Free-Air Temperature − o
C
A
A
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
VCC1 FAILSAFE THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT
VOLTAGE
-80
2.92
2.9
T
= 25oC
-70
-60
-50
-40
-30
-20
A
V
= 5 V
CC
2.88
2.86
V
fs+
V
= 5 V or 3.3 V,
= 15 pF,
CC
C
L
Air Flow at 7 cf/m
V
= 3.3 V
2.84
2.82
CC
V
fs-
2.8
-10
0
2.78
0
1
2
3
4
5
6
-40 -25 -10
5
20
35
50
65
80
95
110 125
− Free-Air Temperature − o
C
V
− High-Level Output Voltage − V
T
OH
A
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT CURRENT vs
LOW-LEVEL OUTPUT VOLTAGE
70
60
T
= 25oC
A
V
= 5 V
CC
50
40
30
20
V
= 3.3 V
CC
10
0
0
1
2
3
4
5
V
− Low-Level Output Voltage − V
OL
Figure 16.
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APPLICATION INFORMATION
MANUFACTURER CROSS-REFERENCE DATA
The ISO72xx isolators have the same functional pinout as most other vendors, and they are often pin-for-pin
drop-in replacements. The notable differences in the products are propagation delay, signaling rate, power
consumption, and transient protection rating. Table 1 is used as a guide for replacing other isolators with the
ISO72x family of single channel isolators.
ISO722
or
ISO721
or
HCPL-xxxx
IL710
ISO722M
ISO721M
ADuM1100
V
V
V
V
V
V
V
DD2
1
2
3
4
1
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
DD1
V
V
V
V
V
V
CC2
DD1
DD2
DD2
DD1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC1
CC2
CC1
IN
V
I
V
V
2
3
4
NC
GND2
V
I
V
I
OE
EN
GND2
OUT
IN
V
O
V
O
NC
DD1
O
OUT
GND2
CC1
CC1
*
GND1
GND2
GND1
GND1
GND2
GND2
GND1
GND1
GND2
Figure 17. Pin Cross Reference
Table 1. CROSS REFERENCE
PIN 7
ISO721
OR
ISO722
OR
ISOLATOR
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 8
ISO721M
ISO722M
ISO721(1)(2)
ADuM1100(1)(2)
VCC1
VDD1
IN
VI
VCC1
VDD1
GND1
GND1
GND2
GND2
OUT
VO
GND2
EN
VCC2
VDD2
GND2
*Leave
HCPL-xxxx
IL710
VDD1
VDD1
VI
VI
GND1
GND1
GND2
GND2
VO
VO
NC(4)
VOE
VDD2
VDD2
Open(3)
NC(5)
(1) The ISO72xx pin 1 and pin 3 are internally connected together. Either or both may be used as VCC1
.
(2) The ISO721 and ISO721M pin 5 and pin 7 are internally connected together. Either or both may be used as GND2.
(3) Pin 3 of the HCPL devices must be left open. This is not a problem when substituting an ISO72xx device since the extra VCC1 on pin 3
may be left an open circuit as well.
(4) An HCPL device PIN 7 must be left floating (open) or grounded when an ISO722 or ISO722M device is to be used as a drop-in
replacement. If pin 7 of the ISO722 or ISO722M device is placed in a high logic state, the output of the device is disabled
(5) Pin 3 of the IL710 must not be tied to ground on the circuit board since this shorts the ISO72xx's VCC1 to ground. The IL710 pin 3 may
only be tied to VCC or left open to drop in an ISO72xx.
VCC1
VCC2
ISO721
or ISO721M
20 mm
max.
from
20 mm
max.
from
m
0.1 F
m
0.1 F
1
8
Vcc1
Vcc2
2
7
6
5
IN
INPUT
GND1
3
4
OUTPUT
GND2
OUT
Figure 18. Basic Application Circuit
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ISOLATION GLOSSARY
Creepage Distance — The shortest path between two conductive input-to-output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance — The shortest distance between two conductive input-to-output leads measured through air (line of
sight).
Input-to-Output Barrier Capacitance -- The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to-Output Barrier Resistance -- The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit -- An internal circuit directly connected to an external supply mains or other equivalent source
that supplies the primary circuit electric power.
Secondary Circuit -- A circuit with no direct connection to primary power, and derives its power from a separate
isolated source.
Comparative Tracking Index (CTI) -- CTI is an index used for electrical insulating materials. It is defined as the
numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that
produces a partially conducting path of localized deterioration on or through the surface of an insulating material
as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the
insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
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Insulation:
Operational insulation -- Insulation needed for the correct operation of the equipment.
Basic insulation -- Insulation to provide basic protection against electric shock.
Supplementary insulation -- Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation -- Insulation comprising both basic and supplementary insulation.
Reinforced insulation -- A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 -- No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 -- Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 -- Conductive pollution occurs or dry nonconductive pollution occurs, which becomes
conductive due to condensation that is to be expected.
Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category -- This section is directed at insulation co-ordination by identifying the transient
overvoltages that may occur, and by assigning four different levels as indicated in IEC 60664.
1. Signal Level -- Special equipment or parts of equipment.
2. Local Level -- Portable equipment etc.
3. Distribution Level -- Fixed installation
4. Primary Supply Level -- Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
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PACKAGE OPTION ADDENDUM
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23-Jun-2008
PACKAGING INFORMATION
Orderable Device
ISO721MMDREP
V62/08627-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ISO721MMDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
533.4 346.0 36.0
ISO721MMDREP
D
8
2500
Pack Materials-Page 2
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
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Medical
Amplifiers
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amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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