ISO7221C-Q1 [TI]
DUAL DIGITAL ISOLATORS; 双通道数字隔离器
| 型号： | ISO7221C-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL DIGITAL ISOLATORS |
| 文件： | 总24页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
www.ti.com
SLLS965C –JULY 2009–REVISED MAY 2012
DUAL DIGITAL ISOLATORS
Check for Samples: ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1
1
FEATURES
•
Qualified for Automotive Applications
•
4000-Vpeak Isolation, 560 Vpeak VIORM
•
1-Mbps and 25-Mbps Signaling Rate Options
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IEC 61010-1, IEC 60950-1 and CSA
Approved
–
–
–
Low Channel-to-Channel Output Skew:
1 ns (Max)
–
50 kV/μs Typical Transient Immunity
Low Pulse-Width Distortion (PWD):
1 ns (Max)
•
•
•
•
Operates with 3.3-V or 5-V Supplies
4 kV ESD Protection
Low Jitter Content: 1 ns (Typ) at 150 Mbps
•
25-Year (Typ) Life at Rated Voltage
(See Application Report SLLA197 and
Figure 14)
High Electromagnetic Immunity
–40°C to 125°C Operating Free-Air
Temperature Range
DESCRIPTION
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented
in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input
and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to
4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and
prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or
damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be
unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The small capacitance and resulting time constant provide fast operation with signaling rates available from 0
Mbps (dc) to 25 Mbps.(1)The A-option and C-option devices have TTL input thresholds and a noise filter at the
input that prevents transient pulses from being passed to the output of the device.
These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
SLLS965C –JULY 2009–REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SIGNALING
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
RATE
1 Mbps
1 Mbps
25 Mbps
SOIC – D
SOIC – D
SOIC – D
Reel of 2500
ISO7220AQDRQ1
ISO7221AQDRQ1
ISO7221CQDRQ1
7220AQ
7221AQ
7221CQ
–40°C to 125°C
Reel of 2500
Reel of 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ISO7221
ISO7220
1
2
3
4
8
7
6
5
VCC1
OUTA
INB
VCC2
1
2
3
4
8
7
6
5
VCC1
INA
INB
VCC2
INA
OUTA
OUTB
GND2
OUTB
GND2
GND1
GND1
SINGLE-CHANNEL FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
Data MUX
AC Detect
Input
+
Filter
Vref
IN
OUT
Output Buffer
AC Channel
REGULATORY INFORMATION
VDE
CSA
UL
Approved under CSA Component
Acceptance Notice
Recognized under 1577 Component
Recognition Program(1)
Certified according to IEC 60747-5-2
File Number: 40016131
File Number: 1698195
File Number: E181974
(1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.
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Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1
ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
www.ti.com
SLLS965C –JULY 2009–REVISED MAY 2012
ABSOLUTE MAXIMUM RATINGS(1)
VCC
Supply voltage(2), VCC1, VCC2
Voltage at IN, OUT
Output current
–0.5 V to 6 V
–0.5 V to 6 V
±15 mA
VI
IO
Human-Body Model
±4 kV
Electrostatic
discharge
ESD
Field-Induced Charged-Device Model
Machine Model
All pins
±1 kV
±200 V
TJ
Maximum junction temperature
Storage temperature
150°C
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX UNIT
VCC
IOH
IOL
Supply voltage(1)
VCC1, VCC2
3
5.5
4
V
High-level output current
Low-level output current
mA
mA
μs
–4
1
ISO722xA
ISO722xC
ISO722xA
ISO722xC
0.67
33
tui
Input pulse width
Signaling rate
40
0
ns
1500
30
1000 kbps
25 Mbps
1/tui
0
VIH
VIL
TJ
High-level input voltage
2
VCC
0.8
V
V
Low-level input voltage
0
Operating virtual-junction temperature
–40
150
°C
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification
1000 A/m
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright © 2009–2012, Texas Instruments Incorporated
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ISO7221A-Q1
ISO7221C-Q1
SLLS965C –JULY 2009–REVISED MAY 2012
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ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5 V(1), over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX UNIT
ISO7220x
ISO7221x
ISO7220A
ISO7221A
2
Quiescent
1 Mbps
8.5
2
17
ICC1
Supply current, VCC1
VI = VCC or 0 V, no load
3
18
22
31
17
32
18
22
mA
mA
10
12
16
8.5
17
10
12
4.6
5
ISO7221C 25 Mbps
ISO7220x
Quiescent
ISO7221x
ICC2
Supply current, VCC2
ISO7220A
1 Mbps
VI = VCC or 0 V, no load
ISO7221A
ISO7221C 25 Mbps
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
VCC – 0.8
VCC – 0.1
VOH
High-level output voltage
Low-level output voltage
V
V
0.2
0
0.4
0.1
VOL
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
IIL
CI
High-level input current
Low-level input current
Input capacitance to ground
IN from 0 V to VCC
10
IN from 0 V to VCC
–10
25
μA
IN at VCC, VI = 0.4 sin (4E6πt)
VI = VCC or 0 V, See Figure 3
1
pF
CMTI Common-mode transient immunity
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS
VCC1 = VCC2 = 5 V, over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay
TEST CONDITIONS
MIN
TYP
405
1
MAX UNIT
tpLH, tpHL
PWD
280
480
14
42
2
ns
ns
ns
ns
ISO722xA See Figure 1
(1)
(1)
Pulse-width distortion |tpHL – tpLH
|
|
tpLH, tpHL
PWD
Propagation delay
22
32
1
ISO722xC See Figure 1
Pulse-width distortion |tpHL – tpLH
ISO722xA
ISO722xC
ISO722xA
ISO722xC
See Figure 1
See Figure 1
180
10
15
1
(2)
tsk(pp)
Part-to-part skew
ns
ns
3
0.2
1
(3)
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
Output signal fall time
ns
ns
μs
tf
1
tfs
Failsafe output delay time from input power loss
See Figure 2
3
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
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SLLS965C –JULY 2009–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS
VCC1 = 5 V, VCC2 = 3.3 V(1), over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX UNIT
ISO7220x
ISO7221x
ISO7220A
ISO7221A
2
Quiescent VI = VCC or 0 V, no load
8.5
2
17
ICC1
Supply current, VCC1
3
18
22
18
9.5
19
11
12
mA
mA
1 Mbps
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
10
12
8
ISO7221C 25 Mbps
ISO7220x
Quiescent VI = VCC or 0 V, no load
ISO7221x
ISO7220A
ISO7221A
4.3
9
ICC2
Supply current, VCC2
1 Mbps
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
5
ISO7221C 25 Mbps
ISO7220x
6
VCC – 0.4
VCC – 0.8
VCC – 0.1
IOH = –4 mA, See Figure 1
ISO7221x
(5-V side)
VOH
High-level output voltage
Low-level output voltage
V
V
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0.4
0.1
VOL
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
IIL
CI
High-level input current
Low-level input current
Input capacitance to ground
IN from 0 V to VCC
10
IN from 0 V to VCC
–10
15
μA
IN at VCC, VI = 0.4 sin (4E6πt)
VI = VCC or 0 V, See Figure 3
1
pF
CMTI Common-mode transient immunity
40
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS
VCC1 = 5 V, VCC2 = 3.3 V, over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay
TEST CONDITIONS
MIN
TYP
410
1
MAX UNIT
tpLH, tpHL
PWD
285
480
14
48
2
ns
ns
ns
ns
ISO722xA See Figure 1
(1)
(1)
Pulse-width distortion |tpHL – tpLH
|
|
tpLH, tpHL
PWD
Propagation delay
25
36
1
ISO722xC See Figure 1
Pulse-width distortion |tpHL – tpLH
ISO722xA
ISO722xC
ISO722xA
ISO722xC
See Figure 1
See Figure 1
180
10
15
1
(2)
tsk(pp)
Part-to-part skew
ns
ns
3
0.2
2
(3)
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
Output signal fall time
ns
tf
2
tfs
Failsafe output delay time from input power loss
See Figure 2
3
μs
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2009–2012, Texas Instruments Incorporated
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ISO7221C-Q1
SLLS965C –JULY 2009–REVISED MAY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
VCC1 = 3.3 V, VCC2 = 5 V(1), over recommended operating conditions (unless otherwise noted)
PARAMETER
ISO7220x
TEST CONDITIONS
MIN
TYP
0.6
4.3
1
MAX UNIT
1
Quiescent
1 Mbps
ISO7221x
ISO7220A
ISO7221A
9.5
ICC1
Supply current, VCC1
VI = VCC or 0 V, no load
2
11
12
31
17
32
18
22
mA
mA
5
ISO7221C 25 Mbps
6
ISO7220x
Quiescent
ISO7221x
16
8.5
18
10
12
ICC2
Supply current, VCC2
ISO7220A
1 Mbps
VI = VCC or 0 V, no load
ISO7221A
ISO7221C 25 Mbps
ISO7220x
VCC – 0.8
VCC – 0.4
VCC – 0.1
IOH = –4 mA, See Figure 1
ISO7221x
(3.3-V side)
VOH
High-level output voltage
Low-level output voltage
V
V
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0.4
0.1
VOL
0
VI(HYS) Input threshold voltage hysteresis
150
mV
μA
IIH
IIL
CI
High-level input current
Low-level input current
Input capacitance to ground
IN from 0 V or VCC
10
IN from 0 V or VCC
–10
15
μA
IN at VCC, VI = 0.4 sin (4E6πt)
VI = VCC or 0 V, See Figure 3
1
pF
CMTI Common-mode transient immunity
40
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS
VCC1 = 3.3 V, VCC2 = 5 V, over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay
TEST CONDITIONS
MIN
TYP
395
1
MAX UNIT
tpLH, tpHL
PWD
285
480
18
48
3
ns
ns
ns
ns
ISO722xA See Figure 1
(1)
(1)
Pulse-width distortion |tpHL – tpLH
|
|
tpLH, tpHL
PWD
Propagation delay
24
36
1
ISO722xC See Figure 1
Pulse-width distortion |tpHL – tpLH
ISO722xA
ISO722xC
ISO722xA
ISO722xC
See Figure 1
See Figure 1
190
10
15
1
(2)
tsk(pp)
Part-to-part skew
ns
ns
3
0.2
1
(3)
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
Output signal fall time
ns
ns
μs
tf
1
tfs
Failsafe output delay time from input power loss
See Figure 2
3
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6
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ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
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SLLS965C –JULY 2009–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 3.3 V(1), over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.6
4.3
1
MAX UNIT
ISO7220x
ISO7221x
ISO7220A
ISO7221A
1
Quiescent
1 Mbps
9.5
ICC1
Supply current, VCC1
VI = VCC or 0 V, no load
2
11
12
18
9.5
19
11
12
mA
mA
5
ISO7221C 25 Mbps
6
ISO7220x
Quiescent
ISO7221x
8
4.3
9
ICC2
Supply current, VCC2
ISO7220A
1 Mbps
VI = VCC or 0 V, no load
ISO7221A
5
ISO7221C 25 Mbps
6
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
VCC – 0.4
VCC – 0.1
3
VOH
High-level output voltage
Low-level output voltage
V
V
3.3
0.2
0
0.4
0.1
VOL
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
IIL
CI
High-level input current
Low-level input current
Input capacitance to ground
IN from 0 V or VCC
10
IN from 0 V or VCC
–10
15
μA
IN at VCC, VI = 0.4 sin (4E6πt)
VI = VCC or 0 V, See Figure 3
1
pF
CMTI Common-mode transient immunity
40
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS
VCC1 = VCC2 = 3.3 V, over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay
TEST CONDITIONS
MIN
TYP
400
1
MAX UNIT
tpLH, tpHL
PWD
290
485
18
52
3
ns
ns
ns
ns
ISO722xA See Figure 1
(1)
(1)
Pulse-width distortion |tpHL – tpLH
|
|
tpLH, tpHL
PWD
Propagation delay
25
40
1
ISO722xC See Figure 1
Pulse-width distortion |tpHL – tpLH
ISO722xA
ISO722xC
ISO722xA
ISO722xC
See Figure 1
See Figure 1
190
10
15
1
tsk(pp)
Part-to-part skew(2)
ns
ns
3
0.2
2
(3)
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
Output signal fall time
ns
ns
μs
tf
2
tfs
Failsafe output delay time from input power loss
See Figure 2
3
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2009–2012, Texas Instruments Incorporated
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PARAMETER MEASUREMENT INFORMATION
V
1
CC
V
V
1/2
V
1/2
I
CC
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
V
C
V
V
O
50 W
OH
OL
L
NOTE B
I
90%
10%
V
O
50%
50%
NOTE A
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
V
I
V
1
CC
V
1
CC
V
I
0 V
or
2.7 V
OUT
IN
V
0 V
V
O
V
1
t
CC
fs
OH
C
V
L
FAILSAFE HIGH
50%
O
NOTE A
V
OL
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
1
V
2
CC
CC
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass-fail criteria:
Output must
remain stable
OUT
IN
S1
NOTE A
V
or V
OL
OH
GND1
GND2
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
V
1
CC
DUT
Tektronix
HFS9009
IN
0 V
V
Tektronix
OUT
784D
PATTERN
/2
GENERATOR
CC
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps.
Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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ISO7221A-Q1
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SLLS965C –JULY 2009–REVISED MAY 2012
DEVICE INFORMATION
IEC PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
L(I01) Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4.8
mm
SOIC-8
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
L(I02)
4.3
≥175
0.008
mm
V
Tracking resistance
CTI
DIN IEC 60112 / VDE 0303 Part 1
Distance through the insulation
(comparative tracking index)
Minimum internal gap (internal
clearance)
mm
Input to output, VIO = 500 V, all pins on each side of the barrier
tied together creating a two-terminal device, TA < 100°C
>1012
>1011
1
Ω
Ω
RIO
Isolation resistance
Input to output, VIO = 500 V, 100°C ≤ TA ≤ max
CIO
CI
Barrier capacitance input to
output
VI = 0.4 sin (4E6πt)
pF
pF
Input capacitance to ground
VI = 0.4 sin (4E6πt)
1
NOTE: Creepage and clearance requirements should be applied according to the specific equipment isolation
standards of an application. Care should be taken to maintain the creepage and clearance distance of a board
design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques
shown in the Isolation Glossary . Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
Material group
SPECIFICATION
Basic isolation group
IIIa
I-IV
I-III
I-II
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Rated mains voltage ≤400 VRMS
Installation classification
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
VIORM
VPR
Maximum working insulation voltage
560
V
Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1 s,
Partial discharge <5 pC
Input to output test voltage
1050
V
VIOTM
RS
Transient overvoltage
Insulation resistance
Pollution degree
t = 60 s
4000
>109
2
V
VIO = 500 V at TS
Ω
(1) Climatic Classification 40/125/21
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DEVICE I/O SCHEMATICS
Input
Output
V
CC2
V
V
V
CC1
CC1
CC1
750 kW
8 W
500 W
IN
OUT
13 W
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
124
mA
190
Safety input, output, or
supply current
IS
SOIC-8
SOIC-8
TS
Maximum case temperature
150
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
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ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
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SLLS965C –JULY 2009–REVISED MAY 2012
SOIC-8 PACKAGE THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K thermal resistance(1)
MIN
TYP
212
122
37
MAX UNIT
θJA
Junction-to-air thermal resistance
°C/W
High-K thermal resistance
θJB
θJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
°C/W
°C/W
69.1
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
250
225
V
at 3.6 V
CC1,2
200
175
150
125
100
75
V
at 5.5 V
CC1,2
50
25
0
0
50
100
- Case Temperature - °C
150
200
T
C
Figure 5. SOIC-8 θJC THERMAL DERATING CURVE per IEC 60747-5-2
DEVICE FUNCTION TABLE
Table 1. ISO7220x or ISO7221x(1)
INPUT SIDE VCC
OUTPUT SIDE VCC
INPUT IN
OUTPUT OUT
H
L
H
L
PU
PD
PU
PU
Open
X
H
H
(1) PU = Powered up(Vcc ≥ 3.0 V), PD = Powered down (Vcc ≤ 2.5 V), X = Irrelevant, H = High level,
L = Low level
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SLLS965C –JULY 2009–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTIC CURVES
3.3-V RMS SUPPLY CURRENT
5-V RMS SUPPLY CURRENT
vs
vs
SIGNALING RATE (Mbps)
SIGNALING RATE (Mbps)
20
18
16
14
30
28
26
24
22
T
= 25°C,
T
= 25°C,
A
A
ISO7220x I
CC2
15 pF Load
15 pF Load
ISO7220x I
CC2
20
18
16
ISO7221x I
CC1&2
12
10
14
12
10
ISO7221x I
CC1&2
8
6
ISO7220x I
CC1
8
6
4
4
2
0
ISO7220x I
CC1
2
0
0
25
50
75
100
0
25
50
75
100
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 6.
Figure 7.
ISO722xA AND ISO722xC INPUT VOLTAGE LOW-TO-HIGH
SWITCHING THRESHOLD
VCC FAILSAFE THRESHOLD
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.92
2.9
1.4
15 pF Load
VCC = 3.3 V or 5 V
5-V Vth+
1.35
VFS
1.3
3.3-V Vth+
2.88
2.86
2.84
2.82
2.8
1.25
1.2
1.15
1.1
15 pF Load
5-V Vth-
VFS-
1.05
3.3-V Vth-
1
2.78
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature - °C
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature - °C
Figure 8.
Figure 9.
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ISO7220A-Q1
ISO7221A-Q1
ISO7221C-Q1
www.ti.com
SLLS965C –JULY 2009–REVISED MAY 2012
TYPICAL CHARACTERISTIC CURVES (continued)
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
70
60
50
40
30
20
10
0
-80
15 pF Load
TA = 25°C
15 pF Load
TA = 25°C
-70
-60
-50
-40
-30
-20
-10
0
VCC = 5 V
VCC = 5 V
VCC = 3.3 V
VCC = 3.3 V
0
2
4
6
0
1
2
3
4
5
VOUT - V
Figure 10.
VOUT - V
Figure 11.
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ISO7221A-Q1
ISO7221C-Q1
SLLS965C –JULY 2009–REVISED MAY 2012
www.ti.com
APPLICATION INFORMATION
Typical Applications
VCC 1
VCC2
2 mm
max .
from
2 mm
max .
from
m
0.1 F
m
0.1 F
Vcc 1
Vcc 2
1
2
8
7
6
5
INA
INB
OUTA
OUTB
OUTPUT
OUTPUT
INPUT
INPUT
3
4
ISO7220
GND 1
GND 2
Figure 12. Typical ISO7220 Application Circuit
VCC 1
VCC2
2 mm
max .
from
2 mm
max .
from
m
0.1 F
m
0.1 F
Vcc 1
Vcc 2
1
2
8
7
OUTA
INB
INA
OUTPUT
INPUT
INPUT
OUTB
OUTPUT
3
4
6
5
ISO 7221
GND 1
GND 2
Figure 13. Typical ISO7221 Application Circuit
100
VIORM at 560 V
28
10
0
250
500
750
1000
120
880
WORKING VOLTAGE (VIORM) -- V
Figure 14. Time-Dependent Dielectric Breakdown Test Results
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ISO7221C-Q1
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SLLS965C –JULY 2009–REVISED MAY 2012
ISOLATION GLOSSARY
Creepage Distance — The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance — The shortest distance between two conductive input to output leads measured through air (line of
sight).
Input-to Output Barrier Capacitance — The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to Output Barrier Resistance — The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit — An internal circuit directly connected to an external supply mains or other equivalent source
which supplies the primary circuit electric power.
Secondary Circuit — A circuit with no direct connection to primary power, and derives its power from a separate
isolated source.
Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials which is defined as
the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the
process that produces a partially conducting path of localized deterioration on or through the surface of an
insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher
CTI value of the insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
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Insulation:
Operational insulation — Insulation needed for the correct operation of the equipment.
Basic insulation — Insulation to provide basic protection against electric shock.
Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation — Insulation comprising both basic and supplementary insulation.
Reinforced insulation — A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 — No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 — Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 — Conductive pollution occurs or dry nonconductive pollution occurs which becomes
conductive due to condensation which is to be expected.
Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category — This section is directed at insulation co-ordination by identifying the transient
overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664.
I: Signal Level — Special equipment or parts of equipment.
II: Local Level — Portable equipment etc.
III: Distribution Level — Fixed installation
IV: Primary Supply Level — Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
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ISO7221C-Q1
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SLLS965C –JULY 2009–REVISED MAY 2012
REVISION HISTORY
Changes from Revision B (March 2010) to Revision C
Page
•
Added storage temperature to Abs Max table. ..................................................................................................................... 3
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PACKAGE OPTION ADDENDUM
www.ti.com
22-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ISO7220AQDRQ1
ISO7221AQDRQ1
ISO7221CQDRQ1
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1 :
Catalog: ISO7220A, ISO7221A, ISO7221C
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-May-2012
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7220AQDRQ1
ISO7221AQDRQ1
ISO7221CQDRQ1
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
6.4
5.2
5.2
5.2
2.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7220AQDRQ1
ISO7221AQDRQ1
ISO7221CQDRQ1
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
Pack Materials-Page 2
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