ISO7240ADW [TI]
QUAD DIGITAL ISOLATORS; 4通道数字隔离器
| 型号： | ISO7240ADW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD DIGITAL ISOLATORS |
| 文件： | 总23页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868–SEPTEMBER 2007
QUAD DIGITAL ISOLATORS
1
FEATURES
•
1, 25, and 150-Mbps Signaling Rate Options
•
•
High Electromagnetic Immunity (see
application report SLLA181)
–40°C to 125°C Operating Range
–
–
–
Low Channel-to-Channel Output Skew;
1 ns Max
Low Pulse-Width Distortion (PWD);
2 ns Max
APPLICATIONS
•
•
•
•
Industrial Fieldbus
Low Jitter Content; 1 ns Typ at 150 Mbps
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
•
Typical 25-Year Life at Rated Working Voltage
(see application note SLLA197 and Figure 14)
•
•
•
•
4000-Vpeak Isolation, 560-Vpeak Working Voltage
UL 1577 Certified
4 kV ESD Protection
Operate With 3.3-V or 5-V Supplies
DESCRIPTION
The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations with
output enable function. These devices have logic input and output buffers separated by TI’s silicon dioxide (SiO2)
isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage, isolate
grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive
circuitry.
The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same
direction and one channel in opposition. The ISO7242 has two channels in each direction.
The A and C option devices have TTL input thresholds and a noise-filter at the input that prevents transient
pulses from being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds
and do not have the input noise-filter or the additional propagation delay.
A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh
pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit
drives the output to a logic high state. (Contact TI for a logic low failsafe option).
These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V,
5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage
supply level being used.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
ISO7240
ISO7241
ISO7242
V
V
V
V
V
V
CC2
1
2
3
4
5
6
7
8
16
15
1
2
3
4
5
6
7
8
16
15
1
2
3
4
5
6
7
8
16
15
CC1
CC2
CC1
CC2
CC1
GND1
GND2
GND1
GND2
GND1
GND2
IN
A
IN
B
IN
C
14
13
12
11
10
9
OUT
A
IN
IN
IN
14
13
12
11
10
9
OUT
A
IN
IN
14
13
12
11
10
9
OUT
A
A
B
C
A
OUT
B
OUT
B
OUT
B
B
OUT
C
OUT
C
OUT
OUT
IN
C
C
OUT
D
OUT
IN
D
IN
D
IN
D
D
D
EN
EN
1
EN
NC
EN
2
EN
2
1
GND1
GND2
GND1
GND2
GND1
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868–SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
Data MUX
AC Detect
Input
+
Filter
Vref
IN
OUT
Output Buffer
AC Channel
(1)
Table 1. Device Function Table ISO724x
INPUT
(IN)
OUTPUT ENABLE
OUTPUT
(OUT)
VCC1
VCC2
(EN)
H or Open
H or Open
L
H
L
H
L
PU
PU
X
Z
H
H
Z
Open
X
H or Open
H or Open
L
PD
PD
PU
PU
X
(1) PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
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Product Folder Link(s): ISO7240 ISO7241 ISO7242
ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868–SEPTEMBER 2007
AVAILABLE OPTIONS
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
MARKED
AS
ORDERING
NUMBER
ISO7240ADW (rail)
ISO7240ADWR (reel)
ISO7240CDW (rail)
ISO7240CDWR (reel)
ISO7240MDW (rail)
ISO7240MDWR (reel)
ISO7241ADW (rail)
ISO7241ADWR (reel)
ISO7241CDW (rail)
ISO7241CDWR (reel)
ISO7241MDW (rail)
ISO7241MDWR (reel)
ISO7242ADW (rail)
ISO7242ADWR (reel)
ISO7242CDW (rail)
ISO7242CDWR (reel)
ISO7242MDW (rail)
ISO7242MDWR (reel)
~1.5 V (TTL)
(CMOS compatible)
ISO7240ADW
ISO7240CDW
1 Mbps
25 Mbps
150 Mbps
1 Mbps
ISO7240A
ISO7240C
ISO7240M
ISO7241A
ISO7241C
ISO7241M
ISO7242A
ISO7242C
ISO7242M
~1.5 V (TTL)
(CMOS compatible)
4/0
ISO7240MDW
ISO7241ADW(1)
ISO7241CDW(1)
ISO7241MDW(1)
ISO7242ADW(1)
ISO7242CDW(1)
Vcc/2 (CMOS)
~1.5 V (TTL)
(CMOS compatible)
~1.5 V (TTL)
(CMOS compatible)
25 Mbps
150 Mbps
1 Mbps
3/1
2/2
Vcc/2 (CMOS)
~1.5 V (TTL)
(CMOS compatible)
~1.5 V (TTL)
(CMOS compatible)
25 Mbps
150 Mbps
ISO7242MDW(1)
Vcc/2 (CMOS)
(1) Product Preview
Copyright © 2007, Texas Instruments Incorporated
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ISO7241
ISO7242
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SLLS868–SEPTEMBER 2007
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
UNIT
VCC Supply voltage(2), VCC1, VCC2
–0.5 to 6
–0.5 to 6
±15
V
V
VI
IO
Voltage at IN, OUT, EN
Output current
mA
Human Body Model
JEDEC Standard 22, Test Method A114-C.01
JEDEC Standard 22, Test Method C101
ANSI/ESDS5.2-1996
±4
kV
Electrostatic Field-Induced-Charged Device
ESD
All pins
±1
discharge
Model
Machine Model
±200
170
V
TJ
Maximum junction temperature
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
3
TYP
MAX UNIT
5.5
V
VCC Supply voltage, VCC1, VCC2
3.6
IOH
IOL
High-level output current
Low-level output current
4
mA
mA
μs
–4
ISO724xA
ISO724xC
ISO724xM
ISO724xA
ISO724xC
ISO724xM
1
tui
Input pulse width
40
ns
6.67
5
250
30(1)
200(1)
0
1000
25
kbps
Mbps
1/tui Signaling rate
0
0
150
VIH
VIL
VIH
VIL
TJ
High-level input voltage (IN)
0.7 VCC
VCC
V
V
ISO724xM
Low-level input voltage (IN)
0
2
0
0.3 VCC
VCC
High-level input voltage (IN) (EN on all devices)
Low-level input voltage (IN) (EN on all devices)
Junction temperature
V
ISO724xA, ISO724xC
0.8
V
150
°C
A/m
H
External magnetic field-strength immunity per IEC 61000-4-8 & IEC 61000-4-9 certification
1000
(1) Typical value at room temperature and well-regulated power supply.
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ISO7241
ISO7242
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SLLS868–SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
ISO7240A/C/M
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
mA
mA
mA
mA
mA
Quiescent
1 Mbps
1
1
7
3
3
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
ISO7240A
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
10.5
TBD
TBD
TBD
TBD
TBD
TBD
22
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC1
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
ISO7242C/M
ISO7240A/C/M
ISO7240A
25 Mbps
Quiescent
1 Mbps
15
16
17
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
22
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
25
TBD
TBD
TBD
TBD
TBD
TBD
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC2
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
ISO7242C/M
25 Mbps
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, Single channel
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0
μA
VCC – 0.4
VCC – 0.1
VOH
High-level output voltage
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
μA
10
IN from 0 V to VCC
IIL
–10
25
CI
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
50
kV/μs
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ISO7241
ISO7242
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SLLS868–SEPTEMBER 2007
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN TYP
MAX UNIT
tPLH, tPHL
PWD
40
80
ISO724xA
ISO724xC
ISO724xM
|
|
|
10
ns
42
tPLH, tPHL
PWD
Propagation delay
18
See Figure 1
Pulse-width distortion(1) |tPHL – tPLH
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
2.5
tPLH, tPHL
PWD
10
22
ns
2
1
ISO724xA/C
ISO724xM
ISO724xA/C
ISO724xM
9
ns
(2)
tsk(pp)
Part-to-part skew
0
2
1
ns
(3)
tsk(o)
Channel-to-channel output skew
0
2
tr
Output signal rise time
Output signal fall time
See Figure 1
ns
ns
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
12
20
20
20
20
See Figure 2
See Figure 3
μs
150 Mbps NRZ data input, Same
polarity input on all channels, See
Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO724xM
1
ns
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6
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ISO7240
ISO7241
ISO7242
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SLLS868–SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
ISO7240A/C/M
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
mA
mA
mA
mA
mA
Quiescent
1 Mbps
1
1
7
3
3
ISO7240A
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
10.5
TBD
TBD
TBD
TBD
TBD
TBD
15
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC1
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ISO7242C/M
ISO7240A/C/M
ISO7240A
25 Mbps
Quiescent
1 Mbps
9.5
10
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
15
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
10.5
17
TBD
TBD
TBD
TBD
TBD
TBD
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC2
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ISO7242C/M
25 Mbps
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
High-level output voltage
EN at VCC, Single channel
ISO7240
0
μA
VCC – 0.4
VCC – 0.8
VCC – 0.1
IOH = –4 mA, See Figure 1
ISO724x
VOH
V
(5-V side)
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
High-level input current
Low-level input current
Input capacitance to ground
10
IN from 0 V to VCC
IIL
–10
25
CI
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity VI = VCC or 0 V, See Figure 4
50
kV/μs
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ISO7241
ISO7242
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SLLS868–SEPTEMBER 2007
SWITCHING CHARACTERISTICS
VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH, tPHL Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH
tPLH, tPHL Propagation delay
TEST CONDITIONS
MIN
TYP MAX
UNIT
40
80
11
46
3
ISO724xA
|
|
ns
20
12
ISO724xC
ISO724xM
See Figure 1
PWD
Pulse-width distortion(1) |tPHL – tPLH
tPLH, tPHL Propagation delay
28
2
ns
ns
PWD
Pulse-width distortion(1) |tPHL – tPLH
|
1
0
ISO724xA/C
ISO724xM
ISO724xA/C
ISO724xM
7.5
(2)
tsk(pp)
Part-to-part skew
2.5
1
ns
ns
(3)
tsk(o)
Channel-to-channel output skew
0
2
tr
Output signal rise time
Output signal fall time
See Figure 1
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
18
20
20
20
20
See Figure 2
See Figure 3
ns
μs
150 Mbps PRBS NRZ data input,
Same polarity input on all
channels, See Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO724xM
1
ns
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
8
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ISO7240
ISO7241
ISO7242
www.ti.com
SLLS868–SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
VCC1 at 3.3-V, VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
mA
mA
mA
mA
mA
ISO7240A/C/M
ISO7240A
Quiescent
1 Mbps
0.5
1
1
2
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
3
5
TBD
TBD
TBD
TBD
TBD
TBD
22
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC1
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ISO7242C/M
ISO7240A/C/M
ISO7240A
25 Mbps
Quiescent
1 Mbps
15
16
17
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
22
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
25
TBD
TBD
TBD
TBD
TBD
TBD
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC2
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ISO7242C/M
25 Mbps
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
High-level output voltage
EN at VCC, Single channel
ISO7240
0
μA
VCC – 0.4
VCC – 0.8
IOH = –4 mA, See Figure 1
ISO724x
VOH
V
(5-V side)
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
VCC – 0.1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
μA
10
IN from 0 V to VCC
IIL
–10
25
CI
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
CMTI
50
kV/μs
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ISO7241
ISO7242
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SWITCHING CHARACTERISTICS
VCC1 at 3.3-V and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tPLH, tPHL
PWD
Propagation delay
40
80
11
51
3
ISO724xA
ISO724xC
ISO724xM
Pulse-width distortion(1) |tPHL – tPLH
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
|
ns
tPLH, tPHL
PWD
22
12
See Figure 1
|
tPLH, tPHL
PWD
Propagation delay
26
2
ns
ns
ns
ns
Pulse-width distortion(1) |tPHL – tPLH
|
1
0
ISO724xA/C
ISO724xM
ISO724xA/C
ISO724xM
10
(2)
tsk(pp)
Part-to-part skew
2.5
1
(3)
tsk(o)
Channel-to-channel output skew
0
2
tr
Output signal rise time
Output signal fall time
See Figure 1
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
12
20
20
20
20
See Figure 2
See Figure 3
ns
μs
150 Mbps NRZ data input, Same polarity
input on all channels, See Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO724xM
1
ns
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ISO7240A/C/M
Quiescent
1 Mbps
0.5
1
1
2
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
ISO7240A
mA
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
3
5
TBD
TBD
TBD
TBD
TBD
TBD
15
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC1
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
mA
mA
mA
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
ISO7242C/M
ISO7240A/C/M
ISO7240A
25 Mbps
Quiescent
1 Mbps
9.5
10
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
15
ISO7240C/M
ISO7241A/C/M
ISO7241A
25 Mbps
Quiescent
1 Mbps
10.5
17
TBD
TBD
TBD
TBD
TBD
TBD
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC2
ISO7241C/M
ISO7242A/C/M
ISO7242A
25 Mbps
Quiescent
1 Mbps
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
ISO7242C/M
25 Mbps
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, single channel
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0
μA
VCC – 0.4
VCC – 0.1
VOH
High-level output voltage
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
150
mV
μA
High-level input current
10
IN from 0 V or VCC
IIL
Low-level input current
–10
25
CI
Input capacitance to ground
Common-mode transient immunity
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
VI = VCC or 0 V, See Figure 4
50
kV/μs
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SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay
TEST CONDITIONS
MIN
TYP MAX
UNIT
tPLH, tPHL
PWD
45
85
12
56
4
ISO724xA
ISO724xC
ISO724xM
(1)
(1)
(1)
Pulse-width distortion |tPHL – tPLH
|
|
|
ns
tPLH, tPHL
PWD
Propagation delay
25
12
See Figure 1
Pulse-width distortion |tPHL – tPLH
Propagation delay
tPLH, tPHL
PWD
32
2
ns
ns
ns
Pulse-width distortion |tPHL – tPLH
1
0
ISO724xA/C
ISO724xM
ISO724xA/C
ISO724xM
9
tsk(pp)
Part-to-part skew(2)
3
1
(3)
tsk(o)
Channel-to-channel output skew
0
2
tr
Output signal rise time
Output signal fall time
See Figure 1
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
18
20
20
20
20
See Figure 2
See Figure 3
ns
μs
150 Mbps PRBS NRZ data input, same
polarity input on all channels, See Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO724xM
1
ns
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7242
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PARAMETER MEASUREMENT INFORMATION
V
1
CC
V
V
1/2
CC
V
1/2
I
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
V
C
V
V
O
50 W
OH
OL
L
NOTE B
I
90%
10%
V
O
50%
50%
NOTE A
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
Vcc
RL = 1 kW 1ꢀ
Vcc/2
50ꢀ
Vcc/2
V
I
IN
0 V
OUT
VO
tPZL
0V
tPLZ
Vcc
0.5 V
EN
CL
V
O
NOTE
B
Input
VOL
VI
Generator
50 W
NOTE A
Vcc
V
O
IN
Vcc/2
Vcc/2
OUT
V
3V
I
0 V
VOH
t
PZH
EN
CL
RL = 1 kW 1ꢀ
50ꢀ
0.5 V
NOTE
B
V
Input
O
0 V
VI
Generator
tPHZ
50 W
NOTE A
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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SLLS868–SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
1
CC
V
1
CC
V
I
0 V
or
2.7 V
OUT
IN
V
0 V
V
O
V
1
t
CC
fs
OH
C
V
L
50%
O
NOTE B
V
OL
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
1
V
2
CC
CC
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass-fail criteria:
Output must
remain stable
OUT
IN
S1
NOTE B
V
or V
OL
OH
GND1
GND2
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
V
1
CC
DUT
Tektronix
HFS9009
IN
0 V
V
Tektronix
784D
OUT
PATTERN
/2
GENERATOR
CC
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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ISO7242
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SLLS868–SEPTEMBER 2007
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
L(I01) Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
7.7
mm
L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the
package surface
8.1
mm
mm
Minimum Internal Gap (Internal
Distance through the insulation
Clearance)
0.008
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device
RIO
Isolation resistance
>1012
Ω
CIO
CI
Barrier capacitance Input to output
Input capacitance to ground
VI = 0.4 sin (4E6πt)
1
1
pF
pF
VI = 0.4 sin (4E6πt)
DEVICE I/O SCHEMATICS
Enable
Output
Input
VCC
VCC
VCC
VCC
VCC
VCC
1 MW
500 W
8 W
500 W
IN
EN
OUT
13 W
1 MW
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SLLS868–SEPTEMBER 2007
REGULATORY INFORMATION
UL
Recognized under 1577 Component Recognition Program(1)
File Number: E181974
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL
1577.
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Low-K Thermal Resistance(1)
168
°C/W
96.1
θJA
Junction-to-air
High-K Thermal Resistance
θJB
θJC
Junction-to-Board Thermal Resistance
Junction-to-Case Thermal Resistance
61
48
°C/W
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
PD
Device Power Dissipation
220
mW
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
TYPICAL CHARACTERISTIC CURVES
3.3-V RMS SUPPLY CURRENT
5-V RMS SUPPLY CURRENT
vs
vs
SIGNALING RATE
SIGNALING RATE
45
40
35
35
30
VCC1 = 5 V,
VCC2 = 5 V,
TA = 25°C,
Load = 15 pF,
All Channels
VCC1 = 3.3 V,
VCC2 = 3.3 V,
TA = 25°C,
Load = 15 pF,
All Channels
25
20
15
10
5
30
ICC2
ICC2
25
20
ICC1
15
ICC1
10
5
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTIC CURVES (continued)
PROPAGATION DELAY
INPUT VOLTAGE THRESHOLD
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
45
40
35
1.4
1.35
1.3
5 V Vth+
tPLH
3.3 V
tPHL
3.3 V Vth+
5 V
30
25
20
tPLH
1.25
1.2
tPHL
Air Flow at 7 cf/m,
Low_K Board
1.15
1.1
15
10
5 V Vth-
Load = 15 pF,
Air Flow at 7 cf/m,
Low-K Board
1.05
1
5
0
3.3 V Vth-
110 125
80
-40
65
95
-40 -25
-10
5
20
35
50
65
80
95
110 125
-25
-10
5
35
20
50
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 8.
Figure 9.
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
3
50
40
30
20
VCC at 5 V or 3.3 V,
Load = 15 pF,
TA = 25°C
VCC = 5 V
2.9
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
2.8
VCC = 3.3 V
2.7
2.6
2.5
2.4
2.3
Vfs+
Vfs-
2.2
10
0
2.1
2
0
-40
-25
-10
5
20
35
50
65
80
95
110 125
4
6
2
VO - Output Voltage - V
TA - Free-Air Temperature - °C
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTIC CURVES (continued)
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
Load = 15 pF,
TA = 25°C
45
40
35
VCC = 3.3 V
30
25
20
VCC = 5 V
15
10
5
0
1
0
2
3
4
5
VO - Output Voltage - V
Figure 12.
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SLLS868–SEPTEMBER 2007
APPLICATION INFORMATION
20 mm
20 mm
V
V
CC1
Max From
CC2
Max From
V
V
CC1
CC2
0.1 mF
0.1 mF
1
2
16
GND1
15
GND2
IN
IN
IN
OUT
A
3
4
5
6
14
13
12
11
10
A
B
C
OUT
B
OUT
C
IN
D
OUT
D
EN
NC
7
8
9
GND2
GND1
ISO7240x
Figure 13. Typical ISO724x Application Circuit
LIFE EXPECTANCY vs. WORKING VOLTAGE
100
V
at 560-V
IORM
28 Years
10
0
120
250
500
750
1000
880
WORKING VOLTAGE (VIORM) -- V
Figure 14. Time-Dependant Dielectric Breakdown Testing Results
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PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
ISO7240ADWR
ISO7240CDWR
ISO7240MDWR
DW
DW
DW
16
16
16
SITE 35
SITE 35
SITE 35
10.9
10.9
10.9
10.78
10.78
10.78
3.0
3.0
3.0
12
12
12
16
16
16
Q1
Q1
Q1
330
16
330
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
ISO7240ADWR
ISO7240CDWR
ISO7240MDWR
DW
DW
DW
16
16
16
SITE 35
SITE 35
SITE 35
406.0
406.0
406.0
348.0
348.0
348.0
63.0
63.0
63.0
Pack Materials-Page 2
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