ISO7310CQDRQ1 [TI]
汽车类低功耗、单通道、25Mbps 数字隔离器 | D | 8 | -40 to 125;
| 型号： | ISO7310CQDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类低功耗、单通道、25Mbps 数字隔离器 | D | 8 | -40 to 125 |
| 文件： | 总27页 (文件大小：795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
ISO7310-Q1 优异 EMC 低功耗单通道数字隔离器
1 特性
2 应用
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
•
在下列使用中的光电耦合器替代产品：
–
工业用 FieldBus
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
–
–
–
ProfiBus
ModBus
–
–
器件人体模型 (HBM) 分类等级 3A
DeviceNet™数据总线
器件充电器件模型 (CDM) 分类等级 C6
–
–
–
–
伺服控制接口
电机控制
电源
•
•
•
•
信号传输速率：25Mbps
输入端集成有噪声滤波器
默认输出高电平和低电平选项
低功耗：ICC 典型值
电池组
3 说明
–
1Mbps 时为 1.9mA，25Mbps 时为 3.8mA（5V
电源供电时）
ISO7310-Q1 器件可提供符合 UL 1577 标准的长达 1
分钟且高达 3000 VRMS的电流隔离，以及符合 VDE V
0884-10 标准的 4242 VPK 隔离。这些器件具有一个隔
离通道，其逻辑输入和输出缓冲器由二氧化硅 (SiO2)
绝缘隔栅分离开来。与隔离式电源一起使用
–
1Mbps 时为 1.4mA，25Mbps 时为
2.6mA（3.3V 电源供电时）
•
•
•
低传播延迟：典型值 32ns（5V 电源供电时）
65kV/μs 瞬态抗扰度，典型值（5V 电源供电时）
优异的电磁兼容性 (EMC)
时，ISO7310-Q1 器件可防止数据总线或者其他电路上
的噪声电流进入本地接地端并干扰或损坏敏感电路。该
器件已集成了针对恶劣工业环境的噪声滤波器，在此类
环境下，器件的输入引脚上可能会出现短噪声脉冲。
–
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及
抗浪涌保护
–
低辐射
•
•
•
•
•
隔离隔栅寿命：> 25 年
由 3.3V 和 5V 电源供电
3.3V 和 5V 电平转换
ISO7310-Q1 器件具有晶体管-晶体管逻辑电路 (TTL)
输入阈值，工作电压范围为 3V 到 5.5V。凭借创新的
芯片设计和布线技术，ISO7310-Q1 器件的电磁兼容性
得到了显著增强，可确保提供系统级 ESD、EFT 和浪
涌保护并符合辐射标准。
窄体小尺寸集成电路 (SOIC)-8 封装
安全及管理批准:
–
符合 DIN V VDE V 0884-10 和 DIN EN 61010-
1 标准的 4242 VPK 隔离 中的“DIN V VDE
0884-10”更改为“DIN V VDE V 0884-10” 中）
器件信息(1)
器件型号
ISO7310-Q1
封装
SOIC (8)
封装尺寸（标称值）
–
–
符合 UL 1577 标准且长达一分钟的 3000 VRMS”
4.90mm x 3.91mm
CSA 组件接受通知 5A，
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
IEC 60950-1 和 IEC 61010-1 终端设备标准中
的 CSA 组件接受列表项中 CSA 组件接受列表
项的“（审批正在审理中）”
简化电路原理图
V
V
CC2
CC1
Isolation
Capacitor
–
已计划符合 GB4943.1-2011 的 CQC 认证
的“所有机构的审批已通过”
IN
OUT
GND1
GND2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSER6
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
Applications and Implementation ...................... 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics—5-V Supply ..................... 5
6.6 Supply Current Characteristics—5-V Supply............ 5
6.7 Electrical Characteristics—3.3-V Supply .................. 5
6.8 Supply Current Characteristics—3.3-V Supply......... 5
6.9 Power Dissipation Characteristics ............................ 6
6.10 Switching Characteristics—5-V Supply................... 6
6.11 Switching Characteristics........................................ 6
6.12 Typical Characteristics............................................ 7
Parameter Measurement Information .................. 9
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 器件和文档支持 ..................................................... 19
12.1 文档支持................................................................ 19
12.2 社区资源................................................................ 19
12.3 商标....................................................................... 19
12.4 静电放电警告......................................................... 19
12.5 Glossary................................................................ 19
13 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 12 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
VCC1
VCC2
1
2
3
4
8
7
6
5
IN
GND2
OUT
VCC1
GND1
GND2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
4
GND1
—
—
Ground connection for VCC1
5
GND2
Ground connection for VCC2
7
IN
2
I
Input
OUT
6
O
Output
1
VCC1
VCC2
—
—
Power supply, VCC1
Power supply, VCC2
3
8
Copyright © 2015, Texas Instruments Incorporated
3
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
MAX
UNIT
Supply voltage(2)
VCC1 , VCC2
IN, OUT
6
V
(2)
Voltage
VCC+0.5(3)
V
IO
Output current
±15
mA
°C
°C
TJ
Junction temperature
Storage temperature
150
Tstg
–65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
V
VCC1, VCC2 Supply voltage
5.5
IOH
IOL
VIH
VIL
tui
High-level output current
–4
mA
mA
V
Low-level output current
High-level input voltage
Low-level input voltage
Input pulse duration
Signaling rate
4
5.5
0.8
2
0
V
40
0
ns
1 / tui
TJ
25
136
125
Mbps
°C
Junction temperature(1)
TA
Ambient temperature
–40
25
°C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
ISO7310-Q1
D (SOIC)
8 PINS
119.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
65.2
61.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19.3
ψJB
60.7
RθJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
6.5 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC2 – 0.5
VCC2 – 0.1
TYP
4.7
5
MAX
UNIT
IOH = –4 mA; see Figure 9
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 9
IOL = 4 mA; see Figure 9
IOL = 20 μA; see Figure 9
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS) Input threshold voltage hysteresis
480
mV
μA
IIH
High-level input current
IN = VCC
10
IIL
Low-level input current
IN = 0 V
–10
25
μA
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11.
65
kV/μs
6.6 Supply Current Characteristics—5-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over
recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
0.3
1.6
0.5
2.2
0.8
3
0.6
2.4
1
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
DC to 1 Mbps
10 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
CL = 15 pF
CL = 15 pF
mA
ICC2
3.2
1.3
4.2
ICC1
25 Mbps
ICC2
6.7 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3
MAX
UNIT
IOH = –4 mA; see Figure 9
VCC2 – 0.5
VCC2 – 0.1
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 9
IOL = 4 mA; see Figure 9
IOL = 20 μA; see Figure 9
3.3
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
450
mV
μA
IN = VCC
10
IIL
Low-level input curre
IN = 0 V
–10
25
μA
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11
50
kV/μs
6.8 Supply Current Characteristics—3.3-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over
recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ICC1
0.2
1.2
0.3
1.6
0.5
2.1
0.4
1.8
0.5
2.2
0.8
3
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
DC to 1 Mbps
10 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
CL = 15 pF
CL = 15 pF
mA
ICC2
ICC1
25 Mbps
ICC2
Copyright © 2015, Texas Instruments Incorporated
5
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
6.9 Power Dissipation Characteristics
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty-cycle square wave (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
34
UNIT
mW
mW
mW
PD
Maximum power dissipation
Power dissipation by Side-1
Power dissipation by Side-2
PD1
PD2
7.9
26.1
6.10 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tPLH, tPHL
PWD(1)
Propagation delay time
Pulse width distortion |tPHL – tPLH
Part-to-part skew time
Output signal rise time
Output signal fall time
See Figure 9
See Figure 9
20
32
58
4
|
ns
(2)
tsk(pp)
24
ns
tr
tf
See Figure 9
See Figure 9
2.5
2
ns
ns
Fail-safe output delay time from input
power loss
tfs
See Figure 10
7.5
μs
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
67
UNIT
ns
tPLH, tPHL
PWD(1)
Propagation delay time
Pulse width distortion |tPHL – tPLH
Part-to-part skew time
Output signal rise time
Output signal fall time
See Figure 9
See Figure 9
22
36
|
3.5
28
ns
(2)
tsk(pp)
ns
tr
tf
See Figure 9
See Figure 9
3.2
2.7
ns
ns
Fail-safe output delay time from input
power loss
tfs
See Figure 10
7.4
μs
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
6.12 Typical Characteristics
3.5
3.5
3
ICC2 at 5 V
ICC2 at 3.3 V
V
ICC1 at 5 V
V
ICC2 at 5 V
I
at 3.3 V
CC2
3
2.5
2
I
at 5 V
CC1
I
at 3.3 V
I
at 3.3 V
CC1
2.5
2
CC1
1.5
1
1.5
1
0.5
0
0.5
0
0
5
10
15
20
25
0
5
10
15
20
25
Data Rate (Mbps)
Data Rate (Mbps)
C014
C014
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 1. Supply Current vs Data Rate (With 15-pF Load)
Figure 2. Supply Current vs Data Rate (With No Load)
6
0.9
V
at 5 V
CC
VCC at 3.3 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 3.3 V
V
at 5 V
CC
CC
5
4
3
2
1
0
œ15
œ10
œ5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
C014
C014
TA = 25°C
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output
Current
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
43
2.5
tpHL at 3.3 V
VCC Rising
41
tpLH at 3.3 V
2.48
2.46
2.44
2.42
2.4
V
Falling
CC
tpHL at 5 V
39
tpLH at 5 V
37
35
33
31
29
27
25
2.38
2.36
2.34
4ꢀ
5
3ꢀ
65
1ꢀꢀ
135
œ40 œ20
0
20
40
60
80
100 120 140
Free-Air Temperature (oC)
Free-Air Temperature (oC)
Cꢀ14
C014
Figure 6. Propagation Delay Time vs Free-Air Temperature
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
Copyright © 2015, Texas Instruments Incorporated
7
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
Typical Characteristics (continued)
29
tGS at 5 V
240
220
200
180
160
140
120
100
tGS at 3.3 V
27
25
23
21
19
17
15
Output Jitter at 3.3 V
Output Jitter at 5 V
±±4
±5
34
65
144
135
0
5
10
15
20
25
Free-Air Temperature (oC)
Data Rate (Mbps)
C41±
C014
TA = 25°C
Figure 7. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 8. Output Jitter vs Data Rate
8
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
7 Parameter Measurement Information
VCC1
VI
50%
50%
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator(1)
(2)
CL
50 Ω
VI
VOH
90%
10%
50%
50%
VO
VOL
tr
tf
(1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCC
VCC
2.7 V
VI
0 V
IN
OUT
IN = 0 V (ISO7310C)
IN = VCC (ISO7310FC)
tfs
VO
VOH
fs high
fs low
50%
VO
(1)
CL
VOL
(1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
VCC1
VCC1
C = 0.1 µF 1ꢀ
C = 0.1 µF 1ꢀ
Pass-fail criteria:
output must remain
stable.
IN
OUT
S1
+
(1)
CL
VOH or VOL
–
GND1
GND2
–
+
VCM
(1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
Copyright © 2015, Texas Instruments Incorporated
9
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to
25 Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitions from 0
to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL)
at the output of the HF channel comparator measures the durations between signal transients. If the duration
between two consecutive transients exceeds a certain time limit (as in the case of a low-frequency signal), the
DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Lsolation .arrier
OSC
[ow t Crequency
/hannel
PWM
VREF
LPF
(5/ꢀꢀꢀ100 kbps)
0
1
ꢃolarity and
Çhreshold {election
OUT
IN
{
Iigh t Crequency
/hannel
DCL
VREF
(100 kbpsꢀꢀꢀ2ꢁ ꢂbps)
ꢃolarity and Çhreshold {election
Figure 12. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
10
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
8.3 Feature Description
ORDERABLE DEVICE
RATED ISOLATION
MAX DATA RATE
DEFAULT OUTPUT
ISO7310CQDQ1 and
ISO7310CQDRQ1
High
(1)
3000 VRMS / 4242 VPK
25 Mbps
ISO7310FCQDQ1 and
ISO7310FCQDRQ1
Low
(1) See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
L(I02)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
400
13
mm
V
Tracking resistance (comparative
tracking index)
CTI
DTI
DIN EN 60112 (VDE 0303-11); IEC 60112
Distance through the insulation
Minimum internal gap (internal
clearance)
µm
VIO = 500 V, TA = 25°C
>1012
>1011
Ω
Ω
Isolation resistance, input to
output(1)
RIO
VIO = 500 V, 100°C ≤ TA ≤ 125°C
Isolation capacitance, input to
output(1)
Input capacitance(2)
CIO
CI
VIO = 0.4 sin (2πft), f = 1 MHz
0.5
1.6
pF
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
Copyright © 2015, Texas Instruments Incorporated
11
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
VIOWM
VIORM
Maximum isolation working voltage
400
VRMS
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566
VPK
After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
680
906
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
VPK
Partial Discharge < 5 pC
Method b1,
VPR = VIORM × 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
Maximum transient overvoltage per
DIN V VDE V 0884-10
VIOTM
4242
6000
VPK
VPK
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
VIOSM
VTEST = VISO = 3000 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 sec (100%
production)
VISO
Withstand isolation voltage per UL 1577
3000
VRMS
RS
Insulation resistance
Pollution degree
VIO = 500 V at TS = 150°C
>109
2
Ω
(1) Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Installation classification
8.3.1.3 Regulatory Information
VDE
CSA
UL
CQC
Certified according to DIN V VDE Approved under CSA
Recognized under UL 1577
Component Recognition
Program
V 0884-10 (VDE V 0884-
Component Acceptance Notice
Plan to certify according to
GB4943.1-2011
10):2006-12 and DIN EN 61010- 5A, IEC 60950-1, and IEC
1 (VDE 0411-1):2011-07
61010-1
400 VRMS Basic Insulation and
200 VRMS Reinforced Insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2;
300 VRMS Basic Insulation
working voltage per CSA
61010-1-12 and IEC 61010-1
3rd Ed.
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK
Maximum Surge Isolation
Voltage, 6000 VPK
;
Basic Insulation, Altitude ≤ 5000 m,
Tropical Climate, 250 VRMS
maximum working voltage
(1)
Single protection, 3000 VRMS
File number: E181974
;
Maximum Repetitive Peak
Voltage, 566 VPK
Master contract number:
220991
Certificate number: 40016131
Certification planned
(1) Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
12
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
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ZHCSEH0 –DECEMBER 2015
8.3.1.4 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
190
290
150
UNIT
mA
R
θJA = 119.9 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
θJA = 119.9 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
Safety input, output, or supply
current
IS
R
TS
Maximum safety temperature
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
350
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
300
250
200
150
100
50
0
0
50
100
150
200
Ambient Temperature (èC)
D001
Figure 13. Thermal Derating Curve per VDE
Copyright © 2015, Texas Instruments Incorporated
13
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7310-Q1 device.
Table 2. Function Table(1)
OUT
VCC1
VCC2
IN
ISO7310CQDQ1 AND
ISO7310FCQDQ1 AND
ISO7310CQDRQ1
ISO7310FCQDRQ1
H
L
H
H
PU
PU
L
H(2)
H(2)
L
L(3)
L(3)
Open
X
PD
X
PU
PD
X
Undetermined
Undetermined
(1) PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (ISO7310C)
VCC1
VCC1
VCC1
VCC1
5 µA
500 Ω
IN
Output
VCC2
40 Ω
OUT
Input (ISO7310FC)
VCC1
VCC1
VCC1
500 Ω
IN
5 µA
Figure 14. Device I/O Schematics
14
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7310-Q1 device uses single-ended TTL-logic switching technology. The supply voltage range is from 3 V
to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (essentially μC or UART), and a data converter or a line transceiver, regardless of the interface
type or standard.
9.2 Typical Application
The ISO7310-Q1 device can be used with a Texas Instruments’ microcontroller, CAN transceiver, transformer
driver, and low-dropout voltage regulator to create an Isolated CAN Interface as shown in Figure 15.
VS
10 ꢀF
3.3 V
2
MBR0520L
Vcc
1:1.33
ISO 3.3V
3
1
1
5
2
D2
D1
IN
OUT
TPS76333-Q1
SN6501-Q1
10 ꢀF
0.1 ꢀF
10 ꢀF
3
EN
GND
MBR0520L
GND
GND
4
5
ISO Barrier
0.1 ꢀF
5,7
4
GND2
GND1
IN
3
0.1 ꢀF
6
8
2
ISO7310-Q1
OUT
VCC
RS
8
10 ꢁ (optional)
10 ꢁ (optional)
1,3
4
1
VCC2
VCC1
R
CANH
29,57
7
6
0.1 ꢀF
0.1 ꢀF
SN65HVD231Q
V
DDIO
26
25
D
CANL
Vref
CANRXA
CANTXA
TMS320F28
035PAGQ
0.1 ꢀF
GND
5
0.1 ꢀF
SM712
2
VCC1
VCC2
1,3
2
8
6
V
SS
IN
OUT
ISO7310-Q1
6,28
GND1
GND2
4
5,7
4.7 nF /
2 kV
(1) Multiple pins and capacitors omitted for clarity purpose.
Figure 15. Isolated CAN Interface
Copyright © 2015, Texas Instruments Incorporated
15
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
For the equations in this section, the following is true:
•
•
•
ICC1 and ICC2 are typical supply currents measured in mA
f is the data rate measured in Mbps
CL is the capacitive load measured in pF
At VCC1 = VCC2 = 5 V
ICC1 = 0.30517 + (0.01983 × f)
(1)
(2)
ICC2 = 1.40021 + (0.02879 × f) + (0.0021 × f × CL)
At VCC1 = VCC2 = 3.3 V
ICC1 = 0.18133 + (0.01166 × f)
(3)
(4)
ICC2 = 1.053 + (0.01607 × f) + (0.001488 × f × CL)
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7310-Q1 device only requires two external bypass capacitors to operate.
VCC1
VCC1
2 mm
maximum
from
2 mm
maximum
from
0.1 µF
VCC2
0.1 µF
VCC1
1
2
8
7
6
5
IN
INPUT
3
4
OUT
OUTPUT
GND1
GND2
Figure 16. Typical ISO7310-Q1 Circuit Hook-up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7310-
Q1 device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
16
Copyright © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
Typical Application (continued)
9.2.3 Application Curves
The following typical eye diagrams of the ISO7310-Q1 device indicate low jitter and wide open eye at the
maximum data rate of 25 Mbps.
Figure 18. Eye Diagram at 25 Mbps, 3.3 V and 25°C
Figure 17. Eye Diagram at 25 Mbps, 5 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-µF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1
device. For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501-Q1 datasheet (SLLSEF3).
Copyright © 2015, Texas Instruments Incorporated
17
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 19). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note SLLA284, Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 19. Recommended Layer Stack
18
版权 © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
•
•
《数字隔离器设计指南》，SLLA284
《ISO7310 评估模块用户指南》，SLLU206
《隔离相关术语》，SLLA353
《SN6501-Q1 用于隔离电源的变压器驱动器》，SLLSEF3
《SN65HVD231Q 3.3V CAN 收发器》，SGLS398
《TMS320F28035 Piccolo™ 微控制器》，SPRS584
《TPS76333-Q1 低功耗 150mA 低压降线性稳压器》，SGLS247
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2015, Texas Instruments Incorporated
19
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
版权 © 2015, Texas Instruments Incorporated
21
ISO7310-Q1
ZHCSEH0 –DECEMBER 2015
www.ti.com.cn
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
22
版权 © 2015, Texas Instruments Incorporated
ISO7310-Q1
www.ti.com.cn
ZHCSEH0 –DECEMBER 2015
EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
版权 © 2015, Texas Instruments Incorporated
23
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只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
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法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
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能源
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接口
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www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
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www.ti.com.cn/industrial
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www.ti.com.cn/logic
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Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7310CQDQ1
ISO7310CQDRQ1
ISO7310FCQDQ1
ISO7310FCQDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7310Q
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
7310Q
7310FQ
7310FQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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