ISO7310FC [TI]
低功耗、单通道、25Mbps、默认输出低电平数字隔离器;
| 型号： | ISO7310FC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗、单通道、25Mbps、默认输出低电平数字隔离器 |
| 文件： | 总26页 (文件大小：1414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
ISO7310x 优异电磁兼容性 (EMC) 低功耗单通道数字隔离器
1 特性
3 说明
1
•
信号传输速率：25Mbps
输入端集成有噪声滤波器
ISO7310x 可提供符合 UL 标准的长达 1 分钟且高达
3000 VRMS 的电流隔离，以及符合 VDE 标准的 4242
•
•
•
VPK 隔离。 这些器件具有一个隔离通道，其逻辑输入
默认输出“高电平”和“低电平”选项
低功耗：ICC 典型值
和输出缓冲器由二氧化硅 (SiO2) 绝缘隔栅分离开来。
通过与隔离电源一起使用，ISO7310x 可防止数据总线
或者其它电路上的噪声电流进入本地接地端并干扰或者
损坏敏感电路。 这些器件已针对恶劣环境集成了噪声
滤波器，在此类环境下，器件的输入引脚上可能会出现
短噪音脉冲。 ISO7310x 具有晶体管晶体管逻辑电路
(TTL) 输入阈值，工作电压范围为 3V 到 5.5V。 凭借
创新的芯片设计和布线技术，ISO7310x 的电磁兼容性
得到了显著增强，从而可确保提供系统级 ESD、EFT
和浪涌保护并符合辐射标准。
–
1Mbps 时为 1.9mA，25Mbps 时为 3.8mA（5V
电源供电时）
–
1Mbps 时为 1.4mA，25Mbps 时为
2.6mA（3.3V 电源供电时）
•
•
•
•
•
低传播延迟：典型值 32ns（5V 电源供电时）
3.3V 和 5V 电平转换
宽 TA 额定范围：-40°C 至 125°C
65KV/μs 瞬态抗扰度，典型值（5V 电源供电时）
优异的电磁兼容性 (EMC)
–
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及
抗浪涌保护
器件信息(1)
器件型号
ISO7310C
ISO7310FC
封装
封装尺寸（标称值）
–
低辐射
•
•
•
•
隔离隔栅寿命：> 25 年
可由 3.3V 和 5V 电压供电
窄体小尺寸集成电路 (SOIC)-8 封装
安全及管理批准:
SOIC (8)
4.90mm x 3.91mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
–
–
–
符合 DIN V VDE V 0884-10 标准和 DIN EN
61010-1 标准的 4242 VPK 隔离 ”中）中）
VCC2
VCC1
Isolation
Capacitor
符合 UL 1577 标准且长达 1 分钟的 3000 VRMS
隔离”
IN
OUT
CSA 组件接受通知 5A，
IEC 60950-1 和 IEC 61010-1 终端设备标准中
的 CSA 组件接受列表项中 CSA 组件接受列表
项的“（审批正在审理中）”
GND1
GND2
–
符合 GB4943.1-2011 的 CQC 认证
的“所有机构的审批已通过”
2 应用
•
在下列应用中的光电耦合器替代产品：
–
工业用 FieldBus
–
–
–
ProfiBus
ModBus
DeviceNet™ 数据总线
–
–
–
–
伺服控制接口
电机控制
电源
电池组
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLLSEI8
ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
www.ti.com.cn
目录
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 15
Applications and Implementation ...................... 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 6
6.7 Electrical Characteristics........................................... 7
6.8 Switching Characteristics.......................................... 7
6.9 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 PCB Material......................................................... 19
11.2 Layout Guidelines ................................................. 19
11.3 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 商标....................................................................... 20
12.2 静电放电警告......................................................... 20
12.3 术语表 ................................................................... 20
13 机械、封装和可订购信息....................................... 20
7
8
4 修订历史记录
Changes from Revision C (March 2015) to Revision D
Page
•
•
•
•
•
•
已添加“和 DINEN 61010-1 标准”至“4242 VPK”（特性............................................................................................................. 1
已删除特性.............................................................................................................................................................................. 1
Deleted IEC from the section title: Insulation and Safety-Related Specifications for D-8 Package .................................... 12
Changed the CTI Test Conditions in Insulation and Safety-Related Specifications for D-8 Package ................................ 12
Changed VISO Test Condition in the Insulation Characteristics table .................................................................................. 13
Changed column CSA in the Regulatory Information table.................................................................................................. 13
Changes from Revision B (September 2014) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
已将特性中的“输入引脚上集成有噪声滤波器”更改为“输入端集成有噪声滤波器” .................................................................... 1
已添加特性 - 默认输出“高电平”和“低电平”选项....................................................................................................................... 1
已将“DIN V VDE 0884-10 标准”更改为 “DIN V VDE V 0884-10”（特性................................................................................. 1
已将特性中的“3 KVRMS 隔离”更改为“3000 VRMS 隔离 ............................................................................................................. 1
已添加“（审批正在审理中）”至特性 ....................................................................................................................................... 1
已将特性中的“通过 GB4943.1-2011 CQC 认证”更改为“符合 GB4943.1-2011 的 CQC 认证”................................................ 1
已将简化电路原理图中的 GND1 更改为 GNDI，GND2 更改为 GNDO.................................................................................. 1
Changed the Handling Ratings to ESD Ratings table and updated guidelines ..................................................................... 5
Changed the CTI MIN value in Insulation and Safety-Related Specifications for D-8 Package From: >400 V To: 400 V .. 12
Added "DT1" to the Minimum internal gap in Insulation and Safety-Related Specifications for D-8 Package ................... 12
Changed the DTI MIN value in Insulation and Safety-Related Specifications for D-8 Package From: 0.014 mm To:
13 µM.................................................................................................................................................................................... 12
•
•
Changed the RIO Test Condition in Insulation and Safety-Related Specifications for D-8 Package From: TA < 100°C
To: TA = 25°C ....................................................................................................................................................................... 12
Changed the RIO Test Condition in Insulation and Safety-Related Specifications for D-8 Package From: TA ≤ max
To: TA = 125°C ..................................................................................................................................................................... 12
•
•
Changed DIN V VDE 0884-10 To: DIN V VDE V 0884-10 in the Insulation Characteristics .............................................. 13
Added VIOSM to the Insulation Characteristics table ............................................................................................................ 13
2
版权 © 2014–2015, Texas Instruments Incorporated
ISO7310C, ISO7310FC
www.ti.com.cn
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
•
•
Changed RS Test Conditions in Insulation Characteristics From: TS To: TS = 150°C ......................................................... 13
Changed the Regulatory Information table, VDE Certified From: DIN V VDE 0884-10 To: DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07............................................................................ 13
•
•
•
•
•
•
•
Changed the Regulatory Information table, deleted (Approval Pending) statement............................................................ 13
Changed the Regulatory Information table, CQC Certified number From: CQC14001109540 To: CQC15001121656...... 13
Changed title From: " IEC Safety Limiting Values" To: Safety Limiting Values .................................................................. 14
Changed Table 2 Header information to include device number for the OUT column. Added Note 3. .............................. 15
Changed Figure 14 to include a diode at VCC1 on the Input circuit ...................................................................................... 15
Changed Figure 15 .............................................................................................................................................................. 16
Added Figure 16 .................................................................................................................................................................. 17
Changes from Revision A (July 2014) to Revision B
Page
•
•
添加了器件 ISO7310FC ......................................................................................................................................................... 1
已将特性中的 “符合 DIN EN 60747-5-5 (VDE 0884-5) 标准的 4242 VPK 隔离”更改为 “符合 DIN V VDE 0884-10
标准的 4242 VPK 隔离............................................................................................................................................................. 1
•
•
•
•
•
已删除特性安全及管理批准..................................................................................................................................................... 1
Replaced Figure 10 ............................................................................................................................................................. 10
Changed DIN EN 60747-5-5 To: DIN V VDE 0884-10 in the Insulation Characteristics .................................................... 13
Changed DIN EN 60747-5-5 (VDE 0884-5) To: DIN V VDE 0884-10 in the Regulatory Information table ......................... 13
Added a NOTE in the Application Information section ........................................................................................................ 16
Changes from Original (March 2014) to Revision A
Page
•
•
•
•
从单页产品预览更改为完整数据表.......................................................................................................................................... 1
已添加特性 - 通过 GB4943.1-2011 CQC 认证 ....................................................................................................................... 1
更改了说明部分，新增：“凭借创新的芯片设计...” .................................................................................................................. 1
已更改简化电路原理图 ........................................................................................................................................................... 1
Copyright © 2014–2015, Texas Instruments Incorporated
3
ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
www.ti.com.cn
5 Pin Configuration and Functions
D PACKAGE
(TOP VIEW)
VCC1
VCC2
8
7
6
5
1
2
3
4
IN
VCC1
GND2
OUT
GND1
GND2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VCC1
NUMBER
1, 3
2
–
I
Power supply, VCC1
Input
IN
GND1
GND2
OUT
VCC2
4
–
–
O
–
Ground connection for VCC1
Ground connection for VCC2
Output
5, 7
6
8
Power supply, VCC2
4
Copyright © 2014–2015, Texas Instruments Incorporated
ISO7310C, ISO7310FC
www.ti.com.cn
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
MAX
UNIT
V
Supply voltage(2)
VCC1 , VCC2
–0.5
6
(2)
Voltage
IN, OUT
IO
–0.5 VCC+0.5(3)
V
Output current
±15
150
mA
°C
Junction temperature
Storage temperature
TJ
Tstg
–65
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
MAX
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3
TYP
MAX
UNIT
VCC1, VCC2 Supply voltage
IOH High-level output current
IOL
5.5
V
mA
mA
V
–4
Low-level output current
High-level input voltage
Low-level input voltage
Input pulse duration
Signaling rate
4
5.5
0.8
VIH
VIL
tui
2
0
V
40
0
ns
1 / tui
25
136
125
Mbps
°C
(1)
TJ
Junction temperature
Ambient temperature
TA
-40
25
°C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
D PACKAGE
(8) PINS
119.9
65.2
THERMAL METRIC(1)
UNIT
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
Maximum power dissipation
61.3
°C/W
19.3
ψJB
60.7
RθJCbot
PD
N/A
34
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 12.5 MHz 50% duty-cycle square wave
PD1
Power dissipation by Side-1
7.9
mW
PD2
Power dissipation by Side-2
26.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014–2015, Texas Instruments Incorporated
5
ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
www.ti.com.cn
6.5 Electrical Characteristics
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC2 – 0.5
VCC2 – 0.1
TYP
4.7
5
MAX
UNIT
IOH = –4 mA; see Figure 9
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 9
IOL = 4 mA; see Figure 9
IOL = 20 μA; see Figure 9
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
480
mV
μA
IN = VCC
10
IIL
Low-level input current
IN = 0 V
–10
25
μA
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11.
65
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ICC1
0.3
1.6
0.5
2.2
0.8
3
0.6
2.4
1
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
DC to 1 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
10 Mbps
25 Mbps
CL = 15pF
CL = 15pF
mA
ICC2
ICC1
ICC2
3.2
1.3
4.2
6.6 Switching Characteristics
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
58
UNIT
ns
tPLH, tPHL
PWD(1)
Propagation delay time
20
32
See Figure 9
Pulse width distortion |tPHL – tPLH
|
4
ns
(2)
tsk(pp)
Part-to-part skew time
24
ns
tr
Output signal rise time
Output signal fall time
2.5
2
ns
See Figure 9
See Figure 10
tf
ns
tfs
Fail-safe output delay time from input power loss
7.5
μs
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6
Copyright © 2014–2015, Texas Instruments Incorporated
ISO7310C, ISO7310FC
www.ti.com.cn
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
6.7 Electrical Characteristics
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC2 – 0.5
VCC2 – 0.1
TYP
3
MAX
UNIT
IOH = –4 mA; see Figure 9
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 9
IOL = 4 mA; see Figure 9
IOL = 20 μA; see Figure 9
3.3
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
450
mV
μA
IN = VCC
10
IIL
Low-level input curre
IN = 0 V
-10
25
μA
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11
50
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ICC1
0.2
1.2
0.3
1.6
0.5
2.1
0.4
1.8
0.5
2.2
0.8
3
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
DC to 1 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
10 Mbps
25 Mbps
CL = 15pF
CL = 15pF
mA
ICC2
ICC1
ICC2
6.8 Switching Characteristics
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tPLH, tPHL
PWD(1)
Propagation delay time
22
36
67
3.5
28
See Figure 9
Pulse width distortion |tPHL – tPLH
|
ns
(2)
tsk(pp)
Part-to-part skew time
ns
tr
Output signal rise time
Output signal fall time
3.2
2.7
7.4
ns
See Figure 9
See Figure 10
tf
ns
tfs
Fail-safe output delay time from input power loss
μs
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2014–2015, Texas Instruments Incorporated
7
ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
www.ti.com.cn
6.9 Typical Characteristics
3.5
3.5
3
ICC2 at 5 V
ICC2 at 3.3 V
V
ICC1 at 5 V
V
ICC2 at 5 V
I
at 3.3 V
CC2
3
2.5
2
I
at 5 V
CC1
I
at 3.3 V
I
at 3.3 V
CC1
2.5
2
CC1
1.5
1
1.5
1
0.5
0
0.5
0
0
5
10
15
20
25
0
5
10
15
20
25
Data Rate (Mbps)
Data Rate (Mbps)
C014
C014
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 1. Supply Current vs Data Rate (with 15 pF Load)
Figure 2. Supply Current vs Data Rate (with No Load)
6
0.9
V
at 5 V
CC
VCC at 3.3 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 3.3 V
V
at 5 V
CC
CC
5
4
3
2
1
0
±15
±10
±5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
C014
C014
TA = 25°C
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output
Current
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
43
2.5
tpHL at 3.3 V
VCC Rising
41
39
37
35
33
31
29
27
25
tpLH at 3.3 V
2.48
2.46
2.44
2.42
2.4
V
Falling
CC
tpHL at 5 V
tpLH at 5 V
2.38
2.36
2.34
±40
±5
30
65
100
135
±40 ±20
0
20
40
60
80
100 120 140
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C014
C014
Figure 6. Propagation Delay Time vs Free-Air Temperature
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
8
Copyright © 2014–2015, Texas Instruments Incorporated
ISO7310C, ISO7310FC
www.ti.com.cn
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
Typical Characteristics (continued)
29
240
220
200
180
160
140
120
100
tGS at 5 V
tGS at 3.3 V
27
25
23
21
19
17
15
Output Jitter at 3.3 V
Output Jitter at 5 V
±40
±5
30
65
100
135
0
5
10
15
20
25
Free-Air Temperature (oC)
Data Rate (Mbps)
C014
C014
TA = 25°C
Figure 7. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 8. Output Jitter vs Data Rate
Copyright © 2014–2015, Texas Instruments Incorporated
9
ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
www.ti.com.cn
7 Parameter Measurement Information
VCC1
VI
50%
50%
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator(1)
(2)
50 W
VI
CL
VOH
VOL
90%
10%
50%
50%
VO
tr
tf
(1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Switching Characteristic Test Circuit and Voltage Waveforms
V
I
V
V
CC
CC
2.7 V
V
I
0 V
V
IN
OUT
IN = 0 V (ISO7310C)
IN = VCC (ISO7310FC)
t
V
fs
O
OH
fs high
fs low
50%
V
O
C
L
V
OL
NOTE A
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
VCC1
VCC2
C = 0.1 μF 1ꢀ
C = 0.1 μF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL(1)
GND2
VOH or VOL
–
GND1
–
+
VCM
(1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
10
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ISO7310C, ISO7310FC
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ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
8 Detailed Description
8.1 Overview
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitioned from
0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic
(DCL) at the output of the HF channel comparator measures the durations between signal transients. If the
duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency
signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Isolation Barrier
OSC
Low ± Frequency
Channel
PWM
VREF
LPF
(DC...100 kbps)
0
1
Polarity and
Threshold Selection
OUT
IN
S
High ± Frequency
Channel
DCL
VREF
(100 kbps...25 Mbps)
Polarity and Threshold Selection
Figure 12. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
Copyright © 2014–2015, Texas Instruments Incorporated
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ISO7310C, ISO7310FC
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www.ti.com.cn
8.3 Feature Description
PRODUCT
ISO7310C
ISO7310FC
RATED ISOLATION
MAX DATA RATE
DEFAULT OUTPUT
High
Low
(1)
3000 VRMS / 4242 VPK
25 Mbps
(1) See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
L(I02)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
400
13
mm
V
Tracking resistance (comparative
tracking index)
CTI
DTI
DIN EN 60112 (VDE 0303-11); IEC 60112
Distance through the insulation
Minimum internal gap (internal
clearance)
µm
VIO = 500 V, TA = 25°C
>1012
>1011
Ω
Ω
Isolation resistance, input to
output(1)
RIO
VIO = 500 V, 100°C ≤ TA ≤ 125°C
Isolation capacitance, input to
output(1)
Input capacitance(2)
CIO
CI
VIO = 0.4 sin (2πft), f = 1 MHz
0.5
1.6
pF
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
12
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
VIOWM
VIORM
Maximum isolation working voltage
400
VRMS
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566
VPK
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
680
Partial discharge < 5 pC
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
906
VPK
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
Maximum transient overvoltage per
DIN V VDE V 0884-10
VIOTM
4242
6000
VPK
VPK
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 7800 VPK (qualification)
VIOSM
VTEST = VISO = 3000 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100%
production)
VISO
Withstand isolation voltage per UL 1577
3000
VRMS
RS
Insulation resistance
Pollution degree
VIO = 500 V at TS = 150°C
>109
2
Ω
(1) Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Installation classification
8.3.1.3 Regulatory Information
VDE
CSA
UL
CQC
Certified according to DIN V VDE Approved under CSA
Recognized under UL 1577
Component Recognition
Program
V 0884-10 (VDE V 0884-
Component Acceptance Notice
Certified according to GB4943.1-
2011
10):2006-12 and DIN EN 61010- 5A, IEC 60950-1, and IEC
1 (VDE 0411-1):2011-07
61010-1
400 VRMS Basic Insulation and
200 VRMS Reinforced Insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2;
300 VRMS Basic Insulation
working voltage per CSA
61010-1-12 and IEC 61010-1
3rd Ed.
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK
Maximum Surge Isolation
Voltage, 6000 VPK
;
Basic Insulation, Altitude ≤ 5000 m,
Tropical Climate, 250 VRMS
maximum working voltage
(1)
Single protection, 3000 VRMS
;
Maximum Repetitive Peak
Voltage, 566 VPK
Master contract number:
220991
Certificate number:
CQC15001121656
Certificate number: 40016131
File number: E181974
(1) Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
Copyright © 2014–2015, Texas Instruments Incorporated
13
ISO7310C, ISO7310FC
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8.3.1.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
190
290
150
UNIT
mA
R
θJA = 119.9 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
θJA = 119.9 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
Safety input, output, or supply
current
IS
R
TS
Maximum case temperature
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolut Maximun
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
350
VCC1 = VCC2 = 3.6 V
300
250
200
VCC1 = VCC2 = 5.5 V
150
100
50
0
0
50
100
Case Temperature (oC)
150
200
C004
Figure 13. θJC Thermal Derating Curve per DIN V VDE 0884-10
14
Copyright © 2014–2015, Texas Instruments Incorporated
ISO7310C, ISO7310FC
www.ti.com.cn
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
8.4 Device Functional Modes
Table 2. Function Table(1)
OUT
VCC1
VCC2
IN
ISO7310C
ISO7310FC
H
L
H
L
H
L
PU
PU
Open
X
H(2)
H(2)
L(3)
L(3)
PD
X
PU
PD
X
Undetermined
Undetermined
(1) PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (ISO7310C)
VCC1
VCC1
VCC1
VCC1
5 PA
500 Q
IN
Output
VCC2
40 Q
OUT
Input (ISO7310FC)
VCC1
VCC1
VCC1
500 Q
IN
5 PA
Figure 14. Device I/O Schematics
Copyright © 2014–2015, Texas Instruments Incorporated
15
ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
www.ti.com.cn
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO7310x use single-ended TTL-logic switching technology. The supply voltage range is from 3 V to 5.5 V for
both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (i.e. μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
ISO7310 can be used with Texas Instruments’ microcontroller, CAN transceiver, transformer driver, and low-
dropout voltage regulator to create an Isolated CAN Interface as shown in Figure 15.
VS
10 ꢀF
3.3V
2
MBR0520L
Vcc
1:2.2
ISO 5V
10ꢀF
3
1
1
5
2
D2
D1
IN
OUT
TPS76350
SN6501
10ꢀF 0.1ꢀF
3
EN
GND
MBR0520L
GND
GND
5
4
ISO-BARRIER
0.1ꢀF
5,7
4
(See Note 1)
GND2
GND1
3
0.1ꢀF
6
8
2
OUT ISO7310 IN
VCC
S
8
10ꢁ (opt)
10ꢁ (opt)
1,3
4
1
VCC2
0.1ꢀF
VCC1
0.1ꢀF
RXD
CANH
40 12(1)
RST VDD VDDA VBAT
3
37
7
6
9(1)
30
31
7
SN65HVD1050
TXD
VDDC
OSC0
OSC1
LDO
25
26
CANL
CAN0Rx
STELLARIS
0.1ꢀF
VCC1
IN
GND
2
Vref
5
0.1ꢀF
VCC2
LM3S5Y36
CAN0Tx
GND GNDA WAKE
10(1)
32
SM712
6MHz
1,3
2
8
6
OUT
ISO7310
18pF 18pF
GND1
GND2
4
0.1ꢀF
(See Note 1)
4
5,7
4.7nF/
2kV
(1) Multiple pins and capacitors omitted for clarity purpose.
Figure 15. Isolated CAN Interface
16
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ISO7310C, ISO7310FC
www.ti.com.cn
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
At VCC1 = VCC2 = 5 V
•
•
ICC1 = 0.30517 + (0.01983 x f)
ICC2 = 1.40021 + (0.02879 x f) + (0.0021 x f x CL)
At VCC1 = VCC2 = 3.3 V
•
•
ICC1 = 0.18133 + (0.01166 x f)
ICC2 = 1.053 + (0.01607 x f) + (0.001488 x f x CL)
ICC1 and ICC2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive
load measured in pF.
9.2.2 Detailed Design Procedure
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO7310x only need two external bypass capacitors to operate.
VCC1
VCC2
2 mm
max.
from
VCC2
2 mm
max.
from
VCC1
0.1mF
0.1mF
1
2
8
7
6
5
IN
INPUT
GND1
3
4
OUT
OUTPUT
GND2
Figure 16. Typical ISO7310 Circuit Hook-up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7310x
incorporate many chip-level design improvements for overall system robustness. Some of these improvements
include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
Copyright © 2014–2015, Texas Instruments Incorporated
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ISO7310C, ISO7310FC
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www.ti.com.cn
Typical Application (continued)
9.2.3 Application Performance Curves
Typical eye diagrams of ISO7310x below indicate very low jitter and wide open eye at the maximum data rate of
25 Mbps.
Figure 18. Eye Diagram at 25 Mbps, 3.3V and 25°C
Figure 17. Eye Diagram at 25 Mbps, 5V and 25°C
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 & VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0) .
18
Copyright © 2014–2015, Texas Instruments Incorporated
ISO7310C, ISO7310FC
www.ti.com.cn
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
11 Layout
11.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 19). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.3 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces , pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 19. Recommended Layer Stack
版权 © 2014–2015, Texas Instruments Incorporated
19
ISO7310C, ISO7310FC
ZHCSCO1D –JUNE 2014–REVISED APRIL 2015
www.ti.com.cn
12 器件和文档支持
12.1 商标
DeviceNet is a trademark of Texas Instruments.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
《隔离相关术语》，SLLA353
13 机械、封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2014–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7310CD
ISO7310CDR
ISO7310FCD
ISO7310FCDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7310C
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
7310C
7310FC
7310FC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7310CDR
ISO7310FCDR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7310CDR
ISO7310FCDR
SOIC
SOIC
D
D
8
8
2500
2500
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7310CD
D
D
SOIC
SOIC
8
8
75
75
505.46
505.46
6.76
6.76
3810
3810
4
4
ISO7310FCD
Pack Materials-Page 3
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