ISO7321CD [TI]
低功耗、双通道、1/1、25Mbps 数字隔离器 | D | 8 | -40 to 125;型号: | ISO7321CD |
厂家: | TEXAS INSTRUMENTS |
描述: | 低功耗、双通道、1/1、25Mbps 数字隔离器 | D | 8 | -40 to 125 |
文件: | 总24页 (文件大小:1535K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
ISO732x 耐用 EMC 低功耗双通道数字隔离器
1 特性
3 说明
1
•
•
•
•
信号传输速率:25Mbps
ISO732x 可提供符合 UL 标准的长达 1 分钟且高达
3000 VRMS 的电流隔离,以及符合 VDE 标准的 4242
PK 隔离。 这些器件具有两个隔离通道,其逻辑输入
输入时使用集成噪声滤波器
V
默认输出“高”和“低”选项
和输出缓冲器由二氧化硅 (SiO2) 绝缘隔栅分离开来。
ISO7320 的两个通道方向相同,而 ISO7321 的两个通
道方向相反。 如果出现输入功率或信号损失,则后缀
为“F”的器件默认输出“低”电平,后缀没有“F”的器件则
默认输出“高”电平。 更多详细信息,请参见器件功能模
式。 与隔离电源配合使用,这些器件可防止数据总线
或者其它电路上的噪声电流进入本地接地并且干扰或损
坏敏感电路。 ISO732x 已针对恶劣环境集成了噪声滤
波器,在此类环境下,器件的输入引脚上可能会出现短
噪音脉冲。 ISO732x 具有晶体管晶体管逻辑电路
(TTL) 输入阈值,工作电压范围为 3V 到 5.5V。 凭借
创新的芯片设计和布线技术,ISO732x 的电磁兼容性
得到了显著增强,从而可确保提供系统级 ESD、EFT
和浪涌保护并符合辐射标准。
低功耗:每通道的 ICC 典型值(1Mbps时):
–
ISO7320:1.2mA(5V 电源供电时),
0.9mA(3.3V 电源供电时)
–
ISO7321:1.7mA(5V 电源供电时),
1.2mA(3.3V 电源供电时)
•
低传播延迟:典型值 33ns
(5V 电源供电时)
•
•
•
3.3V 和 5V 电平转换
宽温度范围:-40°C 至 125°C
65KV/μs 瞬态抗扰度,
典型值(5V 电源供电时)
•
优异的电磁兼容性 (EMC)
–
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及
抗浪涌保护
–
低辐射
器件信息(1)
•
•
•
•
隔离隔栅寿命:> 25 年
可由 3.3V 和 5V 电压供电
窄体小尺寸集成电路 (SOIC)-8 封装
安全及管理批准:
器件型号
ISO7320C
ISO7320FC
ISO7321C
ISO7321FC
封装
封装尺寸(标称值)
SOIC (8)
4.90mm x 3.91mm
–
–
–
符合 DIN V VDE V 0884-10 和 DIN EN 61010-
1 标准的 4242 VPK 隔离中的 4242 VPK 部分
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。
部分增加了脚注。
符合 UL 1577 标准且长达 1 分钟的 3000VRMS
隔离
CSA 组件接受通知 5A,IEC 60950-1、IEC
60601-1 和 IEC 61010-1 标准中 CSA 组件接受
列表项的“(审批正在审理中)”
简化电路原理图
VCCO
VCCI
–
通过 GB4943.1-2011 CQC 认证
Isolation
Capacitor
2 应用
INx
OUTx
•
在下列应用中的光电耦合器替代产品:
–
工业用 FieldBus
–
–
–
ProfiBus
GNDI
GNDO
ModBus
(1)
(2)
V
CCI 和 GNDI 分别是输入通道的电源和接地
连接。
CCO 和 GNDO 分别是输出通道的电源和接
地连接。
DeviceNet™ 数据总线
V
–
–
–
–
伺服控制接口
电机控制
电源
电池组
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEK8
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
Applications and Implementation ...................... 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics, 5 V ................................... 5
6.6 Electrical Characteristics, 3.3 V ................................ 5
6.7 Switching Characteristics, 5 V .................................. 6
6.8 Switching Characteristics, 3.3 V ............................... 6
6.9 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
9
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 PCB Material......................................................... 17
11.2 Layout Guidelines ................................................. 17
11.3 Layout Example .................................................... 17
12 器件和文档支持 ..................................................... 18
12.1 相关链接................................................................ 18
12.2 商标....................................................................... 18
12.3 静电放电警告......................................................... 18
12.4 术语表 ................................................................... 18
13 机械、封装和可订购信息....................................... 18
7
8
4 修订历史记录
Changes from Revision B (April 2015) to Revision C
Page
•
•
•
•
•
•
•
已添加“和 DINEN 61010-1 标准”至特性 ................................................................................................................................ 1
已删除特性 ............................................................................................................................................................................. 1
Changed From: VCC1 To: VCCI in Figure 11 ........................................................................................................................... 9
Changed From: VCC1 To: VCCI and From: VCC2 To: VCCO in Figure 13 .................................................................................. 9
Deleted IEC from the section title: Insulation and Safety-Related Specifications for D-8 Package .................................... 11
Changed the CTI Test Conditions in Insulation and Safety-Related Specifications for D-8 Package ................................ 11
Changed VISO Test Condition in the Insulation Characteristics table ................................................................................... 12
Changes from Revision A (March 2015) to Revision B
Page
•
将器件状态从:产品预览改为:量产 ...................................................................................................................................... 1
Changes from Original (January 2015) to Revision A
Page
•
•
从仅首页更改为完整数据表。 ................................................................................................................................................ 1
将 VCC1 更改为 VCCI、VCC2 更改为 VCCO、GND1 更改为 GNDI、GND2 更改为 GND0,并在简化电路原理图..................... 1
2
Copyright © 2015, Texas Instruments Incorporated
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
www.ti.com.cn
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
5 Pin Configuration and Functions
ISO7320
D PACKAGE
(TOP VIEW)
ISO7321
D PACKAGE
(TOP VIEW)
VCC1
VCC2
8
7
6
5
1
2
3
4
VCC1
VCC2
8
7
6
5
1
2
3
4
INA
INB
OUTA
OUTB
GND2
OUTA
INB
INA
OUTB
GND2
GND1
GND1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
ISO7320
ISO7321
INA
INB
2
3
4
5
7
6
1
8
7
3
4
5
2
6
1
8
I
I
Input, channel A
Input, channel B
GND1
GND2
OUTA
OUTB
VCC1
–
–
O
O
–
–
Ground connection for VCC1
Ground connection for VCC2
Output, channel A
Output, channel B
Power supply, VCC1
Power supply, VCC2
VCC2
Copyright © 2015, Texas Instruments Incorporated
3
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.5
–0.5
MAX UNIT
(2)
Supply voltage, VCC1 , VCC2
6
VCC+ 0.5(3)
±15
V
V
(2)
Voltage
INx, OUTx
Output current, IO
mA
°C
°C
Junction temperature, TJ
Storage temperature, Tstg
150
–65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3
TYP
MAX
UNIT
V
VCC1, VCC2 Supply voltage
IOH High-level output current
IOL
5.5
–4
mA
mA
V
Low-level output current
High-level input voltage
Low-level input voltage
Input pulse duration
Signaling rate
4
5.5
0.8
VIH
VIL
tui
2
0
V
40
0
ns
1 / tui
25
136
125
Mbps
°C
(1)
TJ
Junction temperature
Ambient temperature
TA
-40
25
°C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
D PACKAGE
(8) PINS
121
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJCtop
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
67.9
61.6
21.5
61.1
N/A
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
Maximum power dissipation by ISO7320
Maximum power dissipation by side-1 of ISO7320
Maximum power dissipation by side-2 of ISO7320
Maximum power dissipation by ISO7321
Maximum power dissipation by side-1 of ISO7321
Maximum power dissipation by side-2 of ISO7321
ψJB
RθJCbot
PD (ISO7320)
PD1 (ISO7320)
PD2 (ISO7320)
PD (ISO7321)
PD1 (ISO7321)
PD2 (ISO7321)
56
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 12.5 MHz 50% duty-cycle square
wave
15
mW
mW
41
67
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 12.5 MHz 50% duty-cycle square
wave
33.5
33.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
www.ti.com.cn
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
6.5 Electrical Characteristics, 5 V
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1)– 0.5
VCCO(1) – 0.1
TYP MAX
UNIT
IOH = –4 mA; see Figure 11
4.7
5
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 11
IOL = 4 mA; see Figure 11
IOL = 20 μA; see Figure 11
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
460
mV
μA
IN = VCC
10
IIL
Low-level input current
IN = 0 V
–10
25
μA
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 13.
65
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7320
ICC1
0.4
2
0.9
3.2
1.4
4.4
2.3
6.8
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
DC to 1 Mbps
ICC2
ICC1
0.8
3.2
1.4
4.9
Supply current for VCC1 and VCC2
10 Mbps
25 Mbps
CL = 15pF
CL = 15pF
mA
ICC2
ICC1
ICC2
ISO7321
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
1.7
2.8
ICC1 , ICC2
DC to 1 Mbps
Supply current for VCC1 and VCC2
mA
ICC1 , ICC2
ICC1 , ICC2
10 Mbps
25 Mbps
CL = 15pF
CL = 15pF
2.5
3.7
3.7
5.4
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
6.6 Electrical Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1)– 0.5
VCCO(1)– 0.1
TYP
3
MAX UNIT
IOH = –4 mA; see Figure 11
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 11
IOL = 4 mA; see Figure 11
IOL = 20 μA; see Figure 11
3.3
0.2
0
0.4
V
0.1
VOL
Low-level output voltage
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
450
mV
IN = VCC
10
μA
μA
IIL
Low-level input current
IN = 0 V
-10
25
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 13
50
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7320
ICC1
0.2
1.5
0.5
2.2
0.9
3.3
0.5
2.5
0.8
3.2
1.4
4.7
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
DC to 1 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
10 Mbps
25 Mbps
CL = 15pF
CL = 15pF
mA
ICC2
ICC1
ICC2
ISO7321
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
ICC1 , ICC2
DC to 1 Mbps
1.2
2
Supply current for VCC1 and VCC2
mA
ICC1 , ICC2
ICC1 , ICC2
10 Mbps
25 Mbps
CL = 15pF
CL = 15pF
1.7
2.5
2.5
3.6
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
Copyright © 2015, Texas Instruments Incorporated
5
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
www.ti.com.cn
6.7 Switching Characteristics, 5 V
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
Pulse width distortion |tPHL – tPLH
20
33
57
4
ns
ns
See Figure 11
|
ISO7320
ISO7321
2
(2)
tsk(o)
Channel-to-channel output skew time
ns
17
23
(3)
tsk(pp)
Part-to-part skew time
ns
ns
ns
μs
tr
Output signal rise time
2.4
2.1
7.5
See Figure 11
See Figure 12
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.8 Switching Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT3
tPLH, tPHL
PWD(1)
Propagation delay time
Pulse width distortion |tPHL – tPLH
22
37
66
3
ns
ns
See Figure 11
|
ISO7320
ISO7321
3
(2)
tsk(o)
Channel-to-channel output skew time
ns
16
28
(3)
tsk(pp)
Part-to-part skew time
ns
ns
ns
μs
tr
Output signal rise time
3.1
2.6
7.4
See Figure 11
See Figure 12
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6
Copyright © 2015, Texas Instruments Incorporated
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
www.ti.com.cn
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
6.9 Typical Characteristics
7
4
3.5
3
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
6
5
2.5
2
4
3
2
1
0
1.5
1
0.5
0
0
5
10
15
20
25
30
0
0
0
5
10
15
20
25
30
Data Rate (Mbps)
Data Rate (Mbps)
D001
D002
TA = 25°C
CL = 15 pF
TA = 25°C
No Load
Figure 1. ISO7320 Supply Current vs Data Rate
Figure 2. ISO7320 Supply Current vs Data Rate
4
3
2.5
2
3.5
3
2.5
2
1.5
1
1.5
1
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
0.5
0
0.5
0
0
5
10
15
20
25
30
5
10
15
20
25
30
Data Rate (Mbps)
Data Rate (Mbps)
D003
D004
TA = 25°C
CL = 15 pF
TA = 25°C
No Load
Figure 3. ISO7321 Supply Current vs Data Rate
Figure 4. ISO7321 Supply Current vs Data Rate
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC at 3.3 V
VCC at 5 V
VCC at 3.3 V
VCC at 5 V
-15
-10
-5
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
D005
D006
TA = 25°C
TA = 25°C
Figure 5. High-Level Output Voltage vs High-Level Output
Current
Figure 6. :Low-Level Output Voltage vs Low-Level Output
Current
Copyright © 2015, Texas Instruments Incorporated
7
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
www.ti.com.cn
Typical Characteristics (continued)
2.48
43
41
39
37
35
33
31
29
27
25
VCC Rising
VCC Falling
2.46
2.44
2.42
2.4
2.38
2.36
2.34
tPHL at 3.3 V
tPLH at 5 V
tPLH at 3.3 V
tPHL at 5 V
-50
0
50
100
150
-40
-5
30
65
100
135
Free-Air Temperature (qC)
Free-Air Temperature (qC)
D007
D008
Figure 7. Power Supply Under Voltage Threshold vs Free-
Air Temperature
Figure 8. Propagation Delay Time vs Free-Air Temperature
160
140
120
100
80
29
27
25
23
21
19
60
40
17
20
0
Output Jitter at 3.3 V
Output Jitter at 5 V
tGS at 3.3 V
tGS at 5 V
15
-40
-5
30
65
100
135
0
5
10
15
20
25
Free-Air Temperature (qC)
Data Rate (Mbps)
D009
D010
Figure 9. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 10. Peak-to-Peak Output Jitter vs Data Rate
8
Copyright © 2015, Texas Instruments Incorporated
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
www.ti.com.cn
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
7 Parameter Measurement Information
VCCI
VI
50%
50%
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator(1)
(2)
50 W
VI
CL
VOH
VOL
90%
10%
50%
50%
VO
tr
tf
(1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms
V
I
V
V
CC
CC
2.7 V
V
I
0 V
V
IN
OUT
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
t
V
fs
O
OH
fs high
fs low
50%
V
O
C
L
V
OL
NOTE A
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 μF 1ꢀ
C = 0.1 μF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL
Note A
VOH or VOL
–
GNDI
GNDO
–
+
VCM
(1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Common-Mode Transient Immunity Test Circuit
Copyright © 2015, Texas Instruments Incorporated
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ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
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8 Detailed Description
8.1 Overview
The isolator in Figure 14 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitioned from
0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic
(DCL) at the output of the HF channel comparator measures the durations between signal transients. If the
duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency
signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Isolation Barrier
OSC
Low ± Frequency
Channel
PWM
VREF
LPF
(DC...100 kbps)
0
1
Polarity and
Threshold Selection
OUT
IN
S
High ± Frequency
Channel
DCL
VREF
(100 kbps...25 Mbps)
Polarity and Threshold Selection
Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
10
Copyright © 2015, Texas Instruments Incorporated
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ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
8.3 Feature Description
PRODUCT
ISO7320C
ISO7320FC
ISO7321C
ISO7321FC
CHANNEL DIRECTION
RATED ISOLATION
MAX DATA RATE DEFAULT OUTPUT
High
Same
Low
(1)
3000 VRMS / 4242 VPK
25 Mbps
High
Opposite
Low
(1) See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
L(I02)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
400
13
mm
V
Tracking resistance (comparative
tracking index)
CTI
DTI
DIN EN 60112 (VDE 0303-11); IEC 60112
Distance through insulation
Minimum internal gap (internal
clearance)
µm
VIO = 500 V, TA = 25°C
1012
1011
Ω
Ω
Isolation resistance, input to
output(1)
RIO
VIO = 500 V, 100°C ≤ TA ≤ 125°C
Isolation capacitance, input to
output(1)
Input capacitance(2)
CIO
CI
VIO = 0.4 sin (2πft), f = 1 MHz
1.5
1.8
pF
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
Copyright © 2015, Texas Instruments Incorporated
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
VIOWM
VIORM
Maximum isolation working voltage
400
VRMS
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566
VPK
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
906
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
VPK
Partial Discharge < 5 pC
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
Maximum transient overvoltage per
DIN V VDE V 0884-10
VIOTM
4242
6000
VPK
VPK
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 7800 VPK (qualification)
VIOSM
VTEST = VISO = 3000 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100%
production)
VISO
Withstand isolation voltage per UL 1577
3000
VRMS
RS
Insulation resistance
Pollution degree
VIO = 500 V at TS
>109
2
Ω
(1) Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Installation classification
8.3.1.3 Regulatory Information
VDE
CSA
UL
CQC
Approved under CSA
Certified according to DIN V VDE
V 0884-10 (VDE V 0884-
10):2006-12
Recognized under UL 1577
Component Recognition
Program
Component Acceptance Notice
5A, IEC 60950-1, and IEC
61010-1
Certified according to GB4943.1-
2011
400 VRMS Basic Insulation and
200 VRMS Reinforced Insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2;
300 VRMS Basic Insulation
working voltage per CSA
61010-1-12 and IEC 61010-1
3rd Ed.
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK
Maximum Surge Isolation
Voltage, 6000 VPK
Maximum Repetitive Peak
Voltage, 566 VPK
Basic Insulation, Altitude ≤ 5000 m,
Tropical Climate, 250 VRMS
maximum working voltage
(1)
Single protection, 3000 VRMS
File number: E181974
Master contract number:
220991
Certificate number:
CQC15001121656
Certificate number: 40016131
(1) Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
12
Copyright © 2015, Texas Instruments Incorporated
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ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
8.3.1.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
188
287
150
UNIT
mA
R
θJA = 121 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
θJA = 121 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
Safety input, output, or supply
current
IS
R
TS
Maximum case temperature
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolut Maximun
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
400
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
300
200
100
0
0
50
100
150
200
Case Temperature (qC)
D011
Figure 15. θJC Thermal Derating Curve per DIN V VDE V 0884-10
Copyright © 2015, Texas Instruments Incorporated
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8.4 Device Functional Modes
Table 2. Function Table(1)
OUTA, OUTB
ISO7320C, ISO7321C ISO7320FC, ISO7321FC
VCCI
VCCO
INA, INB
H
L
H
H
PU
PU
L
H(2)
H(2)
L
L(3)
L(3)
Open
X
PD
X
PU
PD
X
Undetermined
Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H =
High level; L = Low level; Open = Not connected
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (Devices Without Suffix F)
Input (Devices With Suffix F)
V
V
CCI
V
V
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
5 mA
500 W
500 W
INx
INx
5 mA
Output
V
CCO
40 W
OUTx
Figure 16. Device I/O Schematics
14
Copyright © 2015, Texas Instruments Incorporated
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ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO732x utilize single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for
both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (i.e. μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
ISO7321 can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,
transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.
VCC1
VCC2
ISO7321
Figure 17. Typical ISO7321 Application Circuit
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ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
www.ti.com.cn
Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
ISO7320:
ISO7321:
At VCC1 = VCC2 = 5 V
At VCC1 = VCC2 = 5 V
•
•
ICC1 = 0.3838 + (0.0431 x f)
ICC2 = 2.74567 + (0.08433 x f) + (0.01 x f x CL)
•
ICC1 and ICC2 = 1.5877 + (0.066 x f) + (0.00123 x f x CL)
At VCC1 = VCC2 = 3.3 V
At VCC1 = VCC2 = 3.3 V
•
•
ICC1 = 0.2394 + (0.02355 x f)
•
ICC1 and ICC2 = 1.187572 + (0.019399 x f) + (0.0019029 x
f x CL)
ICC2 = 2.10681 + (0.04374 x f) + (0.007045 x f x CL)
ICC1 and ICC2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive
load measured in pF.
9.2.2 Detailed Design Procedure
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO732x
incorporate many chip-level design improvements for overall system robustness. Some of these improvements
include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
9.2.3 Application Performance Curves
Typical eye diagrams of ISO732x below indicate low jitter and wide open eye at the maximum data rate of 25
Mbps.
Figure 19. Eye Diagram at 25 Mbps, 3.3 V and 25°C
Figure 18. Eye Diagram at 25 Mbps, 5 V and 25°C
16
Copyright © 2015, Texas Instruments Incorporated
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
www.ti.com.cn
ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 & VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0) .
11 Layout
11.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.3 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces , pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 20. Recommended Layer Stack
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17
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ZHCSDI8C –JANUARY 2015–REVISED APRIL 2015
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12 器件和文档支持
12.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件,并且可以快速访问样片或购买
链接。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
请单击此处
ISO7320C
ISO7320FC
ISO7321C
ISO7321FC
12.2 商标
DeviceNet is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
《隔离相关术语》,SLLA353
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
18
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7320CD
ISO7320CDR
ISO7320FCD
ISO7320FCDR
ISO7321CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7320C
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
7320C
7320FC
7320FC
7321C
ISO7321CDR
ISO7321FCD
ISO7321FCDR
7321C
7321FC
7321FC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7320CDR
ISO7320FCDR
ISO7321CDR
ISO7321FCDR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7320CDR
ISO7320FCDR
ISO7321CDR
ISO7321FCDR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7320CD
ISO7320FCD
ISO7321CD
ISO7321FCD
D
D
D
D
SOIC
SOIC
SOIC
SOIC
8
8
8
8
75
75
75
75
505.46
505.46
505.46
505.46
6.76
6.76
6.76
6.76
3810
3810
3810
3810
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