ISO7321FCQDQ1 [TI]
汽车类低功耗、双通道、1/1、25Mbps 数字隔离器 | D | 8 | -40 to 125;
| 型号： | ISO7321FCQDQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类低功耗、双通道、1/1、25Mbps 数字隔离器 | D | 8 | -40 to 125 |
| 文件： | 总28页 (文件大小：941K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7320-Q1
ISO7321-Q1
ZHCSED4 –NOVEMBER 2015
ISO732x-Q1 耐用 EMC 低功耗双通道数字隔离器
1 特性
–
–
电源
电池组
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
3 说明
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
ISO732x-Q1 系列器件可提供符合 UL 1577 标准的长
达 1 分钟且高达 3000 VRMS 的电流隔离，以及符合
VDE V 0884-10 标准的 4242 VPK 隔离。 这些器件具
有两个隔离通道，其逻辑输入和输出缓冲器由二氧化硅
(SiO2) 绝缘隔栅分离开来。
–
–
器件人体模型 (HBM) 分类等级 3A
器件充电器件模型 (CDM) 分类等级 C6
•
•
•
•
信号传输速率：25Mbps
输入时使用集成噪声滤波器
默认输出高电平和低电平选项
低功耗：每通道的 ICC 典型值（1Mbps 时）：
ISO7320-Q1 的两个通道方向相同，而 ISO7321-Q1
的两个通道方向相反。 如果出现输入功率或信号损
失，默认输出低电平（器件的订购部件号带有后缀 F）
或高电平（器件的订购部件号不带后缀 F）。 更多信
息，请参见Device Functional Modes。 与隔离式电源
一起使用时，这些器件有助于防止数据总线或者其他电
路上的噪声电流进入本地接地或对敏感电路造成干扰或
损坏。 ISO734x-Q1 系列器件已针对恶劣工业环境集
成了噪声滤波器。在此类环境下，器件的输入引脚上可
能会出现短噪声脉冲。 ISO732x-Q1 系列器件具有晶
体管-晶体管逻辑电路 (TTL) 输入阈值，工作电压范围
为 3V 到 5.5V。
–
ISO7320-Q1：1.2mA（5V 电源），
0.9mA（3.3V 电源）
–
ISO7321-Q1：1.7mA（5V 电源），
1.2mA（3.3V 电源）
•
低传播延迟：典型值 33ns
（5V 电源）
•
•
3.3V 和 5V 电平转换
65kV/μs 瞬态抗扰度，
典型值（5V 电源）
•
优异的电磁兼容性 (EMC)
–
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及
抗浪涌保护
凭借创新的芯片设计和布线技术，ISO732x-Q1 系列器
件的电磁兼容性得到了显著增强，可确保提供系统级
ESD、EFT 和浪涌保护并符合辐射标准。
–
低辐射
•
•
•
•
隔离隔栅寿命：> 25 年
由 3.3V 和 5V 电源供电
窄体小尺寸集成电路 (SOIC)-8 封装
安全及管理批准:
器件信息(1)
器件型号
ISO7320-Q1
ISO7321-Q1
封装
封装尺寸（标称值）
SOIC (8)
4.90mm x 3.91mm
–
–
–
符合 DIN V VDE V 0884-10 和 DIN EN 61010-
1 标准的 4242 VPK隔离中的 4242 VPK 部分
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
部分增加了脚注。
符合 UL 1577 标准且长达 1 分钟的 3000 VRMS
隔离
CSA 组件接受通知 5A，IEC 60950-1、IEC
60601-1 和 IEC 61010-1 标准中 CSA 组件接受
列表项的“（审批正在审理中）”
简化电路原理图
V
V
CCI
CCO
Isolation
Capacitor
–
已通过符合 GB4943.1-2011 的 CQC 认证
INx
OUTx
2 应用
•
在下列使用中的光电耦合器替代产品：
–
工业用 FieldBus
GNDI
GNDO
V
CCI 和 GNDI 分别是输入通道的电源和接地
连接。
CCO 和 GNDO 分别是输出通道的电源和接
地连接。
–
–
–
ProfiBus
ModBus
V
DeviceNet™ 数据总线
–
–
伺服控制接口
电机控制
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSER4
ISO7320-Q1
ISO7321-Q1
ZHCSED4 –NOVEMBER 2015
www.ti.com.cn
目录
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics—5-V Supply ..................... 5
6.6 Supply Current Characteristics—5-V Supply............ 5
6.7 Electrical Characteristics—3.3 V............................... 6
6.8 Supply Current Characteristics—3.3-V Supply......... 6
6.9 Power Dissipation Characteristics ............................ 6
6.10 Switching Characteristics—5-V Supply................... 7
6.11 Switching Characteristics—3.3-V Supply................ 7
6.12 Typical Characteristics............................................ 8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 文档支持................................................................ 20
12.2 相关链接................................................................ 20
12.3 社区资源................................................................ 20
12.4 商标....................................................................... 20
12.5 静电放电警告......................................................... 20
12.6 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 21
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 11 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
ISO7320-Q1
ISO7321-Q1
www.ti.com.cn
ZHCSED4 –NOVEMBER 2015
5 Pin Configuration and Functions
ISO7320-Q1 D Package
8-Pin SOIC
ISO7321-Q1 D Package
8-Pin SOIC
Top View
Top View
VCC1
VCC2
VCC1
VCC2
8
7
6
5
8
1
2
3
4
1
2
3
4
7
6
5
INA
INB
OUTA
OUTB
GND2
OUTA
INB
INA
OUTB
GND2
GND1
GND1
Pin Functions
PIN
NO.
ISO7320-Q1 ISO7321-Q1
I/O
DESCRIPTION
NAME
INA
INB
2
3
4
5
7
6
1
8
7
3
4
5
2
6
1
8
I
Input, channel A
I
Input, channel B
GND1
GND2
OUTA
OUTB
VCC1
—
—
O
O
—
—
Ground connection for VCC1
Ground connection for VCC2
Output, channel A
Output, channel B
Power supply, VCC1
Power supply, VCC2
VCC2
Copyright © 2015, Texas Instruments Incorporated
3
ISO7320-Q1
ISO7321-Q1
ZHCSED4 –NOVEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
MAX
UNIT
V
VCC
Supply voltage(2)
Voltage(2)
VCC1 , VCC2
INx, OUTx
6
VCC+ 0.5(3)
±15
V
IO
Output current
mA
°C
TJ
Junction temperature
Storage temperature
150
Tstg
–65
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
V
VCC1, VCC2 Supply voltage,
IOH High-level output current
IOL
5.5
–4
mA
mA
V
Low-level output current
High-level input voltage
Low-level input voltage
Input pulse duration
Signaling rate
4
5.5
0.8
VIH
VIL
tui
2
0
V
40
0
ns
1 / tui
25
136
125
Mbps
°C
(1)
TJ
Junction temperature
Ambient temperature
TA
-40
25
°C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
ISO732x-Q1
D (SOIC)
8 PINS
121
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
67.9
61.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
21.5
ψJB
61.1
RθJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
ISO7320-Q1
ISO7321-Q1
www.ti.com.cn
ZHCSED4 –NOVEMBER 2015
6.5 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1)– 0.5
VCCO(1) – 0.1
TYP MAX
UNIT
IOH = –4 mA; see Figure 11
4.7
5
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 11
IOL = 4 mA; see Figure 11
IOL = 20 μA; see Figure 11
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
460
mV
μA
IN = VCC
10
IIL
Low-level input current
IN = 0 V
–10
25
μA
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 13.
65
kV/μs
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
6.6 Supply Current Characteristics—5-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over
recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ISO7320-Q1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.4
2
0.9
3.2
1.4
4.4
2.3
6.8
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
DC to 1 Mbps
10 Mbps
0.8
3.2
1.4
4.9
Supply current for VCC1 and VCC2
CL = 15 pF
CL = 15 pF
mA
25 Mbps
ISO7321-Q1
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
DC to 1 Mbps
ICC1 , ICC2
1.7
2.8
Supply current for VCC1 and VCC2
mA
10 Mbps
25 Mbps
CL = 15 pF
CL = 15 pF
ICC1 , ICC2
ICC1 , ICC2
2.5
3.7
3.7
5.4
Copyright © 2015, Texas Instruments Incorporated
5
ISO7320-Q1
ISO7321-Q1
ZHCSED4 –NOVEMBER 2015
www.ti.com.cn
6.7 Electrical Characteristics—3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1)– 0.5
VCCO(1)– 0.1
TYP
3
MAX UNIT
IOH = –4 mA; see Figure 11
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 11
IOL = 4 mA; see Figure 11
IOL = 20 μA; see Figure 11
3.3
0.2
0
0.4
V
0.1
VOL
Low-level output voltage
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
450
mV
IN = VCC
10
μA
μA
IIL
Low-level input current
IN = 0 V
–10
25
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 13
50
kV/μs
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
6.8 Supply Current Characteristics—3.3-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over
recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ISO7320-Q1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.2
1.5
0.5
2.2
0.9
3.3
0.5
2.5
0.8
3.2
1.4
4.7
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
DC to 1 Mbps
10 Mbps
Supply current for VCC1 and VCC2
CL = 15 pF
CL = 15 pF
mA
25 Mbps
ISO7321-Q1
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
DC to 1 Mbps
ICC1 , ICC2
1.2
2
Supply current for VCC1 and VCC2
mA
10 Mbps
25 Mbps
CL = 15 pF
CL = 15 pF
ICC1 , ICC2
ICC1 , ICC2
1.7
2.5
2.5
3.6
6.9 Power Dissipation Characteristics
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 12.5 MHz 50% duty-cycle square wave (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
56
UNIT
PD
Maximum power dissipation by ISO7320-Q1
Maximum power dissipation by side-1 of ISO7320-Q1
Maximum power dissipation by side-2 of ISO7320-Q1
Maximum power dissipation by ISO7321-Q1
Maximum power dissipation by side-1 of ISO7321-Q1
Maximum power dissipation by side-2 of ISO7321-Q1
mW
mW
mW
mW
mW
mW
PD1
PD2
PD
15
41
67
PD1
PD2
33.5
33.5
6
Copyright © 2015, Texas Instruments Incorporated
ISO7320-Q1
ISO7321-Q1
www.ti.com.cn
ZHCSED4 –NOVEMBER 2015
6.10 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
MAX
57
4
UNIT
ns
tPLH, tPHL
PWD(1)
See Figure 11
20
33
|
See Figure 11
ns
ISO7320-Q1
ISO7321-Q1
2
(2)
tsk(o)
Channel-to-channel output skew time
ns
17
23
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
ns
ns
ns
μs
tr
See Figure 11
See Figure 11
See Figure 12
2.4
2.1
7.5
tf
tfs
Fail-safe output delay time from input power loss
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
MAX
66
3
UNIT
ns
tPLH, tPHL
PWD(1)
See Figure 11
22
37
|
See Figure 11
ns
ISO7320-Q1
ISO7321-Q1
3
(2)
tsk(o)
Channel-to-channel output skew time
ns
16
28
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
ns
ns
ns
μs
tr
See Figure 11
See Figure 11
See Figure 12
3.1
2.6
7.4
tf
tfs
Fail-safe output delay time from input power loss
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2015, Texas Instruments Incorporated
7
ISO7320-Q1
ISO7321-Q1
ZHCSED4 –NOVEMBER 2015
www.ti.com.cn
6.12 Typical Characteristics
7
4
3.5
3
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
6
5
2.5
2
4
3
2
1
0
1.5
1
0.5
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Data Rate (Mbps)
Data Rate (Mbps)
D001
D002
TA = 25°C
CL = 15 pF
TA = 25°C
No Load
Figure 1. ISO7320-Q1 Supply Current vs Data Rate
Figure 2. ISO7320-Q1 Supply Current vs Data Rate
4
3
2.5
2
3.5
3
2.5
2
1.5
1
1.5
1
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
0.5
0
0.5
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Data Rate (Mbps)
Data Rate (Mbps)
D003
D004
TA = 25°C
CL = 15 pF
TA = 25°C
No Load
Figure 3. ISO7321-Q1 Supply Current vs Data Rate
Figure 4. ISO7321-Q1 Supply Current vs Data Rate
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC at 3.3 V
VCC at 5 V
VCC at 3.3 V
VCC at 5 V
-15
-10
-5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
D005
D006
TA = 25°C
TA = 25°C
Figure 5. High-Level Output Voltage vs High-Level Output
Current
Figure 6. Low-Level Output Voltage vs Low-Level Output
Current
8
Copyright © 2015, Texas Instruments Incorporated
ISO7320-Q1
ISO7321-Q1
www.ti.com.cn
ZHCSED4 –NOVEMBER 2015
Typical Characteristics (continued)
2.48
43
41
39
37
35
33
31
29
27
25
VCC Rising
VCC Falling
2.46
2.44
2.42
2.4
2.38
2.36
2.34
tPHL at 3.3 V
tPLH at 5 V
tPLH at 3.3 V
tPHL at 5 V
-50
0
50
100
150
-40
-5
30
65
100
135
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D007
D008
Figure 7. Power Supply Under Voltage Threshold vs Free-
Air Temperature
Figure 8. Propagation Delay Time vs Free-Air Temperature
160
140
120
100
80
29
27
25
23
21
19
60
40
17
20
0
Output Jitter at 3.3 V
Output Jitter at 5 V
tGS at 3.3 V
tGS at 5 V
15
-40
-5
30
65
100
135
0
5
10
15
20
25
Free-Air Temperature (èC)
Data Rate (Mbps)
D009
D010
Figure 9. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 10. Peak-to-Peak Output Jitter vs Data Rate
Copyright © 2015, Texas Instruments Incorporated
9
ISO7320-Q1
ISO7321-Q1
ZHCSED4 –NOVEMBER 2015
www.ti.com.cn
7 Parameter Measurement Information
VCCI
VI
50%
50%
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator(1)
(2)
50 W
VI
CL
VOH
VOL
90%
10%
50%
50%
VO
tr
tf
(1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCC
VCC
2.7 V
VI
0 V
VOH
IN
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
OUT
t
VO
fs
fs high
fs low
50%
VO
CL
See Note A
VOL
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 μF 1ꢀ
C = 0.1 μF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL
Note A
VOH or VOL
–
GNDI
GNDO
–
+
VCM
(1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Common-Mode Transient Immunity Test Circuit
10
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8 Detailed Description
8.1 Overview
The isolator in Figure 14 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitions from 0
to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL)
at the output of the HF channel comparator measures the durations between signal transients. If the duration
between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the
DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Lsolation .arrier
OSC
[ow t Crequency
/hannel
PWM
VREF
LPF
(5/ꢀꢀꢀ100 kbps)
0
1
ꢃolarity and
Çhreshold {election
OUT
IN
{
Iigh t Crequency
/hannel
DCL
VREF
(100 kbpsꢀꢀꢀ2ꢁ ꢂbps)
ꢃolarity and Çhreshold {election
Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is required to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
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8.3 Feature Description
ORDERABLE DEVICE
CHANNEL DIRECTION
RATED ISOLATION
MAX DATA RATE DEFAULT OUTPUT
ISO7320CQDQ1 and
ISO7320CQDRQ1
High
Same
ISO7320FCQDQ1 and
ISO7320FCQDRQ1
Low
(1)
3000 VRMS / 4242 VPK
25 Mbps
ISO7321CQDQ1 and
ISO7321CQDRQ1
High
Opposite
ISO7321FCQDQ1 and
ISO7321FCQDRQ1
Low
(1) See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
L(I02)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
400
13
mm
V
Tracking resistance (comparative
tracking index)
CTI
DTI
DIN EN 60112 (VDE 0303-11); IEC 60112
Distance through insulation
Minimum internal gap (internal
clearance)
µm
VIO = 500 V, TA = 25°C
1012
1011
Ω
Ω
Isolation resistance, input to
output(1)
RIO
VIO = 500 V, 100°C ≤ TA ≤ 125°C
Isolation capacitance, input to
output(1)
Input capacitance(2)
CIO
CI
VIO = 0.4 sin (2πft), f = 1 MHz
1.5
1.8
pF
pF
VI = VCC / 2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to
help increase these specifications.
12
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
VIOWM
VIORM
Maximum isolation working voltage
400
VRMS
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566
VPK
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
680
Partial discharge < 5 pC
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
906
VPK
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
Maximum transient overvoltage per
DIN V VDE V 0884-10
VIOTM
4242
6000
VPK
VPK
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 7800 VPK (qualification)
VIOSM
VTEST = VISO = 3000 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100%
production)
VISO
Withstand isolation voltage per UL 1577
3000
VRMS
RS
Insulation resistance
Pollution degree
VIO = 500 V at TS
>109
2
Ω
(1) Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Installation classification
8.3.1.3 Regulatory Information
VDE
CSA
UL
CQC
Approved under CSA
Certified according to DIN V VDE
V 0884-10 (VDE V 0884-
10):2006-12
Recognized under UL 1577
Component Recognition
Program
Component Acceptance Notice
5A, IEC 60950-1, and IEC
61010-1
Plan to certify according to
GB4943.1-2011
400 VRMS Basic Insulation and
200 VRMS Reinforced Insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2;
300 VRMS Basic Insulation
working voltage per CSA
61010-1-12 and IEC 61010-1
3rd Ed.
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK
Maximum Surge Isolation
Voltage, 6000 VPK
Maximum Repetitive Peak
Voltage, 566 VPK
Basic Insulation, Altitude ≤ 5000 m,
Tropical Climate, 250 VRMS
maximum working voltage
(1)
Single protection, 3000 VRMS
File number: E181974
Master contract number:
220991
Certificate number: 40016131
Certification Planned
(1) Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
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8.3.1.4 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
188
287
150
UNIT
mA
R
θJA = 121 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
θJA = 121 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
Safety input, output, or supply
current
IS
R
TS
Maximum safety temperature
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
400
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
300
200
100
0
0
50
100
150
200
Ambient Temperature (èC)
D011
Figure 15. Thermal Derating Curve per VDE
14
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO732x-Q1 family of devices.
Table 2. Function Table(1)
OUTA, OUTB
VCCI
VCCO
INA, INB
ISO732xCQDQ1 AND
ISO732xCQDRQ1
ISO732xFCQDQ1 AND
ISO732xFCQDRQ1
H
L
H
H
PU
PU
L
H(2)
H(2)
L
L(3)
L(3)
Open
X
PD
X
PU
PD
X
Undetermined
Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H =
High level; L = Low level; Open = Not connected
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (Devices Without Suffix F)
Input (Devices With Suffix F)
V
V
CCI
V
V
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
5 mA
500 W
500 W
INx
INx
5 mA
Output
V
CCO
40 W
OUTx
Figure 16. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO732x-Q1 family of devices uses single-ended TTL-logic switching technology. The supply voltage range
is from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that
because of the single-ended design structure, digital isolators do not conform to any specific interface standard
and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (essentially, μC or UART), and a data converter or a line transceiver, regardless of
the interface type or standard.
9.2 Typical Application
The ISO7321-Q1 device can be used with Texas Instruments' Piccolo™ microcontroller, CAN transceiver,
transformer driver, and voltage regulator to create an isolated CAN interface.
V
S
0.1 ꢀF
3.3 V
2
MBR0520L
1:1.33
3.3VISO
10 ꢀF
3
1
1
3
5
2
V
CC
D2
IN
OUT
TPS76333-Q1
SN6501-Q1
10 ꢀF 0.1 ꢀF
EN
GND
D1
GND
4, 5
10 ꢀF
MBR0520L
ISO Barrier
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
1
8
3
29,57
V
V
CC2
CC1
VCC
RS
8
V
DDIO
10 ꢁ (optional)
10 ꢁ (optional)
4
7
26
25
2
R
D
CANH
INA
CANRXA
OUTA
ISO7321-Q1
7
6
5
TMS320F28035PAGQ
3
SN65HVD231Q
OUTB
GND2
5
CANTXA
INB
1
6
CANL
Vref
GND1
V
SS
GND
2
4
6,28
SM712
4.7 nF /
2 kV
Multiple pins and discrete components omitted for clarity purpose.
Figure 17. Isolated CAN Interface
16
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
For the equations in this section, the following is true:
•
•
•
ICC1 and ICC2 are typical supply currents measured in mA
f is the data rate measured in Mbps
CL is the capacitive load measured in pF
9.2.1.1.1 ISO7320-Q1
At VCC1 = VCC2 = 5 V
ICC1 = 0.3838 + (0.0431 × f)
(1)
(2)
ICC2 = 2.74567 + (0.08433 × f) + (0.01 x f × CL)
At VCC1 = VCC2 = 3.3 V
ICC1 = 0.2394 + (0.02355 × f)
(3)
(4)
ICC2 = 2.10681 + (0.04374 × f) + (0.007045 × f × CL)
9.2.1.1.2 ISO7321-Q1
At VCC1 = VCC2 = 5 V
ICC1 and ICC2 = 1.5877 + (0.066 × f) + (0.00123 × f × CL)
(5)
(6)
At VCC1 = VCC2 = 3.3 V
ICC1 and ICC2 = 1.187572 + (0.019399 × f) + (0.0019029 × f × CL)
9.2.2 Detailed Design Procedure
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO732x-
Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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Typical Application (continued)
9.2.3 Application Curves
The following typical eye diagrams of the ISO732x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 25 Mbps.
Figure 19. Eye Diagram at 25 Mbps, 3.3 V and 25°C
Figure 18. Eye Diagram at 25 Mbps, 5 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-µF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
the SN6501-Q1 datasheet (SLLSEF3) .
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide, SLLA284.
18
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Layout Guidelines (continued)
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This type of PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 20. Recommended Layer Stack
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ISO7321-Q1
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
•
《数字隔离器设计指南》，SLLA284
《隔离相关术语》，SLLA353
《SN6501-Q1 用于隔离电源的变压器驱动器》，SLLSEF3
《SN65HVD231Q-Q1 3.3V CAN 收发器》，SGLS398
《TMS320F28035 Piccolo™ 微控制器》，SPRS584
《TPS76333-Q1 低功耗 150mA 低压降线性稳压器》，SGLS247
12.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文章
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
ISO7320-Q1
ISO7321-Q1
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
DeviceNet, Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
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13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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ISO7321-Q1
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
24
版权 © 2015, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7320CQDQ1
ISO7320CQDRQ1
ISO7320FCQDQ1
ISO7320FCQDRQ1
ISO7321CQDQ1
ISO7321CQDRQ1
ISO7321FCQDQ1
ISO7321FCQDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7320Q
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
7320Q
7320FQ
7320FQ
7321Q
7321Q
7321FQ
7321FQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
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do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
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flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
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