ISO7342CDWR [TI]
低功耗、四通道、2/2、25Mbps 数字隔离器 | DW | 16 | -40 to 125;
| 型号： | ISO7342CDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗、四通道、2/2、25Mbps 数字隔离器 | DW | 16 | -40 to 125 |
| 文件： | 总38页 (文件大小：1572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
ISO734x 耐用 EMC 低功耗四通道数字隔离器
1 特性
3 说明
1
•
信号传输速率：25Mbps删除了数据表标题中的删
除了数据表标题中的
ISO734x 系列器件可提供符合 UL 1577 标准的长达 1
分钟且高达 3000 VRMS 的电隔离，以及符合 VDE V
0884-10 标准的 4242 VPK 隔离。这些器件具有四个隔
离通道，后者由逻辑输入和输出缓冲器组成，并由二氧
化硅 (SiO2) 绝缘隔栅进行隔离。
•
•
•
输入时使用集成噪声滤波器
默认输出高电平和低电平选项
低功耗，每通道 ICC 典型值（1Mbps 时）：
–
–
–
ISO7340x：0.9mA（5V 电源）、
0.7mA（3.3V 电源）
ISO7340x 器件具有四个正向通道，ISO7341x 器件具
有三个正向通道和一个反向通道，ISO7342x 器件具有
两个正向通道和两个反向通道。如果出现输入功率或信
号损失，默认输出低（器件带有后缀 F）或高（器件不
带后缀 F）。有关更多详细信息，请参阅 器件功能模
式部分。
ISO7341x：1.2mA（5V 电源）、
0.9mA（3.3V 电源）
ISO7342x：1.3mA（5V 电源）、
0.9mA（3.3V 电源）
•
低传播延迟：典型值 31ns
（5V 电源）
器件信息(1)
•
•
•
•
3.3V 和 5V 电平转换
器件型号
ISO7340C
封装
封装尺寸
宽温度范围：-40°C 至 125°C
70KV/μs 瞬态抗扰度，典型值（5V 电源）
优异的电磁兼容性 (EMC)
ISO7340FC
ISO7341C
ISO7341FC
ISO7342C
ISO7342FC
SOIC (16)
10.30mm x 7.50mm
–
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及
抗浪涌保护
–
低辐射
•
•
•
由 3.3V 和 5V 电源供电
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
宽体小外形尺寸集成电路 (SOIC)-16 封装
安全相关认证：
简化电路原理图
–
–
–
–
4242 VPK 基本隔离，符合 DIN V VDE V 0884-
10 和 DIN EN 61010-1 标准
V
V
CCI
CCO
Isolation
Capacitor
符合 UL 1577 标准且长达 1 分钟的 3K VRMS 隔
离
INx
OUTx
ENx
CSA 组件验收通知 5A、IEC 60950-1 和 IEC
61010-1 终端设备标准
GNDI
GNDO
已通过 GB4943.1-2011 CQC 认证
V
CCI 和 GNDI 分别是输入通道的电源和接地
连接。
CCO 和 GNDO 分别是输出的电源和接地连
接。
2 应用
V
•
是下列应用中光耦合器的替代产品：
–
工业现场总线 (Fieldbus)
–
–
–
Profibus 现场总线
Modbus
DeviceNet 数据总线
–
–
–
–
伺服器控制接口
电机控制
电源
电池组
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEI6
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 5
Pin Configuration and Functions......................... 6
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 8
7.5 Power Ratings........................................................... 8
7.6 Insulation Specifications............................................ 9
7.7 Safety-Related Certifications................................... 10
7.8 Safety Limiting Values ............................................ 10
7.9 Electrical Characteristics—5-V Supply ................... 11
7.10 Supply Current Characteristics—5-V Supply........ 11
7.11 Electrical Characteristics—3.3-V Supply .............. 12
7.12 Supply Current Characteristics—3.3-V Supply..... 12
7.13 Switching Characteristics—5-V Supply................. 13
7.14 Switching Characteristics—3.3-V Supply.............. 13
7.15 Insulation Characteristics Curves ......................... 14
7.16 Typical Characteristics.......................................... 15
8
9
Parameter Measurement Information ................ 17
Detailed Description ............................................ 19
9.1 Overview ................................................................. 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 21
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application ................................................ 22
11 Power Supply Recommendations ..................... 26
12 Layout................................................................... 27
12.1 Layout Guidelines ................................................. 27
12.2 Layout Example .................................................... 27
13 器件和文档支持 ..................................................... 28
13.1 文档支持................................................................ 28
13.2 相关链接................................................................ 28
13.3 接收文档更新通知 ................................................. 28
13.4 社区资源................................................................ 28
13.5 商标....................................................................... 28
13.6 静电放电警告......................................................... 28
13.7 Glossary................................................................ 28
14 机械、封装和可订购信息....................................... 29
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision F (August 2016) to Revision G
Page
•
•
已删除 “增强型”....................................................................................................................................................................... 1
the production tested note for the UL VRMS value from the Safety-Related Certifications ................................................... 10
Changes from Revision E (April 2015) to Revision F
Page
•
•
•
Changed the minimum air gap (clearance) parameter (L(I01)) to the external clearance parameter.................................... 9
Changed the minimum external tracking (creepage) parameter (L(I02)) to the external creepage parameter...................... 9
Changed the typ value for the enable propagation delay, high impedance-to-high output parameter of the FC
devices and the typ value for the enable propagation delay, high impedance-to-low output parameter of the C
devices from 16 to 16000 in the Switching Characteristics—3.3-V Supply table ................................................................ 13
•
已添加 接收文档更新通知 部分............................................................................................................................................. 28
Changes from Revision D (March 2015) to Revision E
Page
•
•
•
•
•
•
•
•
删除了 中的“(VDE V0884-10):2006-12”和“(VDE 0411-1:2011-07)”特性 安全及管理批准： .................................................. 1
将“（等待审批）”从 的 CSA 组件验收列表项中删除特性 ....................................................................................................... 1
Deleted IEC from the section title: Insulation and Safety-Related Specifications for DW-16 Package ................................ 9
Changed the TEST Conditions of CTI in Insulation and Safety-Related Specifications for DW-16 Package........................ 9
Changed the Test Conditions of VISO in Insulation Characteristics ....................................................................................... 9
Changed column CSA in the Safety-Related Certifications table ....................................................................................... 10
Changed From: VCC1 To: VCCI in Switching Characteristics Test Circuit and Voltage Waveforms ..................................... 17
Changed From: VCC1 To: VCCI and From: VCC2 To: VCCO in Common-Mode Transient Immunity Test Circuit..................... 18
2
版权 © 2014–2017, Texas Instruments Incorporated
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
Changes from Revision C (December 2014) to Revision D
Page
•
•
•
•
更改了 中的 DIN V VDE 0884-10 编号特性 安全及监管认证：.............................................................................................. 1
向 中的 CSA 组件验收列表项添加了“（等待审批）”特性 ....................................................................................................... 1
删除了 中的“所有已计划机构认证”特性 安全及监管认证：..................................................................................................... 1
已更改简化电路原理图：VCC1 更改为 VCCI、VCC2 更改为 VCCO、GND1 更改为 GNDI、GND2 更改为 GNDO。已添加
注释 1 和注释 2....................................................................................................................................................................... 1
•
•
•
Added Note: "Maximum voltage must not exceed 6 V:" to Absolute Maximum Ratings........................................................ 7
Added "DT1" to the Minimum internal gap in Insulation and Safety-Related Specifications for DW-16 Package................. 9
Changed VIORM "Maximum repetitive peak voltage" To: "Maximum repetitive peak isolation voltage per DIN V VDE V
0884-10" in Insulation Characteristics ................................................................................................................................... 9
•
•
Changed VIOTM From: "DIN V VDE 0884-10 " To: "DIN V VDE V 0884-10" in Insulation Characteristics ............................ 9
Changed VIOSM "Maximum surge voltage per DIN V VDE 0884-10 " To: "Maximum surge isolation voltage per DIN V
VDE V 0884-100" in Insulation Characteristics ..................................................................................................................... 9
•
•
•
Changed VIOSM Test Conditions in Insulation Characteristics ............................................................................................... 9
Changed VPR From: "DIN V VDE 0884-10 " To: "DIN V VDE V 0884-10" in Insulation Characteristics ............................... 9
Changed RS Test Conditions in Insulation and Safety-Related Specifications for DW-16 Package From: TS To: TS =
150°C ..................................................................................................................................................................................... 9
•
•
•
•
•
•
•
•
•
Changed the Safety-Related Certifications table ................................................................................................................ 10
Changed title From: " IEC Safety Limiting Values" To: Safety Limiting Values ................................................................... 10
Changed MIN value for VOH in the Electrical Characteristics From: VCCx - 0.5 To: VCCO - 0.5 ............................................ 11
Changed VCCx To VCCO in Note 1 of the Electrical Characteristics....................................................................................... 11
Changed MIN value for VOH in the Electrical Characteristics From: VCCx - 0.5 To: VCCO - 0.5 ............................................ 12
Changed VCCx To VCCO in Note 1 of the Electrical Characteristics....................................................................................... 12
Changed Function Table Header information From: INPUT-SIDE VCC To: VCCI and OUTPUT-SIDE VCC To: VCCO ......... 21
Changed Device I/O Schematics From: VCC To: VCCI on the inputs and VCCO on Output and Enabled............................... 21
Moved Typical ISO7340x Circuit Hook-up to Typical ISO7342x-Q1 Circuit Hook-up from the Design Requirements
section to the Detailed Design Procedure section................................................................................................................ 23
Changes from Revision B (November 2014) to Revision C
Page
•
•
Changed the Handling Ratings table to ESD Ratings............................................................................................................ 7
Changed Minimum internal gap MIN value in Insulation and Safety-Related Specifications for DW-16 Package
From: 0.014 mm To: 13.5 µm................................................................................................................................................. 9
•
Changed Minimum internal gap MIN value in Insulation and Safety-Related Specifications for DW-16 Package
From: 13.5 µm To: 13 µm....................................................................................................................................................... 9
•
•
•
•
Delete text "per DIN V VDE 0884-10" from VIORM in the table in section Insulation Characteristics ..................................... 9
Changed From: VPEAK To VPK in the UNIT column of the table in section Insulation Characteristics .................................... 9
Added VIOSM to the table in section Insulation Characteristics .............................................................................................. 9
Changed the table in Safety-Related Certifications section - removed text "Certified according to", "Approved
under", "Recognized under", changed "pending" To: "planned" .......................................................................................... 10
•
Changed Maximum Repetitive Peak Voltage, 1414 VPK To: Maximum surge voltage , 6000 VPK in the VDE column
of the table in section Safety-Related Certifications............................................................................................................. 10
•
•
•
•
•
•
Changed the ICC2, Supply current, DC to 1 Mbps TYP value From: 3 To 3.2 mA .............................................................. 11
Changed the ICC2, Supply current, 10 Mbps TYP value From: 5.1 To 5.6 mA .................................................................... 11
Changed the ICC2, Supply current, 25 Mbps TYP value From: 8.6 To 9.3 mA .................................................................... 11
Changed the ICC1, Supply current, 10 Mbps TYP value From: 0.8 To 0.9 mA .................................................................... 12
Changed the ICC2, Supply current, 10 Mbps TYP value From: 0.3.6 To 3.9 mA ................................................................. 12
Changed the ICC2, Supply current, 25 Mbps TYP value From: 5.9 To 6.3 mA .................................................................... 12
版权 © 2014–2017, Texas Instruments Incorporated
3
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
•
•
Added ISO7340 Supply Current vs Data Rate (15-pF Load) and ISO7340x Supply Current vs Data Rate (No Load)....... 15
Changed ISO7341x Supply Current vs Data Rate (No Load).............................................................................................. 15
Changes from Revision A (Octoberr 2014) to Revision B
Page
•
•
Added Test Condition to IEC 60664-1 Ratings Table: Rated mains voltage ≤ 1000 VRMS ................................................... 9
Changed the RIO Test Conditions in Insulation and Safety-Related Specifications for DW-16 Package : Added TA =
25°C at MIN = 1012 ................................................................................................................................................................. 9
•
•
Changed the RIO Test Conditions in Insulation and Safety-Related Specifications for DW-16 Package : Added VIO =
500 V, 100°C ≤ TA ≤ 125°C at MIN = 1011 ............................................................................................................................. 9
Added ISO7341x Supply Current vs Data Rate (15-pF Load) and ISO7341x Supply Current vs Data Rate (No Load)..... 15
Changes from Original (September 2014) to Revision A
Page
•
•
将一页产品预览更改成了完整的数据表................................................................................................................................... 1
已更改简化电路原理图，已添加接地符号 ............................................................................................................................... 1
4
版权 © 2014–2017, Texas Instruments Incorporated
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
5 说明 （续）
这些器件与隔离式电源结合使用，有助于防止数据总线或者其他电路上的噪声电流进入本地接地以及干扰或损坏敏
感电路。ISO734x 器件具有集成噪声滤波器，可适用于严苛工业环境，在这种环境下，短噪声脉冲可能会出现在器
件输入引脚上。ISO734x 器件具有 TTL 输入阈值，工作电压范围为 3V 至 5.5V。凭借创新型芯片设计和布局技
术，ISO734x 系列器件的电磁兼容性得到了显著增强，从而能够实现系统级 ESD、EFT 和浪涌保护并符合辐射标
准。
Copyright © 2014–2017, Texas Instruments Incorporated
5
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
6 Pin Configuration and Functions
DW Package
16-Pin SOIC
DW Package
16-Pin SOIC
ISO7340x Top View
ISO7341x Top View
V
V
CC2
V
V
CC2
1
2
16
15
1
2
16
15
CC1
CC1
GND1
INA
GND2
OUTA
OUTB
OUTC
OUTD
EN
GND1
INA
GND2
OUTA
OUTB
3
4
5
6
7
8
14
13
12
11
10
3
4
5
6
14
13
12
11
INB
INB
INC
INC
OUTC
IND
OUTD
IND
NC
EN1
7
8
10
9
EN2
GND1
GND2
9
GND1
GND2
DW Package
16-Pin SOIC
ISO7342x Top View
VCC1
VCC2
1
2
16
15
GND1
INA
GND2
OUTA
OUTB
INC
3
4
5
6
7
8
14
13
INB
12
11
10
9
OUTC
OUTD
EN1
IND
EN2
GND1
GND2
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
EN
ISO7340x
ISO7341x
ISO7342x
Output enable. All output pins are enabled when EN is high or
disconnected and disabled when EN is low.
10
—
7
—
I
I
I
Output enable 1. Output pins on side-1 are enabled when EN1 is
high or disconnected and disabled when EN1 is low.
EN1
EN2
—
—
7
Output enable 2. Output pins on side-2 are enabled when EN2 is
high or disconnected and disabled when EN2 is low.
10
10
2
8
2
8
2
8
GND1
GND2
—
—
Ground connection for VCC1
Ground connection for VCC2
9
9
9
15
3
15
3
15
3
INA
I
I
Input, channel A
INB
4
4
4
Input, channel B
INC
5
5
12
11
—
14
13
5
I
Input, channel C
IND
6
11
—
14
13
12
6
I
Input, channel D
NC
7
—
O
O
O
O
—
—
No connect pins are floating with no internal connection
Output, channel A
OUTA
OUTB
OUTC
OUTD
VCC1
VCC2
14
13
12
11
1
Output, channel B
Output, channel C
6
Output, channel D
1
1
Power supply, VCC1
Power supply, VCC2
16
16
16
6
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN
–0.5
–0.5
MAX
UNIT
V
VCC
Supply voltage(2)
Voltage
VCC1, VCC2
6
VCC + 0.5(3)
±15
INx, OUTx, ENx
V
IO
Output current
mA
°C
TJ
Maximum junction temperature
Storage temperature
150
Tstg
–65
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
V
VCC1, VCC2 Supply voltage
5.5
IOH
IOL
VIH
VIL
tui
High-level output current
–4
mA
mA
V
Low-level output current
High-level input voltage
Low-level input voltage
Input pulse duration
Signaling rate
4
5.5
0.8
2
0
V
40
0
ns
1 / tui
TJ
25
136
125
Mbps
°C
Junction temperature(1)
TA
Ambient temperature
–40
25
°C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
Copyright © 2014–2017, Texas Instruments Incorporated
7
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
7.4 Thermal Information
ISO734x
DW (SOIC)
16 PINS
78.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
41
43
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
15.6
ψJB
42.5
RθJC(bottom)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5-MHz 50% duty cycle square wave
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
92
PD
Maximum power dissipation by both sides of ISO7340x
Maximum power dissipation by side-1 of ISO7340x
Maximum power dissipation by side-2 of ISO7340x
Maximum power dissipation by both sides of ISO7341x
Maximum power dissipation by side-1 of ISO7341x
Maximum power dissipation by side-2 of ISO7341x
Maximum power dissipation by both sides of ISO7342x
Maximum power dissipation by side-1 of ISO7342x
Maximum power dissipation by side-2 of ISO7342x
PD1
PD2
PD
24 mW
68
102
PD1
PD2
PD
42 mW
60
111
PD1
PD2
55.5 mW
55.5
8
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
>8
>8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
CPG
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
>13
>400
II
µm
V
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I–IV
I–III
I-II
Overvoltage Category
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar)
1414
4242
VPK
VPK
VTEST = VIOTM
;
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
t = 60 s (qualification); t = 1 s (100% production)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
6000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.2 × VIORM = 1697 VPK, tm = 10 s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2262 VPK, tm = 10 s
≤5
≤5
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 2651 VPK, tm = 1 s (100%
production)
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance, input to output(5)
VIO = 0.4 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
2.4
>1012
>1011
>109
pF
VIO = 500 V, 100°C ≤ TA ≤ x°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO = 3000 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device
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7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 and DIN EN 61010- Acceptance Notice 5A, IEC 60950-1, and
1 (VDE 0411-1):2011-07
Approved under CSA Component
Recognized under UL 1577
Component Recognition
Program
Certified according to
GB4943.1-2011
IEC 61010-1
800 VRMS Basic Insulation and 400 VRMS
Reinforced Insulation working voltage per
CSA 60950-1-07+A1+A2 and IEC 60950-1
2nd Ed.+A1+A2;
300 VRMS Basic Insulation working voltage
per CSA 61010-1-12 and IEC 61010-1 3rd
Ed.
Basic Insulation;
Maximum Transient Overvoltage, 4242 VPK
Maximum Surge Isolation Voltage, 6000 VPK
Maximum Repetitive Peak Isolation Voltage,
1414 VPK
;
Reinforced Insulation, Altitude ≤
5000 m, Tropical Climate, 250
VRMS maximum working voltage
Single protection, 3000 VRMS
File number: E181974
;
Certificate number:
CQC15001121716
Certificate number: 40016131
Master contract number: 220991
7.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 78.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
290
see Figure 1
θJA = 78.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 1
Safety input, output, or supply
current
IS
mA
R
443
150
TS
Safety temperature
(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
10
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7.9 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1) – 0.5
VCCO(1) – 0.1
TYP
4.7
5
MAX
UNIT
IOH = –4 mA; see Figure 14
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 14
IOL = 4 mA; see Figure 14
IOL = 20 μA; see Figure 14
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
Input threshold voltage
hysteresis
VI(HYS)
480
mV
IIH
IIL
High-level input current
Low-level input current
VIH = VCC at INx or ENx
VIL = 0 V at INx or ENx
10
μA
μA
–10
25
Common-mode transient
immunity
Input capacitance(2)
CMTI
CI
VI = VCC or 0 V; see Figure 17
70
kV/μs
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
3.4
pF
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
(2) Measured from input pin to ground.
7.10 Supply Current Characteristics—5-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over
recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISO7340x
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.6
0.4
0.6
3.2
1.4
5.6
2.7
9.3
1.4
0.8
1.4
EN = 0 V
Disable
DC to 1 Mbps
10 Mbps
4.8
mA
2.3
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
7.1
4
25 Mbps
12
ISO7341x
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
0.7
2
1.8
1.3
3.2
EN1 = EN2 = 0 V
Disable
DC to 1 Mbps
10 Mbps
2.9
3.2
4.9
5
4.4
mA
4.5
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
6.5
7
25 Mbps
7.8
11
ISO7342x
EN1 = EN2 = 0 V
Disable
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
0.7
2.5
4.1
6.4
1.6
DC to 1 Mbps
10 Mbps
4
mA
5.6
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
Supply current
25 Mbps
9
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1) – 0.5
VCCO(1) – 0.1
TYP
3
MAX
UNIT
IOH = –4 mA; see Figure 14
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 14
IOL = 4 mA; see Figure 14
IOL = 20 μA; see Figure 14
3.3
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
Input threshold voltage
hysteresis
450
mV
IIH
IIL
High-level input current
Low-level input current
VIH = VCC at INx or ENx
VIL = 0 V at INx or ENx
10
μA
μA
–10
25
Common-mode transient
immunity
CMTI
VI = VCC or 0 V; see Figure 17
50
kV/μs
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
7.12 Supply Current Characteristics—3.3-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over
recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISO7340x
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.4
0.3
0.4
2.3
0.9
3.9
1.6
6.3
0.7
0.6
0.7
EN = 0 V
Disable
DC to 1 Mbps
10 Mbps
3.6
mA
1.3
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
5.1
2.4
8
25 Mbps
ISO7341x
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.6
0.5
1.4
2.2
2.2
3.4
3.3
5.2
1
0.8
2.3
EN1 = EN2 = 0 V
Disable
DC to 1 Mbps
10 Mbps
3.2
mA
3
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
4.5
4.7
7.2
25 Mbps
ISO7342x
EN1 = EN2 = 0 V
Disable
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
0.5
1.8
2.8
4.3
0.9
DC to 1 Mbps
10 Mbps
2.8
mA
4
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
Supply current
25 Mbps
5.8
12
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7.13 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH, tPHL
PWD(1)
20
31
58
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Figure 14
|
Same-direction Channels
2.5
17
23
(2)
tsk(o)
Channel-to-channel output skew time
Opposite-direction Channels
(3)
tsk(pp)
Part-to-part skew time
tr
Output signal rise time
2.1
See Figure 14
tf
Output signal fall time
1.7
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
7
7
13
13
ISO734xC
7
13
Enable propagation delay, high
impedance-to-high output
tPZH
See Figure 15
See Figure 16
ns
ISO734xFC
15000
15000
7
23000(4)
23000(4)
13
ISO734xC
Enable propagation delay, high
impedance-to-low output
tPZL
tfs
ns
ISO734xFC
Fail-safe output delay time from input power loss
9.4
μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤ 43 Kbps.
7.14 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH, tPHL
PWD(1)
22
35
66
See Figure 14
|
2.5
Same-direction Channels
3
16
28
ns
ns
(2)
tsk(o)
Channel-to-channel output skew time
Opposite-direction Channels
(3)
tsk(pp)
Part-to-part skew time
tr
Output signal rise time
2.8
2.1
9
See Figure 14
tf
Output signal fall time
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
18
18
18
9
ISO734xC
9
Enable propagation delay, high impedance-
to-high output
tPZH
See Figure 15
See Figure 16
ns
ISO734xFC
16000 24000(4)
16000 24000(4)
ISO734xC
Enable propagation delay, high impedance-
to-low output
tPZL
tfs
ISO734xFC
9
18
Fail-safe output delay time from input power loss
9.4
μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤ 45 Kbps.
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7.15 Insulation Characteristics Curves
500
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
400
300
200
100
0
0
50
100
150
200
Case Temperature (èC)
D009
Figure 1. Thermal Derating Curve for Limiting Current per VDE
14
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7.16 Typical Characteristics
10
6
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
9
5
4
3
2
1
0
8
ICC1 at 3.3 V
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Data Rate (Mbps)
Data Rate (Mbps)
D001
D001
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 2. ISO7340x Supply Current vs Data Rate
(15-pF Load)
Figure 3. ISO7340x Supply Current vs Data Rate
(No Load)
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Data Rate (Mbps)
Data Rate (Mbps)
D001
D001
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 4. ISO7341x Supply Current vs Data Rate
(15-pF Load)
Figure 5. ISO7341x Supply Current vs Data Rate
(No Load)
7
6
5
4
3
2
1
0
5
4.5
4
3.5
3
2.5
2
1.5
1
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
0.5
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Data Rate (Mbps)
Data Rate (Mbps)
D001
D002
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 6. ISO7342x Supply Current vs Data Rate
(15-pF Load)
Figure 7. ISO7342x Supply Current vs Data Rate
(No Load)
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Typical Characteristics (continued)
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC at 3.3 V
VCC at 5 V
VCC at 3.3 V
VCC at 5 V
-15
-10
-5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
D003
D004
TA = 25°C
TA = 25°C
Figure 8. High-Level Output Voltage vs High-level Output
Current
Figure 9. Low-Level Output Voltage vs Low-Level Output
Current
2.46
42
40
38
36
34
VCC Rising
VCC Falling
2.44
2.42
2.4
2.38
2.36
2.34
2.32
32
tPHL at 3.3 V
tPHL at 5 V
tPLH at 3.3 V
tPLH at 5 V
30
28
-40
-50
0
50
100
150
-20
0
20
40
60
80
100 120 140
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D005
D006
Figure 10. Power Supply Undervoltage Threshold vs Free-
Air Temperature
Figure 11. Propagation Delay Time vs Free-Air Temperature
29
27
25
23
21
19
140
120
100
80
60
40
17
20
tGS at 3.3 V
Output Jitter at 3.3 V
tGS at 5 V
Output Jitter at 5 V
15
-40
0
-5
30
65
100
135
0
5
10
15
20 25
Free-Air Temperature (èC)
Data Rate (Mbps)
D007
D008
TA = 25°C
Figure 12. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 13. Output Jitter vs Data Rate
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8 Parameter Measurement Information
V
CCI
V
I
V
/2
V
/2
CC
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
50 Ω
See Note A
V
O
V
V
OH
C
L
I
90%
10%
V
50%
50%
O
See Note B
V
OL
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Switching Characteristics Test Circuit and Voltage Waveforms
V
CC
V
CC
R = 1 kΩ
L
±1%
V
/2
V
/2
CC
CC
V
V
I
0 V
IN
OUT
t
t
V
O
PLZ
PZL
0 V
V
CC
0.5 V
V
50%
EN
O
C
L
See
OL
Input
Generator
See Note A
Note B
V
I
50 Ω
V
CC
V
V
/2
V
/2
O
CC
IN
CC
OUT
V
V
I
3 V
0 V
V
t
EN
PZH
C
OH
L
See
R = 1 kΩ
±1%
L
Input
Generator
See Note A
50%
0.5 V
Note B
O
V
I
50 Ω
0 V
t
PHZ
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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Parameter Measurement Information (continued)
V
I
V
V
CC
CC
2.7 V
V
I
0 V
IN
OUT
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
tfs
V
O
V
OH
fs high
50%
V
O
C
fs low
V
L
OL
See Note A
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF 1ꢀ
C = 0.1 µF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL
See Note A
VOH or VOL
–
GNDI
GNDO
–
+
VCM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 17. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The isolator in Figure 18 is based on a capacitive isolation-barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal through the
inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses,
which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator
can be either above or below the common-mode voltage VREF depending on whether the input bit transitioned
from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic
(DCL) at the output of the HF channel comparator measures the durations between signal transients. If the
duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency
signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
9.2 Functional Block Diagram
Lsolation .arrier
OSC
[ow t Crequency
/hannel
(5/ꢀꢀꢀ100 kbps)
PWM
VREF
LPF
0
1
ꢃolarity and Çhreshold
{election
OUT
IN
{
Iigh t Crequency
/hannel
DCL
VREF
(100 kbpsꢀꢀꢀ2ꢁ ꢂbps)
ꢃolarity and Çhreshold {election
Figure 18. Conceptual Block Diagram of a Digital Capacitive Isolator
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9.3 Feature Description
The ISO734x family of devices are available in multiple channel configurations and default output state options to
enable wide variety of application uses.
PART NUMBER
ISO7340C
CHANNEL DIRECTION
RATED ISOLATION
MAXIMUM DATA RATE DEFAULT OUTPUT
High
Low
4 Forward,
0 Reverse
ISO7340FC
ISO7341C
High
3 Forward,
1 Reverse
(1)
3000 VRMS / 4242 VPK
25 Mbps
Low
ISO7341FC
ISO7342C
High
Low
2 Forward,
2 Reverse
ISO7342FC
(1) See the Safety-Related Certifications section for detailed isolation ratings.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO734x
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
20
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
9.4 Device Functional Modes
Table 1 lists the functional modes for the ISO734x family of devices.
Table 1. Function Table(1)
OUTPUT
(OUTx)
INPUT
(INx)
OUTPUT ENABLE
(ENx)
VCCI
VCCO
ISO734xC
ISO734xFC
H
L
H or Open
H
H
H or Open
L
L
PU
PU
X
L
Z
Z
Open
X
H or Open
H(2)
H(2)
L(3)
L(3)
PD
X
PU
PU
PD
H or Open
X
L
Z
Z
X
X
X
Undetermined
Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H =
High level; L = Low level ; Z = High Impedance
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level
9.4.1 Device I/O Schematics
Input (Devices Without Suffix F)
Input (Devices With Suffix F)
V
V
CCI
V
V
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
5 mA
500 W
500 W
INx
INx
5 mA
Output
Enable
V
CCO
V
V
V
V
CCO
CCO
CCO
CCO
5 mA
500 W
40 W
OUTx
ENx
Figure 19. Device I/O Schematics
Copyright © 2014–2017, Texas Instruments Incorporated
21
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www.ti.com.cn
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO734x family of devices use single-ended TTL-logic switching technology. The supply voltage range is
from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that
because of the single-ended design structure, digital isolators do not conform to any specific interface standard
and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
10.2 Typical Application
10.2.1 Isolated Data Acquisition System for Process Control
The ISO734x family of devices combined with Texas Instruments' precision analog-to-digital converter and mixed
signal micro-controller can create an advanced isolated data acquisition system as shown in Figure 20.
ISO-BARRIER
5V
ISO
5V
ISO
5VISO
3.3 V
3.3 V
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
16
10
1
22
1
V
V
CC1
CC2
2
7
0.1 ꢀF
0.1 ꢀF
AVDD
AIN1+
DVDD
EN2
EN1
INA
11
DV
8
14
3
11
12
14
13
cc
5
A0
OUTA
OUTB
OUTC
IND
P3.0
P3.1
CLK
XOUT
RTD
12
7
13
4
ISO7341
AIN1œ
A1
INB
27
12
5
6
MSP430
F2132
SCLK
INC
XIN
P3.7
P3.6
P3.5
18
17
28
11
6
18
17
16
Bridge
AIN2+
DOUT
OUTD
GND1
SOMI
9,15
2,8
ADS1234
GND2
5V
ISO
5V
ISO
AIN2œ
3.3 V
15
20
19
P3.4
REF+
DV
4
ss
16
10
1
13
14
V
V
CC2
CC1
NC
0.1 ꢀF
AIN3+
REFœ
7
Thermo
couple
0.1 ꢀF
0.1 ꢀF
EN
AIN3œ
23
24
25
26
14
3
GAIN0
GAIN1
SPEED
PWDN
OUTA
OUTB
OUTC
OUTD
GND2
INA
13
4
ISO7340
INB
16
15
AIN4+
12
5
INC
IND
Current
shunt
11
6
AIN4œ
9,15
2,8
AGND DGND
21
GND1
2
Figure 20. Isolated Data-Acquisition System for Process Control
22
Copyright © 2014–2017, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
Typical Application (continued)
10.2.1.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO734x family of devices only requires two external bypass capacitors to operate.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Typical Supply Current Equations
For the equations in this section, the following is true:
•
•
•
ICC1 and ICC2 are typical supply currents measured in mA
f is data rate measured in Mbps
CL is the capacitive load measured in pF
10.2.1.2.1.1 ISO7340x
At VCC1 = VCC2 = 5 V:
ICC1 = 0.54366 + (0.0873 × f)
(1)
(2)
ICC2 = 2.74567 + (0.08433 × f) + (0.01 × f × CL)
At VCC1 = VCC2 = 3.3 V:
ICC1 = 0.3437 + (0.04922 × f)
(3)
(4)
ICC2 = 2.1068 + (0.04374 × f) + (0.007045 × f × CL)
10.2.1.2.1.2 ISO7341x
At VCC1 = VCC2 = 5 V:
ICC1 = 1.7403 + (0.1006 × f) + (0.001711 × f × CL)
ICC2 = 2.502 + (0.09629 × f) + (0.00687 × f × CL)
(5)
(6)
At VCC1 = VCC2 = 3.3 V:
ICC1 = 1.2915 + (0.046 × f) + (0.00185 × f × CL)
ICC2 = 1.8833 + (0.0566 × f) + (0.004514 × f × CL)
(7)
(8)
10.2.1.2.1.3 ISO7342x
At VCC1 = VCC2 = 5 V:
ICC1, ICC2 = 2.1254 + (0.08694 × f) + (0.004868 × f × CL)
(9)
At VCC1 = VCC2 = 3.3 V:
ICC1, ICC2 = 1.5912 + (0.0410 × f) + (0.003785 × f × CL)
(10)
2 mm max
2 mm max
2 mm max
2 mm max
from V
CC1
from V
CC2
from V
CC1
from V
CC2
ISO7340
ISO7341
0.1 µF
0.1 µF
0.1 µF
0.1 µF
V
V
CC2
CC1
V
1
2
3
4
16
1
2
3
4
16
CC2
V
CC1
GND1
GND2
GND1
15
14
GND2
15
14
INA
INB
OUTA
OUTB
OUTC
INA
INB
INC
IND
OUTA
13
13
OUTB
OUTC
OUTD
INC
12
11
10
9
5
6
7
8
12
11
10
9
5
6
7
8
OUTD
IND
NC
EN2
EN1
EN
GND1
GND2
GND1
GND2
Figure 21. Typical ISO7340x Circuit Hook-up
Figure 22. Typical ISO7341x Circuit Hook-up
Copyright © 2014–2017, Texas Instruments Incorporated
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www.ti.com.cn
Typical Application (continued)
2 mm max
from V
2 mm max
from V
CC1
CC2
ISO7342
0.1 µF
0.1 µF
V
V
CC2
CC1
1
2
3
4
16
GND1
GND2
15
14
INA
OUTA
OUTB
INC
13
INB
OUTC
12
11
10
9
5
6
7
8
OUTD
IND
EN2
EN1
GND1
GND2
Figure 23. Typical ISO7342x Circuit Hook-up
10.2.1.3 Application Curves
The typical eye diagrams of the ISO734x family of devices indicate low jitter and a wide open eye at the
maximum data rate of 25 Mbps.
Figure 24. Eye Diagram at 25 Mbps, 5 V and 25°C
Figure 25. Eye Diagram at 25 Mbps, 3.3 V and 25°C
24
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ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
Typical Application (continued)
10.2.2 Typical Application for Module With 16 Inputs
The ISO7341x device and several other components from Texas Instruments can be used to create an isolated
serial peripheral interface (SPI) for input module with 16 inputs.
V
S
0.1 ꢀF
3.3 V
2
MBR0520L
MBR0520L
1:1.33
3.3VISO
3
1
4
3
1
2
V
CC
D2
D1
IN
OUT
GND
TLV70733
SN6501
10 ꢀF 0.1 ꢀF
10 ꢀF
EN
2
4
6
GND
4, 5
V
V
OUT
IN
10 ꢀF
1 ꢀF
22 ꢀF
REF5025
GND
ISO-BARRIER
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
1
16
4.7 kꢁ
4.7 kꢁ
V
V
CC2
CC1
2
3
2
28
32
31
7
10
EN1
INA
EN2
DV
CC
AINP MXO VBD VA REFP
6
3
4
5
6
14
13
12
11
23
24
25
26
20
OUTA
OUTB
OUTC
CS
CH0
P1.4
5
6
ISO7341
7
MSP430
G2132
(14-PW)
XOUT
XIN
INB
SCLK
SDI
SCLK
16 Analog
Inputs
ADS7953
8
INC
SDO
9
5
OUTD
IND
SDO
CH15
SDI
DVss
4
BDGND AGND
27 1, 22
REFM
30
GND1
2, 8
GND2
9, 15
Figure 26. Isolated SPI for an Analog Input Module With 16 Inputs
10.2.2.1 Design Requirements
Refer to Isolated Data Acquisition System for Process Control for the design requirements.
10.2.2.2 Detailed Design Procedure
Refer to Isolated Data Acquisition System for Process Control for the detailed design procedures.
10.2.2.3 Application Curves
Refer to Isolated Data Acquisition System for Process Control for the application curves.
Copyright © 2014–2017, Texas Instruments Incorporated
25
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
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www.ti.com.cn
Typical Application (continued)
10.2.3 Typical Application for RS-232 Interface
Typical isolated RS-232 interface implementation is shown in Figure 27.
V
IN
0.1 ꢀF
3.3 V
2
MBR0520L
MBR0520L
1:2.1
5V
ISO
3
1
1
5
V
CC
D2
D1
IN
OUT
BP
LP2985-50
SN6501
10 ꢀF 0.1 ꢀF
3.3 ꢀF
3
4
ON
GND
GND
4, 5
2
10 nF
10 ꢀF
0.1 ꢀF
ISO-BARRIER
0.1 ꢀF
0.1 ꢀF
16
V
1 ꢀF
1 ꢀF
0.1 ꢀF
CC
2
1
6
V
V
S-
S+
1
16
4
4.7 kꢀ
4.7 kꢀ
C1+
C2+
V
V
CC2
CC1
TRS232
2
1 ꢀF
1 ꢀF
7
10
14
12
13
11
3
5
C1-
EN1
EN2
C2-
T1OUT
R1IN
DV
CC
15
16
12
11
3
5
4
6
11
12
10
9
14
13
7
INA
OUTA
INC
T1IN
TxD
RxD
RST
CST
UCA0TXD
UCA0RXD
P3.1
5
6
ISO7342
XOUT
XIN
OUTC
INB
R1OUT
T2IN
MSP430
F2132
OUTB
T2OUT
R2IN
8
OUTD
IND
R2OUT
P3.0
DV
SS
GND
15
GND1
2, 8
GND2
4
9, 15
ISOGND
Figure 27. Isolated RS-232 Interface
10.2.3.1 Design Requirements
Refer to Isolated Data Acquisition System for Process Control for the design requirements.
10.2.3.2 Detailed Design Procedure
Refer to Isolated Data Acquisition System for Process Control for the detailed design procedures.
10.2.3.3 Application Curves
Refer to Isolated Data Acquisition System for Process Control for the application curves.
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 Transformer Driver for Isolated Power Supplies.
26
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ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 28). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 28. Recommended Layer Stack
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ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
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13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
•
•
•
隔离相关术语
数字隔离器设计指南
《SN6501-Q1 用于隔离电源的变压器驱动器》
13.2 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的
快速链接。
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
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立即订购
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技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
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请单击此处
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支持和社区
请单击此处
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ISO7340C
ISO7340FC
ISO7341C
ISO7341FC
ISO7342C
ISO7342FC
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
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ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
14 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
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ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
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PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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www.ti.com.cn
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
16X (0.6)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
R0.05 TYP
14X (1.27)
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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版权 © 2014–2017, Texas Instruments Incorporated
31
ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
ZHCSCW1G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (0.6)
16X (2)
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
32
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7340CDW
ISO7340CDWR
ISO7340FCDW
ISO7340FCDWR
ISO7341CDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
16
16
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ISO7340C
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO7340C
ISO7340FC
ISO7340FC
ISO7341C
ISO7341C
ISO7341FC
ISO7341FC
ISO7342C
ISO7342C
ISO7342FC
ISO7342FC
ISO7341CDWR
ISO7341FCDW
ISO7341FCDWR
ISO7342CDW
ISO7342CDWR
ISO7342FCDW
ISO7342FCDWR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7340CDWR
ISO7340FCDWR
ISO7341CDWR
ISO7341FCDWR
ISO7342CDWR
ISO7342FCDWR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
2.7
2.7
2.7
2.7
2.7
2.7
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7340CDWR
ISO7340FCDWR
ISO7341CDWR
ISO7341FCDWR
ISO7342CDWR
ISO7342FCDWR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
16
16
16
16
16
16
2000
2000
2000
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7340CDW
ISO7340FCDW
ISO7341CDW
ISO7341FCDW
ISO7342CDW
ISO7342FCDW
DW
DW
DW
DW
DW
DW
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
16
16
16
16
16
16
40
40
40
40
40
40
506.98
506.98
506.98
506.98
506.98
506.98
12.7
12.7
12.7
12.7
12.7
12.7
4826
4826
4826
4826
4826
4826
6.6
6.6
6.6
6.6
6.6
6.6
Pack Materials-Page 3
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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Copyright © 2022，德州仪器 (TI) 公司
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