ISO7710-Q1 [TI]
EMC 性能优异的汽车类单通道、增强型数字隔离器;
| 型号： | ISO7710-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EMC 性能优异的汽车类单通道、增强型数字隔离器 |
| 文件： | 总32页 (文件大小：1613K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7710-Q1
ZHCSG31 –MARCH 2017
EMC 性能优异的 ISO7710-Q1 高速单通道增强型数字隔离器
1 特性
3 说明
1
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
ISO7710-Q1 器件是一款高性能单通道数字隔离器，可
提供符合 UL 1577 的 5000VRMS（DW 封装）和
3000VRMS（D 封装）隔离额定值。此器件还通过了
VDE、TUV、CSA 和 CQC 认证。
•
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
–
–
器件 HBM ESD 分类等级 3A
器件 CDM ESD 分类等级 C6
在隔离互补金属氧化物半导体 (CMOS) 或者低电压互
补金属氧化物半导体 (LVCMOS) 数字 I/O 的同
时，ISO7710-Q1 器件还可提供高电磁抗扰度和低辐
射，同时具备低功耗特性。隔离通道具有逻辑输入和输
出缓冲器，二者通过二氧化硅 (SiO2) 绝缘栅相隔离。
如果输入功率或信号出现损失，不带后缀 F 的器件默
认输出高电平，带后缀 F 的器件默认输出低电平。更
多详细信息，请参见。
•
•
•
•
•
信号传输速率：高达 100Mbps
宽电源电压范围：2.25V 至 5.5V
2.25V 至 5.5V 电平转换
默认输出高电平 和低电平 选项
低功耗，
1Mbps 时的电流典型值为 1.7mA
•
低传播延迟：典型值为 11ns
（由 5V 电源供电）
与隔离式电源结合使用时，该器件有助于防止数据总线
或者其他电路中的噪声电流进入本地接地，进而干扰或
损坏敏感电路。凭借创新型芯片设计和布线技
术，ISO7710-Q1 器件的电磁兼容性得到了显著增强，
可缓解系统级 ESD、EFT 和浪涌问题并符合辐射标
准。ISO7710-Q1 器件可提供 16 引脚 SOIC 宽体
(DW) 和 8 引脚 SOIC 窄体 (D) 封装。
•
•
高 CMTI：±100kV/μs（典型值）
优异的电磁兼容性 (EMC)
–
–
系统级 ESD、EFT 和浪涌抗扰性
低辐射
•
•
隔离栅寿命：> 40 年
宽体小外形尺寸集成电路 (SOIC) (DW-16) 和窄体
小外形尺寸集成电路 (SOIC) (D-8) 封装选项
器件信息(1)
•
安全及管理批准：
器件型号
ISO7710-Q1
封装
SOIC (D)
SOIC (DW)
封装尺寸（标称值）
4.90mm x 3.91mm
10.30mm × 7.50mm
–
VDE 增强型隔离，符合 DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12 标准
–
–
UL 1577 组件认证计划
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
CSA 组件验收通知
5A、IEC 60950-1 和 IEC 60601-1 终端设备标
准
简化原理图
V
V
CC2
–
–
–
符合 GB4943.1-2011 的 CQC 认证
CC1
Isolation
Capacitor
符合 EN 60950-1 和 EN 61010-1 的 TUV 认证
完成 DW-16 封装的 VDE、UL、CSA 和 TUV
认证；已规划其他所有认证
IN
OUT
2 应用
GND1
GND2
Copyright © 2016, Texas Instruments Incorporated
•
•
•
•
混合动力电动汽车
电机控制
电源
光伏逆变器
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEU2
ISO7710-Q1
ZHCSG31 –MARCH 2017
www.ti.com.cn
目录
6.19 Typical Characteristics.......................................... 13
Parameter Measurement Information ................ 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
1
2
3
4
5
6
特性.......................................................................... 1
7
8
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Ratings........................................................... 5
6.6 Insulation Specifications .......................................... 6
6.7 Safety-Related Certifications..................................... 7
6.8 Safety Limiting Values .............................................. 7
6.9 Electrical Characteristics—5-V Supply ..................... 8
6.10 Supply Current Characteristics—5-V Supply.......... 8
6.11 Electrical Characteristics—3.3-V Supply ................ 9
6.12 Supply Current Characteristics—3.3-V Supply....... 9
6.13 Electrical Characteristics—2.5-V Supply .............. 10
6.14 Supply Current Characteristics—2.5-V Supply..... 10
6.15 Switching Characteristics—5-V Supply................. 11
6.16 Switching Characteristics—3.3-V Supply.............. 11
6.17 Switching Characteristics—2.5-V Supply.............. 11
6.18 Insulation Characteristics Curves ......................... 12
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 器件和文档支持 ..................................................... 21
12.1 文档支持................................................................ 21
12.2 相关链接................................................................ 21
12.3 接收文档更新通知 ................................................. 21
12.4 社区资源................................................................ 21
12.5 商标....................................................................... 21
12.6 静电放电警告......................................................... 21
12.7 术语表 ................................................................... 21
13 机械、封装和可订购信息....................................... 21
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 3 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
ISO7710-Q1
www.ti.com.cn
ZHCSG31 –MARCH 2017
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
D Package
8-Pin SOIC
Top View
GND1
NC
1
2
3
4
5
6
7
8
16 GND2
15 NC
1
2
3
4
8
7
6
V
V
CC2
CC1
IN
NC
14
V
V
CC2
CC1
IN
OUT
V
CC1
13 OUT
12 NC
11 NC
10 NC
9 GND2
GND1
5 GND2
NC
NC
GND1
NC
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DW
D
1, 3
8
VCC1
VCC2
GND1
GND2
IN
3
14
—
—
—
—
I
Power supply, VCC1
Power supply, VCC2
Ground connection for VCC1
Ground connection for VCC2
Input channel
1, 7
9, 16
4
4
5
2
OUT
13
6
O
Output channel
2, 5, 6, 8, 10 ,11,
12, 15
NC
7
—
Not connect pin; it has no internal connection
Copyright © 2017, Texas Instruments Incorporated
3
ISO7710-Q1
ZHCSG31 –MARCH 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
–0.5
–0.5
–15
MAX
UNIT
V
VCC1, VCC2
Supply voltage(2)
Voltage at IN, OUT
Output Current
6
VCC + 0.5(3)
15
V
V
IO
mA
°C
TJ
Tstg
Junction temperature
Storage temperature
150
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±6000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
UNIT
V
VCC1, VCC2
VCC(UVLO+)
VCC(UVLO-)
VHYS(UVLO)
Supply voltage
2.25
UVLO threshold when supply voltage is rising
UVLO threshold when supply voltage is falling
Supply voltage UVLO hysteresis
2
1.8
2.25
V
1.7
100
–4
V
200
mV
VCC2 = 5 V
IOH
High-level output current
Low-level output current
VCC2 = 3.3 V
VCC2 = 2.5 V
VCC2 = 5 V
–2
mA
mA
–1
4
IOL
VCC2 = 3.3 V
VCC2 = 2.5 V
2
1
VIH
VIL
DR
TA
High-level input voltage
Low-level input voltage
Signaling rate
0.7 × VCC1
VCC1
V
V
0
0
0.3 × VCC1
100
Mbps
°C
Ambient temperature
–40
25
125
4
Copyright © 2017, Texas Instruments Incorporated
ISO7710-Q1
www.ti.com.cn
ZHCSG31 –MARCH 2017
6.4 Thermal Information
ISO7710-Q1
DW (SOIC)
THERMAL METRIC(1)
D (SOIC)
(8-Pin)
146.1
63.1
UNIT
(16-Pin)
94.4
57.3
57.1
40.0
56.8
n/a
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
80.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
9.6
ψJB
79.0
RθJC(bottom) Junction-to-case(bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
PD
Maximum power dissipation
50
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
12.5
37.5
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
Copyright © 2017, Texas Instruments Incorporated
5
ISO7710-Q1
ZHCSG31 –MARCH 2017
www.ti.com.cn
UNIT
6.6 Insulation Specifications
VALUE
DW-16
PARAMETER
TEST CONDITIONS
D-8
(1)
CLR
CPG
External clearance
External creepage
Shortest terminal-to-terminal distance through air
8
4
mm
mm
Shortest terminal-to-terminal distance across the
package surface
(1)
8
4
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
According to IEC 60664-1
21
>600
I
21
>600
I
μm
V
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I–IV
I–IV
I–IV
I–III
I–IV
I–III
n/a
n/a
Overvoltage category per IEC 60664-1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
Maximum repetitive peak isolation
voltage
VIORM
AC voltage (bipolar)
1414
637
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) test
1000
1414
450
637
VRMS
VDC
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
t = 60 s (qualification)
t= 1 s (100% production)
8000
4242
VPK
VPK
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
VIOSM
8000
≤5
5000
≤5
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
qpd
Apparent charge(4)
pC
Method b1; At routine test (100% production) and
preconditioning (type test)
≤5
≤5
Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz
~0.4
>1012
>1011
>109
2
~0.4
>1012
>1011
>109
2
pF
VIO = 500 V, TA = 25°C
Isolation resistance(5)
VIO = 500 V, 100°C ≤ TA ≤ 125°C
Ω
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
55/125/21 55/125/21
UL 1577
VTEST = VISO, t = 60 s (qualification);
VTEST = 1.2 × VISO, t = 1 s (100% production)
VISO
Withstanding isolation voltage
5000
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
6
Copyright © 2017, Texas Instruments Incorporated
ISO7710-Q1
www.ti.com.cn
ZHCSG31 –MARCH 2017
6.7 Safety-Related Certifications
VDE, CSA, UL and TUV certifications for DW-16 package are complete; All other certifications are planned.
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010 (3rd Ed)
and EN 60950-
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-
12
Certified under CSA
Component Acceptance
Notice 5A, IEC 60950-1,
and IEC 60601-1
Certified according to UL
1577 Component
Recognition Program
Plan to certify according to
GB4943.1-2011
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation per
CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.,
800 VRMS (DW-16) and 400
VRMS (D-8) max working
voltage (pollution degree 2,
material group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed.
3.1, 250 VRMS (DW-16) max
working voltage
Reinforced insulation per
EN 61010-1:2010 (3rd Ed)
up to working voltage of
600 VRMS (DW-16) and
300 VRMS (D-8)
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation per
EN 60950-
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to
working voltage of 800
VRMS (DW-16) and 400
VRMS (D-8)
Maximum transient
isolation voltage, 8000
VPK (DW-16, Reinforced)
and 4242 VPK (D-8);
Maximum repetitive peak
isolation voltage, 1414
VPK (DW-16, Reinforced)
and 637 VPK (D-8);
Maximum surge isolation
voltage, 8000 VPK (DW-
16, Reinforced) and
DW-16: Reinforced
Insulation, Altitude ≤ 5000
m, Tropical Climate, 400
VRMS maximum working
voltage;
D-8: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
DW-16: Single
protection, 5000 VRMS
D-8: Single protection,
3000 VRMS
;
maximum working voltage
5000 VPK (D-8)
Certificate number:
40040142
Master contract number:
220991
File number: E181974
Certification Planned
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
DW-16 Package
TEST CONDITIONS
MIN TYP
MAX UNIT
R
R
R
θJA = 94.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
θJA = 94.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
θJA = 94.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
241
Safety input, output, or
supply current
368
mA
IS
482
see Figure 1
Safety input, output, or
total power
PS
TS
RθJA = 94.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 2
1324 mW
Maximum safety
temperature
150
°C
D-8 Package
R
θJA = 146.1 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3
θJA = 146.1 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
156
238
311
Safety input, output, or
supply current
R
IS
mA
see Figure 3
RθJA = 146.1 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 3
Safety input, output, or
total power
PS
TS
RθJA = 146.1 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
856 mW
150 °C
Maximum safety
temperature
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a High-K test board for leaded surface mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
Copyright © 2017, Texas Instruments Incorporated
7
ISO7710-Q1
ZHCSG31 –MARCH 2017
www.ti.com.cn
6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.8
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
Rising input threshold voltage
Falling input threshold voltage
Input threshold voltage hysteresis
High-level input current
IOH = –4 mA; see Figure 11
VCC2 – 0.4
V
IOL = 4 mA; see Figure 11
0.2
0.4
V
V
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
0.6 x VCC1 0.7 x VCC1
0.4 x VCC1
0.3 x VCC1
0.1 × VCC1
V
0.2 × VCC1
V
VIH = VCC1 at IN
VIL = 0 V at IN
10
μA
μA
kV/μs
pF
IIL
Low-level input current
–10
85
CMTI
CI
Common-mode transient immunity VI = VCC1 or 0 V, VCM = 1200 V; see Figure 13
Input Capacitance(1)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
100
2
(1) Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.5
0.6
1.6
0.6
1.1
0.6
1.1
1.1
1.4
5.9
0.8
1
VI = VCC1 (ISO7710-Q1), VI = 0 V (ISO7710-Q1 with F
suffix)
ICC2
Supply current - DC signal
ICC1
2.5
1
VI = 0 V (ISO7710-Q1), VI = VCC1 (ISO7710-Q1 with F
suffix)
ICC2
ICC1
1.5
mA
1.1
1 Mbps
ICC2
ICC1
1.6
1.6
2
All channels switching with square
10 Mbps
Supply current - AC signal
wave clock input; CL = 15 pF
ICC2
ICC1
100 Mbps
ICC2
7
8
Copyright © 2017, Texas Instruments Incorporated
ISO7710-Q1
www.ti.com.cn
ZHCSG31 –MARCH 2017
6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.2
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –2 mA; see Figure 11
VCC2 – 0.3
V
IOL = 2 mA; see Figure 11
0.1
0.3
V
V
VIT+(IN) Rising input voltage threshold
0.6 x VCC1
0.4 x VCC1
0.2 × VCC1
0.7 x VCC1
VIT-(IN)
VI(HYS)
IIH
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
0.3 x VCC1
0.1 × VCC1
V
V
VIH = VCC1 at IN
VIL = 0 V at IN
10
μA
μA
kV/μs
IIL
Low-level input current
–10
85
CMTI
Common-mode transient immunity VI = VCC1 or 0 V, VCM = 1200 V; see Figure 13
100
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.5
0.6
1.6
0.6
1.1
0.6
1
0.8
1
VI = VCC1 (ISO7710-Q1), VI = 0 V (ISO7710-Q1 with F
suffix)
ICC2
Supply current - DC signal
ICC1
2.5
1
VI = 0 V (ISO7710-Q1), VI = VCC1 (ISO7710-Q1 with F
suffix)
ICC2
ICC1
1.5
mA
1
1 Mbps
ICC2
ICC1
1.6
1.4
1.8
5.3
All channels switching with square
10 Mbps
Supply current - AC signal
wave clock input; CL = 15 pF
ICC2
1.1
1.3
4.3
ICC1
100 Mbps
ICC2
Copyright © 2017, Texas Instruments Incorporated
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.45
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –1 mA; see Figure 11
VCC2 – 0.2
V
IOL = 1 mA; see Figure 11
0.05
0.2
V
V
VIT+(IN) Rising input voltage threshold
0.6 x VCC1
0.4 x VCC1
0.2 × VCC1
0.7 x VCC1
VIT-(IN)
VI(HYS)
IIH
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
0.3 x VCC1
0.1 × VCC1
V
V
VIH = VCC1 at IN
VIL = 0 V at IN
10
μA
μA
IIL
Low-level input current
–10
85
Common-mode transient
immunity
CMTI
VI = VCC1 or 0 V, VCM = 1200 V; see Figure 13
100
kV/μs
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.5
0.6
1.6
0.6
1.1
0.6
1.1
0.9
1.2
3.4
0.8
1
VI = VCC1 (ISO7710-Q1), VI = 0 V (ISO7710-Q1 with F
suffix)
ICC2
Supply current - DC signal
ICC1
2.5
1
VI = 0 V (ISO7710-Q1), VI = VCC1 (ISO7710-Q1 with F
suffix)
ICC2
ICC1
1.5
mA
1
1 Mbps
ICC2
ICC1
1.5
1.4
1.6
4.4
All channels switching with square
10 Mbps
Supply current - AC signal
wave clock input; CL = 15 pF
ICC2
ICC1
100 Mbps
ICC2
10
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Part-to-part skew time(2)
Output signal rise time
TEST CONDITIONS
MIN
TYP
11
MAX UNIT
tPLH, tPHL
6
16
4.9
4.5
3.9
3.9
ns
ns
ns
ns
ns
See Figure 11
PWD
tsk(pp)
tr
|
0.6
1.8
1.9
See Figure 11
tf
Output signal fall time
Measured from the time VCC1 goes below 1.7 V.
See Figure 12
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
1
0.3
μs
216 – 1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Part-to-part skew time(2)
Output signal rise time
TEST CONDITIONS
MIN
TYP
11
MAX UNIT
tPLH, tPHL
6
16
5
ns
ns
ns
ns
ns
See Figure 11
PWD
tsk(pp)
tr
|
0.1
4.5
3
0.7
0.7
See Figure 11
tf
Output signal fall time
3
Measured from the time VCC1 goes below 1.7 V.
See Figure 12
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
1
0.3
μs
216 – 1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Part-to-part skew time(2)
Output signal rise time
TEST CONDITIONS
MIN
TYP
12
MAX
18.5
5.1
UNIT
ns
tPLH, tPHL
7.5
See Figure 11
PWD
tsk(pp)
tr
|
0.2
ns
4.6
ns
1
1
3.5
ns
See Figure 11
tf
Output signal fall time
3.5
ns
Measured from the time VCC1 goes below 1.7 V.
See Figure 12
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
1
0.3
μs
216 – 1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2017, Texas Instruments Incorporated
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6.18 Insulation Characteristics Curves
600
1400
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
400
300
200
100
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D001
D002
Figure 1. Thermal Derating Curve for Limiting Current per
VDE for DW-16 Package
Figure 2. Thermal Derating Curve for Limiting Power per
VDE for DW-16 Package
350
900
800
700
600
500
400
300
200
100
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
0
50
100
Ambient Temperature (èC)
150
200
Ambient Temperature (èC)
D003
D004
Figure 3. Thermal Derating Curve for Limiting Current per
VDE for D-8 Package
Figure 4. Thermal Derating Curve for Limiting Power per
VDE for D-8 Package
12
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6.19 Typical Characteristics
7
2.5
2
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
6
5
4
3
2
1
0
1.5
1
0.5
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D005
D006
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 5. ISO7710-Q1 Supply Current vs Data Rate
(With 15 pF Load)
Figure 6. ISO7710-Q1 Supply Current vs Data Rate
(With No Load)
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
-15
-10
High-Level Output Current (mA)
-5
0
0
5 10
Low-Level Output Current (mA)
15
D011
D012
TA = 25°C
TA = 25°C
Figure 7. High-Level Output Voltage vs High-level
Output Current
Figure 8. Low-Level Output Voltage vs Low-Level
Output Current
2.10
14
13
12
11
10
9
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
8
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
-55
-25
5
35
65
95
125
Free-Air Temperature (èC)
Free Air Temperature (èC)
D009
D010
Figure 9. Power Supply Undervoltage Threshold vs
Free-Air Temperature
Figure 10. Propagation Delay Time vs Free-Air Temperature
Copyright © 2017, Texas Instruments Incorporated
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7 Parameter Measurement Information
V
CC1
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
O
50 ꢀ
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
See Note B
V
CC
V
CC
V
1.7 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
Figure 12. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CC1
CC1
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
EN
V
or V
OH
OL
C
L
œ
See Note A
GND1
GND2
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Common-Mode Transient Immunity Test Circuit
14
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8 Detailed Description
8.1 Overview
The ISO7710-Q1 device has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. The device also
incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 14, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Copyright © 2017, Texas Instruments Incorporated
Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 15 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 15. On-Off Keying (OOK) Based Modulation Scheme
Copyright © 2017, Texas Instruments Incorporated
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8.3 Feature Description
The ISO7710-Q1 device is available in two default output state options to enable a variety of application uses.
Table 1 lists the device features.
Table 1. Device Features
MAXIMUM DATA
RATE
CHANNEL
DIRECTION
DEFAULT OUTPUT
STATE
PART NUMBER
PACKAGE
RATED ISOLATION(1)
DW-16
D-8
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
ISO7710-Q1
100 Mbps
100 Mbps
1 Forward, 0 Reverse
1 Forward, 0 Reverse
High
Low
DW-16
D-8
ISO7710-Q1
with F suffix
(1) See the Safety-Related Certifications section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7710-
Q1 device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
16
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG31 –MARCH 2017
8.4 Device Functional Modes
Table 2 lists the functional modes of ISO7710-Q1 device.
Table 2. Function Table(1)
INPUT
(IN)(2)
OUTPUT
(OUT)
VCC1
VCC2
COMMENTS
H
L
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU
PU
Default mode: When IN is open, the corresponding channel output goes to its
default logic state. Default is High for ISO7710-Q1 and Low for ISO7710-Q1
with F suffix.
Open
Default
Default
Default mode: When VCC1 is unpowered, a channel output assumes the logic
state based on the selected default option. Default is High for ISO7710-Q1 and
Low for ISO7710-Q1 with F suffix.
When VCC1 transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
PD
X
PU
PD
X
When VCC1 transitions from powered-up to unpowered, channel output
assumes the selected default state.
(3)
When VCC2 is unpowered, a channel output is undetermined
.
X
Undetermined
When VCC2 transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
(1) PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCC1, VCC2 < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
Input (Devices with F suffix)
V
V
V
V
CC1
V
V
V
CC1
CC1
CC1
CC1
CC1
CC1
1.5 Mꢀ
985 ꢀ
985 ꢀ
IN
IN
1.5 Mꢀ
Output
V
CC2
~20 ꢀ
OUT
Figure 16. Device I/O Schematics
Copyright © 2017, Texas Instruments Incorporated
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7710-Q1 device is a high-performance, single-channel digital isolator. The device uses single-ended
CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and
VCC2. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The ISO7710-Q1 device can be used with Texas Instruments' mixed signal microcontroller, CAN transceiver,
transformer driver, and low-dropout voltage regulator to create an Isolated CAN Interface as shown below.
VS
10 ꢀF
3.3 V
2
MBR0520L
Vcc
1:1.33
ISO 3.3V
3
1
1
5
2
D2
D1
IN
OUT
TPS76333-Q1
SN6501-Q1
10 ꢀF
0.1 ꢀF
10 ꢀF
3
EN
GND
MBR0520L
GND
GND
4
5
ISO Barrier
0.1 ꢀF
5
4
GND2
GND1
IN
3
0.1 ꢀF
6
8
2
ISO7710-Q1
OUT
VCC
RS
8
10 ꢁ (optional)
10 ꢁ (optional)
1, 3
4
1
VCC2
VCC1
R
CANH
29, 57
7
6
0.1 ꢀF
0.1 ꢀF
SN65HVD231Q
V
DDIO
26
25
D
CANL
Vref
CANRXA
TMS320F28035PAGQ
CANTXA
0.1 ꢀF
GND
5
0.1 ꢀF
SM712
2
VCC1
VCC2
1, 3
2
8
6
V
SS
IN
GND1
OUT
ISO7710-Q1
6, 28
GND2
4
5
4.7 nF /
2 kV
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Isolated CAN Interface
18
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ZHCSG31 –MARCH 2017
Typical Application (continued)
9.2.1 Design Requirements
To design with this device, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
2.25 V to 5.5 V
0.1 µF
Supply voltage, VCC1 and VCC2
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require components to improve performance, provide bias, or limit current, the
ISO7710-Q1 device only requires two external bypass capacitors to operate.
VCC1
VCC2
2 mm
2 mm
maximum
from VCC1
maximum
from VCC2
0.1 …F
0.1 …F
1
2
8
7
IN
INPUT
3
4
OUT 6
5
OUTPUT
GND2
GND1
Figure 18. Typical ISO7710-Q1 Circuit Hook-up
9.2.3 Application Curve
The following typical eye diagram of the ISO7710-Q1 device indicates low jitter and wide open eye at the
maximum data rate of 100 Mbps.
Time = 3.5 ns / div
Figure 19. ISO7710-Q1 Eye Diagram at 100 Mbps PRBS, 5-V Supplies and 25°C
Copyright © 2017, Texas Instruments Incorporated
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ISO7710-Q1
ZHCSG31 –MARCH 2017
www.ti.com.cn
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies.
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
Figure 20. Layout Example
20
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ISO7710-Q1
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ZHCSG31 –MARCH 2017
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
数字隔离器设计指南
《隔离相关术语》
《SN6501-Q1 用于隔离电源的变压器驱动器》
《SN65HVD231Q 汽车 3.3V CAN 收发器》
《TPS76333-Q1 低功耗 150mA 低压降线性稳压器》
《TMS320F28035PAGQ Piccolo™ 微控制器》
12.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017, Texas Instruments Incorporated
21
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7710FQDQ1
ISO7710FQDRQ1
ISO7710FQDWQ1
ISO7710FQDWRQ1
ISO7710QDQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7710FQ
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
7710FQ
DW
DW
D
16
16
8
ISO7710FQ
ISO7710FQ
7710Q
ISO7710QDRQ1
ISO7710QDWQ1
ISO7710QDWRQ1
D
8
7710Q
DW
DW
16
16
ISO7710Q
ISO7710Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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