ISO7720FQDQ1 [TI]
EMC 性能优异的汽车类双通道、2/0、增强型数字隔离器 | D | 8 | -40 to 125;
| 型号： | ISO7720FQDQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EMC 性能优异的汽车类双通道、2/0、增强型数字隔离器 | D | 8 | -40 to 125 光电二极管 接口集成电路 |
| 文件： | 总42页 (文件大小：2964K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7720-Q1, ISO7721-Q1
ZHCSG30B –MARCH 2017 –REVISED OCTOBER 2020
ISO772x-Q1 EMC 性能优异的高速、增强型双通道数字隔离器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列结果：
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
– 器件HBM ESD 分类等级3A
– 器件CDM ESD 分类等级C6
• 提供功能安全
ISO772x-Q1 器件是一款高性能双通道数字隔离器，可
提供符合 UL 1577 标准的 5000VRMS（DW 封装）和
3000VRMS（D 封装）隔离额定值。该系列包含的器件
具有符合 VDE、CSA、TUV 和 CQC 标准的增强绝缘
等级。
在隔离互补金属氧化物半导体 (CMOS) 或者低电压互
补金属氧化物半导体 (LVCMOS) 数字 I/O 的同时，
ISO772x-Q1 器件还可提供高电磁抗扰度和低辐射，同
时具备低功耗特性。每条隔离通道的逻辑输入和输出缓
冲器均由双电容二氧化硅 (SiO2) 绝缘栅相隔离。
ISO7720-Q1 器件具有两条同向通道，而 ISO7721-Q1
器件具有两条反向通道。如果输入功率或信号出现损
失，不带后缀 F 的器件默认输出高电平，带后缀 F 的
器件默认输出低电平。有关更多详细信息，请参阅器件
功能模式部分。
– 可提供用于功能安全系统设计的文档：
ISO7720-Q1、ISO7721-Q1
• 100Mbps 数据速率
• 稳健可靠的隔离栅：
– 在1.5 kVRMS 工作电压下预计寿命超过100 年
– 隔离等级高达5000VRMS
– 浪涌能力高达12.8kV
– CMTI 典型值为±100kV/μs
• 宽电源电压范围：2.25V 至5.5V
• 2.25V 至5.5V 电平转换
• 默认输出高电平(ISO772x) 和低电平(ISO772xF)
选项
• 低功耗，1Mbps 时每通道的电流典型值为1.7mA
• 低传播延迟：11ns（典型值）
• 优异的电磁兼容性(EMC)
这些器件与隔离式电源结合使用，有助于防止 CAN 和
LIN 等数据总线损坏敏感电路。凭借创新型芯片设计和
布线技术，ISO772x-Q1 器件的电磁兼容性得到了显著
增强，可缓解系统级 ESD、EFT 和浪涌问题并符合辐
射标准。ISO772x-Q1 系列器件可提供 16 引脚 SOIC
宽体(DW) 和8 引脚SOIC 窄体(D) 封装。
– 系统级ESD、EFT 和浪涌抗扰性
– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放
电保护
器件信息
封装
器件型号(1)
封装尺寸（标称值）
4.90 mm × 3.91 mm
10.30mm × 7.50mm
D (8)
DW (16)
ISO7720-Q1
ISO7721-Q1
– 低干扰(EMI)
• 宽体SOIC（DW-16）和窄体SOIC (D-8) 封装选项
• 节6.7
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
– DIN VDE V 0884-11:2017-01
– UL 1577 组件认证计划
VCCO
VCCI
– IEC 60950-1、IEC 62368-1、IEC 61010-1、
IEC 60601-1 和GB 4943.1-2011 认证
Series Isolation
Capacitors
INx
OUTx
2 应用
• 混合动力、电动和动力总成系统(EV/HEV)
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
– 电池管理系统(BMS)
– 车载充电器
– 牵引逆变器
– 直流/直流转换器
– 逆变器和电机控制
VCCI = 输入电源，VCCO = 输出电源
GNDI = 输入接地，GNDO = 输出接地
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEU1
ISO7720-Q1, ISO7721-Q1
ZHCSG30B –MARCH 2017 –REVISED OCTOBER 2020
www.ti.com.cn
Table of Contents
7 Parameter Measurement Information..........................17
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................26
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Device Support....................................................... 28
12.2 Documentation Support.......................................... 28
12.3 Related Links.......................................................... 28
12.4 接收文档更新通知................................................... 28
12.5 支持资源..................................................................28
12.6 Trademarks.............................................................28
12.7 静电放电警告.......................................................... 29
12.8 术语表..................................................................... 29
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Power Ratings.............................................................6
6.6 Insulation Specifications............................................. 7
6.7 Safety-Related Certifications...................................... 8
6.8 Safety Limiting Values.................................................9
6.9 Electrical Characteristics—5-V Supply..................... 10
6.10 Supply Current Characteristics—5-V Supply..........10
6.11 Electrical Characteristics—3.3-V Supply.................11
6.12 Supply Current Characteristics—3.3-V Supply....... 11
6.13 Electrical Characteristics—2.5-V Supply................ 12
6.14 Supply Current Characteristics—2.5-V Supply.......12
6.15 Switching Characteristics—5-V Supply...................13
6.16 Switching Characteristics—3.3-V Supply................13
6.17 Switching Characteristics—2.5-V Supply................13
6.18 Insulation Characteristics Curves........................... 14
6.19 Typical Characteristics............................................15
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (April 2020) to Revision B (October 2020)
Page
• 添加了“功能安全”要点....................................................................................................................................1
Changes from Revision * (March 2016) to Revision A (April 2020)
Page
• 通篇进行了编辑性和修饰性更改.........................................................................................................................1
• 将“隔离栅寿命：>40 年”更改为“在1.5kVRMS 工作电压下，预计寿命超过100 年”（在节1 中）.............1
• 在节1 中添加了“隔离等级高达 5000VRMS”....................................................................................................1
• 在节1 中添加了“浪涌能力高达 12.8kV”.........................................................................................................1
• 在节1 中添加了“在整个隔离栅具有 ±8kV IEC 61000-4-2 接触放电保护”......................................................1
• 更新了节1 中与认证相关的要点，并将VDE 标准名称从“DIN V VDE V 0884-10 (VDE V 0884-10):2006-12”
更改为“DIN VDE V 0884-11:2017-01”........................................................................................................... 1
• 更新了节 2 列表..................................................................................................................................................1
• 更新了图3-1，以便显示每个通道的两个串联隔离电容器，而不是单个隔离电容器...........................................1
• Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in 节6.2 table ...................................5
• Changed 'Signaling' rate to 'Data' rate and added table note to Data rate specification in 节6.3 table ............5
• Changed VIORM Value for DW-16 package From: "1414 VPK" To: "2121 VPK" in 节6.6 table ........................... 7
• Changed VIOWM value for DW-16 package From: "1000 VRMS" and "1414 VDC" To: "1500 VRMS" and "2121
VDC" in 节6.6 table ............................................................................................................................................7
• Added 'see 图9-6" to TEST CONDITIONS of VIOWM specification ................................................................... 7
• Changed VIOTM TEST CONDITIONS for 100% production test From: "VTEST = VIOTM" To: "VTEST = 1.2 x
VIOTM" in 节6.6 table ......................................................................................................................................... 7
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English Data Sheet: SLLSEU1
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• Changed VIOSM TEST CONDITIONS From: "Test method per IEC 60065" To: "Test method per IEC 62368-1"
in 节6.6 table .....................................................................................................................................................7
• Changed qpd TEST CONDITIONS for method b1 test From: "Vini = VIOTM" To: "Vini = 1.2 x VIOTM" in 节6.6
table ...................................................................................................................................................................7
• Changed the climatic category for the D package from 5/125/21 to 55/125/21 .................................................7
• Updated certification information in 节6.7 table ................................................................................................8
• Switched the line colors for VCC at 2.5 V and VCC at 3.3 V in the Low-Level Output Voltage vs Low-Level
Output Current graph........................................................................................................................................15
• Deleted EN from the Common-Mode Transient Immunity Test Circuit figure................................................... 17
• Corrected ground symbols for "Input (Devices with F suffix)" in 节8.4.1 ........................................................ 20
• Added 节9.2.3.1 sub-section under 节9.2.3 section ...................................................................................... 24
• Added 'How to use isolation to improve ESD, EFT and Surge immunity in industrial systems' application
report to 节12.2 section .................................................................................................................................. 28
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English Data Sheet: SLLSEU1
ISO7720-Q1, ISO7721-Q1
ZHCSG30B –MARCH 2017 –REVISED OCTOBER 2020
www.ti.com.cn
5 Pin Configuration and Functions
GND1
NC
1
2
3
4
5
6
7
8
16 GND2
15 NC
GND1
NC
1
2
3
4
5
6
7
8
16 GND2
15 NC
14
14
V
V
V
V
CC1
CC2
CC1
CC2
INA
INB
13 OUTA
12 OUTB
11 NC
10 NC
9 GND2
OUTA
INB
13 INA
12 OUTB
11 NC
10 NC
9 GND2
NC
NC
GND1
NC
GND1
NC
图5-1. ISO7720-Q1 DW Package 16-Pin SOIC Top 图5-2. ISO7721-Q1 DW Package 16-Pin SOIC Top
View View
1
2
3
4
8
1
2
3
4
8
7
V
V
CC2
V
V
CC2
CC1
CC1
INA
INB
7 OUTA
6 OUTB
5 GND2
OUTA
INB
INA
6 OUTB
5 GND2
GND1
GND1
图5-3. ISO7720-Q1 D Package 8-Pin SOIC Top View 图5-4. ISO7721-Q1 D Package 8-Pin SOIC Top View
表5-1. Pin Functions
PIN
DW PACKAGE
D PACKAGE
I/O
DESCRIPTION
NAME
GND1
GND2
ISO7720-Q1
ISO7721-Q1
ISO7720-Q1 ISO7721-Q1
1, 7
9
1, 7
9
4
4
Ground connection for VCC1
Ground connection for VCC2
—
—
5
5
16
4
16
13
5
INA
INB
2
3
7
3
I
I
Input, channel A
Input, channel B
5
2, 6, 8, 10, 11, 2, 6, 8, 10, 11,
NC
Not connected
—
—
—
15
13
12
3
15
OUTA
OUTB
VCC1
4
7
6
1
8
2
6
1
8
O
O
Output, channel A
Output, channel B
Power supply, VCC1
Power supply, VCC2
12
3
—
—
VCC2
14
14
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English Data Sheet: SLLSEU1
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
.
MIN
–0.5
–0.5
–15
MAX
UNIT
V
VCC1, VCC2
Supply voltage(2)
6
VCC + 0.5(3)
15
V
Voltage at INx, OUTx
Output current
V
IO
mA
°C
TJ
Tstg
Junction temperature
Storage temperature
150
150
°C
–65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±6000
±1500
±8000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge Charged-device model (CDM), per AEC Q100-011
V
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(2) (3)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(3) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
UNIT
V
VCC1, VCC2
VCC(UVLO+)
VCC(UVLO-)
VHYS(UVLO)
Supply voltage
2.25
UVLO threshold when supply voltage is rising
UVLO threshold when supply voltage is falling
Supply voltage UVLO hysteresis
VCCO (1) = 5 V
2
1.8
2.25
V
1.7
100
–4
–2
–1
V
200
mV
IOH
High-level output current
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 5 V
mA
mA
4
IOL
Low-level output current
VCCO = 3.3 V
VCCO = 2.5 V
2
1
(1)
VIH
VIL
High-level input voltage
Low-level input voltage
Data rate
0.7 × VCC I
VCCI
V
V
0
0
0.3 × VCCI
100
DR(2)
Mbps
°C
TA
Ambient temperature
25
125
–40
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) 100 Mbps is the maximum specified data rate, although higher data rates are possible.
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English Data Sheet: SLLSEU1
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6.4 Thermal Information
ISO772x-Q1
DW (SOIC)
THERMAL METRIC(1)
D (SOIC)
8 PINS
137.7
54.9
UNIT
16 PINS
86.5
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
49.6
49.7
71.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
32.3
7.1
49.2
70.7
ψJB
RθJC(bottom) Junction-to-case(bottom) thermal resistance
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7720-Q1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
PD
Maximum power dissipation
100
20
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
80
ISO7721-Q1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
PD
Maximum power dissipation
100
50
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
50
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6.6 Insulation Specifications
VALUE
UNIT
PARAMETER
TEST CONDITIONS
DW-16
D-8
CLR
CPG
External clearance (1)
External creepage (1)
Shortest terminal-to-terminal distance through air
8
4
mm
mm
Shortest terminal-to-terminal distance across the
package surface
8
4
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
According to IEC 60664-1
21
21
>600
I
μm
>600
I
V
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
I–IV
I–IV
I–IV
I–III
I–IV
I–III
n/a
Overvoltage category per IEC 60664-1
n/a
DIN VDE V 0884-11:2017-01(2)
Maximum repetitive peak isolation
voltage
VIORM
AC voltage (bipolar)
2121
637
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) test; see 图9-6
1500
2121
8000
450
637
VRMS
VDC
VPK
VIOWM Maximum working isolation voltage
DC voltage
VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 x VIOTM, t = 1 s (100% production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
4242
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
5000
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤5
≤5
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
≤5
≤5
qpd
Apparent charge(4)
pC
Method b1; At routine test (100% production) and
preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance(5)
~0.5
>1012
>1011
>109
2
~0.5
>1012
>1011
>109
2
pF
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
55/125/21 55/125/21
UL 1577
VTEST = VISO, t = 60 s(qualification);
VTEST = 1.2 × VISO, t = 1 s (100% production)
VISO
Withstanding isolation voltage
5000
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
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TUV
6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Certified according to EN
61010-1:2010/A1:2019,
EN 60950-1:2006/
A2:2013 and EN
Certified according to IEC
60950-1, IEC 62368-1 and 1577 Component
IEC 60601-1
Recognized under UL
Certified according to DIN
VDE V 0884-11:2017-01
Certified according to
GB4943.1-2011
Recognition Program
62368-1:2014
800 VRMS (DW-16)
reinforced insulation and
400 VRMS (D-8) basic
insulation working voltage
per CSA
60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2,
CSA 62368-1-14 and IEC
62368-1:2014, (pollution
degree 2, material group I);
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation per
EN 61010-1:2010/
A1:2019 up to working
voltage of 600 VRMS
(DW-16) and 300 VRMS
(D-8)
Maximum transient
isolation voltage, 8000 VPK
(DW-16) and 4242 VPK
(D-8);
Maximum repetitive peak
isolation voltage, 2121 VPK
(DW-16) and 637 VPK
(D-8);
DW-16: Reinforced
Insulation, Altitude ≤5000
m, Tropical Climate,700 VRMS
DW-16: Single
protection, 5000 VRMS; maximum working voltage;
D-8: Single protection, D-8: Basic Insulation, Altitude
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation per
EN 60950-1:2006/
A2:2013 and EN
62368-1:2014 up to
working voltage of 800
VRMS (DW-16) and 400
VRMS (D-8)
3000 VRMS
≤5000 m, Tropical Climate,
400 VRMS maximum working
voltage
2 MOPP (Means of Patient
Protection) per CSA
60601-1:14 and IEC
60601-1 Ed. 3.1, 250 VRMS
(DW-16) max working
voltage
Maximum surge isolation
voltage, 8000 VPK (DW-16)
and 5000 VPK (D-8)
Certificate numbers:
File number: E181974 CQC15001121716 (DW-16) Client ID number: 77311
CQC15001121656 (D-8)
Certificate number:
40040142
Master contract number:
220991
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6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DW-16 PACKAGE
263
RθJA = 86.5 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图6-1
RθJA = 86.5 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图6-1
RθJA = 86.5 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图6-1
Safety input, output, or supply
current(1)
IS
401
525
mA
Safety input, output, or total
power(1)
PS
TS
1445 mW
RθJA = 86.5 °C/W, TJ = 150°C, TA = 25°C, see 图6-2
Maximum safety
temperature(1)
150
°C
D-8 PACKAGE
165
252
330
RθJA = 137.7 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图6-3
RθJA = 137.7 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图6-3
RθJA = 137.7 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图6-3
Safety input, output, or supply
IS
mA
current(1)
Safety input, output, or total
power(1)
PS
TS
908 mW
150 °C
RθJA = 137.7 °C/W, TJ = 150°C, TA = 25°C, see 图6-4
Maximum safety
temperature(1)
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the 节6.4 table is that of a device installed on a high-K test board for leaded surface-
mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.8
MAX UNIT
(1)
VCCO
–
0.4
VOH
VOL
High-level output voltage
Low-level output voltage
V
IOH = –4 mA; see 图7-1
0.2
0.4
V
V
IOL = 4 mA; see 图7-1
VIT+(IN) Rising input threshold voltage
0.6 x VCCI 0.7 x VCCI
0.4 x VCCI
VIT-(IN)
VI(HYS)
IIH
Falling input threshold voltage
Input threshold voltage hysteresis
High-level input current
0.3 x VCCI
0.1 × VCCI
V
0.2 × VCCI
V
VIH = VCCI (1) at INx
10
μA
µA
IIL
Low-level input current
VIL = 0 V at INx
–10
CMTI
CI
Common-mode transient immunity
Input Capacitance(2)
85
100
2
VI = VCCI or 0 V, VCM = 1200 V; see 图7-3
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
kV/μs
pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX UNIT
ISO7720-Q1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
1.1
2.9
1.2
1.8
1.3
1.9
2.2
2.5
11.6
1.1
1.7
4.2
1.9
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F suffix)
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F suffix)
1 Mbps
Supply current - DC signal
2.7
mA
1.9
2.7
3
All channels switching with square
10 Mbps
Supply current - AC signal
wave clock input; CL = 15 pF
3.2
14
100 Mbps
ISO7721-Q1
VI = VCCI (ISO7721-Q1),
VI = 0 V (ISO7721-Q1 with F suffix)
ICC1, ICC2
ICC1, ICC2
1
1.6
Supply current - DC signal
VI = 0 V (ISO7721-Q1),
VI = VCCI (ISO7721-Q1 with F suffix)
2.2
3.2
mA
2.4
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.7
2.2
7.3
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
3
9
100 Mbps
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(1)
VCCO
–
0.3
VOH
High-level output voltage
3.2
V
IOH = –2 mA; see 图7-1
VOL
Low-level output voltage
0.1
0.6 x VCCI
0.4 x VCCI
0.3
V
V
IOL = 2 mA; see 图7-1
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input voltage threshold
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
0.7 x VCCI
0.3 x VCCI
V
0.1 × VCCI 0.2 × VCCI
V
VIH = VCCI (1) at INx
10
μA
µA
IIL
Low-level input current
VIL = 0 V at INx
–10
CMTI
Common-mode transient immunity
85
100
VI = VCCI or 0 V, VCM = 1200 V; see 图7-3
kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO7720-Q1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
1.1
2.9
1.2
1.8
1.2
1.9
1.9
2.2
8.6
1.1
1.7
4.2
1.9
2.7
1.9
2.7
2.6
3.1
11
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F suffix)
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F suffix)
1 Mbps
Supply current - DC signal
mA
All channels switching with square wave
10 Mbps
Supply current - AC signal
clock input; CL = 15 pF
100 Mbps
ISO7721-Q1
VI = VCCI (ISO7721-Q1), VI = 0 V (ISO7721-Q1 with F suffix)
VI = 0 V (ISO7721-Q1), VI = VCCI (ISO7721-Q1 with F suffix)
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1
2.2
1.6
2
1.6
3.2
2.4
2.8
7
Supply current - DC signal
mA
All channels switching with square wave
clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
5.6
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.45
0.05
MAX UNIT
IOH = –1 mA; see 图7-1
VCCO (1) –0.2
VOH
High-level output voltage
Low-level output voltage
Rising input voltage threshold
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
V
0.2
VOL
V
V
IOL = 1 mA; see 图7-1
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
0.6 x VCCI 0.7 x VCCI
0.3 x VCCI 0.4 x VCCI
V
0.1 × VCCI 0.2 × VCCI
V
VIH = VCCI (1) at INx
10
μA
μA
kV/μs
IIL
Low-level input current
VIL = 0 V at INx
–10
CMTI
Common-mode transient immunity
85
100
VI = VCCI or 0 V, VCM = 1200 V; see 图7-3
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
ISO7720-Q1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
1.1
2.9
1.2
1.8
1.3
1.9
1.7
2.2
6.8
1.1
1.7
4.2
1.9
2.7
1.9
2.7
2.4
3
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F
suffix)
Supply current - DC signal
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F
suffix)
1 Mbps
mA
All channels switching with square
10 Mbps
Supply current - AC signal
wave clock input; CL = 15 pF
100 Mbps
9
ISO7721-Q1
VI = VCCI (ISO7721-Q1), VI = 0 V (ISO7721-Q1 with F
suffix)
ICC1, ICC2
ICC1, ICC2
1
1.6
3.2
Supply current - DC signal
VI = 0 V (ISO7721-Q1), VI = VCCI (ISO7721-Q1 with F
suffix)
2.2
mA
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1.6
1.9
4.6
2.4
2.7
6
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
11
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
16
4.9
4
ns
ns
ns
ns
ns
ns
See 图7-1
0.5
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same direction channels
4.5
3.9
3.9
Output signal rise time
1.8
1.9
See 图7-1
tf
Output signal fall time
Measured from the time VCC goes below 1.7
V. See 图7-2
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
1
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
11
MAX
16
5
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
See 图7-1
0.5
ns
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same direction channels
4.1
4.5
3
ns
ns
Output signal rise time
0.7
0.7
ns
See 图7-1
tf
Output signal fall time
3
ns
Measured from the time VCC goes
below 1.7 V. See 图7-2
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
1
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
12
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
7.5
18.5
5.1
4.1
4.6
3.5
3.5
ns
ns
ns
ns
ns
ns
See 图7-1
0.5
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same direction channels
Output signal rise time
1
1
See 图7-1
tf
Output signal fall time
Measured from the time VCC goes
below 1.7 V. See 图7-2
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
1
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Insulation Characteristics Curves
600
1600
1400
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
400
300
200
100
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D002
D001
图6-2. Thermal Derating Curve for Limiting Power
图6-1. Thermal Derating Curve for Limiting Current
per VDE for DW-16 Package
per VDE for DW-16 Package
350
1000
900
800
700
600
500
400
300
200
100
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
300
250
200
150
100
50
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D004
D003
图6-4. Thermal Derating Curve for Limiting Power
图6-3. Thermal Derating Curve for Limiting Current
per VDE for D-8 Package
per VDE for D-8 Package
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6.19 Typical Characteristics
14
5
4.5
4
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
10
8
3.5
3
2.5
2
6
1.5
1
4
2
0.5
0
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D006
D005
TA = 25°C
CL = No Load
TA = 25°C
CL = 15 pF
图6-6. ISO7720-Q1 Supply Current vs Data Rate
图6-5. ISO7720-Q1 Supply Current vs Data Rate
(With No Load)
(With 15-pF Load)
9
4
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
8
7
6
5
4
3
2
1
0
3.5
3
2.5
2
1.5
1
0.5
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D008
D007
TA = 25°C
CL = No Load
TA = 25°C
CL = 15 pF
图6-8. ISO7721-Q1 Supply Current vs Data Rate
图6-7. ISO7721-Q1 Supply Current vs Data Rate
(With No Load)
(With 15-pF Load)
6
5
4
3
2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0.1
0
0
0
5
10
Low-Level Output Current (mA)
15
-15
-10 -5
High-Level Output Current (mA)
0
D012
D011
TA = 25°C
TA = 25°C
图6-10. Low-Level Output Voltage vs Low-Level
图6-9. High-Level Output Voltage vs High-level
Output Current
Output Current
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2.1
2.05
2
14
13
12
11
10
9
1.95
1.9
1.85
1.8
1.75
1.7
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
VCC1+
VCC1-
VCC2+
VCC2-
1.65
1.6
8
-55
-55
-25
5
35
65
95
125
-25
5
35
65
95
125
Free-Air Temperature (èC)
Free Air Temperature (èC)
D011
D012
图6-11. Power Supply Undervoltage Threshold vs
图6-12. Propagation Delay Time vs Free-Air
Free-Air Temperature
Temperature
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7 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3 ns, ZO
= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图7-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
See Note B
V
CC
V
CC
V
1.7 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
图7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
V
OH
or V
OL
C
L
œ
See Note A
GNDI
GNDO
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图7-3. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO772x-Q1 family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices
also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, 图8-1, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
图8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
图8-2 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图8-2. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
The ISO772x-Q1 family of devices is available in two channel configurations and default output state options to
enable a variety of application uses. 表8-1 lists the device features of the ISO772x-Q1 devices.
表8-1. Device Features
MAXIMUM DATA
RATE
DEFAULT OUTPUT
STATE
PART NUMBER
CHANNEL DIRECTION
PACKAGE
RATED ISOLATION(1)
DW-16
D-8
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
ISO7720-Q1
100 Mbps
100 Mbps
100 Mbps
100 Mbps
2 Forward, 0 Reverse
High
Low
High
Low
DW-16
D-8
ISO7720-Q1 with F
suffix
2 Forward, 0 Reverse
1 Forward, 1 Reverse
1 Forward, 1 Reverse
DW-16
D-8
ISO7721-Q1
DW-16
D-8
ISO7721-Q1 with F
suffix
(1) See the 节6.7 section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO772x-
Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
表8-2 lists the functional modes for the ISO772x-Q1 devices.
表8-2. Function Table
INPUT
(INx)(3)
OUTPUT
(OUTx)
(1)
VCCI
VCCO
COMMENTS
H
L
H
L
Normal Operation:
A channel output assumes the logic state of the input.
PU
PU
Default mode: When INx is open, the corresponding channel output goes to
the default logic state. The default is High for ISO772x-Q1 and Low for
ISO772x-Q1 with F suffix.
Open
Default
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for ISO772x-Q1
and Low for ISO772x-Q1 with F suffix.
PD
X
PU
PD
X
X
Default
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(2)
.
Undetermined
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥2.25 V); PD = Powered down (VCC ≤1.7 V); X = Irrelevant;
H = High level; L = Low level
(2) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
Input (Devices with F suffix)
V
V
V
V
CCI
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
Output
V
CCO
~20 ꢀ
OUTx
Copyright © 2016, Texas Instruments Incorporated
图8-3. Device I/O Schematics
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9 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The ISO772x-Q1 devices are high-performance, dual-channel digital isolators. The devices use single-ended
CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and
VCC2. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
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9.2 Typical Application
The ISO7721-Q1 device can be used with Texas Instruments' Piccolo™ microcontroller, CAN transceiver,
transformer driver, and voltage regulator to create an isolated CAN interface.
V
S
0.1 ꢀF
3.3 V
2
MBR0520L
1:1.33
3.3VISO
10 ꢀF
3
1
1
3
5
2
V
CC
D2
IN
OUT
TPS76333-Q1
SN6501-Q1
10 ꢀF 0.1 ꢀF
EN
GND
D1
GND
4, 5
10 ꢀF
MBR0520L
ISO Barrier
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
1
8
3
29,57
V
V
CC2
CC1
VCC
RS
8
V
DDIO
10 ꢁ (optional)
10 ꢁ (optional)
4
7
26
25
2
R
D
CANH
INA
CANRXA
OUTA
ISO7721-Q1
7
6
5
TMS320F28035PAGQ
3
SN65HVD231Q
OUTB
GND2
5
CANTXA
INB
1
6
CANL
Vref
GND1
V
SS
GND
2
4
6,28
SM712
4.7 nF /
2 kV
Copyright © 2017, Texas Instruments Incorporated
图9-1. Isolated 4-mA to 20-mA Current Loop
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETER
VALUE
2.25 V to 5.5 V
0.1 µF
Supply voltage, VCC1 and VCC2
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO772x-Q1 devices only require two external bypass capacitors to operate.
V
CC1
V
CC2
GND1
NC
1
2
3
4
5
6
7
8
16 GND2
15 NC
0.1 µF
GND1
0.1 µF
GND2
GND2
GND1
14
V
V
CC2
CC1
INA
OUTA
INB
OUTA
INB
13 INA
12 OUTB
11 NC
10 NC
OUTB
NC
GND1
NC
GND1
9
GND2
GND2
图9-2. Typical ISO7721-Q1 Circuit Hook-up
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9.2.3 Application Curve
The following typical eye diagrams of the ISO772x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 100 Mbps.
Time = 3.5 ns / div
Time = 3.5 ns / div
图9-3. ISO7720-Q1 Eye Diagram at 100 Mbps
PRBS,
图9-4. ISO7721-Q1 Eye Diagram at 100 Mbps
PRBS,
5-V Supplies and 25°C
5-V Supplies and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 9-5 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 9-6 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 135 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified up to 1500 VRMS and D-8 package up to 450
VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 135 years.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图9-5. Test Setup for Insulation Lifetime Measurement
图9-6. Insulation Lifetime Projection Data
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10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 11-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, refer to:
• Isolated CAN Flexible Data (FD) Rate Repeater Reference Design
• Isolated 16-Channel AC Analog Input Module Reference Design Using Dual Simultaneously Sampled ADCs
• Polyphase Shunt Metrology with Isolated AFE Reference Design
• Reference Design for Power-Isolated Ultra-Compact Analog Output Module
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
• Texas Instruments, Isolation Glossary
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN65HVD231Q 3.3-V CAN Transceivers data sheet
• Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet
• Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
ISO7720-Q1
ISO7721-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.6 Trademarks
Piccolo™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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12.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSDE
METAL
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7720FQDQ1
ISO7720FQDRQ1
ISO7720FQDWQ1
ISO7720FQDWRQ1
ISO7720QDQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7720FQ
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
7720FQ
DW
DW
D
16
16
8
ISO7720FQ
ISO7720FQ
7720Q
ISO7720QDRQ1
ISO7720QDWQ1
ISO7720QDWRQ1
ISO7721FQDQ1
ISO7721FQDRQ1
ISO7721FQDWQ1
ISO7721FQDWRQ1
ISO7721QDQ1
D
8
7720Q
DW
DW
D
16
16
8
ISO7720Q
ISO7720Q
7721FQ
D
8
7721FQ
DW
DW
D
16
16
8
ISO7721FQ
ISO7721FQ
7721Q
ISO7721QDRQ1
ISO7721QDWQ1
ISO7721QDWRQ1
D
8
7721Q
DW
DW
16
16
ISO7721Q
ISO7721Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7720FQDRQ1
ISO7720FQDWRQ1
ISO7720QDRQ1
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
DW
D
8
16
8
2500
2000
2500
2000
2500
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
6.4
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
5.2
2.1
2.7
2.1
2.7
2.1
2.7
2.1
2.7
8.0
12.0
8.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
ISO7720QDWRQ1
ISO7721FQDRQ1
ISO7721FQDWRQ1
ISO7721QDRQ1
DW
D
16
8
12.0
8.0
DW
D
16
8
12.0
8.0
ISO7721QDWRQ1
DW
16
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7720FQDRQ1
ISO7720FQDWRQ1
ISO7720QDRQ1
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
DW
D
8
16
8
2500
2000
2500
2000
2500
2000
2500
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
ISO7720QDWRQ1
ISO7721FQDRQ1
ISO7721FQDWRQ1
ISO7721QDRQ1
DW
D
16
8
DW
D
16
8
ISO7721QDWRQ1
DW
16
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7720FQDQ1
ISO7720FQDWQ1
ISO7720QDQ1
D
DW
D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
16
8
75
40
75
40
75
40
75
40
505.46
506.98
505.46
506.98
505.46
506.98
505.46
506.98
6.76
12.7
6.76
12.7
6.76
12.7
6.76
12.7
3810
4826
3810
4826
3810
4826
3810
4826
4
6.6
4
ISO7720QDWQ1
ISO7721FQDQ1
ISO7721FQDWQ1
ISO7721QDQ1
DW
D
16
8
6.6
4
DW
D
16
8
6.6
4
ISO7721QDWQ1
DW
16
6.6
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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