ISO7730FQDWRQ1 [TI]
EMC 性能优异的汽车类三通道、3/0、增强型数字隔离器 | DW | 16 | -40 to 125;
| 型号： | ISO7730FQDWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EMC 性能优异的汽车类三通道、3/0、增强型数字隔离器 | DW | 16 | -40 to 125 |
| 文件： | 总52页 (文件大小：2761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
ISO773x-Q1 EMC 性能优异的高速、增强型三通道数字隔离器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
• 功能安全型
ISO773x-Q1 器件是高性能三通道数字隔离器，可提供
符合UL 1577 的5000VRMS（DW 封装）和3000VRMS
（DBQ 封装）隔离额定值。
该系列包含的器件具有符合 VDE、CSA、TUV 和
CQC 标准的增强绝缘等级。
– 可提供用于功能安全系统设计的文档：
ISO7730-Q1, ISO7731-Q1
• 100Mbps 数据速率
在隔离 CMOS 或 LVCMOS 数字 I/O 时，ISO773x-Q1
系列器件可提供高电磁抗扰度和低辐射，并具备低功耗
特性。每条隔离通道的逻辑输入和输出缓冲器均由双电
容二氧化硅 (SiO2) 绝缘栅相隔离。该器件配有使能引
脚，可用于将各自输出置于高阻态以适用于多主驱动应
用中，并降低功耗。
• 稳健可靠的隔离栅：
– 在1500VRMS 工作电压下预计寿命超过100 年
– 隔离等级高达5000 VRMS
– 浪涌能力高达12.8 kV
– CMTI 典型值为±100kV/μs
器件信息
• 宽电源电压范围：2.25V 至5.5V
• 2.25V 至5.5V 电平转换
• 默认输出高电平(ISO773x) 和低电平(ISO773xF)
选项
器件型号(1)
封装尺寸（标称值）
10.30mm × 7.50mm
4.90mm × 3.90mm
封装
SOIC (DW)
SSOP (DBQ)
ISO7730-Q1
ISO7731-Q1
• 低功耗，1Mbps 时每通道的电流典型值为1.5mA
• 低传播延迟：典型值为11ns（5V 电源）
• 优异的电磁兼容性(EMC)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 系统级ESD、EFT 和浪涌抗扰性
– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放
电保护
VCCO
VCCI
Series Isolation
Capacitors
– 低辐射
• 宽体SOIC (DW-16) 和QSOP (DBQ-16) 封装选项
• 安全相关认证：
INx
OUTx
ENx
– DIN VDE V 0884-11:2017-01
– UL 1577 组件认证计划
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
– CSA、CQC 和TUV 认证
VCCI = 输入电源，VCCO = 输出电源
GNDI = 输入接地，GNDO = 输出接地
2 应用
• 混合动力、电动和动力总成系统(EV/HEV)
简化版原理图
– 电池管理系统(BMS)
– 车载充电器
– 牵引逆变器
– 直流/直流转换器
– 逆变器和电机控制
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
Table of Contents
7.19 Typical Characteristics............................................18
8 Parameter Measurement Information..........................20
9 Detailed Description......................................................22
9.1 Overview...................................................................22
9.2 Functional Block Diagram.........................................22
9.3 Feature Description...................................................23
9.4 Device Functional Modes..........................................24
10 Application and Implementation................................26
10.1 Application Information........................................... 26
10.2 Typical Application.................................................. 26
11 Power Supply Recommendations..............................30
12 Layout...........................................................................31
12.1 Layout Guidelines................................................... 31
12.2 Layout Example...................................................... 31
13 Device and Documentation Support..........................32
13.1 Documentation Support.......................................... 32
13.2 Related Links.......................................................... 32
13.3 Receiving Notification of Documentation Updates..32
13.4 支持资源..................................................................32
13.5 Trademarks.............................................................32
13.6 静电放电警告.......................................................... 32
13.7 术语表..................................................................... 32
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description Continued....................................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings............................................................... 7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................8
7.5 Power Ratings.............................................................8
7.6 Insulation Specifications............................................. 9
7.7 Safety-Related Certifications.................................... 10
7.8 Safety Limiting Values...............................................10
7.9 Electrical Characteristics—5-V Supply......................11
7.10 Supply Current Characteristics—5-V Supply.......... 11
7.11 Electrical Characteristics—3.3-V Supply.................13
7.12 Supply Current Characteristics—3.3-V Supply.......13
7.13 Electrical Characteristics—2.5-V Supply................ 14
7.14 Supply Current Characteristics—2.5-V Supply.......14
7.15 Switching Characteristics—5-V Supply...................15
7.16 Switching Characteristics—3.3-V Supply................16
7.17 Switching Characteristics—2.5-V Supply................16
7.18 Insulation Characteristics Curves........................... 17
Information.................................................................... 33
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (March 2020) to Revision D (October 2020)
Page
• 在节 1 中添加了“功能安全”要点..................................................................................................................... 1
Changes from Revision B (September 2018) to Revision C (March 2020)
Page
• 通篇进行了编辑性和修饰性更改.........................................................................................................................1
• 将“隔离栅寿命：超过40 年”更改为“在1500VRMS 工作电压下预计寿命超过 100 年”（位于节1）..........1
• 在节1 中添加了“隔离等级高达 5000VRMS”....................................................................................................1
• 在节1 中添加了“浪涌能力高达 12.8kV”.........................................................................................................1
• 在节1 中添加了“在整个隔离栅具有 ±8kV IEC 61000-4-2 接触放电保护”......................................................1
• 将UL 认证要点从“符合UL 1577 的5000VRMS (DW) 和2500VRMS (DBQ) 隔离额定值”更改为“UL 1577 组
件认证计划”（在节 1 中）................................................................................................................................1
• 删除了节1 中的“除DBQ-16 封装器件的 CQC 认证外，所有认证均已完成”要点..........................................1
• 更新了节 2 部分的应用列表................................................................................................................................1
• 更新了图3-1，以便显示每个通道的两个串联隔离电容器，而不是单个隔离电容器...........................................1
• Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in 节7.2 table....................................7
• Added the following table note to Data rate specification in 节7.3 table: "100 Mbps is the maximum specified
data rate, although higher data rates are possible." .......................................................................................... 7
• Changed VIORM value for DW-16 package From: "1414 VPK" To: "2121 VPK" in 节7.6 table ............................9
• Changed VIOWM value for DW-16 package AC voltage From: "1000 VRMS" To: "1500 VRMS" and DC voltage
From: "1414 VDC" To: "2121 VDC" in 节7.6 table ...............................................................................................9
• Added 'see 图10-8' to TEST CONDITIONS of VIOWM specification in 节7.6 ................................................... 9
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English Data Sheet: SLLSEU3
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ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
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• Changed VIOSM TEST CONDITIONS From: "Test method per IEC 60065" To: "Test method per IEC 62368-1"
in 节7.6 table......................................................................................................................................................9
• Updated certification information in 节7.7 table ..............................................................................................10
• Corrected ground symbols for "Input (Devices with F suffix)" in 节9.4.1 ........................................................ 25
• Added 节10.2.3.1 sub-section under 节10.2.3 section................................................................................... 29
• Added 'How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems' application
report to 节13.1 section .................................................................................................................................. 32
Changes from Revision A (May 2017) to Revision B (June 2018)
Page
• 通篇更改了 DIN 认证编号和认证状态.................................................................................................................1
• 将DBQ 封装的隔离等级从 2500VRMS 更改为3000VRMS ..................................................................................1
• Moved the HBM and CDM values from the Features section to the ESD Ratings table.................................... 7
• Added VTEST to the conditions for the maximum transient isolation voltage parameter in the Insulation
Specifications table.............................................................................................................................................9
• Changed the value for the DBQ package from 3600 VPK to 4242 VPK throughout the document.....................9
• Changed the method b1 Vini condition for apparent charge in the Insulation Specifications table..................... 9
Changes from Revision * (November 2016) to Revision A (May 2017)
Page
• Updated the Safety-Related Certifications table...............................................................................................10
• Changed the minimum CMTI from 40 to 85 in all Electrical Characteristics tables ..........................................11
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English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
5 Description Continued
The ISO7730-Q1 device has all three channels in the same direction and the ISO7731-Q1 device has two
forward and one reverse-direction channel. If the input power or signal is lost, the default output is high for
devices without suffix F and low for devices with suffix F. See the Device Functional Modes section for further
details.
Used in conjunction with isolated power supplies, this family of devices helps prevent noise currents on data
buses, such as CAN and LIN, or other circuits from entering the local ground and interfering with or damaging
sensitive circuitry. Through innovative chip design and layout techniques, electromagnetic compatibility of the
ISO773x-Q1 device has been significantly enhanced to ease system-level ESD, EFT, surge, and emissions
compliance. The ISO773x-Q1 family of devices is available in 16-pin wide-SOIC and QSOP packages.
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6 Pin Configuration and Functions
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
GND1
INA
15 GND2
14 OUTA
13 OUTB
12 OUTC
11 NC
INB
INC
NC
NC
10 EN2
9 GND2
GND1
图6-1. ISO7730-Q1 DW and DBQ Packages 16-Pin SOIC-WB and QSOP Top View
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English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
GND1
INA
15 GND2
14 OUTA
13 OUTB
12 INC
11 NC
10 EN2
9 GND2
INB
OUTC
NC
EN1
GND1
图6-2. ISO7731-Q1 DW and DBQ Packages 16-Pin SOIC-WB and QSOP Top View
表6-1. Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
ISO7730-Q1
ISO7731-Q1
Output enable 1. Output pins on side 1 are enabled when EN1 is high or
open and in high-impedance state when EN1 is low.
EN1
EN2
7
I
I
—
Output enable 2. Output pins on side 2 are enabled when EN2 is high or
open and in high-impedance state when EN2 is low.
10
10
GND1
GND2
INA
2, 8
2, 8
9, 15
3
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
—
—
I
9, 15
3
INB
4
5
4
I
Input, channel B
INC
12
6, 11
14
13
5
I
Input, channel C
NC
6, 7, 11
14
Not connected
—
O
O
O
OUTA
OUTB
OUTC
VCC1
VCC2
Output, channel A
Output, channel B
Output, channel C
Power supply, VCC1
Power supply, VCC2
13
12
1
1
—
—
16
16
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7 Specifications
7.1 Absolute Maximum Ratings
See (1)
MIN
–0.5
–0.5
–15
MAX
UNIT
V
VCC1, VCC2
Supply voltage(2)
6
VCCX + 0.5(3)
15
V
Voltage at INx, OUTx, ENx
Output current
V
IO
mA
°C
TJ
Tstg
Junction temperature
Storage temperature
150
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 3A
±6000
Electrostatic
discharge
V(ESD)
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
V
±1500
±8000
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(2) (3)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(3) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
UNIT
VCC1, VCC2
VCC(UVLO+)
VCC(UVLO–)
VHYS(UVLO)
Supply voltage
2.25
V
V
UVLO threshold when supply voltage is rising
UVLO threshold when supply voltage is falling
Supply voltage UVLO hysteresis
VCCO (1) = 5 V
2
1.8
2.25
1.7
100
–4
–2
–1
V
200
mV
IOH
High-level output current
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 5 V
mA
mA
4
IOL
Low-level output current
VCCO = 3.3 V
VCCO = 2.5 V
2
1
(1)
VIH
VIL
High-level input voltage
Low-level input voltage
Data rate(2)
0.7 × VCCI
VCCI
V
V
0
0
0.3 × VCCI
100
DR(2)
Mbps
°C
TA
Ambient temperature
-40
25
125
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) 100 Mbps is the maximum specified data rate, although higher data rates are possible.
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English Data Sheet: SLLSEU3
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ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
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7.4 Thermal Information
ISO773x-Q1
DW (SOIC) DBQ (QSOP)
THERMAL METRIC(1)
UNIT
16 Pins
81.4
16 Pins
109
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44.9
46.8
60.6
35.9
60
45.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
28.1
ψJT
45.5
ψJB
RθJC(bottom)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISO7730-Q1
PD
Maximum power dissipation
150
25
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input
a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
125
ISO7731-Q1
PD
Maximum power dissipation
150
50
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input
a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
100
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7.6 Insulation Specifications
SPECIFICATION
PARAMETER
TEST CONDITIONS
UNIT
DW-16
DBQ-16
CLR
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
>3.7
mm
mm
Shortest terminal-to-terminal distance across the
package surface
CPG External creepage (1)
>8
>3.7
DTI
CTI
Distance through the insulation
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
According to IEC 60664-1
>21
>600
I
>21
>600
I
μm
Comparative tracking index
Material group
V
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
I–IV
I–IV
I–IV
I–III
I–IV
I–III
n/a
Overvoltage category per IEC 60664-1
n/a
DIN VDE V 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM
AC voltage (bipolar)
2121
566
VPK
voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test; See 图10-8
1500
2121
400
566
VRMS
VDC
VIOWM Maximum working isolation voltage
DC Voltage
VTEST = VIOTM
,
t = 60 s (qualification);
VTEST = 1.2 × VIOTM,
t = 1 s (100% production)
VIOTM Maximum transient isolation voltage
VIOSM Maximum surge isolation voltage (3)
8000
4242
VPK
Test method per IEC 62368-1; 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
≤5
4000
≤5
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
qpd
Apparent charge(4)
pC
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
≤5
≤5
Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance(5)
~0.7
>1012
>1011
>109
2
~0.7
>1012
>1011
>109
2
pF
VIO = 0.4 x sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
55/125/21 55/125/21
UL 1577
VISO Withstanding isolation voltage
VTEST = VISO , t = 60 s (qualificati
on), VTEST = 1.2 × VISO , t = 1 s (100% production)
5000
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
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TUV
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Certified according to EN
Certified according to IEC
60950-1, IEC 62368-1 and IEC Component Recognition
60601-1
Certified according to UL 1577
Certified according to DIN
VDE V 0884-11:2017-01
Certified according to GB
4943.1-2011
61010-1:2010/A1:2019, EN
60950-1:2006/A2:2013 and
EN 62368-1:2014
Program
5000 VRMS (DW-16) and
3000 VRMS (DBQ-16)
Reinforced insulation per CSA
60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2, CSA
62368-1-14 and IEC
Reinforced insulation per
EN 61010-1:2010/A1:2019
up to working voltage of 600
VRMS (DW-16) and 300
VRMS (DBQ-16)
Maximum transient isolation
voltage, 8000 VPK (DW-16)
and 4242 VPK (DBQ-16);
Maximum repetitive peak
isolation voltage, 2121 VPK
(DW-16, Reinforced) and
566 VPK (DBQ-16);
Maximum surge isolation
voltage, 8000 VPK (DW-16)
and 4000 VPK (DBQ-16)
DW-16: Reinforced Insulation,
Altitude ≤5000 m, Tropical
DW-16: Single protection, 5000 Climate, 700 VRMS maximum
62368-1:2014,
800 VRMS (DW-16) max working
voltage (pollution degree 2,
material group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-1:14
and IEC 60601-1 Ed. 3.1, 250
VRMS (DW-16) max working
voltage
VRMS
;
working voltage;
5000 VRMS (DW-16) and
3000 VRMS (DBQ-16)
DBQ-16: Single protection,
3000 VRMS
DBQ-16: Basic Insulation,
Altitude ≤5000 m, Tropical
Climate, 400 VRMS maximum
working voltage
Reinforced insulation per
EN 60950-1:2006/A2:2013
and EN 62368-1:2014 up to
working voltage of 800
VRMS (DW -16) and 370
VRMS (DBQ-16)
Certificate numbers:
CQC15001121716 (DW-16)
CQC18001199097 (DBQ-16)
Certificate number:
40040142
Master contract number: 220991 File number: E181974
Client ID number: 77311
7.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DW-16 PACKAGE
279
RθJA = 81.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图7-1
RθJA = 81.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图7-1
RθJA = 81.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图7-1
Safety input, output, or
supply current
IS
427
558
mA
Safety input, output, or total
power
PS
TS
1536 mW
RθJA = 81.4 °C/W, TJ = 150°C, TA = 25°C, see 图7-3
Maximum safety
temperature
150
°C
DBQ-16 PACKAGE
209
319
417
RθJA = 109.0°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see 图7-2
RθJA = 109.0 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see 图7-2
RθJA = 109.0°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see 图7-2
Safety input, output, or
supply current
IS
mA
Safety input, output, or total
power
PS
TS
1147 mW
150 °C
RθJA = 109.0°C/W, TJ = 150°C, TA = 25°C, see 图7-4
Maximum safety
temperature
(1) The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-
air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-
to-air thermal resistance in the 节7.4 is that of a device installed on a High-K test board for leaded surface mount packages. The
power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus
the power times the junction-to-air thermal resistance.
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7.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.8
MAX
UNIT
IOH = –4 mA; see 图8-1
VCCO (1) –0.4
VOH
High-level output voltage
Low-level output voltage
Rising input voltage threshold
Falling input voltage threshold
V
V
V
V
VOL
0.2
0.4
IOL = 4 mA; see 图8-1
VIT+(IN)
VIT-(IN)
0.6 × VCCI 0.7 × VCCI
0.4 × VCCI
0.3 × VCCI
0.1 × VCCI
Input threshold voltage
hysteresis
VI(HYS)
0.2 × VCCI
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
μA
–10
Common-mode transient
immunity
CMTI
CI
85
100
2
VI = VCCI or 0 V, VCM = 1200 V; see 图8-4
kV/μs
Input Capacitance(2)
pF
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) Measured from input pin to ground.
7.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO7730-Q1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1
0.3
4.3
0.3
1
1.4
0.4
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN2 = 0 V; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
Supply current - disable
EN2 = 0 V; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
0.4
1.4
2.5
6
EN2 = VCC2; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
1.6
4.3
1.8
2.6
1.9
2.7
3.3
3.6
17.5
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
2.7
3.7
2.8
3.8
4.5
4.6
21
1 Mbps
EN2 = VCCI; All channels switching with
square wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
ISO7731-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
0.7
3
1.2
1
mA
mA
mA
mA
mA
mA
mA
mA
Supply current - disable
4.3
2.6
1.7
2.2
5
EN1 = EN2 = 0 V; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
1.8
1.3
1.6
3.5
2.8
EN1 = EN2 = VCCI; VI = VCCI (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
4.1
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VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
2.7
2.3
3
3.4
3.3
4
mA
mA
mA
mA
mA
mA
1 Mbps
ICC2
ICC1
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
ICC2
3.3
8.5
13.1
4.4
11
ICC1
ICC2
16
(1) VCCI = Input-side VCC
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.2
MAX
UNIT
V
IOH = –2 mA; see 图8-1
VCCO (1) –0.3
VOH
High-level output voltage
Low-level output voltage
Rising input voltage threshold
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
VOL
0.1
0.3
V
IOL = 2 mA; see 图8-1
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
0.6 × VCCI 0.7 × VCCI
V
0.3 × VCCI
0.1 × VCCI
0.4 × VCCI
0.2 × VCCI
10
V
V
VIH = VCCI (1) at INx or ENx
VIL = 0 V at INx or ENx
μA
μA
IIL
Low-level input current
–10
Common-mode transient
immunity
CMTI
85
100
VI = VCCI or 0 V, VCM = 1200 V; see 图8-4
kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
7.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO7730-Q1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1
0.3
4.3
0.3
1
1.4
0.4
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN2 = 0 V; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
Supply current - disable
EN2 = 0 V; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
0.4
1.4
2.5
6
EN2 = VCC2; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
1.6
4.3
1.8
2.6
1.8
2.7
2.8
3.3
13
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
2.7
3.7
2.8
3.8
3.9
4.3
17
1 Mbps
EN2 = VCCI; All channels switching with
square wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
ISO7731-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
0.7
3
1.2
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply current - disable
4.3
2.6
1.7
2.2
5
EN1 = EN2 = 0 V; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
1.8
1.3
1.6
3.5
2.8
2.4
2.2
2.8
2.9
6.7
10
EN1 = EN2 = VCCI; VI = VCCI (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
4.1
3.4
3.3
3.8
4
1 Mbps
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
8.5
12.5
(1) VCCI = Input-side VCC
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7.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.45
0.05
MAX
UNIT
V
IOH = –1 mA; see 图8-1
VCCO (1) –0.2
VOH
High-level output voltage
Low-level output voltage
VOL
0.2
V
IOL = 1 mA; see 图8-1
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input voltage threshold
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
0.6 × VCCI 0.7 × VCCI
0.4 × VCCI
V
0.3 × VCCI
0.1 × VCCI
V
0.2 × VCCI
V
VIH = VCCI (1) at INx or ENx
10
μA
μA
kV/μs
IIL
Low-level input current
VIL = 0 V at INx or ENx
–10
CMTI
Common-mode transient immunity
85
100
VI = VCCI or 0 V, VCM = 1200 V; see 图8-4
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
7.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO7730-Q1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1
0.3
4.3
0.3
1
1.4
0.4
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN2 = 0 V; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
Supply current - disable
EN2 = 0 V; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
0.4
1.4
2.5
6
EN2 = VCC2; VI = VCC1 (ISO7730-Q1);
VI = 0 V (ISO7730-Q1 with F suffix)
1.6
4.3
1.8
2.6
1.8
2.6
2.5
3.1
10.2
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7730-Q1);
VI = VCC1 (ISO7730-Q1 with F suffix)
2.7
3.7
2.7
3.8
3.6
4.2
14
1 Mbps
EN2 = VCC2; All channels switching with
square wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
ISO7731-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
0.7
3
1.2
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply current - disable
4.3
2.6
1.7
2.2
5
EN1 = EN2 = 0 V; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
1.8
1.3
1.6
3.5
2.8
2.4
2.2
2.7
2.7
5.6
8
EN1 = EN2 = VCCI; VI = VCCI (ISO7731-Q1);
VI = 0 V (ISO7731-Q1 with F suffix)
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7731-Q1);
VI = VCCI (ISO7731-Q1 with F suffix)
4.1
3.4
3.2
3.7
3.8
7
1 Mbps
EN1 = EN2 = VCCI; All channels switching
with square wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
10
(1) VCCI = Input-side VCC
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7.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
11
16
See 图8-1
0.6
4.9
4
ns
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
ns
4.5
3.9
3.9
20
20
ns
Output signal rise time
1.3
1.4
8
ns
See 图8-1
tf
Output signal fall time
ns
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
ns
8
ns
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1
7
3
3
7
20
8.5
8.5
20
ns
μs
μs
ns
tPZH
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1 with F suffix
See 图8-2
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1
tPZL
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1 with F suffix
Measured from the time VCC goes
below 1.7 V. See 图8-3
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.6
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
TYP
11
MAX
16
5
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
See 图8-1
0.1
ns
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
4.5
3
ns
ns
Output signal rise time
1.3
1.3
17
ns
See 图8-1
tf
Output signal fall time
3
ns
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
30
30
ns
17
ns
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1
17
3.2
3.2
17
30
8.5
8.5
30
ns
μs
μs
ns
tPZH
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1 with F suffix
See 图8-2
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1
tPZL
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1 with F suffix
Measured from the time VCC goes
below 1.7 V. See 图8-3
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.6
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
TEST CONDITIONS
MIN
7.5
TYP
MAX
18.5
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
12
See 图8-1
0.2
5.1
4.1
4.6
3.5
3.5
40
ns
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction Channels
ns
ns
Output signal rise time
1
1
ns
See 图8-1
tf
Output signal fall time
ns
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
22
22
ns
40
ns
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1
18
3.3
3.3
18
40
8.5
8.5
40
ns
μs
μs
ns
tPZH
Enable propagation delay, high impedance-to-high output for
ISO773x-Q1 with F suffix
See 图8-2
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1
tPZL
Enable propagation delay, high impedance-to-low output for
ISO773x-Q1 with F suffix
Measured from the time VCC goes
below 1.7 V. See 图8-3
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.6
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.18 Insulation Characteristics Curves
600
450
400
350
300
250
200
150
100
50
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
400
300
200
100
0
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D002
D001
图7-2. Thermal Derating Curve for Safety Limiting
图7-1. Thermal Derating Curve for Safety Limiting
Current per VDE for DBQ-16 Package
Current per VDE for DW-16 Package
1800
1600
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D003
D004
图7-3. Thermal Derating Curve for Safety Limiting 图7-4. Thermal Derating Curve for Safety Limiting
Power per VDE for DW-16 Package
Power per VDE for DBQ-16 Package
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7.19 Typical Characteristics
20
7
6
5
4
3
2
1
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
18
16
14
12
10
8
ICC2 at 5 V
6
4
2
0
0
25
50
Data Rate (Mbps)
75
100
1
26
51
Data Rate (Mbps)
76
100
D005
D006
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
图7-5. ISO7730-Q1 Supply Current vs Data Rate
图7-6. ISO7730-Q1 Supply Current vs Data Rate
(With 15-pF Load)
(With No Load)
14
6
5
4
3
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
10
8
6
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
2
4
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
1
0
2
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D007
D008
TA = 25°C
CL = 15 pF
A.
TA = 25°C
CL = No Load
图7-7. ISO7731-Q1 Supply Current vs Data Rate
图7-8. ISO7731-Q1 Supply Current vs Data Rate
(With 15-pF Load)
(With No Load)
6
5
4
3
2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0.1
0
0
0
5
10
Low-Level Output Current (mA)
15
-15
-10 -5
High-Level Output Current (mA)
0
D012
D011
TA = 25°C
TA = 25°C
图7-10. Low-Level Output Voltage vs Low-Level
图7-9. High-Level Output Voltage vs High-level
Output Current
Output Current
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2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
14
13
12
11
10
9
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
8
-55
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
-25
5
35
65
95
125
Free-Air Temperature (èC)
D009
Free-Air Temperature (èC)
D010
图7-11. Power Supply Undervoltage Threshold vs
图7-12. Propagation Delay Time vs Free-Air
Free-Air Temperature
Temperature
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8 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3ns, ZO
= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
CCO
V
CC
R
L
= 1 kꢀ 1%
V
/ 2
CC
V
/ 2
CC
V
I
IN
OUT
0 V
V
0 V
O
t
t
PZL
PLZ
V
OH
EN
0.5 V
V
V
O
50%
C
L
OL
See Note B
Input
Generator
(See Note A)
V
I
50 ꢀ
V
CC
V
O
IN
OUT
3 V
V / 2
CC
V
/ 2
CC
V
I
0 V
t
PZH
EN
See Note B
R
L
= 1 kꢀ 1%
V
OH
C
L
50%
Input
Generator
(See Note A)
0.5 V
V
O
V
I
0 V
t
50 ꢀ
PHZ
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤10 kHz, 50% duty cycle,
tr ≤3 ns, tf ≤3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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V
I
See Note B
V
CC
V
CC
V
1.7 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
图8-3. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
C
L
V
or V
OL
OH
See Note A
œ
GNDO
GNDI
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-4. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISO773x-Q1 family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is
low then the output goes to high impedance. The ISO773x-Q1 family of devices also incorporates advanced
circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the high
frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, 图 9-1,
shows a functional block diagram of a typical channel.
9.2 Functional Block Diagram
Transmitter
Receiver
EN
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Copyright © 2016, Texas Instruments Incorporated
图9-1. Conceptual Block Diagram of a Digital Capacitive Isolator
图9-2 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图9-2. On-Off Keying (OOK) Based Modulation Scheme
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9.3 Feature Description
表9-1 provides an overview of the device features.
表9-1. Device Features
MAXIMUM DATA
RATE
PART NUMBER
CHANNEL DIRECTION
DEFAULT OUTPUT
PACKAGE
RATED ISOLATION(1)
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
3 Forward,
0 Reverse
ISO7730-Q1
100 Mbps
100 Mbps
100 Mbps
100 Mbps
High
ISO7730-Q1 with F
suffix
3 Forward,
0 Reverse
Low
High
Low
2 Forward,
1 Reverse
ISO7731-Q1
ISO7731-Q1 with F
suffix
2 Forward,
1 Reverse
(1) See 节7.7 for detailed isolation ratings.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO773x-
Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.4 Device Functional Modes
表9-2 lists the functional modes for the ISO773x-Q1 devices.
表9-2. Function Table
OUTPUT
ENABLE
(ENx)
INPUT
(INx)(3)
OUTPUT
(OUTx)
(1)
VCCI
VCCO
COMMENTS
H
L
H or open
H or open
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU
X
PU
PU
Default mode: When INx is open, the corresponding channel output goes
to its default logic state. Default is High for ISO773x-Q1 and Low for
ISO773x-Q1 with F suffix.
Open
X
H or open
L
Default
Z
A low value of Output Enable causes the outputs to be high-impedance
Default mode: When VCCI is unpowered, a channel output assumes the
logic state based on the selected default option. Default is High for
ISO773x-Q1 and Low for ISO773x-Q1 with F suffix.
PD
X
PU
PD
X
X
H or open
Default
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(2)
.
X
Undetermined When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥2.25 V); PD = Powered down (VCC ≤1.7 V); X = Irrelevant;
H = High level; L = Low level ; Z = High Impedance
(2) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
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9.4.1 Device I/O Schematics
Input (Devices without F suffix)
Input (Devices with F suffix)
V
V
V
V
CCI
V
V
CCI
V
CCI
CCI
CCI
CCI
CCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
Output
Enable
V
CCO
V
V
V
V
CCO
CCO
CCO
CCO
2 Mꢀ
~20 ꢀ
1970 ꢀ
OUTx
ENx
Copyright © 2016, Texas Instruments Incorporated
图9-3. Device I/O Schematics
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10 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The ISO773x-Q1 devices are high-performance, triple-channel digital isolators. These devices come with enable
pins on each side which can be used to put the respective outputs in high impedance for multi-master driving
applications and reduce power consumption. The ISO773x-Q1 family of devices use single-ended CMOS-logic
switching technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When
designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators
do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL
digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data
converter or a line transceiver, regardless of the interface type or standard.
10.2 Typical Application
The ISO7731-Q1 device combined with Texas Instruments' Piccolo™ microcontroller, analog-to-digital receiver,
transformer driver, and voltage regulator can create an isolated serial peripheral interface (SPI) as shown in 图
10-1.
V
S
0.1 µF
3.3 V
2
MBR0520L
MBR0520L
1:1.33
3.3VISO
3
1
4
3
1
2
V
CC
D2
IN
OUT
TPS76333-Q1
SN6501-Q1
EN
GND
10 µF
0.1 µF
10 µF
2
4
6
D1
GND
4, 5
V
V
OUT
IN
1 µF
REF5025A-Q1
GND
22 µF
10 µF
ISO Barrier
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1
16
4.7 kꢀ
4.7 kꢀ
V
V
CC2
CC1
29, 57
8
7
36
5
4
7
10
EN1
EN2
V
DDIO
AINP MXO +VBD +VA REFP
28
6
3
NC
NC 11
CS
CH0
TMS320F28035PAGQ
SPICLKA
ISO7731-Q1
33
36
34
14
13
12
32
33
34
INA
INB
OUTA
OUTB
SCLK
SDI
16 Analog
Inputs
ADS7953-Q1
4
5
SPISIMOA
SPISOMIA
11
OUTC
GND1
2, 8
INC
SDO
CH15
V
BDGND AGND
27 1, 22
REFM
30
SS
GND2
6, 28
9, 15
Copyright © 2016, Texas Instruments Incorporated
Multiple pins and discrete components are omitted for clarity.
图10-1. Isolated SPI for an Analog Input Module With 16 Inputs and a Single Slave
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10.2.1 Design Requirements
To design with these devices, use the parameters listed in 表10-1.
表10-1. Design Parameters
PARAMETER
VALUE
2.25 to 5.5 V
0.1 µF
Supply voltage, VCC1 and VCC2
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
10.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO773x-Q1 family of devices only requires two external bypass capacitors to operate. 图 10-2 and 图 10-3
show the typical circuit hook-up for the devices.
2 mm maximum
from VCC1
2 mm maximum
from VCC2
0.1 µF
0.1 µF
VCC2
VCC1
1
2
3
16
GND1
GND2
15
14
13
INA
INB
INC
OUTA
OUTB
OUTC
4
12
11
10
9
5
6
7
8
NC
EN
NC
NC
GND2
GND1
图10-2. Typical ISO7730-Q1 Circuit Hook-Up
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2 mm maximum
from VCC1
2 mm maximum
from VCC2
0.1 µF
0.1 µF
VCC2
VCC1
1
16
GND1
2
GND2
15
14
13
INA
INB
3
4
OUTA
OUTB
INC
OUTC
12
11
10
9
5
6
7
8
NC
NC
EN1
EN2
GND2
GND1
图10-3. Typical ISO7731-Q1 Circuit Hook-Up
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10.2.3 Application Curves
The following typical eye diagrams of the ISO773x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
图10-4. Eye Diagram at 100 Mbps PRBS 216 –1, 5 图10-5. Eye Diagram at 100 Mbps PRBS 216 –1,
V and 25°C 3.3 V and 25°C
Time = 2.5 ns / div
图10-6. Eye Diagram at 100 Mbps PRBS 216 –1, 2.5 V and 25°C
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 10-7 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 10-8 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 135 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1500 VRMS and DBQ-16 package up to
400 VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 135 years.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图10-7. Test Setup for Insulation Lifetime Measurement
图10-8. Insulation Lifetime Projection Data
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
the SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet.
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12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 12-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
图12-1. Layout Example Schematic
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
• Texas Instruments, REF50xxA-Q1 Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
• Texas Instruments, TMS320F28035 Piccolo™ Microcontrollers data sheet
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表13-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
ISO7730-Q1
ISO7731-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
Piccolo™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSEU3
32
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ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: ISO7730-Q1 ISO7731-Q1
English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ISO7730-Q1 ISO7731-Q1
English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
R0.05 TYP
14X (1.27)
R0.05 TYP
9
9
8
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ISO7730-Q1 ISO7731-Q1
English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (0.6)
16X (2)
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ISO7730-Q1 ISO7731-Q1
English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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Product Folder Links: ISO7730-Q1 ISO7731-Q1
English Data Sheet: SLLSEU3
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSEU3
38
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Product Folder Links: ISO7730-Q1 ISO7731-Q1
ISO7730-Q1, ISO7731-Q1
ZHCSFU6D –NOVEMBER 2016 –REVISED OCTOBER 2020
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ISO7730-Q1 ISO7731-Q1
English Data Sheet: SLLSEU3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7730FQDBQQ1
ISO7730FQDBQRQ1
ISO7730FQDWQ1
ISO7730FQDWRQ1
ISO7730QDBQQ1
ISO7730QDBQRQ1
ISO7730QDWQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
DBQ
DBQ
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7730FQ
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
7730FQ
ISO7730FQ
ISO7730FQ
7730Q
DW
DBQ
DBQ
DW
7730Q
ISO7730Q
ISO7730Q
7731FQ
ISO7730QDWRQ1
ISO7731FQDBQQ1
ISO7731FQDBQRQ1
ISO7731FQDWQ1
ISO7731FQDWRQ1
ISO7731QDBQQ1
ISO7731QDBQRQ1
ISO7731QDWQ1
DW
DBQ
DBQ
DW
7731FQ
ISO7731FQ
ISO7731FQ
7731Q
DW
DBQ
DBQ
DW
7731Q
ISO7731Q
ISO7731Q
ISO7731QDWRQ1
DW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7730FQDBQRQ1
ISO7730FQDWRQ1
ISO7730FQDWRQ1
ISO7730FQDWRQ1
ISO7730QDBQRQ1
ISO7730QDWRQ1
ISO7730QDWRQ1
ISO7730QDWRQ1
ISO7731FQDBQRQ1
ISO7731FQDWRQ1
ISO7731FQDWRQ1
ISO7731FQDWRQ1
ISO7731QDBQRQ1
ISO7731QDWRQ1
ISO7731QDWRQ1
ISO7731QDWRQ1
SSOP
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
DBQ
DW
DW
DW
DBQ
DW
DW
DW
DBQ
DW
DW
DW
DBQ
DW
DW
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2000
2000
2500
2000
2000
2000
2500
2000
2000
2000
2500
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
16.4
16.4
12.4
16.4
16.4
16.4
12.4
16.4
16.4
16.4
12.4
16.4
16.4
16.4
6.4
5.2
2.1
2.7
2.7
2.7
2.1
2.7
2.7
2.7
2.1
2.7
2.7
2.7
2.1
2.7
2.7
2.7
8.0
12.0
12.0
12.0
8.0
12.0
16.0
16.0
16.0
12.0
16.0
16.0
16.0
12.0
16.0
16.0
16.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
10.75 10.7
10.75 10.7
10.75 10.7
6.4
5.2
10.75 10.7
10.75 10.7
10.75 10.7
12.0
12.0
12.0
8.0
6.4
5.2
10.75 10.7
10.75 10.7
10.75 10.7
12.0
12.0
12.0
8.0
6.4
5.2
10.75 10.7
10.75 10.7
10.75 10.7
12.0
12.0
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7730FQDBQRQ1
ISO7730FQDWRQ1
ISO7730FQDWRQ1
ISO7730FQDWRQ1
ISO7730QDBQRQ1
ISO7730QDWRQ1
ISO7730QDWRQ1
ISO7730QDWRQ1
ISO7731FQDBQRQ1
ISO7731FQDWRQ1
ISO7731FQDWRQ1
ISO7731FQDWRQ1
ISO7731QDBQRQ1
ISO7731QDWRQ1
ISO7731QDWRQ1
ISO7731QDWRQ1
SSOP
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
DBQ
DW
DW
DW
DBQ
DW
DW
DW
DBQ
DW
DW
DW
DBQ
DW
DW
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2000
2000
2500
2000
2000
2000
2500
2000
2000
2000
2500
2000
2000
2000
350.0
350.0
356.0
356.0
350.0
350.0
356.0
356.0
350.0
356.0
356.0
350.0
350.0
356.0
350.0
356.0
350.0
350.0
356.0
356.0
350.0
350.0
356.0
356.0
350.0
356.0
356.0
350.0
350.0
356.0
350.0
356.0
43.0
43.0
35.0
35.0
43.0
43.0
35.0
35.0
43.0
35.0
35.0
43.0
43.0
35.0
43.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7730FQDBQQ1
ISO7730FQDWQ1
ISO7730FQDWQ1
ISO7730QDBQQ1
ISO7730QDWQ1
ISO7730QDWQ1
ISO7731FQDBQQ1
ISO7731FQDWQ1
ISO7731FQDWQ1
ISO7731QDBQQ1
ISO7731QDWQ1
ISO7731QDWQ1
DBQ
DW
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
16
16
16
16
16
16
16
16
16
16
16
16
75
40
40
75
40
40
75
40
40
75
40
40
505.46
506.98
507
6.76
12.7
3810
4826
5080
3810
5080
4826
3810
5080
4826
3810
4826
5080
4
6.6
6.6
4
DW
12.83
6.76
DBQ
DW
505.46
507
12.83
12.7
6.6
6.6
4
DW
506.98
505.46
507
DBQ
DW
6.76
12.83
12.7
6.6
6.6
4
DW
506.98
505.46
506.98
507
DBQ
DW
6.76
12.7
6.6
6.6
DW
12.83
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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