ISO7763FQDBQRQ1 [TI]
EMC 性能优异的汽车类 6 通道、3/3、增强型数字隔离器 | DBQ | 16 | -40 to 125;
| 型号： | ISO7763FQDBQRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EMC 性能优异的汽车类 6 通道、3/3、增强型数字隔离器 | DBQ | 16 | -40 to 125 |
| 文件： | 总51页 (文件大小：2603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
EMC 性能优异的ISO776x-Q1 高速、增强型六通道数字隔离器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
ISO776x-Q1 器件是高性能六通道数字隔离器，可提供
符合UL 1577 的5000VRMS（DW 封装）和3000VRMS
（DBQ 封装）隔离额定值。该系列器件还通过了
VDE、CSA、TUV 和CQC 认证。
– 器件温度等级1：–40°C 至+125°C 的环境温
度范围
– 器件HBM ESD 分类等级3A
– 器件CDM ESD 分类等级C6
• 提供功能安全
在隔离 CMOS 或 LVCMOS 数字 I/O 的同时，
ISO776x-Q1 系列的器件还可提供高电磁抗扰度和低辐
射，同时具备低功耗特性。每个隔离通道都有一个由二
氧化硅 (SiO2) 绝缘栅分开的逻辑输入和逻辑输出缓冲
器。ISO776x-Q1 系列的器件采用所有可能的引脚配
置，因此所有六个通道都可以处于同一方向，或者一
个、两个或三个通道处于反向，而其余通道处于正向。
如果输入电源或信号丢失，不带后缀 F 的器件默认输
出高电平，带后缀 F 的器件默认输出低电平。更多详
细信息，请参阅器件功能模式部分。
– 可提供用于功能安全系统设计的文档：
ISO7760-Q1、ISO7761-Q1、ISO7762-Q1、
ISO7763-Q1
• 100 Mbps 数据速率
• 稳健可靠的隔离栅：
– 预计寿命超过100 年
– 隔离等级高达5000 VRMS
– 浪涌能力高达12.8 kV
器件信息
封装
– CMTI 典型值为±100kV/μs
• 宽电源电压范围：2.25V 至5.5V
• 2.25V 至5.5V 电平转换
• 默认输出高电平(ISO776x) 和低电平(ISO776xF)
选项
器件型号(1)
ISO7760-Q1
ISO7761-Q1
ISO7762-Q1
IOS7763-Q1
封装尺寸（标称值）
SOIC (16)
10.30mm × 7.50mm
SSOP (16)
4.90mm × 3.90mm
• 低功耗，1Mbps 时每通道的电流典型值为1.4mA
• 低传播延迟：5V 时为11ns（典型值）
• 优异的电磁兼容性(EMC)：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 系统级ESD、EFT 和浪涌抗扰性
– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放
电保护
VCCO
VCCI
Series Isolation
Capacitors
– 低辐射
• 宽体SOIC (DW-16) 和SSOP (DBQ-16) 封装选项
• 安全相关认证：
INx
OUTx
– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标
准的增强型绝缘
– UL 1577 组件认证计划
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
– 符合IEC 62368-1 和IEC 60601-1 标准的CSA
认证
– 符合GB4943.1 标准的CQC 认证
– 符合EN 62368-1 和EN 61010-1 标准的TUV
认证
VCCI=输入VCC，VCCO=输出VCC
GNDI=输入接地，GNDO=输出接地
简化版原理图
2 应用
• 混合动力、电动和动力总成系统(EV/HEV)
– 电池管理系统(BMS)
– 车载充电器
– 牵引逆变器
– 直流/直流转换器
– 起动机/发电机
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEU7
ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
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Table of Contents
7.18 Insulation Characteristics Curves........................... 20
7.19 Typical Characteristics............................................21
8 Detailed Description......................................................25
8.1 Overview...................................................................25
8.2 Functional Block Diagram.........................................25
8.3 Feature Description...................................................26
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 28
10 Power Supply Recommendations..............................31
11 Layout...........................................................................32
11.1 Layout Guidelines................................................... 32
11.2 Layout Example...................................................... 32
12 Device and Documentation Support..........................33
12.1 Documentation Support.......................................... 33
12.2 Related Links.......................................................... 33
12.3 Receiving Notification of Documentation Updates..33
12.4 支持资源..................................................................33
12.5 Trademarks.............................................................33
12.6 Electrostatic Discharge Caution..............................33
12.7 术语表..................................................................... 34
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................8
7.5 Power Ratings.............................................................8
7.6 Insulation Specifications............................................. 9
7.7 Safety-Related Certifications.....................................11
7.8 Safety Limiting Values...............................................11
7.9 Electrical Characteristics—5-V Supply..................... 12
7.10 Supply Current Characteristics—5-V Supply..........13
7.11 Electrical Characteristics—3.3-V Supply.................14
7.12 Supply Current Characteristics—3.3-V Supply.......15
7.13 Electrical Characteristics—2.5-V Supply................ 16
7.14 Supply Current Characteristics—2.5-V Supply.......17
7.15 Switching Characteristics—5-V Supply...................18
7.16 Switching Characteristics—3.3-V Supply................18
7.17 Switching Characteristics—2.5-V Supply................19
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (October 2020) to Revision C (October 2022)
Page
• 将整个文档中的标准名称从“DIN V VDE V 0884-11:2017-01”更改为“DIN EN IEC 60747-17 (VDE
0884-17)”..........................................................................................................................................................1
• 通篇删除了对标准IEC/EN/CSA 60950-1 的引用................................................................................................1
• Added Maximum impulse voltage (VIMP) specification in Insulation Specifications per DIN EN IEC 60747-17
(VDE 0884-17) ...................................................................................................................................................9
• Changed test conditions and values of Maximum surge isolation voltage (VIOSM) specification in Insulation
Specifications per DIN EN IEC 60747-17 (VDE 0884-17................................................................................... 9
• Clarified method b test conditions of Apparent charge (qPD) in Insulation Specifications ................................ 9
• Changed maximum working voltage value From: 250 VRMS To: 400 VRMS for DBQ-16 devices per GB 4943.1
in Safety-Related Certifications.........................................................................................................................11
• Changed working voltage lifetime margin From: 87.5% To: 50%, minimum required insulation lifetime From:
37.5 years To: 30 years and insulation lifetime per TDDB From: 135 years To: 169 years in Insulation Lifetime
per DIN EN IEC 60747-17 (VDE 0884-17)....................................................................................................... 30
• Changed Figure 9-7 per DIN EN IEC 60747-17 (VDE 0884-17)...................................................................... 30
Changes from Revision A (February 2019) to Revision B (October 2020)
Page
• 添加了“功能安全”要点.................................................................................................................................... 1
Changes from Revision * (November 2018) to Revision A (February 2019)
Page
• Changed CPG parameter description From: "External clearance" To: "External creepage" in 节7.6 table ...... 9
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5 说明（续）
该系列器件与隔离式电源结合使用，有助于防止数据总线（例如，CAN 和 LIN）或者其他电路上的噪声电流进入
本地接地以及干扰或损坏敏感电路。凭借创新型芯片设计和布局技术，ISO776x-Q1 系列器件的电磁兼容性得到了
显著增强，可缓解系统级 ESD、EFT 和浪涌问题并符合辐射标准。ISO776x-Q1 系列器件可采用 16 引脚 SOIC
和SSOP 封装。
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6 Pin Configuration and Functions
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
INA
INB
15 OUTA
14 OUTB
13 OUTC
12 OUTD
11 OUTE
10 OUTF
9 GND2
INC
IND
INE
INF
GND1
图6-1. ISO7760-Q1 DW and DBQ Packages 16-Pin SOIC and SSOP Top View
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
INA
INB
15 OUTA
14 OUTB
13 OUTC
12 OUTD
11 OUTE
10 INF
INC
IND
INE
OUTF
GND1
9 GND2
图6-2. ISO7761-Q1 DW and DBQ Packages 16-Pin SOIC and SSOP Top View
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1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
INA
INB
15 OUTA
14 OUTB
13 OUTC
12 OUTD
11 INE
10 INF
9 GND2
INC
IND
OUTE
OUTF
GND1
图6-3. ISO7762-Q1 DW and DBQ Packages 16-Pin SOIC and SSOP Top View
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
INA
INB
15 OUTA
14 OUTB
13 OUTC
12 IND
11 INE
10 INF
9 GND2
INC
OUTD
OUTE
OUTF
GND1
图6-4. ISO7763-Q1 DW and DBQ Packages 16-Pin SOIC and SSOP Top View
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表6-1. Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
ISO7760-Q1
ISO7761-Q1
ISO7762-Q1
ISO7763-Q1
GND1
GND2
INA
8
9
8
9
8
9
8
9
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
—
—
I
2
2
2
2
INB
3
3
3
3
I
Input, channel B
INC
4
4
4
4
I
Input, channel C
IND
5
5
5
12
11
10
15
14
13
5
I
Input, channel D
INE
6
6
11
10
15
14
13
12
6
I
Input, channel E
INF
7
10
15
14
13
12
11
7
I
Input, channel F
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
VCC1
VCC2
15
14
13
12
11
10
1
O
O
O
O
O
O
Output, channel A
Output, channel B
Output, channel C
Output, channel D
Output, channel E
Output, channel F
Power supply, side 1
Power supply, side 2
6
7
7
1
1
1
—
—
16
16
16
16
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7 Specifications
7.1 Absolute Maximum Ratings
See (1)
MIN
MAX
UNIT
VCC1
VCC2
,
Supply voltage(2)
6
V
–0.5
V
Voltage at INx, OUTx
Output current
VCCX + 0.5(3)
V
–0.5
–15
IO
15
mA
°C
°C
TJ
Tstg
Junction temperature
Storage temperature
150
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
7.2 ESD Ratings
VALUE
±6000
±1500
±8000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge Charged-device model (CDM), per AEC Q100-011
V
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(2) (3)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(3) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
UNIT
V
VCC1, VCC2 Supply voltage
2.25
VCC(UVLO+) UVLO threshold when supply voltage is rising
VCC(UVLO-) UVLO threshold when supply voltage is falling
VHYS(UVLO) Supply voltage UVLO hysteresis
VCCO (1) = 5 V
2
1.8
2.25
V
1.7
100
–4
–2
–1
V
200
mV
IOH
High-level output current
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 5 V
mA
mA
4
IOL
Low-level output current
VCCO = 3.3 V
VCCO = 2.5 V
2
1
(1)
VIH
VIL
High-level input voltage
Low-level input voltage
Data rate
0.7 × VCCI
VCCI
V
V
0
0
0.3 × VCCI
100
DR(2)
Mbps
°C
TA
Ambient temperature
-40
25
125
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) 100 Mbps is the maximum specified data rate, although higher data rates are possible.
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7.4 Thermal Information
ISO776x-Q1
DW (SOIC)
THERMAL METRIC(1)
DBQ (SSOP)
16 PINS
86.5
UNIT
16 PINS
60.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case(top) thermal resistance
24.0
26.9
RθJB
ψJT
Junction-to-board thermal resistance
29.3
36.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3.3
1.7
28.7
36.1
ψJB
Rθ
Junction-to-case(bottom) thermal resistance
n/a
n/a
°C/W
JC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISO7760-Q1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side 1)
Maximum power dissipation (side 2)
292 mW
50 mW
242 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD1
PD2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
ISO7761-Q1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD
Maximum power dissipation (both sides)
292 mW
83 mW
209 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation (side 1)
Maximum power dissipation (side 2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
ISO7762-Q1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD
Maximum power dissipation (both sides)
292 mW
116 mW
176 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation (side 1)
Maximum power dissipation (side 2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
ISO7763-Q1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD
Maximum power dissipation (both sides)
292 mW
146 mW
146 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation (side 1)
Maximum power dissipation (side 2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50-MHz 50% duty cycle square wave
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7.6 Insulation Specifications
VALUE
PARAMETER
TEST CONDITIONS
UNIT
DW-16 DBQ-16
CLR External clearance(1)
CPG External creepage(1)
Shortest terminal-to-terminal distance through air
Shortest terminal-to-terminal distance across the package surface
Minimum internal gap (internal clearance)
>8
>8
>3.7
>3.7
>21
mm
mm
μm
DTI
CTI
Distance through the insulation
>21
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
>600
>600
V
Material group
According to IEC 60664-1
I
I
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
I–IV
I–IV
I–IV
I–III
I–IV
I–III
n/a
Overvoltage category per IEC
60664-1
n/a
DIN EN IEC 60747-17 (VDE 0884-17)(2)
Maximum repetitive peak isolation
voltage
VIORM
AC voltage (bipolar)
2121
566
VPK
AC voltage; Time dependent dielectric breakdown (TDDB) test; see
图9-7
1500
2121
8000
400
566
VRMS
VDC
VPK
Maximum working isolation
voltage
VIOWM
DC voltage
Maximum transient isolation
voltage
VTEST = VIOTM , t = 60 s (qualification)
VTEST = 1.2 x VIOTM, t = 1 s (100% production)
VIOTM
4242
VIMP Maximum impulse voltage(3)
8000
4000
VPK
VPK
Tested in air, 1.2/50-μs waveform per IEC 62368-1
Tested in oil (qualification test), 1.2/50-μs waveform per IEC
Maximum surge isolation
VIOSM
12800
10000
voltage(4)
62368-1
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd
Apparent charge(5)
pC
Method b: At routine test (100% production) and preconditioning
(type test);
Vini = 1.2 x VIOTM, tini = 1 s;
≤5
≤5
Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)
Barrier capacitance, input to
output(6)
CIO
RIO
~1.1
~0.9
pF
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
>1012
>1011
>109
2
>1012
>1011
>109
2
Isolation resistance(6)
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V, TS = 150°C
Ω
Pollution degree
Climatic category
55/125/ 55/125/
21
21
UL 1577
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
VISO Withstanding isolation voltage
5000
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
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(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-terminal device.
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7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to
DIN EN IEC 60747-17
(VDE 0884-17)
Recognized under UL 1577
Component Recognition
Program
Certified according to
EN 61010-1 and EN
62368-1
Certified according to IEC
62368-1 and IEC 60601-1
Certified according to GB
4943.1
Reinforced Insulation;
Maximum transient
isolation voltage, 8000
VPK (DW-16) and 4242
VPK (DBQ-16);
Maximum repetitive
peak isolation voltage,
2121 VPK (DW-16) and
566 VPK (DBQ-16);
Maximum surge
Reinforced insulation per
CSA 62368-1 and IEC
62368-1
800 VRMS (DW-16) and 370
VRMS (DBQ-16) maximum
working voltage (pollution
degree 2, material group I);
DW-16: 2 MOPP (Means of 3000 VRMS
Patient Protection) per CSA
60601-1 and IEC 60601-1,
250 VRMS maximum working
voltage
5000 VRMS Reinforced
insulation per EN
61010-1 up to working
voltage of 600 VRMS
(DW-16) and 300 VRMS
(DBQ-16)
5000 VRMS Reinforced
insulation per EN
62368-1 up to working
voltage of 800 VRMS
(DW-16) and 370 VRMS
(DBQ-16)
DW-16: Reinforced
Insulation, Altitude ≤5000
m, Tropical Climate, 700
VRMS maximum working
voltage;
DBQ-16: Basic Insulation,
Altitude ≤5000 m,
DW-16: Single protection,
5000 VRMS
;
DBQ-16: Single protection,
Tropical Climate, 400 VRMS
maximum working voltage
isolation voltage, 12800
VPK (DW-16) and 10000
VPK (DBQ-16)
Certificate numbers:
CQC15001121716 (DW)
CQC18001199097 (DBQ)
Certificate number:
40040142
Master contract number:
220991
File number: E181974
Client ID number: 77311
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DW-16 PACKAGE
R
θJA = 60.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
377
see 图7-1
θJA = 60.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see 图7-1
θJA = 60.3 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see 图7-1
R
Safety input, output, or supply
current(1)
IS
576 mA
R
754
PS
TS
Safety input, output, or total power(1)
Maximum safety temperature(1)
2073 mW
RθJA = 60.3 °C/W, TJ = 150°C, TA = 25°C, see 图7-3
150
°C
DBQ-16 PACKAGE
R
θJA = 86.5 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
263
see 图7-2
θJA = 86.5 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see 图7-2
θJA = 86.5 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see 图7-2
θJA = 86.5 °C/W, TJ = 150°C, TA = 25°C, see 图7-4
R
Safety input, output, or supply
IS
401 mA
current(1)
R
525
PS
TS
Safety input, output, or total power(1)
Maximum safety temperature(1)
1445 mW
R
150
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the 节7.4 table is that of a device installed on a high-K test board for leaded surface-
mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
VCCO
–
0.4
VOH
High-level output voltage
4.8
V
IOH = –4 mA; see 图8-1
VOL
Low-level output voltage
0.2
0.6 x VCCI
0.4 x VCCI
0.2 x VCCI
0.4
V
V
IOL = 4 mA; see 图8-1
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
Rising input threshold voltage
Falling input threshold voltage
Input threshold voltage hysteresis
High-level input current
0.7 x VCCI
0.3 x VCCI
0.1 × VCCI
V
V
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
μA
μA
IIL
Low-level input current
–10
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see 图
8-3
CMTI
CI
85
100
2
kV/μs
VI = VCC / 2 + 0.4 × sin (2πft), f = 1
MHz, VCC = 5 V
Input capacitance(2)
pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) Measured from input pin to ground.
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7.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
SUPPLY
CURRENT
PARAMETER
ISO7760-Q1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.6
3
2.3
4.9
11.3
5.3
6.4
5.6
6.7
9
VI = VCC1 (ISO7760-Q1);
VI = 0 V (ISO7760-Q1 with F suffix)
Supply current - DC
signal
mA
8
VI = 0 V (ISO7760-Q1);
VI = VCC1 (ISO7760-Q1 with F suffix)
3.3
5
1 Mbps
3.5
5.2
6.4
7
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
mA
9
35
44
ISO7761-Q1
VI = VCCI (1)(ISO7761-Q1);
VI = 0 V (ISO7761-Q1 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.9
2.9
2.7
4.7
10.6
6.6
6.4
5.9
7.2
8.8
15
Supply current - DC
signal
mA
mA
7.3
VI = 0 V (ISO7761-Q1);
VI = VCCI (ISO7761-Q1 with F suffix)
4.2
4.7
1 Mbps
3.8
5.3
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
6.3
11.5
30.5
38
ISO7762-Q1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
2.1
2.6
6.5
5
3.2
4.2
9.3
7.5
6.3
6.1
7.6
8.4
21
VI = VCCI (ISO7762-Q1);
VI = 0 V (ISO7762-Q1 with F suffix)
Supply current - DC
signal
mA
mA
VI = 0 V (ISO7762-Q1);
VI = VCCI (ISO7762-Q1 with F suffix)
4.5
4
1 Mbps
5.6
6
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
16.5
25.7
32
ISO7763-Q1
VI = VCCI (ISO7763-Q1);
VI = 0 V (ISO7763-Q1 with F suffix)
ICC1, ICC2
ICC1, ICC2
2.4
5.7
3.7
8.6
Supply current - DC
signal
mA
mA
VI = 0 V (ISO7763-Q1);
VI = VCCI (ISO7763-Q1 with F suffix)
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
4.2
5.8
21
6.1
8
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
26.5
(1) VCCI = Input-side VCC
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.2
MAX UNIT
IOH = –2 mA; see 图8-1
VCCO (1) –0.3
VOH
VOL
High-level output voltage
Low-level output voltage
V
0.1
0.3
V
V
IOL = 2 mA; see 图8-1
0.7 x
VCCI
VIT+(IN) Rising input threshold voltage
0.6 x VCCI
VIT-(IN)
Falling input threshold voltage
0.3 x VCCI
0.1 × VCCI
0.4 x VCCI
0.2 x VCCI
V
VI(HYS) Input threshold voltage hysteresis
V
IIH
IIL
High-level input current
Low-level input current
VCCI IH = V(1) at INx
VIL = 0 V at INx
10
μA
μA
–10
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see 图
8-3
CMTI
85
100
kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
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7.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
SUPPLY
CURRENT
PARAMETER
ISO7760-Q1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.6
3
2.2
4.8
11.4
5.3
6.6
5.3
6.7
7.8
8.2
33
VI = VCC1 (ISO7760-Q1);
VI = 0 V (ISO7760-Q1 with F suffix)
Supply current - DC
signal
mA
8
VI = 0 V (ISO7760-Q1);
VI = VCC1 (ISO7760-Q1 with F suffix)
3.3
4.9
3.4
5
1 Mbps
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
mA
5.5
6.3
26
ISO7761-Q1
VI = VCCI (1) (ISO7761-Q1);
VI = 0 V (ISO7761-Q1 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.8
2.9
7.2
4.2
4.6
3.7
5.1
5.5
9.4
22.8
2.7
4.7
10.3
6.6
6.5
5.7
7
Supply current - DC
signal
mA
mA
VI = 0 V (ISO7761-Q1);
VI = VCCI (ISO7761-Q1 with F suffix)
1 Mbps
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
7.8
12
29
ISO7762-Q1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
2.1
2.5
6.5
5
3.2
4.2
9.4
7.5
6.2
5.8
7.1
7.5
16.5
25
VI = VCCI (ISO7762-Q1);
VI = 0 V (ISO7762-Q1 with F suffix)
Supply current - DC
signal
mA
mA
VI = 0 V (ISO7762-Q1);
VI = VCCI (ISO7762-Q1 with F suffix)
4.4
3.9
5.2
5.4
12.9
19.5
1 Mbps
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
ISO7763-Q1
VI = VCCI (ISO7763-Q1);
VI = 0 V (ISO7763-Q1 with F suffix)
ICC1, ICC2
ICC1, ICC2
2.4
5.7
3.7
8.4
Supply current - DC
signal
mA
mA
VI = 0 V (ISO7763-Q1);
VI = VCCI (ISO7763-Q1 with F suffix)
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
4.2
5.2
16
6.2
7.5
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
20.5
(1) VCCI = Input-side VCC
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7.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –1 mA; see 图8-1
IOL = 1 mA; see 图8-1
MIN
TYP
2.45
0.05
MAX
UNIT
V
VCCO (1) –0.2
VOH
VOL
High-level output voltage
Low-level output voltage
0.2
V
0.7 x
VCCI
VIT+(IN) Rising input threshold voltage
0.6 x VCCI
V
VIT-(IN) Falling input threshold voltage
VI(HYS) Input threshold voltage hysteresis
0.3 x VCCI
0.1 × VCCI
0.4 x VCCI
0.2 x VCCI
V
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
10
μA
μA
–10
VI = VCCI or 0 V, VCM = 1200 V; see 图
8-3
CMTI
Common-mode transient immunity
85
100
kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
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7.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
SUPPLY
CURRENT
PARAMETER
ISO7760-Q1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.6
3
2.2
4.8
11.6
5.3
6.8
5.3
7
VI = VCC1 (ISO7760-Q1);
VI = 0 V (ISO7760-Q1 with F suffix)
Supply current - DC
signal
mA
8
VI = 0 V (ISO7760-Q1);
VI = VCC1 (ISO7760-Q1 with F suffix)
3.3
4.9
3.4
5
1 Mbps
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
mA
4.9
6
7.2
8
20.3
26
ISO7761-Q1
VI = VCCI (1) (ISO7761-Q1);
VI = 0 V (ISO7761-Q1 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.8
2.9
7.2
4.2
4.6
3.7
4.9
5
2.7
4.6
10.3
6.5
6.7
5.8
7.1
7.3
10.7
24
Supply current - DC
signal
mA
mA
VI = 0 V (ISO7761-Q1);
VI = VCCI (ISO7761-Q1 with F suffix)
1 Mbps
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
8.3
18.1
ISO7762-Q1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
2.1
2.6
6.5
4.9
4.4
3.9
5
3.2
4.1
VI = VCCI (ISO7762-Q1);
VI = 0 V (ISO7762-Q1 with F suffix)
Supply current - DC
signal
mA
mA
9.6
VI = 0 V (ISO7762-Q1);
VI = VCCI (ISO7762-Q1 with F suffix)
7.5
6.4
1 Mbps
5.8
7.1
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
5
7.1
10.9
15.6
14.1
20.1
ISO7763-Q1
VI = VCCI (ISO7763-Q1);
VI = 0 V (ISO7763-Q1 with F suffix)
ICC1, ICC2
ICC1, ICC2
2.3
5.7
3.7
8.4
Supply current - DC
signal
mA
mA
VI = 0 V (ISO7763-Q1);
VI = VCCI (ISO7763-Q1 with F suffix)
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
4.1
4.9
13
6.1
7.1
17
Supply current - AC
signal
All channels switching with square wave clock
input; CL = 15 pF
10 Mbps
100 Mbps
(1) VCCI = Input-side VCC
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MAX UNIT
7.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
tPLH, tPHL Propagation delay time
6
16
4.9
4
ns
ns
ns
ns
ns
ns
See 图8-1
Pulse width distortion(1) |tPHL –tPLH
|
PWD
tsk(o)
tsk(pp)
tr
0.4
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.5
3.9
3.9
Output signal rise time
1.1
1.4
See 图8-1
tf
Output signal fall time
Measured from the time VCC goes
below 1.7 V. See 图8-2
tDO
tie
Default output delay time from input power loss
Time interval error
0.2
1.3
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
12
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
Propagation delay time
6
16
5
ns
ns
ns
ns
ns
ns
See 图8-1
Pulse width distortion(1) |tPHL –tPLH
|
0.5
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
4.5
3
Output signal rise time
1
1
See 图8-1
tf
Output signal fall time
3
Measured from the time VCC goes
below 1.7 V. See 图8-2
tDO
tie
Default output delay time from input power loss
Time interval error
0.2
1.3
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
13
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
Propagation delay time
7.5
18.5
5.1
4.1
4.6
3.5
3.5
ns
ns
ns
ns
ns
ns
See 图8-1
Pulse width distortion(1) |tPHL –tPLH
|
0.6
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
Output signal rise time
1
1
See 图8-1
tf
Output signal fall time
Measured from the time VCC goes
below 1.7 V. See 图8-2
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
1.3
0.3
μs
216 –1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.18 Insulation Characteristics Curves
800
600
500
400
300
200
100
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
700
600
500
400
300
200
100
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D008
D009
图7-1. Thermal Derating Curve for Limiting Current 图7-2. Thermal Derating Curve for Limiting Current
per VDE for DW-16 Package per VDE for DBQ-16 Package
2500
2000
1500
1000
500
1600
1400
1200
1000
800
600
400
200
0
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D010
D011
图7-3. Thermal Derating Curve for Limiting Power
图7-4. Thermal Derating Curve for Limiting Power
per VDE for DW-16 Package
per VDE for DBQ-16 Package
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7.19 Typical Characteristics
48
14
12
10
8
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
44
40
36
32
28
24
20
16
12
8
ICC2 at 5 V
6
4
2
4
0
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D001
D002
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
图7-5. ISO7760-Q1 Supply Current vs Data Rate
图7-6. ISO7760-Q1 Supply Current vs Data Rate
(With 15-pF Load)
(With No Load)
48
14
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
44
12
40
36
32
28
24
20
16
12
8
10
8
6
4
2
4
0
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D012
D013
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
图7-7. ISO7761-Q1 Supply Current vs Data Rate
图7-8. ISO7761-Q1 Supply Current vs Data Rate
(With 15-pF Load)
(With No Load)
48
14
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
44
12
40
36
32
28
24
20
16
12
8
10
8
6
4
2
4
0
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D014
D015
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
图7-9. ISO7762-Q1 Supply Current vs Data Rate
图7-10. ISO7762-Q1 Supply Current vs Data Rate
(With 15-pF Load)
(With No Load)
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48
14
12
10
8
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
44
40
36
32
28
24
20
16
12
8
ICC2 at 5 V
6
4
2
4
0
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D016
D017
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
图7-11. ISO7763-Q1 Supply Current vs Data Rate 图7-12. ISO7763-Q1 Supply Current vs Data Rate
(With 15-pF Load) (With No Load)
6
5
4
3
2
1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
0
5
10
Low-Level Output Current (mA)
15
-15
-10 -5
High-Level Output Current (mA)
0
D004
D003
TA = 25°C
TA = 25°C
图7-14. Low-Level Output Voltage vs Low-Level
图7-13. High-Level Output Voltage vs High-Level
Output Current
Output Current
2.25
14
13
12
11
10
VCC1 Rising
2.2
VCC1 Falling
VCC2 Rising
VCC2 Falling
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
1.75
1.7
-60
9
-55
-30
0
30
60
90
120
-10
35
Free-Air Temperature (èC)
80
125
Free-Air Temperature (èC)
D005
D006
图7-15. Power Supply Undervoltage Threshold vs
图7-16. Propagation Delay Time vs Free-Air
Free-Air Temperature
Temperature
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1600
1400
1200
1000
800
Rising Edge Jitter at 2.5 V
Falling Edge Jitter at 2.5 V
Rising Edge Jitter at 3.3 V
Falling Edge Jitter at 3.3 V
Rising Edge Jitter at 5 V
Falling Edge Jitter at 5 V
600
0
25
50
Data Rate (Mbps)
75
100
D007
TA = 25°C
图7-17. Peak-to-Peak Output Jitter vs Data Rate
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Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input
Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3 ns, ZO
= 50 Ω. At the input, a 50-Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
See Note B
V
CC
V
CC
V
1.7 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power-supply ramp rate = 10 mV/ns
图8-2. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
V
OH
or V
OL
C
L
œ
See Note A
GNDI
GNDO
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-3. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO776x-Q1 family of devices uses an ON-OFF keying (OOK) modulation scheme to transmit the digital
data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the
barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The
ISO776x-Q1 family of devices also incorporates advanced circuit techniques to maximize the CMTI performance
and minimize the radiated emissions because of the high-frequency carrier and IO buffer switching. The
conceptual block diagram of a digital capacitive isolator, 图 8-1, shows a functional block diagram of a typical
channel. 图8-2 shows a conceptual detail of how the ON-OFF keying scheme works.
8.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Copyright © 2016, Texas Instruments Incorporated
图8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
TX IN
Carrier signal through
isolation barrier
RX OUT
图8-2. ON-OFF Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
表8-1 lists the device features.
表8-1. Device Features
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PART NUMBER
CHANNEL DIRECTION
PACKAGE
RATED ISOLATION(1)
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
6 Forward,
0 Reverse
ISO7760-Q1
100 Mbps
100 Mbps
100 Mbps
100 Mbps
100 Mbps
100 Mbps
100 Mbps
100 Mbps
High
Low
High
Low
High
Low
High
Low
6 Forward,
0 Reverse
ISO7760-Q1 with F suffix
ISO7761-Q1
5 Forward,
1 Reverse
5 Forward,
1 Reverse
ISO7761-Q1 with F suffix
ISO7762-Q1
4 Forward,
2 Reverse
4 Forward,
2 Reverse
ISO7762-Q1 with F suffix
ISO7763-Q1
3 Forward,
3 Reverse
3 Forward,
3 Reverse
ISO7763-Q1 with F suffix
(1) See 节7.7 for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO776x-
Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
表8-2 lists the functional modes for the ISO776x-Q1.
表8-2. Function Table
INPUT
(INx)(3)
OUTPUT
(OUTx)
(1)
VCCI
VCCO
COMMENTS
H
L
H
L
Normal Operation:
A channel output assumes the logic state of the input.
PU
PU
Default mode: When INx is open, the corresponding channel output goes to its
default logic state. Default is High for ISO776x-Q1 and Low for ISO776x-Q1
with F suffix.
Open
Default
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. Default is High for ISO776x-Q1 and
Low for ISO776x-Q1 with F suffix.
PD
X
PU
PD
X
X
Default
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined (2)
.
Undetermined
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥2.25 V); PD = Powered down (VCC ≤1.7 V); X = Irrelevant;
H = High level; L = Low level
(2) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
Input (Devices with F suffix)
V
V
V
V
CCI
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
Output
V
CCO
~20 ꢀ
OUTx
Copyright © 2016, Texas Instruments Incorporated
图8-3. Device I/O Schematics
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO776x-Q1 family of devices is a high-performance, six-channel digital isolators. The ISO776x-Q1 family of
devices uses single-ended CMOS-logic switching technology. The voltage range is from 2.25 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the single-ended
design structure, digital isolators do not conform to any specific interface standard and are only intended for
isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data
controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
图 9-1 shows the isolated serial-peripheral interface (SPI) and controller-area network (CAN) interface
implementation.
VS
10 ꢀF
3.3 V
2
MBR0520L
Vcc
1:1.33
ISO 3.3V
3
1
1
5
D2
D1
IN
OUT
10 ꢀF
TPS76333-Q1
2
4
6
SN6501-Q1
VIN
VOUT
0.1 ꢀF
10 ꢀF
3
2
EN
GND
1 µF
REF5025A-Q1
GND
22 µF
MBR0520L
GND
GND
4
5
ISO Barrier
0.1 ꢀF
0.1 µF
0.1 ꢀF
8
7
36
5
4
16
1
0.1 ꢀF
AINP MXO +VBD +VA REFP
31
VCC2
28
VCC1
CS
CH0
32
33
34
2
3
SCLK
SDI
16 Analog
Inputs
INA
OUTA
OUTB
29, 57
ADS7953-Q1
44
15
14
INB
11
SPICLKA
VDDIO
SDO
CH15
33
BDGND AGND
27 1, 22
REFM
30
4
6
ISO7762-Q1
INC
SPISIMOA
SPISOMIA
OUTC
INE
36
34
13
OUTE
11
10
TMS320F28035Q
7
5
CANRXA
CANTXA
INF
OUTF
IND
0.1 ꢀF
26
25
OUTD
12
3
VSS
VCC
RS
8
GND1
8
GND2
9
10 ꢁ (optional)
6, 28
4
1
R
CANH
CAN Bus
7
6
SN65HVD231Q-Q1
CANL
Vref
10 ꢁ (optional)
D
GND
5
SM712
2
4.7 nF /
2 kV
Copyright © 2016, Texas Instruments Incorporated
Multiple pins and discrete components omitted for clarity purpose.
图9-1. Isolated SPI and CAN Interface
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9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETER
VALUE
2.25 to 5.5 V
0.1 µF
Supply voltage, VCC1 and VCC2
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO776x-Q1 family of devices only requires two external bypass capacitors to operate.
0.1 µF
0.1 µF
VCC1
1
16
VCC2
2
3
INA
INB
15
14
OUTA
OUTB
13
OUTC
INC
4
IND
INE
12
11
10
9
OUTD
OUTE
5
6
7
8
OUTF
INF
GND1
GND2
图9-2. Typical ISO7761-Q1 Circuit Hook-up
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9.2.3 Application Curves
The typical eye diagram of the ISO776x-Q1 family of devices indicates low jitter and a wide open eye at the
maximum data rate of 100 Mbps.
图9-4. Eye Diagram at 100 Mbps PRBS 216 –1
图9-3. Eye Diagram at 100 Mbps PRBS 216 –1
Data,
Data,
3.3 V and 25°C
5 V and 25°C
图9-5. Eye Diagram at 100 Mbps PRBS 216 –1 Data,
2.5 V and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 9-6 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 50% for
lifetime which translates into minimum required insulation lifetime of 30 years at a working voltage that's 20%
higher than the specified value.
图 9-7 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 169 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1500 VRMS and DBQ-16 package up to
400 VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 169 years.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图9-6. Test Setup for Insulation Lifetime Measurement
图9-7. Insulation Lifetime Projection Data
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505. For such applications, detailed power supply design and transformer selection recommendations are
available in the SN6501 Transformer Driver for Isolated Power Supplies data sheet or the SN6505 Low-Noise 1-
A Transformer Drivers for Isolated Power Supplies data sheet.
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ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 11-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide application report.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
图11-1. Layout Example Schematic
Copyright © 2022 Texas Instruments Incorporated
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ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
www.ti.com.cn
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide application report
• Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
• Texas Instruments, Isolation Glossary
• Texas Instruments, TMS320F2803xPiccolo™ Microcontrollers data sheet
• Texas Instruments, ADS7953-Q1 Automotive 12-Bit, 1MSPS, 16-Channel Single-Ended Micropower, Serial
Interface ADC data sheet
• Texas Instruments, REF50xxA-Q1 Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN65HVD231Q-Q1 3.3-V CAN Transceiver data sheet
• Texas Instruments, TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
ISO7760-Q1
ISO7761-Q1
ISO7762-Q1
ISO7763-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
Piccolo™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
Copyright © 2022 Texas Instruments Incorporated
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ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
www.ti.com.cn
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: ISO7760-Q1 ISO7761-Q1 ISO7762-Q1 ISO7763-Q1
ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
www.ti.com.cn
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
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ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
16X (0.6)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
9
8
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
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ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1
www.ti.com.cn
ZHCSJ25C –NOVEMBER 2018 –REVISED OCTOBER 2022
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
R0.05 TYP
14X (1.27)
8
9
8
9
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Product Folder Links: ISO7760-Q1 ISO7761-Q1 ISO7762-Q1 ISO7763-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7760FQDBQQ1
ISO7760FQDBQRQ1
ISO7760FQDWQ1
ISO7760FQDWRQ1
ISO7760QDBQQ1
ISO7760QDBQRQ1
ISO7760QDWQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
DBQ
DBQ
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7760FQ
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
7760FQ
ISO7760FQ
ISO7760FQ
7760Q
DW
DBQ
DBQ
DW
7760Q
ISO7760Q
ISO7760Q
7761FQ
ISO7760QDWRQ1
ISO7761FQDBQQ1
ISO7761FQDBQRQ1
ISO7761FQDWQ1
ISO7761FQDWRQ1
ISO7761QDBQQ1
ISO7761QDBQRQ1
ISO7761QDWQ1
DW
DBQ
DBQ
DW
7761FQ
ISO7761FQ
ISO7761FQ
7761Q
DW
DBQ
DBQ
DW
7761Q
ISO7761Q
ISO7761Q
7762FQ
ISO7761QDWRQ1
ISO7762FQDBQQ1
ISO7762FQDBQRQ1
ISO7762FQDWQ1
ISO7762FQDWRQ1
DW
DBQ
DBQ
DW
7762FQ
ISO7762FQ
ISO7762FQ
DW
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7762QDBQQ1
ISO7762QDBQRQ1
ISO7762QDWQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
DBQ
DBQ
DW
16
16
16
16
16
16
16
16
16
16
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7762Q
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
7762Q
ISO7762Q
ISO7762Q
7763FQ
ISO7762QDWRQ1
ISO7763FQDBQQ1
ISO7763FQDBQRQ1
ISO7763FQDWQ1
ISO7763FQDWRQ1
ISO7763QDBQQ1
ISO7763QDBQRQ1
ISO7763QDWQ1
DW
DBQ
DBQ
DW
7763FQ
ISO7763FQ
ISO7763FQ
7763Q
DW
DBQ
DBQ
DW
7763Q
ISO7763Q
ISO7763Q
ISO7763QDWRQ1
DW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2022
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7760-Q1, ISO7761-Q1, ISO7762-Q1, ISO7763-Q1 :
Catalog : ISO7760, ISO7761, ISO7762, ISO7763
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7760FQDBQRQ1
ISO7760FQDWRQ1
ISO7760QDBQRQ1
ISO7760QDWRQ1
ISO7761FQDBQRQ1
ISO7761FQDWRQ1
ISO7761QDBQRQ1
ISO7761QDWRQ1
ISO7762FQDBQRQ1
ISO7762FQDWRQ1
ISO7762QDBQRQ1
ISO7762QDWRQ1
ISO7763FQDBQRQ1
ISO7763FQDWRQ1
ISO7763QDBQRQ1
ISO7763QDWRQ1
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
DBQ
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
6.4
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
6.4 5.2
10.75 10.7
5.2
2.1
2.7
2.1
2.7
2.1
2.7
2.1
2.7
2.1
2.7
2.1
2.7
2.1
2.7
2.1
2.7
8.0
12.0
8.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
DBQ
DW
12.0
8.0
DBQ
DW
12.0
8.0
DBQ
DW
12.0
8.0
DBQ
DW
12.0
8.0
DBQ
DW
12.0
8.0
DBQ
DW
12.0
8.0
DBQ
DW
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7760FQDBQRQ1
ISO7760FQDWRQ1
ISO7760QDBQRQ1
ISO7760QDWRQ1
ISO7761FQDBQRQ1
ISO7761FQDWRQ1
ISO7761QDBQRQ1
ISO7761QDWRQ1
ISO7762FQDBQRQ1
ISO7762FQDWRQ1
ISO7762QDBQRQ1
ISO7762QDWRQ1
ISO7763FQDBQRQ1
ISO7763FQDWRQ1
ISO7763QDBQRQ1
ISO7763QDWRQ1
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
DBQ
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
2500
2000
350.0
350.0
367.0
350.0
367.0
350.0
367.0
350.0
367.0
350.0
367.0
350.0
350.0
350.0
367.0
350.0
350.0
350.0
367.0
350.0
367.0
350.0
367.0
350.0
367.0
350.0
367.0
350.0
350.0
350.0
367.0
350.0
43.0
43.0
38.0
43.0
38.0
43.0
38.0
43.0
38.0
43.0
38.0
43.0
43.0
43.0
38.0
43.0
DBQ
DW
DBQ
DW
DBQ
DW
DBQ
DW
DBQ
DW
DBQ
DW
DBQ
DW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Feb-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7760FQDBQQ1
ISO7760FQDWQ1
ISO7760QDBQQ1
ISO7760QDWQ1
ISO7761FQDBQQ1
ISO7761FQDWQ1
ISO7761QDBQQ1
ISO7761QDWQ1
ISO7762FQDBQQ1
ISO7762FQDWQ1
ISO7762QDBQQ1
ISO7762QDWQ1
ISO7763FQDBQQ1
ISO7763FQDWQ1
ISO7763QDBQQ1
ISO7763QDWQ1
DBQ
DW
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
SSOP
SOIC
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
75
40
75
40
75
40
75
40
75
40
75
40
75
40
75
40
505.46
506.98
505.46
506.98
505.46
506.98
505.46
506.98
505.46
506.98
505.46
506.98
505.46
506.98
505.46
506.98
6.76
12.7
6.76
12.7
6.76
12.7
6.76
12.7
6.76
12.7
6.76
12.7
6.76
12.7
6.76
12.7
3810
4826
3810
4826
3810
4826
3810
4826
3810
4826
3810
4826
3810
4826
3810
4826
4
6.6
4
DBQ
DW
6.6
4
DBQ
DW
6.6
4
DBQ
DW
6.6
4
DBQ
DW
6.6
4
DBQ
DW
6.6
4
DBQ
DW
6.6
4
DBQ
DW
6.6
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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