ISO7810DWR [TI]
高隔离额定值、单通道、增强型数字隔离器 | DW | 16 | -55 to 125;型号: | ISO7810DWR |
厂家: | TEXAS INSTRUMENTS |
描述: | 高隔离额定值、单通道、增强型数字隔离器 | DW | 16 | -55 to 125 |
文件: | 总26页 (文件大小:1583K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ISO7810, ISO7810F
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
ISO7810 高性能 8000 VPK 增强型单通道数字隔离器
1 特性
2 应用范围
1
•
•
•
•
•
•
信号传输速率:高达 100Mbps
•
•
•
•
•
•
工业自动化
电机控制
宽电源电压范围:2.25V 至 5.5V
2.25V 至 5.5V 电平转换
电源
宽温度范围:-55°C 至 125°C
太阳能逆变器
医疗设备
低功耗,每通道电流典型值为 1.8mA(1Mbps 时)
低传播延迟:典型值 11ns
(5V 电源供电时)
混合动力电动汽车
3 说明
•
•
•
行业领先的 CMTI:±100kV/μs
优异的电磁兼容性 (EMC)
7810ISO 是一款高性能单通道数字隔离器,隔离电压
高达 8000 VPK。 该器件已通过符合 VDE、CSA 和
CQC 标准的增强型隔离认证。 在隔离 CMOS 或者
LVCMOS 数字 I/O 时,该隔离器可提供高电磁抗扰度
和低辐射,且具有低功耗特性。 每个隔离通道的逻辑
输入和输出缓冲器均由二氧化硅 (SiO2) 绝缘隔栅分离
开来。 如果出现输入功率或信号丢失,ISO7810 器件
默认输出“高”电平,ISO7810F 器件默认输出“低”电
平。 更多详细信息,请参见器件功能模式。与隔离式
电源一起使用时,此器件可防止数据总线或者其它电路
上的噪音电流进入本地接地,以及干扰或损坏敏感电
路。 凭借创新的芯片设计和布线技术,ISO7810 的电
磁兼容性得到了显著增强,从而可确保提供系统级
ESD、EFT 和浪涌保护并符合辐射标准。 ISO7810 采
用 16 引脚 SOIC 宽体 (DW) 封装。
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪
涌保护
•
•
•
•
低辐射
隔离隔栅寿命:> 25 年
宽体 (DW) 小外形尺寸集成电路 (SOIC)-16 封装
安全及管理批准:
–
8000 VPK VIOTM 和 2121 VPK VIORM 增强型隔
离,符合 DIN V VDE V 0884-10 (VDE V 0884-
10):2006-12 标准
–
–
–
符合 UL 1577 标准且长达 1 分钟的 5.7kVRMS
隔离
CSA 组件接受通知 5A,IEC 60950-1、IEC
60601-1 和 IEC 61010-1 终端设备标准
通过 GB4943.1-2011 CQC 认证
器件信息(1)
部件号
ISO7810
ISO7810F
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
封装
封装尺寸(标称值)
SOIC,DW (16) 10.30mm x 7.50mm
简化电路原理图
ë//h
ë//L
Lsolation
/apacitor
Lbx
hÜÇx
Db5L
Db5h
(1)
(2)
V
CCI 和 GNDI 分别是输入通道的电源和接地连接。
CCO 和 GNDO 分别是输出通道的电源和接地连接。
V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEP1
ISO7810, ISO7810F
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
目录
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 15
Applications and Implementation ...................... 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Rating............................................................. 5
6.6 Electrical Characteristics, 5 V ................................... 5
6.7 Electrical Characteristics, 3.3 V ................................ 6
6.8 Electrical Characteristics, 2.5 V ................................ 6
6.9 Switching Characteristics, 5 V .................................. 7
6.10 Switching Characteristics, 3.3 V ............................. 7
6.11 Switching Characteristics, 2.5 V ............................. 7
6.12 Typical Characteristics............................................ 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 PCB Material......................................................... 19
11.2 Layout Guidelines ................................................. 19
11.3 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 文档支持................................................................ 20
12.2 相关链接................................................................ 20
12.3 社区资源................................................................ 20
12.4 商标....................................................................... 20
12.5 静电放电警告......................................................... 20
12.6 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
7
8
4 修订历史记录
Changes from Original (July 2015) to Revision A
Page
•
已从“单页产品预览”更改为“量产”数据表 ................................................................................................................................. 1
2
Copyright © 2015, Texas Instruments Incorporated
ISO7810, ISO7810F
www.ti.com.cn
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
DW Package
16-Pin (SOIC)
Top View
GND1
GND2
1
16
15
14
13
12
11
10
9
NC
NC
2
VCC1
VCC2
3
INA
OUTA
4
NC
NC
5
NC
NC
NC
6
GND1
7
NC
GND2
8
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND1
GND2
INA
NO.
1, 7
9, 16
4
–
–
I
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
2, 5, 6, 8, 10 , 11,
12, 15
NC
–
Not connected
OUTA
VCC1
VCC2
13
3
O
–
Output, channel A
Power supply, VCC1
Power supply, VCC2
14
–
Copyright © 2015, Texas Instruments Incorporated
3
ISO7810, ISO7810F
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.5
–0.5
-15
MAX
UNIT
V
Supply voltage(2)
Voltage
VCC1, VCC2
6
VCC + 0.5(3)
15
INx, OUTx
IO
V
Output Current
Storage temperature, Tstg
mA
°C
–65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins
±6000
V
(1)
VESD
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±1500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
2.25
-4
TYP
MAX
UNIT
VCC1, VCC2
Supply voltage
5.5
V
VCCO(1) = 5 V
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 5 V
IOH
High-level output current
-2
mA
mA
-1
4
IOL
Low-level output current
VCCO = 3.3 V
VCCO = 2.5 V
2
1
(1)
VIH
VIL
tui
High-level input voltage
Low-level input voltage
Input pulse duration
Signaling rate
0.7 x VCCI
VCCI
V
V
0
7
0.3 x VCCI
ns
DR
TJ
0
100
150
125
Mbps
°C
Junction temperature(2)
-55
-55
TA
Ambient temperature
25
°C
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
4
Copyright © 2015, Texas Instruments Incorporated
ISO7810, ISO7810F
www.ti.com.cn
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
6.4 Thermal Information
SOIC
UNIT
THERMAL METRIC
16 Pins (DW)
RθJA
Junction-to-ambient thermal resistance
84.7
47.3
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
49.4
°C/W
19.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
48.8
n/a
RθJC(bottom)
6.5 Power Rating
VALUE
100
40
UNIT
PD
Maximum power dissipation by ISO7810
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
PD1
PD2
Maximum power dissipation by side-1 of ISO7810 CL = 15 pF, input a 50 MHz 50% duty cycle
mW
square wave
Maximum power dissipation by side-2 of ISO7810
60
6.6 Electrical Characteristics, 5 V
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
VOL
VI(HYS)
IIH
High-level output voltage
Low-level output voltage
Input threshold voltage hysteresis
High-level input current
Low-level input current
IOH = –4 mA; see Figure 7
VCCX(1) – 0.4 VCCX(1) – 0.2
V
IOL = 4 mA; see Figure 7
0.2
0.4
10
V
V
(1)
0.1 x VCCX
VIH = VCCX(1) at INx or ENx
VIL = 0 V at INx or ENx
μA
IIL
-10
CMTI
ICC1
Common-mode transient immunity VI = VCCX(1) or 0 V; see Figure 9
50
100
0.6
kV/μs
DC signal: VI = 0 V (Devices with
1.1
1.1
2.7
1.1
suffix F) , VI = VCCX (Devices without
suffix F)
ICC2
ICC1
ICC2
0.6
1.8
0.7
Supply current
Supply current
DC Signal
mA
mA
DC signal: VI = VCCX (Devices with
suffix F) , VI = 0 V (Devices without
suffix F)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.2
0.6
1.2
1.1
1.3
5.7
1.9
1.1
1.9
1.6
2
1 Mbps
AC Signal: All channels switching with
square wave clock input;
CL = 15 pF
10 Mbps
100 Mbps
6.7
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
Copyright © 2015, Texas Instruments Incorporated
5
ISO7810, ISO7810F
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
6.7 Electrical Characteristics, 3.3 V
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCX(1) – 0.4 VCCX(1) – 0.2
0.2
TYP
MAX UNIT
VOH
VOL
VI(HYS)
IIH
High-level output voltage
Low-level output voltage
Input threshold voltage hysteresis
High-level input current
Low-level input current
IOH = –2 mA; see Figure 7
V
IOL = 2 mA; see Figure 7
0.4
10
V
V
(1)
0.1 x VCCX
VIH = VCCX(1) at INx or ENx
VIL = 0 V at INx or ENX
μA
IIL
-10
CMTI
ICC1
Common-mode transient immunity VI = VCCX or 0 V; see Figure 9
DC signal: VI = 0 V (Devices with
50
100
0.6
kV/μs
1.1
1
suffix F) , VI = VCCX (Devices without
suffix F)
ICC2
ICC1
ICC2
0.6
1.8
0.6
Supply current
DC Signal
mA
mA
DC signal: VI = VCCx (Devices with
suffix F) , VI = 0 V(Devices without
suffix F)
2.7
1.1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.2
0.6
1.2
0.9
1.3
4.1
1.9
1.1
1.9
1.4
2
1 Mbps
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
Supply current
10 Mbps
100 Mbps
4.9
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
6.8 Electrical Characteristics, 2.5 V
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
VOL
VI(HYS)
IIH
High-level output voltage
Low-level output voltage
Input threshold voltage hysteresis
High-level input current
Low-level input current
IOH = –1 mA; see Figure 7
VCCX(1) – 0.4 VCCX(1) – 0.2
V
IOL = 1 mA; see Figure 7
0.2
0.4
10
V
V
(1)
0.1 x VCCX
VIH = VCCX(1) at INx or ENx
VIL = 0 V at INx or ENx
μA
IIL
-10
CMTI
ICC1
Common-mode transient immunity VI = VCCX or 0 V; see Figure 9
DC signal: VI = 0 V (Devices with
70
100
0.6
kV/μs
1.1
1
suffix F) , VI = VCCX (Devices without
suffix F)
ICC2
ICC1
ICC2
0.6
1.8
0.6
Supply current
DC Signal
mA
mA
DC signal: VI = VCCX (Devices with
suffix F) , VI = 0 V(Devices without
suffix F)
2.7
1.1
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.2
0.6
1.2
0.9
1.3
3.3
1.9
1.1
1.9
1.3
2
1 Mbps
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
Supply current
10 Mbps
100 Mbps
4.1
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
6
Copyright © 2015, Texas Instruments Incorporated
ISO7810, ISO7810F
www.ti.com.cn
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
6.9 Switching Characteristics, 5 V
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
10.7
0.6
MAX UNIT
tPLH, tPHL
PWD(1)
6
16
ns
4.6
See Figure 7
|
(2)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
4.5
3.9
3.9
ns
ns
tr
tf
2.4
2.4
See Figure 7
Measured from the time VCC
goes below 1.7 V. See Figure 8
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
1
9
μs
216 - 1 PRBS data at 100 Mbps
ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.10 Switching Characteristics, 3.3 V
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10.8
0.7
MAX
16
4.7
4.5
3
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
6
See Figure 7
ns
Pulse width distortion |tPHL – tPLH
|
(2)
tsk(pp)
Part-to-part skew time
tr
tf
Output signal rise time
Output signal fall time
1.3
1.3
ns
See Figure 7
3
Measured from the time VCC goes
below 1.7 V. See Figure 8
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
1
9
μs
216 - 1 PRBS data at 100 Mbps
ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics, 2.5 V
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
11.7
0.7
MAX
17.5
4.7
UNIT
tPLH, tPHL
PWD(1)
7.5
See Figure 7
ns
|
(2)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
4.5
tr
tf
1.8
1.8
3.5
ns
See Figure 7
3.5
Measured from the time VCC goes
below 1.7 V. See Figure 8
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
1
9
μs
216 - 1 PRBS data at 100 Mbps
ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2015, Texas Instruments Incorporated
7
ISO7810, ISO7810F
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
6.12 Typical Characteristics
12
8
6
4
2
0
ICC1 at 2.5 V (mA)
ICC2 at 2.5 V (mA)
ICC1 at 3.3 V (mA)
ICC2 at 3.3 V (mA)
ICC1 at 5 V (mA)
ICC1 at 2.5 V (mA)
ICC2 at 2.5 V (mA)
ICC1 at 3.3 V (mA)
ICC2 at 3.3 V (mA)
ICC1 at 5 V (mA)
ICC2 at 5 V (mA)
8
ICC2 at 5 V (mA)
4
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Data Rate (Mbps)
Data Rate (Mbps)
D001
D002
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 1. Supply Current vs Data Rate (with 15 pF Load)
Figure 2. Supply Current vs Data Rate (with No Load)
6
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC at 2.5V
VCC at 3.3V
VCC at 5.0V
5
4
3
2
VCC at 2.5V
VCC at 3.3V
VCC at 5.0V
1
0
-15
-10
-5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
D001
D001
TA = 25°C
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output
Current
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
2.25
15
14
13
12
11
10
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
9
tPLH at 2.5 V
8
7
6
5
tPHL at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
tPLH at 5 V
tPHL at 5 V
-50
0
50
100
150
-60
-30
0
30
60
90
120
Free-Air Temperature (oC )
Free-Air Temperature (oC )
D001
D006
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
Figure 6. Propagation Delay Time vs Free-Air Temperature
8
Copyright © 2015, Texas Instruments Incorporated
ISO7810, ISO7810F
www.ti.com.cn
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
7 Parameter Measurement Information
VCCI
VI
50%
50%
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator
Note A
50 W
VI
CL
VOH
VOL
90%
10%
Note B
50%
50%
VO
tr
tf
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
V
V
CC
CC
2.7 V
V
I
0 V
V
IN
OUT
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
t
V
fs
O
OH
fs high
fs low
50%
V
O
C
L
V
OL
NOTE A
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 μF 1ꢀ
C = 0.1 μF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL
Note A
VOH or VOL
–
GNDI
GNDO
–
+
VCM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Common-Mode Transient Immunity Test Circuit
Copyright © 2015, Texas Instruments Incorporated
9
ISO7810, ISO7810F
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
ISO7810 employs an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon
dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one
digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after
advanced signal conditioning and produces the output through a buffer stage. These devices also incorporates
advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the
high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator,
Figure 10, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
RECEIVER
TRANSMITTER
OOK
MODULATION
SiO2 based
Capacitive
Isolation
TX SIGNAL
CONDITIONING
TX IN
RX OUT
RX SIGNAL
CONDITIONING
ENVELOPE
DETECTION
Barrier
EMISSIONS
REDUCTION
TECHNIQUES
OSCILLATOR
Figure 10. Conceptual Block Diagram of a Digital Capacitive Isolator
Also a conceptual detail of how the ON/OFF Keying scheme works is shown in Figure 11.
TX IN
Carrier signal
through
isolation barrier
RX OUT
Figure 11. On-Off Keying (OOK) Based Modulation Scheme
10
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ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
8.3 Feature Description
ISO7810 is available in two channel configurations and default output state options to enable a variety of
application uses.
PRODUCT
ISO7810
CHANNEL DIRECTION
1 Forward
RATED ISOLATION
5700 VRMS / 8000 VPK
5700 VRMS / 8000 VPK
MAX DATA RATE
100 Mbps
DEFAULT OUTPUT
(1)
(1)
High
Low
ISO7810F
1 Forward
100 Mbps
(1) See the Regulatory Information section for detailed isolation ratings.
8.3.1 High Voltage Feature Description
8.3.1.1 Package Insulation and Safety-Related Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Shortest terminal-to-terminal distance
through air
MIN
TYP MAX
UNIT
L(I01)
L(I02)(1)
CTI
Minimum air gap (clearance)
DW-16
DW-16
8
mm
mm
V
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance
across the package surface
8
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
600
VIO = 500 V, TA = 25°C
1012
1011
Ω
Ω
RIO
Isolation resistance, input to output(2)
VIO = 500 V, 100°C ≤ TA ≤ max
CIO
CI
Barrier capacitance, input to output(2) VIO = 0.4 x sin (2πft), f = 1 MHz
Input capacitance(3)
VI = VCC/2 + 0.4 x sin (2πft), f = 1 MHz, VCC = 5 V
2
2
pF
pF
(1) Per JEDEC package dimensions.
(2) All pins on each side of the barrier tied together creating a two-terminal device.
(3) Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
Copyright © 2015, Texas Instruments Incorporated
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ISO7810, ISO7810F
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www.ti.com.cn
8.3.1.2 Insulation Characteristics
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
μm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
21
1500
2121
VRMS
VDC
VIOWM
Maximum isolation working voltage
Time dependent dielectric breakdown (TDDB) test
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VTEST = VIOTM
VIOTM
Maximum transient isolation voltage
t = 60 sec (qualification)
t= 1 sec (100% production)
8000
VPK
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM = 12800 VPK (qualification)
VIOSM
VIORM
Maximum surge isolation voltage
8000
2121
VPK
VPK
Maximum repetitive peak isolation voltage
Method a, After Input/Output safety test subgroup
2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
2545
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
VPR
Input-to-output test voltage
VPK
3394
3977
Method b1,After environmental tests subgroup 1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
RS
Isolation resistance
Pollution degree
VIO = 500 V at TS
>109
2
Ω
UL 1577
VISO
VTEST = VISO = 5700 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 x VISO = 6840 VRMS , t = 1 sec (100%
production)
Withstanding isolation voltage
5700
VRMS
(1) Climatic Classification 55/125/21
8.3.1.3 IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Material group
SPECIFICATION
Basic isolation group
I
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I–IV
I–III
Installation classification
DW package
12
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
8.3.1.4 Regulatory Information
DW package certifications are complete.
VDE
CSA
UL
CQC
Certified according to DIN V VDE Approved under CSA
Recognized under UL 1577
Component Recognition
Program
V 0884-10 (VDE V 0884-
Component Acceptance Notice
Certified according to GB 4943.1-
2011
10):2006-12 and DIN EN 60950- 5A, IEC 60950-1, IEC 61010-1,
1 (VDE 0805 Teil 1):2011-01
and IEC 60601-1
Reinforced insulation per CSA
61010-1-12 and IEC 61010-1
3rd Ed., 300 VRMS max working
voltage;
Reinforced insulation
Maximum transient isolation
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.,
voltage, 8000 VPK
;
Reinforced Insulation, Altitude ≤
5000 m, Tropical Climate, 250 VRMS
maximum working voltage
(1)
Maximum repetitive peak
isolation voltage, 2121 VPK
Maximum surge isolation
voltage, 8000 VPK
Single protection, 5700 VRMS
800 VRMS max working voltage
(pollution degree 2, material
group I);
;
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage
Master contract number:
220991
Certificate number:
CQC15001121716
Certificate number: 40040142
File number: E181974
(1) Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.
Copyright © 2015, Texas Instruments Incorporated
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ISO7810, ISO7810F
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8.3.1.5 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
268
410
537
UNIT
R
R
R
R
θJA = 84.7°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
θJA = 84.7°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
θJA = 84.7°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C
θJA = 84.7°C/W, TJ = 150°C, TA = 25°C
Safety input, output, or supply
current for DW-16 package
IS (DW-16)
mA
PS
TS
Safety input, output, or total
power
mW
°C
1476
150
Maximum case temperature
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware
determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal
Informationis that of a device installed on a High-K test board for Leaded Surface Mount Packages. The
power is the recommended maximum input voltage times the current. The junction temperature is then the
ambient temperature plus the power times the junction-to-air thermal resistance.
600
500
400
300
200
100
0
1600
1400
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Power
0
50
100
150
200
0
50
100
150
200
Ambient Temperature (èC)
Ambient Temperature (èC)
D014
D015
Figure 12. Thermal Derating Curve per VDE for
DW-16 Package
Figure 13. Thermal Derating Curve for Safety Limiting
Power per VDE
14
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ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
8.4 Device Functional Modes
ISO7810DW functional modes are shown in Table 1.
Table 1. ISO7810DW Function Table(1)
INPUT
(INx)(2)
OUTPUT
(OUTx)
VCCI
VCCO
COMMENTS
H
L
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU
PU
Default mode: When INx is open, the corresponding channel output goes to its
default high logic state. Default= High for ISO7810 and Low for ISO7810F.
Open
Default
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option.Default= High for ISO7810 and Low
for ISO7810F.
PD
X
PU
PD
X
Default
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output assumes
the selected default state.
(3)
When VCCO is unpowered, a channel output is undetermined
.
X
Undetermined
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without suffix F)
Input (Devices with suffix F)
V
V
V
V
CCI
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
1.5 MW
985 W
985 W
INx
INx
1.5 MW
Output
V
CCO
~20 W
OUTx
Figure 14. Device I/O Schematics
Copyright © 2015, Texas Instruments Incorporated
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ISO7810, ISO7810F
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www.ti.com.cn
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7810 is a high-performance, dual-channel digital isolator with 5.7 kVRMS isolation voltage. It utilizes
single-ended CMOS-logic switching technology. Its supply voltage range is from 2.25 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type
or standard.
9.2 Typical Application
ISO7810DW can be used with Texas Instruments' mixed signal micro-controller, gatedrivers, transformer driver,
and voltage regulator to create an isolated MOSFET/IGBT drive circuit.
Figure 15. Low Side Gate Driver Hookup
9.2.1 Design Requirements
For the ISO7810, use the parameters shown in Table 2.
Table 2. Design Parameters
PARAMETER
VALUE
2.25 V to 5.5 V
0.1 µF
Supply voltage
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
16
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ISO7810, ISO7810F
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ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
9.2.2 Detailed Design Procedure
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO7810 only needs two external bypass capacitors to operate.
VCC1
VCC2
GND1
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
GND2
m
0.1 F
m
0.1 F
NC
NC
GND1
GND2
VCC1
VCC2
INA
INA
OUTA
OUTA
NC
NC
NC
NC
NC
GND1
GND1
NC
GND2
GND2
Figure 16. Typical ISO7810DW Circuit Hook-up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7810
incorporate many chip-level design improvements for overall system robustness. Some of these improvements
include:
•
•
•
•
Robust ESD protection for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
Copyright © 2015, Texas Instruments Incorporated
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ISO7810, ISO7810F
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www.ti.com.cn
9.2.3 Application Performance Curve
Typical eye diagram of ISO7810 indicate low jitter and wide open eye at the maximum data rate of 100 Mbps.
Figure 17. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0) .
18
Copyright © 2015, Texas Instruments Incorporated
ISO7810, ISO7810F
www.ti.com.cn
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
11 Layout
11.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 18). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.3 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces , pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 18. Layout Example
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19
ISO7810, ISO7810F
ZHCSE63A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
请参见隔离术语表 (SLLA353)
12.2 相关链接
下面的表格列出了快速访问链接。 范围包括技术文档、支持和社区资源、工具和软件,以及样片或购买的快速访
问。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
ISO7810
ISO7810F
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
20
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7810DW
ISO7810DWR
ISO7810DWW
ISO7810DWWR
ISO7810FDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
16
16
16
16
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
ISO7810
2000 RoHS & Green
45 RoHS & Green
1000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
45 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO7810
ISO7810
ISO7810
ISO7810F
ISO7810F
ISO7810F
ISO7810F
DWW
DWW
DW
ISO7810FDWR
ISO7810FDWW
ISO7810FDWWR
DW
DWW
DWW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7810DWR
ISO7810DWWR
ISO7810FDWR
ISO7810FDWWR
SOIC
SOIC
SOIC
SOIC
DW
DWW
DW
16
16
16
16
2000
1000
2000
1000
330.0
330.0
330.0
330.0
16.4
24.4
16.4
24.4
10.75 10.7
18.0 10.0
10.75 10.7
18.0 10.0
2.7
3.0
2.7
3.0
12.0
20.0
12.0
20.0
16.0
24.0
16.0
24.0
Q1
Q1
Q1
Q1
DWW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7810DWR
ISO7810DWWR
ISO7810FDWR
ISO7810FDWWR
SOIC
SOIC
SOIC
SOIC
DW
DWW
DW
16
16
16
16
2000
1000
2000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
DWW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7810DW
ISO7810DWW
ISO7810FDW
ISO7810FDWW
DW
DWW
DW
SOIC
SOIC
SOIC
SOIC
16
16
16
16
40
45
40
45
506.98
507
12.7
20
4826
5000
4826
5000
6.6
9
506.98
507
12.7
20
6.6
9
DWW
Pack Materials-Page 3
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