ISO7820FDW [TI]

高隔离额定值、双通道、2/0、增强型数字隔离器 | DW | 16 | -55 to 125;


型号：	ISO7820FDW
厂家：	TEXAS INSTRUMENTS
描述：	高隔离额定值、双通道、2/0、增强型数字隔离器 \| DW \| 16 \| -55 to 125
文件：	总24页 (文件大小：981K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

ISO7820 ISO7820F 高性能 8000 V_PK增强型双通道数字隔离器

1 特性

3 说明

•

信号传输速率：高达 100Mbps

ISO7820 是一款高性能双通道数字隔离器，隔离电压

高达 8000 V_PK。该器件已通过符合 VDE、CSA 和

CQC 标准的增强型隔离认证。在隔离 CMOS 或者

LVCMOS 数字 I/O 时，该隔离器可提供高电磁抗扰度

和低辐射，且具有低功耗特性。每个隔离通道的逻辑

输入和输出缓冲器均由二氧化硅 (SiO₂) 绝缘隔栅分离

开来。 ISO7820 具有两个正向通道，但没有反向通

道。如果出现输入功率或信号丢失，ISO7820 器件默

认输出“高”电平，ISO7820F 器件默认输出“低”电平。

更多详细信息与隔离式电源一起使用时，此器件可防止

数据总线或者其它电路上的噪音电流进入本地接地，以

及干扰或损坏敏感电路。凭借创新的芯片设计和布线

技术，ISO7820 的电磁兼容性得到了显著增强，从而

可确保提供系统级 ESD、EFT 和浪涌保护并符合辐射

标准。 ISO7820 采用 16 引脚 SOIC 宽体 (DW) 封

装。

宽电源范围：2.25V 至 5.5V

2.25V 至 5.5V 电平转换

宽温度范围：–55°C 至 125°C

低功耗，每通道电流典型值为 1.7mA（1Mbps 时）

低传播延迟：典型值 11ns

（5V 电源供电时）

•

行业领先的 CMTI：±100kV/μs

优异的电磁兼容性 (EMC)

系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪

涌保护

•

低辐射

隔离隔栅寿命：> 25 年

宽体 (DW) 小外形尺寸集成电路 (SOIC)-16 封装

安全及管理批准：中的安全及管理批准列表

–

8000 V_PKV_IOTM和 2121 V_PKV_IORM增强型隔

离，符合 DIN V VDE V 0884-10 (VDE V 0884-

10):2006-12 标准

器件信息⁽¹⁾

器件型号

ISO7820/

ISO7820F

封装

封装尺寸（标称值）

–

符合 UL 1577 标准且长达 1 分钟的 5.7kV_RMS

隔离

SOIC，DW (16) 10.30mm x 7.50mm

CSA 组件接受通知 5A，IEC 60950-1、IEC

60601-1 和 IEC 61010-1 终端设备标准

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

符合 GB4943.1-2011 的 CQC 认证

空白

2 应用范围

•

工业自动化

电机控制

电源

太阳能逆变器

医疗设备

混合动力电动汽车

中添加了注释 1 和 2

简化电路原理图

V_CCO

V_CCI

Isolation

Capacitor

INx

OUTx

GNDI

GNDO

(1)

(2)

_CCI和 GNDI 分别是输入通道的电源和接地连接。

_CCO和 GNDO 分别是输出通道的电源和接地连接。

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEP0

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram ....................................... 10

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 15

Applications and Implementation ...................... 16

9.1 Application Information............................................ 16

9.2 Typical Application .................................................. 16

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Power Rating............................................................. 5

6.6 Electrical Characteristics, 5 V ................................... 5

6.7 Electrical Characteristics, 3.3 V ................................ 6

6.8 Electrical Characteristics, 2.5 V ................................ 6

6.9 Switching Characteristics, 5 V .................................. 7

6.10 Switching Characteristics, 3.3 V ............................. 7

6.11 Switching Characteristics, 2.5 V ............................. 7

6.12 Typical Characteristics............................................ 8

Parameter Measurement Information .................. 9

Detailed Description ............................................ 10

10 Power Supply Recommendations ..................... 18

11 Layout................................................................... 19

11.1 PCB Material......................................................... 19

11.2 Layout Guidelines ................................................. 19

11.3 Layout Example .................................................... 19

12 器件和文档支持 ..................................................... 20

12.1 文档支持................................................................ 20

12.2 相关链接................................................................ 20

12.3 社区资源................................................................ 20

12.4 商标....................................................................... 20

12.5 静电放电警告......................................................... 20

12.6 Glossary................................................................ 20

13 机械、封装和可订购信息....................................... 20

4 修订历史记录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

日期

修订版本

注释

2015 年 7 月

最初发布版本。

ISO7820, ISO7820F

www.ti.com.cn

ZHCSDV2 –JULY 2015

5 Pin Configuration and Functions

DW Package

16-Pin (SOIC)

Top View

GND1

GND2

VCC1

INA

14 VCC2

OUTA

OUTB

INB

GND1

GND2

Pin Functions

NO.

1, 7

9, 16

I/O

DESCRIPTION

NAME

GND1

GND2

INA

–

Ground connection for V_CC1

Ground connection for V_CC2

Input, channel A

INB

Input, channel B

2, 6, 8, 10 ,11, 15

–

Not connected

OUTA

OUTB

VCC1

VCC2

Output, channel A

Output, channel B

Power supply, V_CC1

Power supply, V_CC2

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.5

-15

MAX

UNIT

Supply voltage⁽²⁾

V_CC1, V_CC2

V_CC+ 0.5⁽³⁾

Voltage

INx, OUTx

I_O

Output Current

°C

Surge Immunity

12.8

Maximum junction temperature, T_J

Storage temperature, T_stg

150

–65

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak

voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins

±6000

(1)

V_ESD

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

2.25

-4

TYP

MAX

UNIT

V_CC1, V_CC2

Supply voltage

5.5

V_CCO⁽¹⁾= 5 V

V_CCO= 3.3 V

V_CCO= 2.5 V

V_CCO= 5 V

I_OH

High-level output current

-2

-1

I_OL

Low-level output current

V_CCO= 3.3 V

V_CCO= 2.5 V

(1)

V_IH

V_IL

T_J

High-level input voltage

Low-level input voltage

Signaling rate

0.7 x V_CCI

V_CCI

0.3 x V_CCI

100

Mbps

°C

Junction temperature⁽²⁾

-55

150

T_A

Ambient temperature

125

°C

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) To maintain the recommended operating conditions for T_J, see the Thermal Information table.

ISO7820, ISO7820F

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ZHCSDV2 –JULY 2015

6.4 Thermal Information

THERMAL METRIC

DW (16 Pins)

UNIT

R_θJA

Junction-to-ambient thermal resistance

84.7

47.3

49.4

19.1

48.8

n/a

R_θJC(top)

R_θJB

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

ψ_JB

R_θJC(bottom)

6.5 Power Rating

VALUE

UNIT

P_D

Maximum power dissipation by ISO7820

100

V_CC1= V_CC2= 5.5 V, T_J= 150°C,

P_D1

P_D2

Maximum power dissipation by side-1 of ISO7820 C_L= 15 pF, input a 50 MHz 50% duty cycle

square wave

Maximum power dissipation by side-2 of ISO7820

6.6 Electrical Characteristics, 5 V

V_CC1= V_CC2= 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

V_OH

V_OL

V_I(HYS)

I_IH

High-level output voltage

Low-level output voltage

Input threshold voltage hysteresis

High-level input current

Low-level input current

I_OH= –4 mA; see Figure 7

V_CCx⁽¹⁾– 0.4

V_CCx– 0.2

0.2

I_OL= 4 mA; see Figure 7

0.4

(1)

0.1 x V_CCx

V_IH= V_CCx⁽¹⁾at INx

V_IL= 0 V at INx

μA

I_IL

-10

Common-mode transient

immunity

CMTI

V_I= V_CCx⁽¹⁾or 0 V; see Figure 9

100

kV/μs

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

0.9

1.2

3.2

1.3

2.1

1.3

2.1

2.3

2.7

11.9

1.3

1.8

4.6

DC signal: V_I= 0 V (Devices with suffix F) , V_I= V_CCI(Devices

without suffix F)

Supply current, DC Signal

Supply current

DC signal: V_I= V_CCI(Devices with suffix F) , V_I= 0 V(Devices

without suffix F)

1 Mbps

AC Signal: All channels

switching with square wave

clock input;

Supply current

10 Mbps

3.8

3.3

15.3

C_L= 15 pF

Supply current

100 Mbps

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

6.7 Electrical Characteristics, 3.3 V

V_CC1= V_CC2= 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

V_OH

V_OL

V_I(HYS)

I_IH

High-level output voltage

Low-level output voltage

Input threshold voltage hysteresis

High-level input current

Low-level input current

I_OH= –2 mA; see Figure 7

V_CCx⁽¹⁾– 0.4

V_CCx– 0.2

I_OL= 2 mA; see Figure 7

0.2

0.4

(1)

0.1 x V_CCx

V_IH= V_CCx⁽¹⁾at INx

V_IL= 0 V at INx

μA

I_IL

-10

Common-mode transient

immunity

CMTI

V_I= V_CCx⁽¹⁾or 0 V; see Figure 9

100

kV/μs

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

0.9

1.2

3.2

1.3

2.1

1.3

2.1

2.3

2.5

8.9

1.3

1.8

4.6

DC signal: V_I= 0 V (Devices with suffix F) , V_I= V_CCI(Devices

without suffix F)

Supply current, DC Signal

Supply current

DC signal: V_I= V_CCI(Devices with suffix F) , V_I= 0 V(Devices

without suffix F)

1 Mbps

AC Signal: All channels

switching with square wave

clock input;

Supply current

10 Mbps

3.8

3.2

11.5

C_L= 15 pF

Supply current

100 Mbps

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

6.8 Electrical Characteristics, 2.5 V

V_CC1= V_CC2= 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

V_OH

V_OL

V_I(HYS)

I_IH

High-level output voltage

Low-level output voltage

Input threshold voltage hysteresis

High-level input current

Low-level input current

I_OH= –1 mA; see Figure 7

V_CCx⁽¹⁾– 0.4

V_CCx– 0.2

I_OL= 1 mA; see Figure 7

0.2

0.4

(1)

0.1 x V_CCx

V_IH= V_CCx⁽¹⁾at INx

V_IL= 0 V at INx

μA

I_IL

-10

Common-mode transient

immunity

CMTI

V_I= V_CCx⁽¹⁾or 0 V; see Figure 9

100

kV/μs

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

0.9

1.2

3.2

1.3

2.1

1.3

2.1

1.8

2.4

1.3

1.8

4.6

DC signal: V_I= 0 V (Devices with suffix F) , V_I= V_CCI(Devices

without suffix F)

Supply current, DC Signal

Supply current

DC signal: V_I= V_CCI(Devices with suffix F) , V_I= 0 V(Devices

without suffix F)

1 Mbps

AC Signal: All channels

switching with square wave

clock input;

Supply current

10 Mbps

2.7

3.2

9.1

C_L= 15 pF

Supply current

100 Mbps

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

ISO7820, ISO7820F

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ZHCSDV2 –JULY 2015

6.9 Switching Characteristics, 5 V

V_CC1= V_CC2= 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

Propagation delay time

Pulse width distortion |t_PHL– t_PLH

TEST CONDITIONS

MIN

TYP

10.7

0.6

MAX UNIT

t_PLH, t_PHL

PWD⁽¹⁾

4.6

See Figure 7

(2)

t_sk(pp)

Part-to-part skew time

Output signal rise time

Output signal fall time

4.5

3.9

t_r

t_f

2.4

See Figure 7

Measured from the time V_CC

goes below 1.7 V. See Figure 8

t_fs

t_ie

Default output delay time from input power loss

Time interval error

0.2

μs

2¹⁶- 1 PRBS data at 100 Mbps

(1) Also known as Pulse Skew.

(2) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

6.10 Switching Characteristics, 3.3 V

V_CC1= V_CC2= 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

10.8

0.7

MAX

4.7

4.5

UNIT

t_PLH, t_PHL

PWD⁽¹⁾

Propagation delay time

See Figure 7

Pulse width distortion |t_PHL– t_PLH

(2)

t_sk(pp)

Part-to-part skew time

t_r

t_f

Output signal rise time

Output signal fall time

1.3

See Figure 7

Measured from the time V_CCgoes

below 1.7 V. See Figure 8

t_fs

t_ie

Default output delay time from input power loss

Time interval error

0.2

μs

2¹⁶- 1 PRBS data at 100 Mbps

(1) Also known as Pulse Skew.

(2) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

6.11 Switching Characteristics, 2.5 V

V_CC1= V_CC2= 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

Propagation delay time

Pulse width distortion |t_PHL– t_PLH

TEST CONDITIONS

MIN

TYP

11.7

0.7

MAX

17.5

4.7

UNIT

t_PLH, t_PHL

PWD⁽¹⁾

7.5

See Figure 7

(2)

t_sk(pp)

Part-to-part skew time

Output signal rise time

Output signal fall time

4.5

t_r

t_f

1.8

3.5

See Figure 7

3.5

Measured from the time V_CCgoes

below 1.7 V. See Figure 8

t_fs

t_ie

Default output delay time from input power loss

Time interval error

0.2

μs

2¹⁶- 1 PRBS data at 100 Mbps

(1) Also known as Pulse Skew.

(2) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

6.12 Typical Characteristics

I_CC1at 2.5 V

I_CC2at 2.5 V

I_CC1at 3.3 V

I_CC2at 3.3 V

I_CC1at 5 V

I_CC2at 5 V

I_CC1at 2.5 V

I_CC2at 2.5 V

I_CC1at 3.3 V

I_CC2at 3.3 V

I_CC1at 5 V

I_CC2at 5 V

100

125

150

100

125

150

Data Rate (Mbps)

D001

D002

T_A= 25°C

C_L= 15 pF

T_A= 25°C

C_L= No Load

Figure 1. Supply Current vs Data Rate (with 15 pF Load)

Figure 2. Supply Current vs Data Rate (with No Load)

1.0

V_CCat 2.5V

V_CCat 3.3V

V_CCat 5.0V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V_CCat 2.5V

V_CCat 3.3V

V_CCat 5.0V

-15

-10

-5

High-Level Output Current (mA)

Low-Level Output Current (mA)

D001

T_A= 25°C

Figure 3. High-Level Output Voltage vs High-level Output

Current

Figure 4. Low-Level Output Voltage vs Low-Level Output

Current

2.25

V_CC1Rising

V_CC1Falling

V_CC2Rising

V_CC2Falling

2.20

2.15

2.10

2.05

2.00

1.95

1.90

1.85

1.80

1.75

1.70

t_PLHat 2.5 V

t_PHLat 2.5 V

t_PHLat 3.3 V

t_PLHat 3.3 V

t_PLHat 5 V

t_PHLat 5 V

-50

100

150

-60

-30

120

Free-Air Temperature (^oC )

D001

D006

Figure 5. Power Supply Undervoltage Threshold vs Free-Air

Temperature

Figure 6. Propagation Delay Time vs Free-Air Temperature

ISO7820, ISO7820F

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ZHCSDV2 –JULY 2015

7 Parameter Measurement Information

V_CCI

V_I

50%

OUT

V_O

0 V

t_PLH

t_PHL

Input

Generator

Note A

50 W

V_I

C_L

V_OH

90%

10%

Note B

50%

V_O

V_OL

t_r

t_f

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, t_r≤ 3

ns, t_f≤ 3ns, Z_O= 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in

actual application.

B. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 7. Switching Characteristics Test Circuit and Voltage Waveforms

2.7 V

0 V

OUT

IN = 0 V (Devices without suffix F)

IN = V_CC(Devices with suffix F)

fs high

fs low

50%

NOTE A

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 8. Default Output Delay Time Test Circuit and Voltage Waveforms

V_CCI

V_CCO

C = 0.1 μF 1ꢀ

Pass-fail criteria –

output must remain

stable.

OUT

C_L

Note A

V_OHor V_OL

–

GNDI

GNDO

–

V_CM

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 9. Common-Mode Transient Immunity Test Circuit

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

8 Detailed Description

8.1 Overview

ISO7820 employs an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon

dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one

digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after

advanced signal conditioning and produces the output through a buffer stage. These devices also incorporates

advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the

high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator,

Figure 10, shows a functional block diagram of a typical channel.

8.2 Functional Block Diagram

RECEIVER

TRANSMITTER

OOK

MODULATION

SiO₂based

Capacitive

Isolation

TX SIGNAL

CONDITIONING

TX IN

RX OUT

RX SIGNAL

CONDITIONING

ENVELOPE

DETECTION

Barrier

EMISSIONS

REDUCTION

TECHNIQUES

OSCILLATOR

Figure 10. Conceptual Block Diagram of a Digital Capacitive Isolator

Also a conceptual detail of how the ON/OFF Keying scheme works is shown in Figure 11.

TX IN

Carrier signal

through

isolation barrier

RX OUT

Figure 11. On-Off Keying (OOK) Based Modulation Scheme

ISO7820, ISO7820F

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ZHCSDV2 –JULY 2015

8.3 Feature Description

ISO7820 is available in two channel configurations and default output state options to enable a variety of

application uses.

PRODUCT

ISO7820

CHANNEL DIRECTION

2 Forward, 0 Reverse

RATED ISOLATION

5700 V_RMS/ 8000 V_PK

MAX DATA RATE

100 Mbps

DEFAULT OUTPUT

(1)

High

Low

ISO7820F

100 Mbps

(1) See the Regulatory Information section for detailed isolation ratings.

8.3.1 High Voltage Feature Description

8.3.1.1 Package Insulation and Safety-Related Specifications

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Shortest terminal-to-terminal distance

through air

MIN

TYP MAX

UNIT

L(I01)

L(I02)⁽¹⁾

CTI

Minimum air gap (clearance)

DW-16

Minimum external tracking

(creepage)

Shortest terminal-to-terminal distance

across the package surface

Tracking resistance (comparative

tracking index)

DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A

600

V_IO= 500 V, T_A= 25°C

10¹²

10¹¹

Ω

R_IO

Isolation resistance, input to output⁽²⁾

V_IO= 500 V, 100°C ≤ T_A≤ max

C_IO

C_I

Barrier capacitance, input to output⁽²⁾V_IO= 0.4 x sin (2πft), f = 1 MHz

Input capacitance⁽³⁾

V_I= V_CC/2 + 0.4 x sin (2πft), f = 1 MHz, V_CC= 5 V

(1) Per JEDEC package dimensions.

(2) All pins on each side of the barrier tied together creating a two-terminal device.

(3) Measured from input pin to ground.

NOTE

Creepage and clearance requirements should be applied according to the specific

equipment isolation standards of an application. Care should be taken to maintain the

creepage and clearance distance of a board design to ensure that the mounting pads of

the isolator on the printed-circuit board do not reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to

help increase these specifications.

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

8.3.1.2 Insulation Characteristics

PARAMETER⁽¹⁾

TEST CONDITIONS

SPECIFICATION

UNIT

μm

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

1500

2121

V_RMS

V_DC

V_IOWM

Maximum isolation working voltage

Time dependent dielectric breakdown (TDDB) test

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V_TEST= V_IOTM

V_IOTM

Maximum transient isolation voltage

t = 60 sec (qualification)

t= 1 sec (100% production)

8000

V_PK

Test method per IEC 60065, 1.2/50 µs waveform,

V_TEST= 1.6 x V_IOSM= 12800 V_PK(qualification)

V_IOSM

V_IORM

Maximum surge isolation voltage

8000

2121

V_PK

Maximum repetitive peak isolation voltage

Method a, After Input/Output safety test subgroup

2/3,

V_PR= V_IORMx 1.2, t = 10 s,

Partial discharge < 5 pC

2545

Method a, After environmental tests subgroup 1,

V_PR= V_IORMx 1.6, t = 10 s,

Partial Discharge < 5 pC

V_PR

Input-to-output test voltage

V_PK

3394

3977

Method b1,After environmental tests subgroup 1,

V_PR= V_IORMx 1.875, t = 1 s (100% Production test)

Partial discharge < 5 pC

R_S

Isolation resistance

Pollution degree

V_IO= 500 V at T_S

>10⁹

Ω

UL 1577

V_ISO

V_TEST= V_ISO= 5700 V_RMS, t = 60 sec

(qualification);

V_TEST= 1.2 x V_ISO= 6840 V_RMS, t = 1 sec (100%

production)

Withstanding isolation voltage

5700

V_RMS

(1) Climatic Classification 55/125/21

8.3.1.3 IEC 60664-1 Ratings Table

PARAMETER

TEST CONDITIONS

Material group

SPECIFICATION

Basic isolation group

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I–IV

I–III

Installation classification

DW package

ISO7820, ISO7820F

www.ti.com.cn

ZHCSDV2 –JULY 2015

8.3.1.4 Regulatory Information

DW package certifications are complete.

VDE

CSA

CQC

Certified according to DIN V VDE Approved under CSA

Recognized under UL 1577

Component Recognition

Program

V 0884-10 (VDE V 0884-

Component Acceptance Notice

Certified according to GB 4943.1-

2011

10):2006-12 and DIN EN 60950- 5A, IEC 60950-1, IEC 61010-1,

1 (VDE 0805 Teil 1):2011-01

and IEC 60601-1

Reinforced insulation per CSA

61010-1-12 and IEC 61010-1

3rd Ed., 300 V_RMSmax working

voltage;

Reinforced insulation

Maximum transient isolation

Reinforced insulation per CSA

60950-1-07+A1+A2 and IEC

60950-1 2nd Ed.,

voltage, 8000 V_PK

;

Reinforced Insulation, Altitude ≤

5000 m, Tropical Climate, 250 V_RMS

maximum working voltage

(1)

Maximum repetitive peak

isolation voltage, 2121 V_PK

Maximum surge isolation

voltage, 8000 V_PK

Single protection, 5700 V_RMS

800 V_RMSmax working voltage

(pollution degree 2, material

group I);

;

2 MOPP (Means of Patient

Protection) per CSA 60601-

1:14 and IEC 60601-1 Ed. 3.1,

250 V_RMS(354 V_PK) max

working voltage

Master contract number:

220991

Certificate number:

CQC15001121716

Certificate number: 40040142

File number: E181974

(1) Production tested ≥ 6840 V_RMSfor 1 second in accordance with UL 1577.

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

8.3.1.5 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of

the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

268

410

537

UNIT

_θJA= 84.7°C/W, V_I= 5.5 V, T_J= 150°C, T_A= 25°C

_θJA= 84.7°C/W, V_I= 3.6 V, T_J= 150°C, T_A= 25°C

_θJA= 84.7°C/W, V_I= 2.75 V, T_J= 150°C, T_A= 25°C

_θJA= 84.7°C/W, T_J= 150°C, T_A= 25°C

Safety input, output, or supply

current for DW-16 package

I_S(DW-16)

P_S

T_S

Safety input, output, or total

power

°C

1476

150

Maximum case temperature

The maximum safety temperature is the maximum junction temperature specified for the device. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware

determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal

Informationis that of a device installed on a High-K test board for Leaded Surface Mount Packages. The

power is the recommended maximum input voltage times the current. The junction temperature is then the

ambient temperature plus the power times the junction-to-air thermal resistance.

600

500

400

300

200

100

1600

1400

1200

1000

800

600

400

200

V_CC1= V_CC2= 2.75 V

V_CC1= V_CC2= 3.6 V

V_CC1= V_CC2= 5.5 V

Power

100

150

200

100

150

200

Ambient Temperature (qC)

D014

D015

Figure 12. θ_JCThermal Derating Curve per VDE for

Figure 13. Thermal Derating Curve for Safety Limiting

Power per VDE

DW-16 Package

ISO7820, ISO7820F

www.ti.com.cn

ZHCSDV2 –JULY 2015

8.4 Device Functional Modes

ISO7820DW functional modes are shown in Table 1.

Table 1. ISO7820DW Function Table⁽¹⁾

INPUT

OUTPUT

(OUTx)

V_CCI

V_CCO

COMMENTS

(INx)⁽²⁾

Normal Operation:

A channel output assumes the logic state of its input.

Default mode: When INx is open, the corresponding channel output goes to its

default high logic state. Default= High for ISO7820 and Low for ISO7820F.

Open

Default

Default mode: When V_CCIis unpowered, a channel output assumes the logic

state based on the selected default option.Default= High for ISO7820 and Low

for ISO7820F.

Default

When V_CCItransitions from unpowered to powered-up, a channel output

assumes the logic state of its input.

When V_CCItransitions from powered-up to unpowered, channel output assumes

the selected default state.

(3)

When V_CCOis unpowered, a channel output is undetermined

Undetermined

When V_CCOtransitions from unpowered to powered-up, a channel output

assumes the logic state of its input

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC; PU = Powered up (V_CC≥ 2.25 V); PD = Powered down (V_CC≤ 1.7 V); X = Irrelevant; H

= High level; L = Low level

(2) A strongly driven input signal can weakly power the floating V_CCvia an internal protection diode and cause undetermined output.

(3) The outputs are in undetermined state when 1.7 V < V_CCI, V_CCO< 2.25 V.

8.4.1 Device I/O Schematics

Input

Enable

CCI

CCO

CCI

CCO

1.5 MW

2 MW

985 W

1970 W

INx

ENx

Output

CCO

~20 W

OUTx

Figure 14. Device I/O Schematics

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO7821 is a high-performance, dual-channel digital isolator with 5.7 kV_RMSisolation voltage. It utilizes

single-ended CMOS-logic switching technology. Its supply voltage range is from 2.25 V to 5.5 V for both

supplies, V_CC1and V_CC2. When designing with digital isolators, it is important to keep in mind that due to the

single-ended design structure, digital isolators do not conform to any specific interface standard and are only

intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the

data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type

or standard.

9.2 Typical Application

ISO7820DW can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,

transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.

V_CC1

V_CC2

ISO7821

1, 7

9, 16

Figure 15. Isolated 4-20 mA Current Loop

9.2.1 Design Requirements

For the ISO7820, use the parameters shown in Table 2.

Table 2. Design Parameters

PARAMETER

VALUE

2.25 V to 5.5 V

0.1 µF

Supply voltage

Decoupling capacitor between V_CC1and GND1

Decoupling capacitor from V_CC2and GND2

0.1 µF

ISO7820, ISO7820F

www.ti.com.cn

ZHCSDV2 –JULY 2015

9.2.2 Detailed Design Procedure

Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,

ISO7820 only needs two external bypass capacitors to operate.

ISO7820

V_CC1

V_CC2

GND1

GND2

1166

1155

1144

1133

1122

111

1100

GND1

GND2

0.1

GND1

GND2

V_CC1

VCC1

VCC2

V_CC2

INA

OUTA

INA

OUTA

OUTB

INB

OUTB

ININBB

GND1

GND2

Figure 16. Typical ISO7820DW Circuit Hook-up

9.2.2.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO7820

incorporate many chip-level design improvements for overall system robustness. Some of these improvements

include:

•

Robust ESD protection for input and output signal pins and inter-chip bond pads.

Low-resistance connectivity of ESD cells to supply and ground pins.

Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

•

PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

9.2.3 Application Performance Curve

Typical eye diagram of ISO7820 indicate low jitter and wide open eye at the maximum data rate of 100 Mbps.

Figure 17. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C

10 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at

input and output supply pins (V_CC1and V_CC2). The capacitors should be placed as close to the supply pins as

possible. If only a single primary-side power supply is available in an application, isolated power can be

generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For

such applications, detailed power supply design and transformer selection recommendations are available in

SN6501 datasheet (SLLSEA0) .

ISO7820, ISO7820F

www.ti.com.cn

ZHCSDV2 –JULY 2015

11 Layout

11.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of

up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the

requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower

dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-

extinguishing flammability-characteristics.

11.2 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 18). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

•

Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in².

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the

stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be placed closer together, thus increasing the high-frequency

bypass capacitance significantly.

For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.

11.3 Layout Example

High-speed traces

10 mils

Ground plane

Keep this

FR-4

0 ~ 4.5

space free

from planes,

traces , pads,

and vias

40 mils

10 mils

Power plane

Low-speed traces

Figure 18. Layout Example

ISO7820, ISO7820F

ZHCSDV2 –JULY 2015

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参见隔离术语表 (SLLA353)

12.2 相关链接

以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买

链接。

表 3. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

ISO7820

ISO7820F

12.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

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邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ISO7820DW

ISO7820DWR

ISO7820DWW

ISO7820DWWR

ISO7820FDW

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

Level-3-260C-168 HR

-55 to 125

ISO7820

2000 RoHS & Green

45 RoHS & Green

1000 RoHS & Green

40 RoHS & Green

2000 RoHS & Green

45 RoHS & Green

1000 RoHS & Green

NIPDAU

ISO7820

ISO7820F

DWW

ISO7820FDWR

ISO7820FDWW

ISO7820FDWWR

DWW

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

重要声明和免责声明

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