ISO7821DWW [TI]

高隔离额定值、双通道、1/1、增强型数字隔离器 | DWW | 16 | -55 to 125;


型号：	ISO7821DWW
厂家：	TEXAS INSTRUMENTS
描述：	高隔离额定值、双通道、1/1、增强型数字隔离器 \| DWW \| 16 \| -55 to 125
文件：	总38页 (文件大小：1576K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISO7821, ISO7821F

ZHCSD31G –NOVEMBER 2014 –REVISED JULY 2022

ISO7821x 高性能8000V_PK增强型双通道数字隔离器

1 特性

3 说明

• 信令速率：高达100Mbps

• 宽电源电压范围：2.25V 至5.5V

• 2.25V 至5.5V 电平转换

• 宽温度范围：-55°C 至125°C

• 低功耗，每通道电流典型值为1.8mA（1Mbps 时）

• 低传播延迟：典型值为11ns

（5V 电源）

• 卓越的CMTI（下限值）：±100kV/μs

• 优异的电磁兼容性(EMC)

• 系统级ESD、EFT 和浪涌抗扰性

• 低辐射

ISO7821 是一款高性能双通道数字隔离器，隔离电压

高达 8000 V_PK。该器件已通过符合 VDE、CSA、

CQC 和 TUV 标准的增强型隔离认证。该隔离器以低

功耗提供高电磁抗扰度和低辐射，同时隔离 CMOS 或

LVCMOS 数字 I/O。每个隔离通道都有逻辑输入和输

出缓冲器，由二氧化硅 (SiO₂) 绝缘栅隔离。ISO7821

具有一个正向通道和一个反向通道。。如果输入功率或

信号丢失，ISO7821 器件默认输出‘高电平’，

ISO7821F 器件默认输出‘低电平’。与隔离式电源一

起使用时，这款器件可防止数据总线或者其他电路上的

噪音电流进入本地接地和干扰或损坏敏感电路。凭借创

新的芯片设计和布线技术，ISO7821 的电磁兼容性得

到了显著增强，从而可确保提供系统级 ESD、EFT 和

浪涌保护并符合辐射标准。ISO7821 可采用 16 引脚

SOIC 宽体 (DW) 和超宽体 (DWW) 封装。DWW 封装

选项带有使能引脚，可用于将各自输出置于高阻抗，适

用于多主驱动应用并降低功耗。

• 隔离栅寿命：> 25 年

• SOIC-16 宽体(DW) 和超宽体(DWW) 封装选项

• 安全和监管批准：

– 8000V_PK增强型隔离，符合DIN V VDE V

0884-10 (VDE V 0884-10): 2006-12

– 符合UL 1577 标准且长达1 分钟的5.7kV_RMS

隔离

– CSA 组件验收通知5A、IEC 60950-1 和IEC

60601-1 终端设备标准

– 符合GB4943.1-2011 的CQC 认证

– 符合EN 61010-1 和EN 60950-1 标准的TUV

认证

器件信息

封装尺寸（标称值）

器件型号

ISO7821、

封装

SOIC，DW (16) 10.30mm x 7.50mm

超宽SOIC、

ISO7821F

10.30mm x 14.0mm

DWW (16)

– 已完成所有DW 封装认证；已完成符合UL、

VDE 标准的DWW 封装认证，并已针对VDE、

CSA 和CQC 进行规划

空白

CCO

CCI

Isolation

Capacitor

2 应用

INx

OUTx

ENx (DWW package only)

• 工业自动化

• 电机控制

• 电源

• 光伏逆变器

• 医疗设备

• 混合动力电动汽车

GNDI

GNDO

_CCI和GNDI 分别是输入通道的电源和接地连接引脚。

_CCO和GNDO 分别是输出通道的电源和接地连接引脚。

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSEM2

ISO7821, ISO7821F

ZHCSD31G –NOVEMBER 2014 –REVISED JULY 2022

www.ti.com.cn

Table of Contents

7 Parameter Measurement Information..........................14

8 Detailed Description......................................................16

8.1 Overview...................................................................16

8.2 Functional Block Diagram.........................................16

8.3 Feature Description...................................................17

8.4 Device Functional Modes..........................................21

9 Application and Implementation..................................22

9.1 Application Information............................................. 22

9.2 Typical Application.................................................... 22

10 Layout...........................................................................25

10.1 PCB Material...........................................................25

10.2 Layout Guidelines................................................... 25

10.3 Layout Example...................................................... 25

11 Device and Documentation Support..........................26

11.1 Documentation Support.......................................... 26

11.2 Trademarks............................................................. 26

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................5

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings ....................................... 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................7

6.5 Power Dissipation Characteristics.............................. 7

6.6 Electrical Characteristics, 5 V..................................... 8

6.7 Electrical Characteristics, 3.3 V.................................. 9

6.8 Electrical Characteristics, 2.5 V................................ 10

6.9 Switching Characteristics, 5 V...................................11

6.10 Switching Characteristics, 3.3 V..............................11

6.11 Switching Characteristics, 2.5 V..............................12

6.12 Typical Characteristics............................................13

Information.................................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision F (March 2016) to Revision G (July 2022)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1

Changes from Revision E (December 2015) to Revision F (March 2016)

Page

• 更改了节1 中的安全及管理批准列表..................................................................................................................1

• 添加了节1“符合EN 61010-1 和EN 60950-1 标准的TUV 认证”...................................................................1

• 将节3 的第一段中的文本从“符合VDE、CSA 和CQC 认证标准”更改为更改为“符合VDE、CSA、CQC 和

TUV 认证标准。”..............................................................................................................................................1

• Added Note 1 to 表8-2 ....................................................................................................................................17

• Added TUV to the 节8.3.1.1 section and 表8-4. Deleted Note 1 in Table 4 ...................................................19

• Changed 图8-5 ............................................................................................................................................... 21

Changes from Revision D (July 2015) to Revision E (December 2015)

Page

• 将节1 从8000V_{PK IOTM}和2121V_{PK IORM}增强型更改为：8000V_PK增强型.................................................1

• 添加了节1：已完成DW 封装认证；已规划DWW 认证.....................................................................................1

• 在说明中添加了文本：和超宽体(DWW) 封装.................................................................................................... 1

• 添加了封装：在器件信息表中添加了超宽SOIC、DWW (16).............................................................................1

• Added the DWW pinout image .......................................................................................................................... 5

• Added the DWW package to the 节6.4 .............................................................................................................7

• Changed the MIN value of CMTI in 节6.6 table From: 70 To: 100 kV/µs, deleted the TYP value of 100 kV/µs .

• Added the DW package value to the Supply Current section of the 节6.6 ....................................................... 8

• Added the DWW package value to the Supply Current section of the 节6.6 ....................................................8

• Changed the MIN value of CMTI in 节6.7 table From: 70 To: 100 kV/µs, deleted the TYP value of 100 kV/µs .

• Added the DW package value to the Supply Current section of the 节6.7 ....................................................... 9

• Added the DWW package value to the Supply Current section of the 节6.7 ....................................................9

• Changed the MIN value of CMTI in 节6.8 table From: 70 To: 100 kV/µs, deleted the TYP value of 100 kV/µs .

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• Added the DW package value to the Supply Current section of the 节6.8 ..................................................... 10

• Added the DWW package value to the Supply Current section of the 节6.8 ..................................................10

• Added t_PHZ, t_PLZ, t_PZH, and t_PZLto 节6.10 ....................................................................................................... 11

• Added t_PHZ, t_PLZ, t_PZH, and t_PZLto 节6.11 ....................................................................................................... 12

• Added 图7-2 ....................................................................................................................................................14

• Added the DWW package to 表8-1 .................................................................................................................17

• Changed C_IOtyp value From: 2 To 1 pF in 表8-1 ........................................................................................... 17

• Added the DWW package to 表8-2 .................................................................................................................17

• Changed Parameter information and added the DWW package information in 表8-3 ................................... 17

• Added the DWW package information to 表8-4 ..............................................................................................19

• added DWW-16 package options to 表8-5 ..................................................................................................... 20

• Changed 表8-6 ............................................................................................................................................... 21

• Added text to the 节9.1 section: "isolation voltage per UL 1577." .................................................................. 22

Changes from Revision C (May 2015) to Revision D (July 2015)

Page

• 在数据表中添加了ISO7821F 器件..................................................................................................................... 1

• 更改了节3，以便包含：“ISO7821 器件默认输出为‘高电平’，ISO7821F 器件默认输出为‘低电平’。... 1

• 更改了图3-1 ...................................................................................................................................................... 1

• Changed t_PLHand t_PHLFrom: 5.5 V to 5 V in 图6-6 ........................................................................................13

• Changed 图7-3 ............................................................................................................................................... 14

• Changed the 节8.2 ..........................................................................................................................................16

• Changed 表8-1 title From: IEC Insulation and Safety-Related Specifications for DW-16 Package To: Package

Insulation and Safety-Related Specifications .................................................................................................. 17

• Changed 图8-3 , Added 图8-4 ....................................................................................................................... 20

Changes from Revision B (April 2015) to Revision C (May 2015)

Page

• 在整个数据表中V_CC1和V_CC2更改为：V_CCI和V_CCO，GND1 和GND2 更改为：GNDI 和GNDO，并在图3-1

中添加了注释1 和2............................................................................................................................................1

• Changed the MIN value of CMTI in 节6.6 table From: 50 To: 70 kV/µs ............................................................8

• Changed the MIN value of CMTI in 节6.7 table From: 50 To: 70 kV/µs ............................................................9

• Changed the MIN value of CMTI in 节6.8 table From: 50 To: 70 kV/µs ..........................................................10

• Added sentence "If the EN pin is available and low then the output goes to high impedance." to the 节8.1

section ............................................................................................................................................................. 16

• Changed the 节8.2 to include the EN pin on the Receiver side.......................................................................16

• Changed the Installation classification of the 表8-3 to include DW package information................................17

• Changed "ISO782W functional modes" To: "ISO7821DW functional modes" in 节8.4 ...................................21

• Changed 表8-6 title From: "Functional Table" To: "ISO7821DW Function Table"............................................21

• Added the 节8.4.1 section .............................................................................................................................. 21

• Changed device number ISO7821 To: ISO7821DW in 图9-2 .........................................................................23

Changes from Revision A (December 2014) to Revision B (April 2015)

Page

• 将文档标题从“通道数字隔离器”更改为：“通道1/1 数字隔离器”................................................................1

• 添加了节1：2.25V 至5.5V 电平转换.................................................................................................................1

• 更改了节1 中的安全及管理批准列表..................................................................................................................1

• 将节3 中的文本从“该器件正在接受VDE 和CSA 的增强型隔离认证审核。更改为“该器件已通过VDE、

CSA 和CQC 的增强型隔离认证。”..................................................................................................................1

• Added Note (3) to the 节6.1 table......................................................................................................................6

• Changed From: V_CCXTo: V_CCOIn I_OHand I_OLof the 节6.3 table ..................................................................... 6

• Changed From: V_CCXTo: V_CCIIn V_IHand V_ILof the 节6.3 table .......................................................................6

• Changed Note (1) of the 节6.3 table .................................................................................................................6

• Changed From: V_CCXTo: V_CCOIn V_OHof the 节6.6 table .................................................................................8

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• Changed From: V_CCXTo: V_CCOIn V_I(HYS)of the 节6.6 table .............................................................................8

• Changed From: V_CCXTo: V_CCIIn I_IHof the 节6.6 table .....................................................................................8

• Changed From: V_CCXTo: V_CCIIn CMTI of the 节6.6 table ................................................................................8

• Changed From: V_CCXTo: V_CCIIn Supply Current, DC Signal of the 节6.6 table............................................... 8

• Changed Note (1) of the 节6.6 table .................................................................................................................8

• Changed From: V_CCXTo: V_CCOIn V_OHof the 节6.7 table .................................................................................9

• Changed From: V_CCXTo: V_CCOIn V_I(HYS)of the 节6.7 table .............................................................................9

• Changed From: V_CCXTo: V_CCIIn I_IHof the 节6.7 table......................................................................................9

• Changed From: V_CCXTo: V_CCIIn CMTI of the 节6.7 table ................................................................................9

• Changed From: V_CCXTo: V_CCIIn Supply Current, DC Signal of the 节6.7 table .............................................. 9

• Changed Note (1) of the 节6.7 table .................................................................................................................9

• Changed From: V_CCXTo: V_CCOIn V_OHof the 节6.8 table ...............................................................................10

• Changed From: V_CCXTo: V_CCIIn I_IHof the 节6.8 table ...................................................................................10

• Changed From: V_CCXTo: V_CCIIn Supply Current, DC Signal of the 节6.8 table ............................................ 10

• Changed Note (1) of the 节6.8 table ...............................................................................................................10

• Changed 图7-1 ............................................................................................................................................... 14

• Changed From: V_CC1To: V_CCIin 图7-3 ...........................................................................................................14

• Changed 图7-4 ............................................................................................................................................... 14

• Changed the Test Condition of CTI in 表8-1 ...................................................................................................17

• Changed the MIN value of CTI From" > 600 V To: 600 V.................................................................................17

• Changed 表8-2 title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation Characteristics To:

Added the DWW package to ........................................................................................................................... 17

• Changed 表8-2 ............................................................................................................................................... 17

• Changed columns VDE and CSA to 表8-4 ..................................................................................................... 19

• Changed title From: IEC Safety Limiting Values To: 节8.3.1.2 ....................................................................... 20

• Changed the table in 节8.3.1.2, added I_SDW-16 package options.................................................................20

• Changed 图8-3 ............................................................................................................................................... 20

• Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of 表8-6 .....................................................21

• Changed Note (1) of 表8-6 ............................................................................................................................. 21

• Changed the 节9.1 section.............................................................................................................................. 22

• Changed the 节9.2 section and 图9-1 ........................................................................................................... 22

• Added text and 图9-2 to the 节9.2.2 section ..................................................................................................23

Changes from Revision * (November 2014) to Revision A (December 2014)

Page

• 将仅包含第1 页和引脚分配部分的产品预发布更改为：完整数据表...................................................................1

• Added Note: "This coupler..." to the 节8.3.1 section .......................................................................................17

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5 Pin Configuration and Functions

GND1

16 GND2

15 NC

CC2

CC1

OUTA

13 INA

12 OUTB

11 NC

10 NC

INB

GND1

GND2

图5-1. DW Package 16-Pin (SOIC) Top View

CC1

CC2

GND1

15 GND2

14 NC

13 EN2

12 INA

11 OUTB

10 NC

EN1

OUTA

INB

GND1

9 GND2

图5-2. DWW Package 16-Pin (SOIC) Top View

表5-1. Pin Functions

NO.

I/O

DESCRIPTION

NAME

DWW

GND1

GND2

INA

1, 7

2,8

Ground connection for V_CC1

Ground connection for V_CC2

Input, channel A

–

9, 16

9,15

INB

Input, channel B

2, 6, 8, 10 ,11, 15

3,7,10,14

Not connected

–

OUTA

OUTB

V_CC1

V_CC2

Output, channel A

Output, channel B

Power supply, V_CC1

Power supply, V_CC2

–

Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and

in high-impedance state when EN1 is low.

EN1

EN2

–

Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and

in high-impedance state when EN2 is low.

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6 Specifications

6.1 Absolute Maximum Ratings

MIN

–0.5

-15

MAX

UNIT

Supply voltage⁽¹⁾

Voltage

V_CC+ 0.5⁽²⁾

V_CC1, V_CC2

INx, OUTx

I_O

Output Current

Surge Immunity

Storage temperature, T_stg

°C

12.8

150

–65

(1) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak

voltage values.

(2) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins ⁽¹⁾

±6000

V_ESD

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-

C101, all pins⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

2.25

-4

TYP

MAX

UNIT

V_CC1, V_CC2

Supply voltage

5.5

V_CCO⁽²⁾= 5 V

V_CCO= 3.3 V

V_CCO= 2.5 V

V_CCO= 5 V

I_OH

High-level output current

-2

-1

I_OL

Low-level output current

V_CCO= 3.3 V

V_CCO= 2.5 V

(2)

V_IH

V_IL

T_J

High-level input voltage

Low-level input voltage

Signaling rate

0.7 x V_{CC I}

V_CCI

0.3 x V_CCI

100

Mbps

°C

Junction temperature⁽¹⁾

-55

150

T_A

Ambient temperature

125

°C

(1) To maintain the recommended operating conditions for T_J, see the Thermal Information table.

(2) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

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6.4 Thermal Information

ISO7821

THERMAL METRIC⁽¹⁾

DW (SOIC)

16 PINS

84.7

DWW (SOIC)

16-PINS

84.7

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

47.3

46.0

49.4

54.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

19.1

18.5

48.8

53.8

ψ_JB

R_θJC(bottom)Junction-to-case(bottom) thermal resistance

n/a

(1) For more information about trdational and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Dissipation Characteristics

VALUE

UNIT

P_D

Maximum power dissipation by ISO7821 x

100

Maximum power dissipation by side-1 of ISO7821 V_CC1= V_CC2= 5.5 V, T_J= 150°C,

P_D1

C_L= 15 pF, input a 50 MHz 50% duty cycle

square wave

Maximum power dissipation by side-2 of ISO7821

P_D2

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6.6 Electrical Characteristics, 5 V

V_CC1= V_CC2= 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

_CCO–0.2

0.2

MAX

0.4

UNIT

I_OH= –4 mA; see 图7-1

V_CCO⁽¹⁾–0.4

V_OH

V_OL

V_I(HYS)

I_IH

High-level output voltage

Low-level output voltage

Input threshold voltage hysteresis

High-level input current

I_OL= 4 mA; see 图7-1

(1)

0.1 x V_CCO

V_IH= V_CCI⁽¹⁾at INx or ENx

V_IL= 0 V at INx or ENx

μA

I_IL

Low-level input current

-10

CMTI

Common-mode transient immunity

100

V_I= V_CCIor 0 V; see 图7-4

kV/μs

Supply Current - ISO7821DW and ISO7821FDW

(1)

V_I= 0 V (ISO7821F) , V_I= V_CCI

(ISO7821)

I_CC1, I_CC2

DC Signal

1.2

2.4

1.7

3.4

V_I= V_CCI⁽¹⁾(ISO7821F) , V_I= 0 V

(ISO7821)

I_CC1, I_CC2

1 Mbps

1.8

2.4

7.5

2.6

3.2

9.3

All channels switching with square wave

clock input;

C_L= 15 pF

10 Mbps

100 Mbps

Supply Current - ISO7821DWW and ISO7821FDWW

EN1 = EN2 = 0V, V_I= 0 V (ISO7821F) ,

V_I= V_CCI⁽¹⁾(ISO7821)

I_CC1, I_CC2

Disable

0.7

1.8

1.2

2.4

1.1

2.9

1.7

3.5

(1)

EN1 = EN2 = 0V, V_I= V_CCI

Disable

(ISO7821F) , V_I= 0 V (ISO7821)

(1)

V_I= 0 V (ISO7821F) , V_I= V_CCI

DC Signal

(ISO7821)

V_I= V_CCI⁽¹⁾(ISO7821F) , V_I= 0 V

(ISO7821)

I_CC1, I_CC2

1 Mbps

1.9

2.5

7.7

2.7

3.2

9.3

All channels switching with square wave

clock input; C_L= 15 pF

10 Mbps

100 Mbps

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

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6.7 Electrical Characteristics, 3.3 V

V_CC1= V_CC2= 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

_CCO–0.2

0.2

MAX

0.4

UNIT

I_OH= –2 mA; see 图7-1

V_CCO⁽¹⁾–0.4

V_OH

V_OL

V_I(HYS)

I_IH

High-level output voltage

Low-level output voltage

Input threshold voltage hysteresis

High-level input current

I_OL= 2 mA; see 图7-1

0.1 x V_CCO

V_IH= V_CCI⁽¹⁾at INx or ENx

V_IL= 0 V at INx or ENx

μA

I_IL

Low-level input current

-10

CMTI

Common-mode transient immunity

100

V_I= V_CCIor 0 V; see 图7-4

kV/μs

Supply Current - ISO7821DW and ISO7821FDW

(1)

V_I= 0 V (ISO7821F) , V_I= V_CCI

(ISO7821)

I_CC1, I_CC2

DC Signal

1.2

2.4

1.7

3.4

V_I= V_CCI⁽¹⁾(ISO7821F) , V_I= 0 V

(ISO7821)

I_CC1, I_CC2

1 Mbps

1.8

2.2

5.8

2.6

All channels switching with square wave

clock input; C_L= 15 pF

10 Mbps

100 Mbps

7.1

Supply Current - ISO7821DWW and ISO7821FDWW

EN1 = EN2 = 0V, V_I= 0 V (ISO7821F) ,

V_I= V_CCI⁽¹⁾(ISO7821)

I_CC1, I_CC2

Disable

0.7

1.8

1.2

2.4

1.1

2.9

1.7

3.5

(1)

EN1 = EN2 = 0V, V_I= V_CCI

Disable

(ISO7821F) , V_I= 0 V (ISO7821)

(1)

V_I= 0 V (ISO7821F) , V_I= V_CCI

DC Signal

(ISO7821)

V_I= V_CCI⁽¹⁾(ISO7821F) , V_I= 0 V

(ISO7821)

I_CC1, I_CC2

1 Mbps

1.9

2.3

5.9

2.6

All channels switching with square wave

clock input; C_L= 15 pF

10 Mbps

100 Mbps

7.1

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

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6.8 Electrical Characteristics, 2.5 V

V_CC1= V_CC2= 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

_CCO–0.2

0.2

MAX

0.4

UNIT

I_OH= –1 mA; see 图7-1

V_CCO⁽¹⁾–0.4

V_OH

V_OL

V_I(HYS)

I_IH

High-level output voltage

Low-level output voltage

Input threshold voltage hysteresis

High-level input current

I_OL= 1 mA; see 图7-1

0.1 x V_CCO

V_IH= V_CCI⁽¹⁾at INx or ENx

V_IL= 0 V at INx or ENx

μA

I_IL

Low-level input current

-10

CMTI

Common-mode transient immunity

100

V_I= V_CCIor 0 V; see 图7-4

kV/μs

Supply Current - ISO7821DW and ISO7821FDW

(1)

V_I= 0 V (ISO7821F) , V_I= V_CCI

(ISO7821)

I_CC1, I_CC2

DC Signal

1.2

2.4

1.7

3.4

V_I= V_CCI⁽¹⁾(ISO7821F) , V_I= 0 V

(ISO7821)

I_CC1, I_CC2

1 Mbps

1.8

2.1

4.9

2.6

2.8

5.9

All channels switching with square wave

clock input; C_L= 15 pF

10 Mbps

100 Mbps

Supply Current - ISO7821DWW and ISO7821FDWW

EN1 = EN2 = 0V, V_I= 0 V (ISO7821F) ,

V_I= V_CCI⁽¹⁾(ISO7821)

I_CC1, I_CC2

Disable

0.7

1.8

1.2

2.4

1.1

2.9

1.7

3.5

(1)

EN1 = EN2 = 0V, V_I= V_CCI

Disable

(ISO7821F) , V_I= 0 V (ISO7821)

(1)

V_I= 0 V (ISO7821F) , V_I= V_CCI

DC Signal

(ISO7821)

V_I= V_CCI⁽¹⁾(ISO7821F) , V_I= 0 V

(ISO7821)

I_CC1, I_CC2

1 Mbps

1.9

2.2

2.6

2.9

All channels switching with square wave

clock input; C_L= 15 pF

10 Mbps

100 Mbps

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

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6.9 Switching Characteristics, 5 V

V_CC1= V_CC2= 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

Propagation delay time

Pulse width distortion |t_PHL–t_PLH

TEST CONDITIONS

MIN

TYP

10.7

0.6

MAX UNIT

t_PLH, t_PHL

PWD⁽¹⁾

4.6

See 图7-1

(2)

t_sk(pp)

Part-to-part skew time

Output signal rise time

Output signal fall time

4.5

3.9

t_r

t_f

2.4

See 图7-1

Disable propagation delay, high-to-high impedance output for

ISO7821DWW and ISO7821FDWW

t_PHZ

t_PLZ

2.5

Disable propagation delay, low-to-high impedance output for

ISO7821DWW and ISO7821FDWW

Enable propagation delay, high impedance-to-high output for

ISO7821DWW

t_PZH

See 图7-2

Enable propagation delay, high impedance-to-high output for

ISO7821FDWW

μs

Enable propagation delay, high impedance-to-low output for

ISO7821DWW

t_PZL

Enable propagation delay, high impedance-to-low output for

ISO7821FDWW

Measured from the time V_CCgoes

below 1.7 V. See 图7-3

t_fs

t_ie

Default output delay time from input power loss

Time interval error

0.2

μs

2¹⁶- 1 PRBS data at 100 Mbps

(1) Also known as Pulse Skew.

(2) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

6.10 Switching Characteristics, 3.3 V

V_CC1= V_CC2= 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

10.8

0.7

MAX

4.7

4.5

UNIT

t_PLH, t_PHL

PWD⁽¹⁾

Propagation delay time

See 图7-1

Pulse width distortion |t_PHL–t_PLH

(2)

t_sk(pp)

Part-to-part skew time

t_r

t_f

Output signal rise time

1.3

See 图7-1

Output signal fall time

Disable propagation delay, high-to-high impedance output for

ISO7821DWW and ISO7821FDWW

t_PHZ

t_PLZ

2.5

Disable propagation delay, low-to-high impedance output for

ISO7821DWW and ISO7821FDWW

Enable propagation delay, high impedance-to-high output for

ISO7821DWW

t_PZH

See 图7-2

Enable propagation delay, high impedance-to-high output for

ISO7821FDWW

μs

Enable propagation delay, high impedance-to-low output for

ISO7821DWW

t_PZL

Enable propagation delay, high impedance-to-low output for

ISO7821FDWW

Measured from the time V_CCgoes

below 1.7 V. See 图7-3

t_fs

t_ie

Default output delay time from input power loss

Time interval error

0.2

μs

2¹⁶- 1 PRBS data at 100 Mbps

(1) Also known as Pulse Skew.

(2) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

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MAX UNIT

6.11 Switching Characteristics, 2.5 V

V_CC1= V_CC2= 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

11.7

0.7

t_PLH, t_PHL

PWD⁽¹⁾

Propagation delay time

7.5

17.5

4.7

See 图7-1

Pulse width distortion |t_PHL–t_PLH

(2)

t_sk(pp)

Part-to-part skew time

4.5

t_r

t_f

Output signal rise time

1.8

3.5

See 图7-1

Output signal fall time

Disable propagation delay, high-to-high impedance output for

ISO7821DWW and ISO7821FDWW

t_PHZ

t_PLZ

2.5

Disable propagation delay, low-to-high impedance output for

ISO7821DWW and ISO7821FDWW

Enable propagation delay, high impedance-to-high output for

ISO7821DWW

t_PZH

See 图7-2

Enable propagation delay, high impedance-to-high output for

ISO7821FDWW

μs

Enable propagation delay, high impedance-to-low output for

ISO7821DWW

t_PZL

Enable propagation delay, high impedance-to-low output for

ISO7821FDWW

Measured from the time V_CCgoes

below 1.7 V. See 图7-3

t_fs

t_ie

Default output delay time from input power loss

Time interval error

0.2

μs

2¹⁶- 1 PRBS data at 100 Mbps

(1) Also known as Pulse Skew.

(2) t_sk(pp)is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

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6.12 Typical Characteristics

I_CC1at 2.5 V

I_CC2at 2.5 V

I_CC1at 3.3 V

I_CC2at 3.3 V

I_CC1at 5.0 V

I_CC2at 5.0 V

I_CC1at 2.5 V

I_CC2at 2.5 V

I_CC1at 3.3 V

I_CC2at 3.3 V

I_CC1at 5.0 V

I_CC2at 5.0 V

Data Rate (Mbps)

100

125

150

Data Rate (Mbps)

100

125

150

D001

D002

T_A= 25°C

C_L= 15 pF

T_A= 25°C

C_L= No Load

图6-1. Supply Current vs Data Rate (with 15 pF

图6-2. Supply Current vs Data Rate (with No Load)

Load)

1.0

V_CCat 2.5V

V_CCat 3.3V

V_CCat 5.0V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V_CCat 2.5V

V_CCat 3.3V

V_CCat 5.0V

-15

-10

High-Level Output Current (mA)

-5

5 10

Low-Level Output Current (mA)

D001

T_A= 25°C

图6-3. High-Level Output Voltage vs High-level

图6-4. Low-Level Output Voltage vs Low-Level

Output Current

2.25

V_CC1Rising

2.20

V_CC1Falling

V_CC2Rising

V_CC2Falling

2.15

2.10

2.05

2.00

1.95

1.90

1.85

1.80

1.75

1.70

t_PLHat 2.5 V

t_PHLat 2.5 V

t_PHLat 3.3 V

t_PLHat 3.3 V

t_PLHat 5 V

t_PHLat 5 V

-50

100

150

-60

-30

120

Free-Air Temperature (^oC )

D001

D006

图6-5. Power Supply Undervoltage Threshold vs

图6-6. Propagation Delay Time vs Free-Air

Free-Air Temperature

Temperature

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7 Parameter Measurement Information

CCI

50%

OUT

0 V

PHL

PLH

Input

Generator

(See Note A)

50 ꢀ

See Note B

90%

10%

50%

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, t_r≤3 ns, t_f≤3ns, Z_O

= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.

B. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图7-1. Switching Characteristics Test Circuit and Voltage Waveforms

CCO

= 1 kꢀ 1%

/ 2

OUT

0 V

PZL

PLZ

0.5 V

50%

See Note B

Input

Generator

(See Note A)

50 ꢀ

OUT

3 V

V / 2

/ 2

0 V

PZH

See Note B

= 1 kꢀ 1%

50%

Input

Generator

(See Note A)

0.5 V

0 V

50 ꢀ

PHZ

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤10 kHz, 50% duty cycle, t_r≤3 ns, t_f≤3 ns, Z_O

= 50 Ω.

B. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图7-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform

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V_I

V_CC

2.7 V

V_I

0 V

IN = 0 V (Devices without suffix F)

IN = V_CC(Devices with suffix F)

OUT

V_O

V_OH

fs high

fs low

50%

V_O

C_L

See Note A

V_OL

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图7-3. Default Output Delay Time Test Circuit and Voltage Waveforms

CCO

CCI

C = 0.1 µF 1%

Pass-fail criteria:

The output must

remain stable.

OUT

or V

See Note A

GNDI

GNDO

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图7-4. Common-Mode Transient Immunity Test Circuit

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8 Detailed Description

8.1 Overview

ISO7821 employs an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon

dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one

digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after

advanced signal conditioning and produces the output through a buffer stage. These devices also incorporates

advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the

high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, 图

8-1, shows a functional block diagram of a typical channel.

8.2 Functional Block Diagram

Transmitter

Receiver

OOK

Modulation

TX IN

SiO based

RX OUT

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

Capacitive

Isolation

Barrier

Emissions

Reduction

Techniques

Oscillator

图8-1. Conceptual Block Diagram of a Digital Capacitive Isolator

Also a conceptual detail of how the ON/OFF Keying scheme works is shown in 图8-2.

TX IN

Carrier signal through

isolation barrier

RX OUT

图8-2. On-Off Keying (OOK) Based Modulation Scheme

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8.3 Feature Description

ISO7821 is available in two channel configurations and default output state options to enable a variety of

application uses.

PRODUCT

ISO7821

CHANNEL DIRECTION

1 Forward, 1 Reverse

RATED ISOLATION

5700 V_RMS/ 8000 V_PK

MAX DATA RATE

100 Mbps

DEFAULT OUTPUT

(1)

High

Low

ISO7821F

100 Mbps

(1) See the Regulatory Information section for detailed isolation ratings.

8.3.1 High Voltage Feature Description

备注

This coupler is suitable for 'safe electrical insulation' only within the safety ratings. Compliance with

the safety ratings shall be ensured by means of suitable protective circuits.

表8-1. Package Insulation and Safety-Related Specifications

(over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

DW-16

Shortest terminal-to-terminal distance

through air

CLR

External clearance

DWW-16

DW-16

14.5

Shortest terminal-to-terminal distance

across the package surface

CPG

CTI

R_IO

External creepage

DWW-16

14.5

600

10¹²

10¹¹

Comparative tracking index

Isolation resistance, input to output⁽¹⁾

DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A

V_IO= 500 V, T_A= 25°C

Ω

V_IO= 500 V, 100°C ≤T_A≤max

Ω

C_IO

C_I

Barrier capacitance, input to output⁽¹⁾

Input capacitance⁽²⁾

V_IO= 0.4 x sin (2πft), f = 1 MHz

V_I= V_CC/2 + 0.4 x sin (2πft), f = 1 MHz, V_CC= 5 V

(1) All pins on each side of the barrier tied together creating a two-terminal device.

(2) Measured from input pin to ground.

备注

Creepage and clearance requirements should be applied according to the specific equipment isolation

standards of an application. Care should be taken to maintain the creepage and clearance distance of

a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not

reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such

as inserting grooves and/or ribs on a printed circuit board are used to help increase these

specifications.

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表8-2. Insulation Characteristics

PARAMETER

TEST CONDITIONS

SPECIFICATION

UNIT

DWW

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

μm

V_RMS

V_DC

1500

2121

2000

2828

Maximum working isolation

voltage

V_IOWM

Time dependent dielectric breakdown (TDDB) test

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V_TEST= V_IOTM

t = 60 sec (qualification)

t= 1 sec (100% production)

Maximum transient isolation

voltage

V_IOTM

8000

V_PK

Test method per IEC 60065, 1.2/50 µs waveform,

V_TEST= 1.6 x V_IOSM= 12800 V_PK⁽¹⁾(qualification)

V_IOSMMaximum surge isolation voltage

8000

2121

8000

2828

V_PK

Maximum repetitive peak isolation

V_IORM

voltage

Method a, After Input/Output safety test subgroup 2/3,

V_PR= V_IORMx 1.2, t = 10 s,

Partial discharge < 5 pC

2545

3394

3977

3394

4525

5303

Method a, After environmental tests subgroup 1,

V_PR= V_IORMx 1.6, t = 10 s,

Partial Discharge < 5 pC

V_PR

Input-to-output test voltage

V_PK

Method b1,After environmental tests subgroup 1,

V_PR= V_IORMx 1.875, t = 1 s (100% Production test)

Partial discharge < 5 pC

R_S

Isolation resistance

Pollution degree

Climatic category

V_IO= 500 V at T_S

>10⁹

Ω

55/125/21 55/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 sec (qualification);

V_TEST= 1.2 x V_ISO= 6840 V_RMS, t = 1 sec (100%

production)

V_ISO

Withstanding isolation voltage

5700

V_RMS

(1) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

表8-3. IEC 60664-1 Ratings Table

PARAMETER

TEST CONDITIONS

SPECIFICATION

Material group

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

I–IV

I–III

I–IV

DW package

Overvoltage category /

Installation classification

DWW package

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8.3.1.1 Regulatory Information

DW package certifications are complete; DWW package certifications completed for UL and TUV and planned

for VDE, CSA, and CQC.

表8-4. Regulatory Information

VDE

CSA

CQC

TUV

Certified according to

DIN V VDE V 0884-10

(VDE V

0884-10):2006-12 and

DIN EN 60950-1 (VDE

0805 Teil 1):2011-01

Approved under CSA

Component Acceptance

Notice 5A, IEC 60950-1

and IEC 60601-1

Certified according to

Recognized under UL

1577 Component

Recognition Program

Certified according to

GB 4943.1-2011

EN 61010-1:2010 (3rd Ed) and

EN 60950-1:2006/A11:2009/

A1:2010/A12:2011/A2:2013

Reinforced insulation per

CSA 60950-1-07+A1+A2

and IEC 60950-1 2nd Ed.,

800 V_RMS(DW package)

and 1450 V_RMS(DWW

package) max working

voltage (pollution degree

2, material group I);

5700 V_RMSReinforced insulation

per EN 61010-1:2010 (3rd Ed)

up to working voltage of 600

V_RMS(DW package) and 1000

V_RMS(DWW package)

Reinforced insulation

Maximum transient

isolation voltage, 8000

Reinforced Insulation,

Altitude ≤5000 m,

Tropical Climate, 250

V_RMSmaximum working

voltage

V_PK

;

Maximum repetitive peak

isolation voltage, 2121

V_PK(DW), 2828 V_PK

(DWW);

Maximum surge isolation

voltage, 8000 V_PK

Single protection, 5700

V_RMS

2 MOPP (Means of Patient

Protection) per CSA

60601-1:14 and IEC

60601-1 Ed. 3.1,

250 V_RMS(354 V_PK) max

working voltage (DW

package)

5700 V_RMSReinforced insulation

per EN 60950-1:2006/A11:2009/

A1:2010/A12:2011/A2:2013 up

to working voltage of 800 V_RMS

(DW package) and 1450 V_RMS

(DWW package)

Certificate number:

40040142

Master contract number:

220991

Certificate number:

CQC15001121716

File number: E181974

Client ID number: 77311

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8.3.1.2 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.

A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate

sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system

failures.

表8-5. Safety Limiting

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

268

410

537

UNIT

_θJA= 84.7°C/W, V_I= 5.5 V, T_J= 150°C, T_A= 25°C

_θJA= 84.7°C/W, V_I= 3.6 V, T_J= 150°C, T_A= 25°C

_θJA= 84.7°C/W, V_I= 2.75 V, T_J= 150°C, T_A= 25°C

_θJA= 84.7°C/W, T_J= 150°C, T_A= 25°C

Safety input, output, or supply

current for DW-16 package

and DWW-16 Packages

I_S

P_S

T_S

Safety input, output, or total

power

°C

1476

150

Maximum safety temperature

The maximum safety temperature is the maximum junction temperature specified for the device. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines

the junction temperature. The assumed junction-to-air thermal resistance in the 节6.4 is that of a device installed

on a High-K test board for Leaded Surface Mount Packages. The power is the recommended maximum input

voltage times the current. The junction temperature is then the ambient temperature plus the power times the

junction-to-air thermal resistance.

600

500

400

300

200

100

1600

1400

1200

1000

800

600

400

200

Power

V_CC1= V_CC2= 2.75 V

V_CC1= V_CC2= 3.6 V

V_CC1= V_CC2= 5.5 V

100

Ambient Temperature (èC)

150

200

100

Ambient Temperature (èC)

150

200

D015

D014

图8-4. Thermal Derating Curve for Safety Limiting

图8-3. Thermal Derating Curve for Safety Limiting

Power per VDE

Current per VDE

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8.4 Device Functional Modes

ISO7821 functional modes are shown in 表8-6.

表8-6. ISO7821 Function Table

OUTPUT ENABLE

(ENx)

(DWW Package Only)

INPUT

(INx)⁽²⁾

OUTPUT

(OUTx)

V_CCI

V_CCO

COMMENTS

H or open

Normal Operation:

A channel output assumes the logic state of its input.

Default mode: When INx is open, the corresponding channel output

goes to its default high logic state. Default= High for ISO7821 and Low

for ISO7821F.

Open

H or open

Default

A low value of Output Enable causes the outputs to be high-

impedance.

Default mode: When V_CCIis unpowered, a channel output assumes

the logic state based on the selected default option.Default= High for

ISO7821 and Low for ISO7821F.

H or open

Default

When V_CCItransitions from unpowered to powered-up, a channel

output assumes the logic state of its input.

When V_CCItransitions from powered-up to unpowered, channel output

assumes the selected default state.

When V_CCOis unpowered, a channel output is undetermined ⁽¹⁾

Undetermined When V_CCOtransitions from unpowered to powered-up, a channel

output assumes the logic state of its input

(1) The outputs are in undetermined state when 1.7 V < V_CCI, V_CCO< 2.25 V.

(2) A strongly driven input signal can weakly power the floating V_CCvia an internal protection diode and cause undetermined output.

8.4.1 Device I/O Schematics

Input (Device Without Suffix F)

Input (Device With Suffix F)

CCI

1.5 MW

985 W

INx

1.5 MW

Output

Enable

CCO

2 MW

1970 W

~20 W

Enx

OUTx

图8-5. Device I/O Schematics

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The ISO7821 is a high-performance, dual-channel digital isolator with 5.7 kV_RMSisolation voltage per UL 1577. It

utilizes single-ended CMOS-logic switching technology. Its supply voltage range is from 2.25 V to 5.5 V for both

supplies, V_CC1and V_CC2. When designing with digital isolators, it is important to keep in mind that due to the

single-ended design structure, digital isolators do not conform to any specific interface standard and are only

intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the

data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type

or standard.

9.2 Typical Application

ISO7821 can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,

transformer driver, and voltage regulator to create an isolated 4-20 mA current loop .

0.1 ꢀF

3.3 V

MBR0520L

1:1.33

3.3V_ISO

OUT

GND

10 ꢀF

TPS76333

SN6501

10 ꢀF 0.1 ꢀF

GND

4, 5

10 ꢀF

MBR0520L

Isolation Barrier

0.1 ꢀF

20 ꢁ

LOOP+

0.1 ꢀF

LOW

BASE

OUT

CC2

0.1 ꢀF 1 ꢀF

ERRLVL

CC1

DAC161P997

22 ꢁ

INA

DBACK

DIN

XOUT

XIN

P3.0

P3.1

OUTA

INB

ISO7821

MSP430G2132

OUTB

LOOPœ

C1 C2 C3 COMA COMD

GND1

1, 7

GND2

9, 16

14 13 12

3 × 2.2 nF

图9-1. Isolated 4-20 mA Current Loop

9.2.1 Design Requirements

For the ISO7821, use the parameters shown in 表9-1.

表9-1. Design Parameters

PARAMETER

VALUE

Supply voltage

2.25 V to 5.5 V

0.1 µF

Decoupling capacitor between V_CC1and GND1

Decoupling capacitor from V_CC2and GND2

0.1 µF

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9.2.2 Detailed Design Procedure

Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,

ISO7821 only needs two external bypass capacitors to operate.

ISO7821DW

CC2

CC1

GND1

16 GND2

15 NC

GND1

GND2

0.1 µF

GND1

GND2

CC2

CC1

INA

OUTA

INB

13 INA

12 OUTB

11 NC

10 NC

INB

OUTB

GND1

GND2

图9-2. Typical ISO7821 Circuit Hook-up

9.2.2.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO7821

incorporate many chip-level design improvements for overall system robustness. Some of these improvements

include:

• Robust ESD protection for input and output signal pins and inter-chip bond pads.

• Low-resistance connectivity of ESD cells to supply and ground pins.

• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

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9.2.3 Application Performance Curve

Typical eye diagram of ISO7821 indicate low jitter and wide open eye at the maximum data rate of 100 Mbps.

图9-3. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C

Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at

input and output supply pins (V_CC1and V_CC2). The capacitors should be placed as close to the supply pins as

possible. If only a single primary-side power supply is available in an application, isolated power can be

generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For

such applications, detailed power supply design and transformer selection recommendations are available in

SN6501 datasheet (SLLSEA0) .

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10 Layout

10.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of

up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the

requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower

dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-

extinguishing flammability-characteristics.

10.2 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see 图 10-1). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in².

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the

stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be placed closer together, thus increasing the high-

frequency bypass capacitance significantly.

For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.

10.3 Layout Example

High-speed traces

10 mils

Ground plane

Keep this

FR-4

space free

from planes,

traces, pads,

and vias

40 mils

10 mils

0 ~ 4.5

Power plane

Low-speed traces

图10-1. Layout Example

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

See the Isolation Glossary (SLLA353)

11.2 Trademarks

所有商标均为其各自所有者的财产。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

SOIC

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

14X 1.27

10.5

10.1

NOTE 3

8.89

0.51

0.31

16X

7.6

7.4

2.65 MAX

0.25

C A

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

16X (1.65)

16X (0.6)

SEE

DETAILS

SEE

DETAILS

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

14X (1.27)

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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PACKAGE OUTLINE

DWW0016A

SOIC - 2.65 mm max height

PLASTIC SMALL OUTLINE

17.4

17.1

SEATING PLANE

0.1 C

PIN 1 ID AREA

14X 1.27

10.4

10.2

NOTE 3

8.89

0.51

16X

(2.286)

0.31

14.1

13.9

NOTE 4

0.25

A B

2.65 MAX

0.28

0.22

TYP

SEE DETAIL A

(1.625)

0.25

GAGE PLANE

0.3

0.1

1.1

0.6

0 -8

DETAIL A

TYPICAL

4221501/A 11/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0,15 mm per side.

4. This dimension does not include interlead flash.

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EXAMPLE BOARD LAYOUT

DWW0016A

SOIC - 2.65 mm max height

PLASTIC SMALL OUTLINE

16X (1.875)

(14.5)

16X (2)

(14.25)

16X (0.6)

SYMM

14X

(1.27)

14X

(1.27)

SYMM

(16.25)

SYMM

(16.375)

LAND PATTERN EXAMPLE

PCB CLEARANCE & CREEPAGE OPTIMIZED

SCALE:3X

LAND PATTERN EXAMPLE

STANDARD

SCALE:3X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221501/A 11/2014

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DWW0016A

SOIC - 2.65 mm max height

PLASTIC SMALL OUTLINE

16X (2)

SYMM

16X (0.6)

SYMM

14X (1.27)

(16.25)

SOLDER PASTE EXAMPLE

STANDARD

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

16X (1.875)

SYMM

16X (0.6)

SYMM

14X (1.27)

(16.375)

SOLDER PASTE EXAMPLE

PCB CLEARANCE & CREEPAGE OPTIMIZED

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221501/A 11/2014

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

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PACKAGE OPTION ADDENDUM

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5-Jul-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ISO7821DW

ISO7821DWR

ISO7821DWW

ISO7821DWWR

ISO7821FDW

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

Level-3-260C-168 HR

-55 to 125

ISO7821

Samples

2000 RoHS & Green

45 RoHS & Green

1000 RoHS & Green

40 RoHS & Green

2000 RoHS & Green

45 RoHS & Green

1000 RoHS & Green

NIPDAU

ISO7821

ISO7821F

DWW

ISO7821FDWR

ISO7821FDWW

ISO7821FDWWR

DWW

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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5-Jul-2022

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

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9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ISO7821DWR

ISO7821DWWR

ISO7821FDWR

ISO7821FDWWR

SOIC

DWW

2000

1000

2000

1000

330.0

16.4

24.4

16.4

24.4

10.75 10.7

18.0 10.0

10.75 10.7

18.0 10.0

2.7

3.0

2.7

3.0

12.0

20.0

12.0

20.0

16.0

24.0

16.0

24.0

DWW

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ISO7821DWR

ISO7821DWWR

ISO7821FDWR

ISO7821FDWWR

SOIC

DWW

2000

1000

2000

1000

350.0

43.0

DWW

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ISO7821DW

ISO7821DWW

ISO7821FDW

ISO7821FDWW

DWW

SOIC

506.98

507

12.7

4826

5000

4826

5000

6.6

506.98

507

12.7

6.6

DWW

Pack Materials-Page 3

重要声明和免责声明

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ISO7821DWW [TI]

相关型号：

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SI9135LG-T1

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SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E