ISO7831DWW [TI]
高隔离额定值、三通道、2/1、增强型数字隔离器 | DWW | 16 | -55 to 125;型号: | ISO7831DWW |
厂家: | TEXAS INSTRUMENTS |
描述: | 高隔离额定值、三通道、2/1、增强型数字隔离器 | DWW | 16 | -55 to 125 |
文件: | 总30页 (文件大小:1624K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ISO7831, ISO7831F
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
ISO7831 高性能 8000 VPK 增强型三通道数字隔离器
1 特性
3 说明
1
•
•
•
•
•
•
信号传输速率:高达 100Mbps
ISO7831 是一款高性能三通道数字隔离器,隔离电压
高达 8000 VPK。 该器件已通过符合 VDE、CSA 和
CQC 标准的增强型隔离认证。 在隔离 CMOS 或者
LVCMOS 数字 I/O 时,该隔离器可提供高电磁抗扰度
和低辐射,且具有低功耗特性。 每个隔离通道的逻辑
输入和输出缓冲器均由二氧化硅 (SiO2) 绝缘隔栅分离
开来。 该器件配有使能引脚,可用于将多个主驱动应
用中的相应输出置于高阻态,也可用于降低功耗。
ISO7831 具有两个正向通道和一个反向通道。 如果出
现输入功率或信号丢失,ISO7831 器件默认输出“高”电
平,ISO7831F 器件默认输出“低”电平。 更多详细信
息,请参见器件功能模式。 与隔离式电源一起使用
时,此器件可防止数据总线或者其他电路上的噪声电流
进入本地接地,以及干扰或损坏敏感电路。 凭借创新
的芯片设计和布线技术,ISO7831 的电磁兼容性得到
了显著增强,从而可确保提供系统级 ESD、EFT 和浪
涌保护并符合辐射标准。 ISO7831 采用 16 引脚小外
形尺寸集成电路 (SOIC) 宽体 (DW) 封装。
宽电源电压范围:2.25V 至 5.5V
2.25V 至 5.5V 电平转换
宽温度范围:–55°C 至 125°C
低功耗,每通道电流典型值为 2.5mA(1Mbps 时)
低传播延迟:典型值 11ns
(5V 电源供电时)
•
•
•
行业领先的 CMTI:±100kV/μs
优异的电磁兼容性 (EMC)
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪
涌保护
•
•
•
•
低辐射
隔离隔栅寿命:> 25 年
宽体小外形尺寸集成电路 (SOIC)-16 封装
安全及管理批准:
–
8000 VPK VIOTM 和 2121 VPK VIORM 增强型隔
离,符合 DIN V VDE V 0884-10 (VDE V 0884-
10):2006-12 标准
–
–
–
符合 UL 1577 标准且长达 1 分钟的 5.7kVRMS
隔离
器件信息(1)
器件型号
ISO7831
ISO7831F
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
封装
封装尺寸(标称值)
CSA 组件接受通知 5A,IEC 60950-1、IEC
60601-1 和 IEC 61010-1 终端设备标准
SOIC,DW (16) 10.30mm x 7.50mm
通过 GB4943.1-2011 CQC 认证
2 应用范围
•
•
•
•
•
•
工业自动化
电机控制
电源
太阳能逆变器
医疗设备
混合动力电动汽车
简化电路原理图
V
V
CCI
CCO
Isolation
Capacitor
INx
OUTx
ENx
GNDI
GNDO
(1)
(2)
V
CCI 和 GNDI 分别是输入通道的电源和接地连接。
CCO 和 GNDO 分别是输出通道的电源和接地连接。
V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEP8
ISO7831, ISO7831F
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
目录
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Rating............................................................. 5
6.6 Electrical Characteristics, 5 V ................................... 6
6.7 Electrical Characteristics, 3.3 V ................................ 7
6.8 Electrical Characteristics, 2.5 V ................................ 8
6.9 Switching Characteristics, 5 V .................................. 9
6.10 Switching Characteristics, 3.3 V ............................. 9
6.11 Switching Characteristics, 2.5 V ........................... 10
6.12 Typical Characteristics.......................................... 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 14
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 24
12.1 文档支持................................................................ 24
12.2 相关链接................................................................ 24
12.3 社区资源................................................................ 24
12.4 商标....................................................................... 24
12.5 静电放电警告......................................................... 24
12.6 Glossary................................................................ 24
13 机械、封装和可订购信息....................................... 24
7
8
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2015) to Revision A
Page
•
已从“单页产品预览”更改为“量产”数据表 ................................................................................................................................. 1
2
Copyright © 2015, Texas Instruments Incorporated
ISO7831, ISO7831F
www.ti.com.cn
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
VCC1
VCC2
1
16
15
14
13
12
11
10
9
GND1
GND2
2
INA
OUTA
OUTB
3
INB
4
OUTC
INC
5
NC
NC
6
EN2
EN1
7
GND1
GND2
8
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-
impedance state when EN1 is low.
EN1
EN2
7
I
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-
impedance state when EN2 is low.
10
GND1
GND2
INA
2, 8
9, 15
3
—
—
I
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
INB
4
I
Input, channel B
INC
12
14
13
5
I
Input, channel C
OUTA
OUTB
OUTC
NC
O
O
O
—
—
—
Output, channel A
Output, channel B
Output, channel C
Not connected
6,11
1
VCC1
VCC2
Power supply, VCC1
Power supply, VCC2
16
Copyright © 2015, Texas Instruments Incorporated
3
ISO7831, ISO7831F
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
VCC1
VCC2
,
Supply voltage(2)
–0.5
6
V
INx
Voltage
OUTx
ENx
–0.5
VCCX + 0.5(3)
V
IO
Output current
–15
–65
15
mA
°C
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±6000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC1
VCC2
,
Supply voltage
2.25
5.5
V
VCCO(1) = 5 V
VCCO(1) = 3.3 V
VCCO(1) = 2.5 V
VCCO(1) = 5 V
VCCO(1) = 3.3 V
VCCO(1) = 2.5 V
–4
–2
–1
IOH
High-level output current
mA
mA
4
2
IOL
Low-level output current
1
(1)
(1)
VIH
VIL
DR
TJ
High-level input voltage
Low-level input voltage
Signaling rate
0.7 × VCCI
VCCI
V
V
(1)
0
0
0.3 × VCCI
100
150
125
Mbps
°C
Junction temperature(2)
–55
–55
TA
Ambient temperature
25
°C
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) To maintain the recommended operating conditions for TJ, see Thermal Information.
4
Copyright © 2015, Texas Instruments Incorporated
ISO7831, ISO7831F
www.ti.com.cn
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
6.4 Thermal Information
DW (SOIC)
UNIT
THERMAL METRIC(1)
16 Pins
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
78.9
41.6
RθJC(top)
RθJB
Junction-to-board thermal resistance
43.6
°C/W
15.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
43.1
N/A
RθJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Power Rating
VALUE
150
UNIT
PD
Maximum power dissipation by ISO7831
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
PD1
PD2
Maximum power dissipation by side-1 of ISO7831 CL = 15 pF, input a 50 MHz 50% duty cycle
50
mW
square wave
Maximum power dissipation by side-2 of ISO7831
100
Copyright © 2015, Texas Instruments Incorporated
5
ISO7831, ISO7831F
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
6.6 Electrical Characteristics, 5 V
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 7
MIN
VCCO(1) – 0.4
TYP
VCCO(1) – 0.2
0.2
MAX
UNIT
V
VOH
VOL
High-level output voltage
Low-level output voltage
IOL = 4 mA; see Figure 7
0.4
10
V
Input threshold voltage
hysteresis
(1)
VI(HYS)
0.1 × VCCO
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
μA
μA
–10
70
Common-mode transient
immunity
CMTI
VI = VCCI(1) or 0 V; see Figure 10
100
1.0
kV/μs
DC signal: VI = 0 V
(Devices with suffix F) ,
Disable;
ICC1
1.6
1.3
4.8
2.9
2.3
2.6
5.6
4.3
EN1 = EN2 = 0 V VI = VCCI (Devices
without suffix F)
DC signal: VI = 0 V
Disable;
(Devices with suffix F) ,
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
3.3
2
EN1 = EN2 = 0 V VI = VCCI (Devices
without suffix F)
DC signal: VI = VCCI
Disable;
(Devices with suffix F) ,
EN1 = EN2 = 0 V VI = 0 V(Devices without
suffix F)
DC signal: VI = VCCI
Disable;
(Devices with suffix F) ,
EN1 = EN2 = 0 V VI = 0 V(Devices without
suffix F)
DC signal: VI = 0 V
(Devices with suffix F) ,
VI = VCCI (Devices
DC signal
1.4
1.7
3.8
3
without suffix F)
Supply current
mA
DC signal: VI = 0 V
(Devices with suffix F) ,
VI = VCCI (Devices
DC signal
without suffix F)
DC signal: VI = VCCI
(Devices with suffix F) ,
VI = 0 V(Devices without
DC signal
suffix F)
DC signal: VI = VCCI
(Devices with suffix F) ,
VI = 0 V(Devices without
DC signal
suffix F)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1 Mbps
2.6
2.4
3.2
3.4
8.7
13.2
4
1 Mbps
3.6
AC signal: All channels
10 Mbps
10 Mbps
100 Mbps
100 Mbps
4.5
switching with square
wave clock input;
CL = 15 pF
4.6
10.5
15.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
6
Copyright © 2015, Texas Instruments Incorporated
ISO7831, ISO7831F
www.ti.com.cn
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
6.7 Electrical Characteristics, 3.3 V
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –2 mA; see Figure 7
MIN
VCCO(1) – 0.4 VCCO(1) – 0.2
0.2
TYP
MAX
UNIT
V
VOH
VOL
High-level output voltage
Low-level output voltage
IOL = 2 mA; see Figure 7
0.4
V
Input threshold voltage
hysteresis
(1)
VI(HYS)
0.1 × VCCO
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
μA
-10
Common-mode transient
immunity
CMTI
VI = VCCI(1) or 0 V; see Figure 10
70
100
1.0
kV/μs
DC signal: VI = 0 V
Disable;
EN1 = EN2 = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
ICC1
1.6
1.3
4.8
2.9
2.3
2.6
5.6
4.3
DC signal: VI = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
Disable;
EN1 = EN2 = 0 V
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
3.3
1.9
1.4
1.7
3.8
2.9
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
DC signal
DC signal
DC signal
DC signal
Supply current
mA
DC signal: VI = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1 Mbps
2.6
2.4
3.0
3.1
6.9
10.1
4
1 Mbps
3.5
4.3
4.3
8.3
12.2
AC signal: All channels
switching with square
wave clock input;
CL = 15 pF
10 Mbps
10 Mbps
100 Mbps
100 Mbps
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
Copyright © 2015, Texas Instruments Incorporated
7
ISO7831, ISO7831F
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
6.8 Electrical Characteristics, 2.5 V
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
VCCO
–
VOH
High-level output voltage
Low-level output voltage
IOH = –1 mA; see Figure 7
VCCO(1) – 0.4
V
V
V
0.2
VOL
IOL = 1 mA; see Figure 7
0.2
0.4
10
Input threshold voltage
hysteresis
(1)
VI(HYS)
0.1 × VCCO
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
μA
μA
–10
70
Common-mode transient
immunity
CMTI
VI = VCCI(1) or 0 V; see Figure 10
100
0.9
kV/μs
DC signal: VI = 0 V
Disable;
EN1 = EN2 = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
ICC1
1.6
1.3
4.8
2.9
2.3
2.6
5.6
4.3
DC signal: VI = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
Disable;
EN1 = EN2 = 0 V
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.8
3.3
1.9
1.4
1.7
3.8
2.9
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
DC signal
DC signal
DC signal
DC signal
Supply current
mA
DC signal: VI = 0 V
(Devices with suffix F) , VI
= VCCI (Devices without
suffix F)
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
DC signal: VI = VCCI
(Devices with suffix F) , VI
= 0 V(Devices without
suffix F)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1 Mbps
2.6
2.3
2.9
2.9
5.8
8.2
4
1 Mbps
3.5
4.3
4.1
7.2
10.0
AC signal: All channels
switching with square
wave clock input;
CL = 15 pF
10 Mbps
10 Mbps
100 Mbps
100 Mbps
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
8
Copyright © 2015, Texas Instruments Incorporated
ISO7831, ISO7831F
www.ti.com.cn
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
6.9 Switching Characteristics, 5 V
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
11
MAX
16
UNIT
tPLH, tPHL
PWD(1)
6
See Figure 7
|
0.55
4.1
2.5
4.5
3.9
3.9
20
(2)
tsk(o)
Channel-to-channel output skew time
Same-direction channels
See Figure 7
(3)
tsk(pp)
Part-to-part skew time
ns
tr
Output signal rise time
1.7
1.9
12
12
10
2
tf
Output signal fall time
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
Enable propagation delay, high impedance-to-high output
Enable propagation delay, high impedance-to-high output
Enable propagation delay, high impedance-to-low output
Enable propagation delay, high impedance-to-low output
20
20
ns
μs
μs
ns
tPZH
See Figure 8
2.5
2.5
20
2
tPZL
10
Measured from the time VCC
goes below 1.7 V. See Figure 9
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
9
μs
216 – 1 PRBS data at 100 Mbps
0.90
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.10 Switching Characteristics, 3.3 V
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10.8
0.7
MAX
16
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
6
See Figure 7
Pulse width distortion |tPHL – tPLH
|
4.2
2.2
4.5
3
(2)
tsk(o)
Channel-to-channel output skew time
Part-to-part skew time
Same-direction channels
See Figure 7
(3)
tsk(pp)
tr
tf
Output signal rise time
0.8
0.8
ns
Output signal fall time
3
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
17
17
17
2
32
32
32
2.5
2.5
32
9
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output
ns
μs
μs
ns
tPZH
See Figure 8
Enable propagation delay, high impedance-to-high
output
Enable propagation delay, high impedance-to-low
output
2
tPZL
Enable propagation delay, high impedance-to-low
output
17
Measured from the time VCC goes
below 1.7 V. See Figure 9
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
μs
216 – 1 PRBS data at 100 Mbps
0.91
ns
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.11 Switching Characteristics, 2.5 V
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11.7
0.66
MAX
17.5
4.2
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
7.5
See Figure 7
Pulse width distortion |tPHL – tPLH
|
(2)
tsk(o)
Channel-to-channel output skew time
Part-to-part skew time
Same-direction Channels
See Figure 7
2.2
(3)
tsk(pp)
4.5
tr
tf
Output signal rise time
1
3.5
ns
Output signal fall time
1.2
3.5
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
22
22
18
2
45
45
45
2.5
2.5
45
9
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output
ns
μs
μs
ns
tPZH
See Figure 8
Enable propagation delay, high impedance-to-high
output
Enable propagation delay, high impedance-to-low
output
2
tPZL
Enable propagation delay, high impedance-to-low
output
18
Measured from the time VCC goes
below 1.7 V. See Figure 9
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
μs
216 – 1 PRBS data at 100 Mbps
0.91
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
10
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6.12 Typical Characteristics
24
10
8
ICC1 at 2.5 V (mA)
ICC2 at 2.5 V (mA)
ICC1 at 3.3 V (mA)
ICC2 at 3.3 V (mA)
ICC1 at 5 V (mA)
ICC2 at 5 V (mA)
ICC1 at 2.5 V (mA)
ICC2 at 2.5 V (mA)
ICC1 at 3.3 V (mA)
ICC2 at 3.3 V (mA)
ICC1 at 5 V (mA)
ICC2 at 5 V (mA)
20
16
12
8
6
4
2
4
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Data Rate (Mbps)
Data Rate (Mbps)
D001
D002
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 1. Supply Current vs Data Rate (With 15-pF Load)
Figure 2. Supply Current vs Data Rate (With No Load)
6
1
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
1
0
-15
-10
-5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
D003
D0041
TA = 25°C
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output
Current
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
2.25
13
12
11
10
9
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5.0 V
tPHL at 5.0 V
1.75
1.7
8
-50
0
50
Free-Air Temperature (oC)
100
150
-60
-30
0
30
60
90
120
Free-Air Temperature (oC)
D005
D006
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
Figure 6. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
VCCI
VI
50%
50%
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator
Note A
50 W
VI
CL
VOH
VOL
90%
10%
Note B
50%
50%
VO
tr
tf
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7. Switching Characteristics Test Circuit and Voltage Waveforms
V
CCO
V
CC
R = 1 kW
L
±1%
V
/2
V
/2
CC
CC
V
V
I
0 V
IN
OUT
t
t
V
O
PLZ
PZL
0V
V
CCO
0.5 V
V
50%
EN
O
C
L
OL
Note B
Input
V
I
Generator
Note A
50W
V
CC
V
O
V
/2
V
/2
CC
IN
CC
OUT
V
V
I
3V
0 V
V
t
EN
PZH
C
L
OH
R = 1 kW
±1%
L
Note B
50%
Input
Generator
Note A
0.5 V
O
V
I
50W
0 V
t
PHZ
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Enable/Disable Propagation Delay Time Test Circuit and Waveform
12
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Parameter Measurement Information (continued)
V
I
V
V
CC
CC
2.7 V
V
I
0 V
V
IN
OUT
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
t
V
fs
O
OH
fs high
fs low
50%
V
O
C
L
V
OL
NOTE A
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 μF 1ꢀ
C = 0.1 μF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL
Note A
VOH or VOL
–
GNDI
GNDO
–
+
VCM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
ISO7831 employs an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon
dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one
digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after
advanced signal conditioning and produces the output through a buffer stage. If the EN pin is low then the output
goes to high impedance. ISO7831 also incorporates advanced circuit techniques to maximize the CMTI
performance and minimize the radiated emissions due the high frequency carrier and IO buffer switching. The
conceptual block diagram of a digital capacitive isolator, Figure 11, shows a functional block diagram of a typical
channel.
8.2 Functional Block Diagram
w9/9Lë9w
Çw!b{aLÇÇ9w
9b
hhY
ah5Ü[!ÇLhb
{ih2 ꢀꢁsed
Çó {LDb![
/hb5LÇLhbLbD
Çó Lb
wó hÜÇ
/ꢁpꢁciꢂiꢃe
Lsolꢁꢂion
.ꢁrrier
wó {LDb![
/hb5LÇLhbLbD
9bë9[ht9
59Ç9/ÇLhb
9aL{{Lhb{
w95Ü/ÇLhb
Ç9/IbLvÜ9{
h{/L[[!Çhw
Figure 11. Conceptual Block Diagram of a Digital Capacitive Isolator
Also a conceptual detail of how the ON/OFF Keying scheme works is shown in Figure 12.
TX IN
Carrier signal
through
isolation barrier
RX OUT
Figure 12. On-Off Keying (OOK) Based Modulation Scheme
14
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8.3 Feature Description
PRODUCT
ISO7831
ISO7831
CHANNEL DIRECTION
RATED ISOLATION
5700 VRMS / 8000 VPK
5700 VRMS / 8000 VPK
MAX DATA RATE
DEFAULT OUTPUT
(1)
(1)
2 Forward, 1 Reverse
2 Forward, 1 Reverse
100 Mbps
100 Mbps
High
Low
(1) See Regulatory Information for detailed isolation ratings.
8.3.1 High Voltage Feature Description
8.3.1.1 Package Insulation and Safety-Related Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Shortest terminal-to-terminal distance
through air
L(I01)
L(I02)(1)
CTI
Minimum air gap (clearance)
DW-16
DW-16
8
mm
mm
V
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance
across the package surface
8
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
600
VIO = 500 V, TA = 25°C
1012
1011
Ω
Ω
Isolation resistance, input to
output(2)
RIO
VIO = 500 V, 100°C ≤ TA ≤ max
Barrier capacitance, input to
output(2)
Input capacitance(3)
CIO
CI
VIO = 0.4 x sin (2πft), f = 1 MHz
2
2
pF
pF
VI = VCC/2 + 0.4 x sin (2πft), f = 1 MHz, VCC = 5 V
(1) Per JEDEC package dimensions.
(2) All pins on each side of the barrier tied together creating a two-terminal device.
(3) Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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8.3.1.2 Insulation Characteristics
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
μm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
21
1500
2121
VRMS
VDC
VIOWM
Maximum isolation working voltage
Time dependent dielectric breakdown (TDDB) Test
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VTEST = VIOTM
VIOTM
Maximum transient isolation voltage
t = 60 sec (qualification)
t= 1 sec (100% production)
8000
VPK
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM = 12800 VPK (qualification)
VIOSM
VIORM
Maximum surge isolation voltage
8000
2121
VPK
VPK
Maximum repetitive peak isolation voltage
Method a, After Input/Output safety test subgroup
2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
2545
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
VPR
Input-to-output test voltage
VPK
3394
3977
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
RS
Isolation resistance
Pollution degree
VIO = 500 V at TS
>109
2
Ω
UL 1577
VISO
VTEST = VISO = 5700 VRMS, t = 60 sec
(qualification),
VTEST = 1.2 x VISO = 6840 VRMS, t = 1 sec (100%
production)
Withstanding isolation voltage
5700
VRMS
(1) Climatic Classification 55/125/21
8.3.1.3 IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I
I–IV
I–III
Installation classification
16
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8.3.1.4 Regulatory Information
DW package certifications are complete.
VDE
CSA
UL
CQC
Certified according to DIN V VDE Approved under CSA
Certified according to UL 1577
Component Recognition
Program
V 0884-10 (VDE V 0884-
Component Acceptance Notice
Certified according to GB 4943.1-
2011
10):2006-12 and DIN EN 60950- 5A, IEC 60950-1, IEC 61010-1,
1 (VDE 0805 Teil 1):2011-01
and IEC 60601-1
Reinforced insulation per CSA
61010-1-12 and IEC 61010-1
3rd Ed., 300 VRMS max working
voltage;
Reinforced insulation
Maximum transient isolation
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
max working voltage (pollution
degree 2, material group I) ;
voltage, 8000 VPK
;
Reinforced Insulation, Altitude ≤
5000 m, Tropical Climate, 250 VRMS
maximum working voltage
(1)
Maximum repetitive peak
isolation voltage, 2121 VPK
Maximum surge isolation
voltage, 8000 VPK
Single protection, 5700 VRMS
;
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage
Master contract number:
220991
Certificate number:
CQC15001121716
Certificate number: 40040142
File number: E181974
(1) Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.
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8.3.1.5 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
288
440
576
UNIT
R
R
R
R
θJA = 78.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
θJA = 78.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
θJA = 78.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C
θJA = 78.9°C/W, TJ = 150°C, TA = 25°C
Safety input, output, or supply
current for DW-16 Package
IS
mA
PS
TS
Safety input, output, or total
power
mW
°C
1584
150
Maximum case temperature
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a High-K test board for Leaded Surface Mount Packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance
700
600
500
400
300
200
100
0
1800
1600
1400
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Power
0
50
100
150
200
0
50
100
150
200
Ambient Temperature (èC)
Ambient Temperature (èC)
D014
D015
Figure 13. Thermal Derating Curve per VDE for
DW-16 Package
Figure 14. Thermal Derating Curve for Safety Limiting
Power per VDE
18
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8.4 Device Functional Modes
ISO7831 functional modes are shown in Table 1.
Table 1. Function Table(1)
OUTPUT
ENABLE
(ENx)
INPUT
(INx)(2)
OUTPUT
(OUTx)
VCCI
VCCO
COMMENTS
H
L
H or open
H or open
H or open
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU
X
PU
PU
Open
Default
A low value of Output Enable causes the outputs to be high-
impedance
X
X
L
Z
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option.
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of its input.
PD
PU
H or open
Default
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
(3)
When VCCO is unpowered, a channel output is undetermined
.
X
PD
X
X
Undetermined When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of its input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without suffix F)
V
CCI
Enable
V
V
V
CCI
V
V
V
V
CCO
CCI
CCI
CCO
CCO
CCO
1.5 MW
2 MW
985 W
1970 W
INx
ENx
Output
Input (Devices with suffix F)
V
CCO
V
V
V
CCI
CCI
CCI
~20 W
985 W
OUTx
INx
1.5 MW
Figure 15. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7831 is a high-performance, quad-channel digital isolator with 5.7 kVRMS isolation voltage. The device
comes with enable pins on each side which can be used to put the respective outputs in high impedance for
multi master driving applications and reduce power consumption. ISO7831 uses single-ended CMOS-logic
switching technology. Its supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When
designing with digital isolators, it is important to keep in mind that due to the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The Isolated SPI Interface is shown in Figure 16.
V
IN
0.1ꢀF
3.3V
2
MBR0520L
1:2.2
5V
ISO
3
1
1
5
2
Vcc
D2
IN
OUT
TPS76350
SN6501
10ꢀF 0.1ꢀF
10ꢀF
3
EN
GND
D1
GND
4,5
10ꢀF
MBR0520L
ISO-BARRIER
0.1ꢀF
0.1ꢀF
0.1ꢀF
0.1ꢀF
1
16
2
VCC1
VCC2
DVcc
VCC
B
3
4
5
7
11
15
16
14
10ꢁ MELF
10ꢁ MELF
P3.0
INA
OUTA
RE
DE
5
6
2
3
4
XOUT
XIN
ISO7831
13
12
10
MSP430
F2132
UCA0TXD
UCA0RXD
INB
OUTB
SN65HVD
D
R
3082E
A
OUTC
EN1
INC
EN2
DVss
4
GND
1
SM712
GND1
GND2
2,8
9,15
4.7nF/
2kV
Figure 16. Isolated SPI Interface for an Analog Input Module With 16 Input
20
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Typical Application (continued)
9.2.1 Design Requirements
For ISO7831, use the parameters shown in Table 2.
Table 2. Design Parameters
PARAMETER
VALUE
2.25 to 5.5 V
0.1 µF
Supply voltage
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO7831 only needs two external bypass capacitors to operate.
2 mm max from VCC1
2 mm max from VCC2
0.1 µF
0.1 µF
VCC1
VCC2
1
2
3
4
16
GND1
GND2
15
14
INA
INB
OUTA
OUTB
INC
13
OUTC
12
11
10
9
5
6
7
8
NC
NC
EN2
EN1
GND1
GND2
Figure 17. Typical ISO7831 Circuit Hook-up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7831
incorporate many chip-level design improvements for overall system robustness. Some of these improvements
include:
•
•
•
•
Robust ESD protection for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.2.3 Application Curve
Typical eye diagram of ISO7831 indicate low jitter and wide open eye at the maximum data rate of 100 Mbps.
Figure 18. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 data sheet (SLLSEA0).
22
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 19). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see application note SLLA284, Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (flame retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces , pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 19. Layout Example Schematic
版权 © 2015, Texas Instruments Incorporated
23
ISO7831, ISO7831F
ZHCSE62A –JULY 2015–REVISED SEPTEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
《SN6501 用于隔离电源的变压器驱动器》,SLLSEA0
《数字隔离器设计指南》,SLLA284
12.1.1 相关文档
请参见隔离术语表 (SLLA353)
12.2 相关链接
下面的表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件,以及样片与购买的快速访
问。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文章
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
ISO7831
ISO7831F
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
24
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7831DW
ISO7831DWR
ISO7831DWW
ISO7831DWWR
ISO7831FDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
16
16
16
16
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
ISO7831
2000 RoHS & Green
45 RoHS & Green
1000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
45 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO7831
ISO7831
ISO7831
ISO7831F
ISO7831F
ISO7831F
ISO7831F
DWW
DWW
DW
ISO7831FDWR
ISO7831FDWW
ISO7831FDWWR
DW
DWW
DWW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7831DWR
ISO7831DWWR
ISO7831FDWR
ISO7831FDWWR
SOIC
SOIC
SOIC
SOIC
DW
DWW
DW
16
16
16
16
2000
1000
2000
1000
330.0
330.0
330.0
330.0
16.4
24.4
16.4
24.4
10.75 10.7
18.0 10.0
10.75 10.7
18.0 10.0
2.7
3.0
2.7
3.0
12.0
20.0
12.0
20.0
16.0
24.0
16.0
24.0
Q1
Q1
Q1
Q1
DWW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7831DWR
ISO7831DWWR
ISO7831FDWR
ISO7831FDWWR
SOIC
SOIC
SOIC
SOIC
DW
DWW
DW
16
16
16
16
2000
1000
2000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
DWW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7831DW
ISO7831DWW
ISO7831FDW
ISO7831FDWW
DW
DWW
DW
SOIC
SOIC
SOIC
SOIC
16
16
16
16
40
45
40
45
506.98
507
12.7
20
4826
5000
4826
5000
6.6
9
506.98
507
12.7
20
6.6
9
DWW
Pack Materials-Page 3
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