ISO7840DW [TI]
高隔离额定值、四通道、4/0、增强型数字隔离器 | DW | 16 | -55 to 125;
| 型号： | ISO7840DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高隔离额定值、四通道、4/0、增强型数字隔离器 | DW | 16 | -55 to 125 |
| 文件： | 总38页 (文件大小：1729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
ISO7840x 高性能、8000VPK 增强型四通道数字隔离器
1 特性
3 说明
1
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信号传输速率：高达 100Mbps
ISO7840x 器件是一款高性能四通道数字隔离器，隔离
电压为 8000VPK。该器件已通过符合 VDE、CSA、
CQC 和 TUV 标准的增强型隔离认证。在隔离互补金
属氧化物半导体 (CMOS) 或者低电压互补金属氧化物
半导体 (LVCMOS) 数字 I/O 时，该隔离器可提供高电
磁抗扰度和低辐射，同时具备低功耗特性。每个隔离通
道都有一个由二氧化硅 (SiO2) 绝缘隔栅分开的逻辑输
入和输出缓冲器。
宽电源电压范围：2.25V 至 5.5V
2.25V 至 5.5V 电平转换
宽温度范围：–55°C 至 +125°C
低功耗：电流典型值为 1.7mA/通道（1Mbps 时）
低传播延迟：典型值为 11ns
（5V 电源供电时）
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•
行业领先的 CMTI（最小值）：±100 kV/μs
优异的电磁兼容性 (EMC)
该器件配有使能引脚，可用于将多个主驱动应用中的相
应输出置于 高阻抗状态， 也可用于降低功耗。
ISO7840 器件具有 4 个正向通道和 0 个反向通道。如
果出现输入功率或信号丢失，ISO7840 器件默认输出
高电平，ISO7840F 器件默认输出低电平。有关更多详
细信息，请参阅 Device Functional Modes器件功能模
式部分。
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪
涌保护
•
•
•
•
低辐射
隔离层寿命：40 年以上
宽体 SOIC-16 封装和超宽体 SOIC-16 封装选项
安全及管理批准：中的“安全及管理批准”列表中的
“安全及管理批准”列表
–
–
–
8000 VPK 增强型隔离，符合 DIN V VDE V
0884-10 (VDE V 0884-10)：2006-12
与隔离式电源结合使用时，该器件有助于防止数据总线
或者其他电路中的噪声电流进入本地接地，进而干扰或
损坏敏感电路。凭借创新的芯片设计和布线技
术，ISO7840 器件的电磁兼容性得到了显著增强，可
确保提供系统级 ESD、EFT 和浪涌保护并符合辐射标
准。
符合 UL 1577 标准且长达 1 分钟的 5.7kVRMS
隔离
CSA 组件验收通知 5A，IEC 60950-1 和 IEC
60601-1 终端设备标准
–
–
符合 GB4943.1-2011 标准的 CQC 认证
ISO7840 器件采用 16 引脚 SOIC 宽体 (DW) 和超宽体
(DWW) 封装。
符合 EN 61010-1 和 EN 60950-1 标准的 TUV
认证
–
完成了所有 DW 封装认证；完成了符合 UL、
VDE、TUV 标准的 DWW 封装认证并且已针对
CSA 和 CQC 进行了规划
器件信息(1)
产品型号
ISO7840
封装
封装尺寸（标称值）
10.30mm x 7.50mm
10.30mm x 14.0mm
DW (16)
DWW (16)
ISO7840F
2 应用
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
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工业自动化
电机控制
简化电路原理图
电源
V
V
CCI
CCO
Isolation
Capacitor
太阳能逆变器
医疗设备
INx
OUTx
ENx
混合动力电动汽车
GNDI
GNDO
V
CCI 和 GNDI 分别是输入通道的电源和接地
连接。
CCO 和 GNDO 分别是输出通道的电源和接
地连接。
V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEN2
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
目录
6.19 Typical Characteristics.......................................... 15
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Power Ratings........................................................... 6
6.6 Insulation Specifications............................................ 7
6.7 Safety-Related Certifications..................................... 8
6.8 Safety Limiting Values .............................................. 8
6.9 Electrical Characteristics—5-V Supply ..................... 9
6.10 Supply Characteristics—5-V Supply ....................... 9
6.11 Electrical Characteristics—3.3-V Supply .............. 10
6.12 Supply Current Characteristics—3.3-V Supply..... 10
6.13 Electrical Characteristics—2.5-V Supply .............. 11
6.14 Supply Current Characteristics—2.5-V Supply..... 11
6.15 Switching Characteristics—5-V Supply................. 12
6.16 Switching Characteristics—3.3-V Supply.............. 12
6.17 Switching Characteristics—2.5-V Supply.............. 13
6.18 Insulation Characteristics Curves ......................... 14
7
8
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 文档支持................................................................ 25
12.2 相关链接................................................................ 25
12.3 接收文档更新通知 ................................................. 25
12.4 社区资源................................................................ 25
12.5 商标....................................................................... 25
12.6 静电放电警告......................................................... 25
12.7 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 26
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2016) to Revision B
Page
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在特性部分添加了“2.25V 至 5.5V 电平转换”........................................................................................................................... 1
已更改 隔离层寿命年数（特性部分） ..................................................................................................................................... 1
VDE 认证现在已完成 .............................................................................................................................................................. 1
Changed the input-to-output test voltage parameter to apparent charge in the Insulation Specifications ............................ 7
Changed VCCO to VCCI for the minimum value of the input threshold voltage hysteresis parameter in all electrical
characteristics tables .............................................................................................................................................................. 9
•
•
Added VCM to the test condition of the common-mode transient immunity parameter in all electrical characteristics tables 9
Added the lifetime projection graphs for DW and DWW packages to the Safety Limiting Values section ......................... 14
Changes from Original (July 2015) to Revision A
Page
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•
•
•
•
•
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将特性中的“行业领先的 CMTI”更改为“行业领先的 CMTI（最小值）...................................................................................... 1
更改了“特性”中的“安全及管理批准”列表 ................................................................................................................................. 1
在特性中添加了“符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证” ................................................................................... 1
将说明的第一段中的文本从“符合 VDE、CSA 和 CQC 的认证” 更改为“符合 VDE、CSA、CQC 和 TUV 的认证。” ............ 1
Added the DWW pinout image ............................................................................................................................................... 4
Added the DWW package to the Thermal Information .......................................................................................................... 6
Changed Package Insulation and Safety-Related Specifications, added the 16-DWW Package information....................... 7
Added the DWW package information, added "Climatic category", and deleted Note 1 in Insulation Characteristics ......... 7
Added Note 1 to Insulation Characteristics ........................................................................................................................... 7
Changed IEC 60664-1 Ratings Table ................................................................................................................................... 7
2
Copyright © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
•
Added the TUV and DWW package information to the Regulatory Information section and Regulatory Information.
Deleted Note 1 in Regulatory Information .............................................................................................................................. 8
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•
Changed the Supply Current section of Supply Characteristics—5-V Supply ....................................................................... 9
Changed the Supply Current section of Supply Current Characteristics—3.3-V Supply ..................................................... 10
Changed the Supply Current section ofSupply Current Characteristics—2.5-V Supply ..................................................... 11
Changed Device I/O Schematics ......................................................................................................................................... 20
Copyright © 2015–2016, Texas Instruments Incorporated
3
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
5 Pin Configuration and Functions
DW and DWW Packages
16-Pin SOIC
Top View
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
GND1
INA
15 GND2
14 OUTA
13 OUTB
12 OUTC
11 OUTD
10 EN2
9 GND2
INB
INC
IND
NC
GND1
Pin Functions
PIN
I/O
I
DESCRIPTION
NAME
EN2
NO.
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-
impedance state when EN2 is low.
10
2
8
GND1
GND2
—
Ground connection for VCC1
Ground connection for VCC2
9
—
15
3
INA
I
I
Input, channel A
Input, channel B
Input, channel C
Input, channel D
Not connected
INB
4
INC
5
I
IND
6
I
NC
7
—
O
O
O
O
—
—
OUTA
OUTB
OUTC
OUTD
VCC1
VCC2
14
13
12
11
1
Output, channel A
Output, channel B
Output, channel C
Output, channel D
Power supply, VCC1
Power supply, VCC2
16
4
Copyright © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
VCC1
VCC2
,
Supply voltage(2)
Voltage
–0.5
6
V
INx
–0.5
–0.5
–0.5
–15
VCCX + 0.5(3)
VCCX + 0.5(3)
VCCX + 0.5(3)
15
OUTx
EN2
V
IO
Output current
Surge immunity
mA
kV
°C
12.8
Tstg
Storage temperature
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±6000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC1
VCC2
,
Supply voltage
2.25
5.5
V
VCCO(1) = 5 V
VCCO(1) = 3.3 V
VCCO(1) = 2.5 V
VCCO(1) = 5 V
VCCO(1) = 3.3 V
VCCO(1) = 2.5 V
–4
–2
–1
IOH
High-level output current
mA
mA
4
2
IOL
Low-level output current
1
(1)
(1)
VIH
VIL
DR
TJ
High-level input voltage
Low-level input voltage
Signaling rate
0.7 × VCCI
VCCI
V
V
(1)
0
0
0.3 × VCCI
100
150
125
Mbps
°C
Junction temperature(2)
–55
–55
TA
Ambient temperature
25
°C
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) To maintain the recommended operating conditions for TJ, see Thermal Information.
Copyright © 2015–2016, Texas Instruments Incorporated
5
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
6.4 Thermal Information
ISO7840
DW (SOIC)
16 Pins
78.9
DWW (SOIC)
16 Pins
78.9
UNIT
THERMAL METRIC(1)
Junction-to-ambient thermal resistance
RθJA
RθJC(top)
RθJB
ψJT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
41.6
41.1
43.6
49.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
15.5
15.2
ψJB
43.1
48.8
RθJC(bottom) Junction-to-case(bottom) thermal resistance
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Maximum power dissipation by ISO7840x
200
mW
Maximum power dissipation by side-1 of
ISO7840x
PD1
40
mW
mW
Maximum power dissipation by side-2 of
ISO7840x
PD2
160
6
Copyright © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
6.6 Insulation Specifications
SPECIFICATION
UNIT
PARAMETER
TEST CONDITIONS
DW
DWW
GENERAL
CLR
CPG
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance through air
>8
>8
>14.5
>14.5
mm
mm
Shortest pin-to-pin distance across the package
surfaceHigh Voltage Feature Description
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
>21
>600
I
>21
>600
I
μm
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
V
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I–IV
I–III
I–IV
I–IV
Overvoltage category per IEC
60664-1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
Maximum repetitive peak isolation
voltage
VIORM
2121
2828
VPK
AC voltage (sine wave); Time dependent dielectric
breakdown (TDDB) Test, see Figure 1 and Figure 2
1500
2121
2000
2828
VRMS
VDC
VIOWM Maximum isolation working voltage
DC voltage
VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)
Maximum transient isolation
voltage
VIOTM
8000
8000
8000
8000
VPK
VPK
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
VIOSM Maximum surge isolation voltage(3)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and 3394 VPK
(DWW), tm = 10 s
≤5
≤5
≤5
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK
(DWW), tm = 10 s
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 1 s;
≤5
≤5
Vpd(m) = 1.875 × VIORM = 3977 VPK (DW) and 5303 VPK
(DWW), tm = 1 s
Barrier capacitance, input to
output(5)
CIO
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
2
2
pF
VIO = 500 V, TA = 25°C
>1012
>1011
>109
>1012
>1011
>109
Isolation resistance, input to
output(5)
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
2
55/125/21
55/125/21
UL 1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
5700
5700
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
Copyright © 2015–2016, Texas Instruments Incorporated
7
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
6.7 Safety-Related Certifications
Certifications for the DW package are complete. DWW package certifications are complete for UL, VDE and TUV and
planned for CSA and CQC.
VDE
CSA
UL
CQC
TUV
Certified according to DIN
V VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN
EN 60950-1 (VDE 0805
Teil 1):2011-01
Approved under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Certified according to
Certified according to UL
1577 Component
Recognition Program
Certified according to GB
4943.1-2011
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
(DW package) and 1450 VRMS
(DWW package) max working
voltage (pollution degree 2,
material group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS (DW package) and
1450 VRMS (DWW package)
Reinforced insulation
Maximum transient
isolation voltage, 8000 VPK
Maximum repetitive peak
isolation voltage, 2121 VPK
(DW), 2828 VPK (DWW);
Maximum surge isolation
voltage, 8000 VPK
;
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
Single protection, 5700
VRMS
maximum working voltage
working voltage (DW package)
Certificate number:
40040142
Master contract number:
220991
Certificate number:
CQC15001121716
File number: E181974
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RθJA = 78.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
RθJA = 78.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
RθJA = 78.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C
288
Safety input, output, or supply
current
IS
440
576
mA
Safety input, output, or total
power
PS
TS
RθJA = 78.9°C/W, TJ = 150°C, TA = 25°C
1584
150
mW
°C
Maximum safety temperature
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
8
Copyright © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 11
MIN
TYP
VCCO – 0.2
0.2
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
VCCO – 0.4
V
IOL = 4 mA; see Figure 11
0.4
10
V
Input threshold voltage
hysteresis
VI(HYS)
0.1 × VCCI
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI at INx or EN2
VIL = 0 V at INx or EN2
μA
μA
–10
100
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1500 V; see
Figure 14
CMTI
CI
kV/μs
VI = VCC/2 + 0.4 × sin (2πft), f = 1 MHz, VCC
5 V
=
Input capacitance
2
pF
6.10 Supply Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
1.3
0.4
6
2
mA
0.6
EN2 = 0 V, VI = 0 V (ISO7840F), VI =
VCCI(1) (ISO7840)
ICC2
Disable
ICC1
8.5
mA
0.6
EN2 = 0 V, VI = VCCI (ISO7840F), VI = 0
V (ISO7840) EN2 = 0 V
ICC2
0.4
1.3
2.2
5.9
2.5
3.6
2.6
3.8
4.5
5.1
23.8
5.1
23.8
ICC1
2
mA
3.1
VI = 0 V (ISO7840F), VI = VCCI
(ISO7840)
ICC2
DC signal
ICC1
8.6
mA
3.3
VI = VCCI (ISO7840F), VI = 0 V
(ISO7840)
ICC2
Supply current
ICC1
5.3
mA
3.7
1 Mbps
ICC2
ICC1
5.4
mA
5.9
10 Mbps
All channels switching with
square wave clock input;
CL = 15 pF
ICC2
ICC1
5.9
mA
DW package
ICC2
27.4
100 Mbps
ICC1
5.9
mA
DWW package
ICC2
28.5
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –2 mA; see Figure 11
MIN
TYP
VCCO – 0.2
0.2
MAX
UNIT
V
VOH
VOL
High-level output voltage
Low-level output voltage
VCCO – 0.4
IOL = 2 mA; see Figure 11
0.4
10
V
Input threshold voltage
hysteresis
VI(HYS)
0.1 × VCCI
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI at INx or EN2
VIL = 0 V at INx or EN2
μA
μA
–10
100
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V, VCM = 1500 V; see Figure 14
kV/μs
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
1.3
0.4
6
2
0.6
8.5
0.6
2
EN2 = 0 V, VI = 0 V (ISO7840F), VI =
mA
VCCI(1) (ISO7840)
ICC2
Disable
EN2 = 0 V, VI = VCCI(1) (ISO7840F), VI
= 0 V (ISO7840)
ICC1
mA
mA
mA
mA
mA
mA
ICC2
0.4
1.3
2.2
5.9
2.4
3.6
2.5
3.7
3.9
4.5
17.7
(1)
ICC1
VI = 0 V (ISO7840F), VI = VCCI
(ISO7840)
ICC2
3
DC signal
VI = VCCI(1) (ISO7840F), VI = 0 V
(ISO7840)
ICC1
8.6
3.3
5.3
3.6
5.3
5.1
5.8
20.6
Supply current
ICC2
ICC1
1 Mbps
ICC2
All channels switching with
square wave clock input;
CL = 15 pF
ICC1
10 Mbps
100 Mbps
ICC2
ICC1
ICC2
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
10
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –1 mA; see Figure 11
MIN
TYP
MAX
UNIT
V
VOH
VOL
High-level output voltage
Low-level output voltage
VCCO – 0.4 VCCO – 0.2
0.2
IOL = 1 mA; see Figure 11
0.4
V
Input threshold voltage
hysteresis
VI(HYS)
0.1 × VCCI
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI at INx or EN2
VIL = 0 V at INx or EN2
10
μA
μA
–10
100
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V, VCM = 1500 V; see Figure 14
kV/μs
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
1.3
0.4
6
2
0.6
8.5
EN2 = 0 V, VI = 0 V (Devices with suffix
F), VI = VCCI(1) (Devices without suffix F)
mA
ICC2
Disable
EN2 = 0 V, VI = VCCI(1) (Devices with
ICC1
suffix F), VI = 0 V (Devices without suffix
F)
mA
ICC2
0.4
0.6
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.3
2.2
5.9
2.4
3.6
2.5
3.7
3.5
4.4
13.9
2
3
VI = 0 V (Devices with suffix F), VI =
VCCI(1) (Devices without suffix F)
mA
mA
mA
mA
mA
DC signal
VI = VCCI(1) (Devices with suffix F), VI =
0 V (Devices without suffix F)
8.6
3.3
5.3
3.5
5.3
4.7
5.7
16.4
Supply current
1 Mbps
All channels switching
with square wave clock
input;
10 Mbps
100 Mbps
CL = 15 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
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MAX UNIT
6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
6
16
4.1
2.5
4.5
3.9
3.9
ns
ns
ns
ns
ns
ns
See Figure 11
|
0.55
Same-direction channels
Output signal rise time
1.7
1.9
See Figure 11
tf
Output signal fall time
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
12
12
10
2
20
20
20
2.5
2.5
20
9
ns
ns
ns
μs
μs
ns
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output for ISO7840
tPZH
See Figure 12
Enable propagation delay, high impedance-to-high
output for ISO7840F
Enable propagation delay, high impedance-to-low
output for ISO7840
2
tPZL
Enable propagation delay, high impedance-to-low
output for ISO7840F
10
Measured from the time VCC goes below 1.7 V. See
Figure 13
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
μs
216 – 1 PRBS data at 100 Mbps
0.90
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10.8
0.7
MAX
16
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
6
See Figure 11
|
4.2
2.2
4.5
3
ns
Same-direction channels
ns
ns
Output signal rise time
0.8
0.8
ns
See Figure 11
tf
Output signal fall time
3
ns
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
17
17
17
2
32
32
32
2.5
2.5
32
9
ns
ns
ns
μs
μs
ns
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output for ISO7840
tPZH
See Figure 12
Enable propagation delay, high impedance-to-high
output for ISO7840F
Enable propagation delay, high impedance-to-low
output for ISO7840
2
tPZL
Enable propagation delay, high impedance-to-low
output for ISO7840F
17
Measured from the time VCC goes below 1.7 V.
See Figure 13
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
μs
216 – 1 PRBS data at 100 Mbps
0.91
ns
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
12
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6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11.7
0.66
MAX
17.5
4.2
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
7.5
See Figure 11
|
ns
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction Channels
2.2
ns
4.5
ns
Output signal rise time
1
3.5
ns
See Figure 11
tf
Output signal fall time
1.2
3.5
ns
Disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
22
22
18
2
45
45
45
2.5
2.5
45
9
ns
ns
ns
μs
μs
ns
Disable propagation delay, low-to-high impedance
output
Enable propagation delay, high impedance-to-high
output for ISO7840
tPZH
See Figure 12
Enable propagation delay, high impedance-to-high
output for ISO7840F
Enable propagation delay, high impedance-to-low
output for ISO7840
2
tPZL
Enable propagation delay, high impedance-to-low
output for ISO7840F
18
Measured from the time VCC goes below 1.7 V.
See Figure 13
tfs
tie
Default output delay time from input power loss
Time interval error
0.2
μs
216 – 1 PRBS data at 100 Mbps
0.91
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Insulation Characteristics Curves
1.E+11
1.E+11
1.E+10
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
1.E+2
1.E+1
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
1.E+2
1.E+1
87.5%
87.5%
20%
20%
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
400 1400 2400 3400 4400 5400 6400 7400 8400 9400
Stress Voltage (VRMS
)
Stress Voltage (VRMS
)
TA upto 150°C
Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
TA upto 150°C
Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 1. Reinforced Isolation Capacitor Life Time
Projection for Devices in DW Package
Figure 2. Reinforced Isolation Capacitor Life Time
Projection for Devices in DWW Package
700
600
500
400
300
200
100
0
1800
1600
1400
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Power
0
50
100
150
200
0
50
100
150
200
Ambient Temperature (èC)
Ambient Temperature (èC)
D014
D015
Figure 3. Thermal Derating Curve for Limiting Current per
VDE
Figure 4. Thermal Derating Curve for Limiting Power per
VDE
14
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6.19 Typical Characteristics
24
10
8
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
20
16
12
8
ICC2 at 5 V
6
4
2
4
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Data Rate (Mbps)
Data Rate (Mbps)
D001
D002
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 5. Supply Current vs Data Rate (With 15-pF Load)
Figure 6. Supply Current vs Data Rate (With No Load)
6
1
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
1
0
-15
-10
-5
0
0
5
10
15
High-Level Output Current (mA)
Low-Level Output Current (mA)
D003
D0041
TA = 25°C
TA = 25°C
Figure 7. High-Level Output Voltage vs High-level Output
Current
Figure 8. Low-Level Output Voltage vs Low-Level Output
Current
2.25
13
12
11
10
9
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5.0 V
tPHL at 5.0 V
1.75
1.7
8
-50
0
50
Free-Air Temperature (oC)
100
150
-60
-30
0
30
60
90
120
Free-Air Temperature (oC)
D005
D006
Figure 9. Power Supply Undervoltage Threshold vs Free-Air
Temperature
Figure 10. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input
Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristics Test Circuit and Voltage Waveforms
V
CCO
V
CC
R
L
= 1 kꢀ ±1%
V
/ 2
CC
V
/ 2
CC
V
I
IN
OUT
0 V
V
0 V
O
t
t
PZL
PLZ
V
OH
EN
0.5 V
V
V
O
50%
C
L
OL
See Note B
Input
Generator
(See Note A)
V
I
50 ꢀ
V
CC
V
O
IN
OUT
3 V
V / 2
CC
V
/ 2
CC
V
I
0 V
t
PZH
EN
See Note B
R
L
= 1 kꢀ ±1%
V
OH
C
L
50%
Input
Generator
(See Note A)
0.5 V
V
O
V
I
0 V
t
50 ꢀ
PHZ
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Enable/Disable Propagation Delay Time Test Circuit and Waveform
16
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Parameter Measurement Information (continued)
VI
VCC
VCC
2.7 V
VI
0 V
VOH
IN
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
OUT
t
VO
fs
fs high
fs low
50%
VO
CL
See Note A
VOL
Copyright © 2016, Texas Instruments Incorporated
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF ±1%
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
EN
V
OH
or V
OL
C
L
œ
See Note A
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7840 device uses an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. If the EN pin is low
then the output goes to high impedance. The ISO7840 device also incorporates advanced circuit techniques to
maximize the CMTI performance and minimize the radiated emissions because of the high-frequency carrier and
IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 15, shows a functional
block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Oscillator
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 16 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 16. On-Off Keying (OOK) Based Modulation Scheme
18
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ZHCSDU2B –JULY 2015–REVISED APRIL 2016
8.3 Feature Description
Table 1 lists the device features.
Table 1. Device Features
PART NUMBER
CHANNEL DIRECTION
RATED ISOLATION
MAXIMUM DATA RATE
DEFAULT OUTPUT
4 Forward,
0 Reverse
4 Forward,
0 Reverse
(1)
ISO7840
5700 VRMS / 8000 VPK
100 Mbps
100 Mbps
High
(1)
ISO7840F
5700 VRMS / 8000 VPK
Low
(1) See for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7840
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the ISO7840 functional modes.
Table 2. Function Table(1)
OUTPUT
INPUT
OUTPUT
(OUTx)
VCCI
VCCO
ENABLE
(EN2)
COMMENTS
(INx)(2)
H
L
H or open
H or open
H
Normal Operation:
A channel output assumes the logic state of its input.
L
Default
Z
PU
X
PU
PU
Default mode: When INx is open, the corresponding channel output goes to
its default logic state. Default= High for ISO7840 and Low for ISO7840F.
Open
X
H or open
L
A low value of Output Enable causes the outputs to be high-impedance
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. Default= High for IISO7840 and
Low for ISO7840F.
PD
X
PU
PD
X
X
H or open
Default
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
(3)
When VCCO is unpowered, a channel output is undetermined
.
X
Undetermined When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
(2) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Device Without Suffix F)
Input (Device With Suffix F)
V
V
V
V
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
CCI
1.5 MW
985 W
985 W
INx
INx
1.5 MW
Output
Enable
V
CCO
V
V
V
V
CCO
CCO
CCO
CCO
2 MW
1970 W
~20 W
Enx
OUTx
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Device I/O Schematics
20
Copyright © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7840 device is a high-performance, quad-channel digital isolator with a 5.7-kVRMS isolation voltage. The
device comes with enable pins on each side that can be used to put the respective outputs in high impedance for
multi-master driving applications and reduce power consumption. The ISO7840 device uses single-ended
CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and
VCC2. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
Isolation
5 VISO 5 VISO
Barrier
5 VISO
3.3 V
3.3 V
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
16
10
14
13
12
11
1
22
AVDD DVDD
AIN1+
1
VCC2
VCC1
EN1
INA
0.1 ꢀF
0.1 ꢀF
2
7
EN2
11
DVcc
8
3
11
12
14
13
5
P3.0
P3.1
A0
OUTA
OUTB
OUTC
IND
XOUT
RTD
12
7
4
ISO7841
AIN1œ
A1
INB
IN
C
MSP430F2132
CLK
27
5
6
SCLK
XIN
P3.7
P3.6
P3.5
18
17
28
6
18
17
16
Bridge
AIN2+
DOUT
OUTD
SOMI
9, 15
2, 8
ADS1234
AIN2œ
5 VISO
GND2
GND1
5 VISO
3.3 V
15
20
19
P3.4
REF+
DVss
4
16
10
1
0.1 ꢀF
0.1 ꢀF
13
14
VCC2
VCC1
NC
AIN3+
REFœ
0.1 ꢀF
7
Thermo
couple
EN
AIN3œ
23
24
25
26
14
3
GAIN0
GAIN1
SPEED
PWDN
OUTA
OUTB
OUTC
OUTD
GND2
INA
13
4
ISO7840
INB
IN
C
16
15
AIN4+
12
5
Current
shunt
11
6
AIN4œ
IND
9, 15
2, 8
AGND DGND
GND1
21
2
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Isolated Data Acquisition System for Process Control
Copyright © 2015–2016, Texas Instruments Incorporated
21
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
2.25 to 5.5 V
0.1 µF
Supply voltage
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7840 device only requires two external bypass capacitors to operate.
VCC1
VCC2
0.1 µF
0.1 µF
1
16
V
CC1
V
CC2
GND1
GND2
GND1
INA
2
3
GND2
OUTA
OUTB
OUTC
OUTD
INA
14
13
OUTB
INB
OUTC
INB
4
INC
INC
IND
12
11
OUTC
OUTD
5
6
7
8
IND
EN
NC
10 EN2
GND1
9
GND2
GND1
GND2
ISO7840
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Typical ISO7840 Circuit Hook-Up
9.2.3 Application Curve
The typical eye diagram of the ISO7840 device indicates low jitter and wide open eye at the maximum data rate
of 100 Mbps.
Figure 20. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C
22
Copyright © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas InstrumentsSN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 Transformer Driver for Isolated Power Supplies.
Copyright © 2015–2016, Texas Instruments Incorporated
23
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 21). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
Figure 21. Layout Example Schematic
24
版权 © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
相关文档如下：
•
•
•
•
•
《ADS1234 用于桥式传感器的 24 位模数转换器》
数字隔离器设计指南
隔离相关术语
《MSP430G2x32、MSP430G2x02 混合信号微控制器》
《SN6501 用于隔离电源的变压器驱动器》
12.2 相关链接
以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
ISO7840
ISO7840F
12.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2015–2016, Texas Instruments Incorporated
25
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
版权 © 2015–2016, Texas Instruments Incorporated
27
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
16X (0.6)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
R0.05 TYP
14X (1.27)
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
28
版权 © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
R0.05 TYP
14X (1.27)
8
9
8
9
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
版权 © 2015–2016, Texas Instruments Incorporated
29
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
PACKAGE OUTLINE
DWW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC SMALL OUTLINE
C
17.4
17.1
SEATING PLANE
A
0.1 C
PIN 1 ID AREA
14X 1.27
16
1
10.4
10.2
NOTE 3
2X
8.89
8
9
0.51
16X
(2.286)
0.31
14.1
13.9
NOTE 4
B
0.25
A B
C
2.65 MAX
0.28
0.22
TYP
SEE DETAIL A
(1.625)
0.25
GAGE PLANE
0.3
0.1
1.1
0.6
0 -8
DETAIL A
TYPICAL
4221501/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0,15 mm per side.
4. This dimension does not include interlead flash.
www.ti.com
30
版权 © 2015–2016, Texas Instruments Incorporated
ISO7840, ISO7840F
www.ti.com.cn
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
EXAMPLE BOARD LAYOUT
DWW0016A
SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
16X (1.875)
(14.5)
16X (2)
(14.25)
16X (0.6)
16X (0.6)
1
1
16
16
SYMM
SYMM
14X
(1.27)
14X
(1.27)
8
9
8
9
SYMM
(16.25)
SYMM
(16.375)
LAND PATTERN EXAMPLE
PCB CLEARANCE & CREEPAGE OPTIMIZED
SCALE:3X
LAND PATTERN EXAMPLE
STANDARD
SCALE:3X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221501/A 11/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
版权 © 2015–2016, Texas Instruments Incorporated
31
ISO7840, ISO7840F
ZHCSDU2B –JULY 2015–REVISED APRIL 2016
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DWW0016A
SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
8
9
(16.25)
SOLDER PASTE EXAMPLE
STANDARD
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
16X (1.875)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
8
9
(16.375)
SOLDER PASTE EXAMPLE
PCB CLEARANCE & CREEPAGE OPTIMIZED
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221501/A 11/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
32
版权 © 2015–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7840DW
ISO7840DWR
ISO7840DWW
ISO7840DWWR
ISO7840FDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
16
16
16
16
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
ISO7840
2000 RoHS & Green
45 RoHS & Green
1000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
45 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO7840
ISO7840
ISO7840
ISO7840F
ISO7840F
ISO7840F
ISO7840F
DWW
DWW
DW
ISO7840FDWR
ISO7840FDWW
ISO7840FDWWR
DW
DWW
DWW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7840DWR
ISO7840DWWR
ISO7840FDWR
ISO7840FDWWR
SOIC
SOIC
SOIC
SOIC
DW
DWW
DW
16
16
16
16
2000
1000
2000
1000
330.0
330.0
330.0
330.0
16.4
24.4
16.4
24.4
10.75 10.7
18.0 10.0
10.75 10.7
18.0 10.0
2.7
3.0
2.7
3.0
12.0
20.0
12.0
20.0
16.0
24.0
16.0
24.0
Q1
Q1
Q1
Q1
DWW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7840DWR
ISO7840DWWR
ISO7840FDWR
ISO7840FDWWR
SOIC
SOIC
SOIC
SOIC
DW
DWW
DW
16
16
16
16
2000
1000
2000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
DWW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7840DW
ISO7840DWW
ISO7840FDW
ISO7840FDWW
DW
DWW
DW
SOIC
SOIC
SOIC
SOIC
16
16
16
16
40
45
40
45
506.98
507
12.7
20
4826
5000
4826
5000
6.6
9
506.98
507
12.7
20
6.6
9
DWW
Pack Materials-Page 3
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