ISOW7841AQDWERQ1 [TI]
具有集成电源的汽车类、四通道、3/1、增强型数字隔离器 | DWE | 16 | -40 to 125;
| 型号： | ISOW7841AQDWERQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电源的汽车类、四通道、3/1、增强型数字隔离器 | DWE | 16 | -40 to 125 |
| 文件： | 总41页 (文件大小：2137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISOW7841A-Q1
ZHCSKT4B –FEBRUARY 2020 –REVISED DECEMBER 2020
ISOW7841A-Q1 具有集成式高效低辐射直流/直流转换器的汽车类高性能
5000VRMS 四通道增强型数字隔离器
1 特性
2 应用
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
• 电池管理系统(BMS)
• 车载充电器(OBC)
• 牵引逆变器
– 器件温度等级1：–40°C 至125°C 环境工作温
度
• 直流/直流转换器
• 100Mbps 数据速率
• 提供功能安全
3 说明
ISOW7841A-Q1 是具有集成式高效电源转换器且符合
汽车标准的高性能四通道增强型数字隔离器。低排放集
成式直流/直流转换器高效运行，提供最高可达650mW
的隔离式电源，可按各种输入和输出电压进行配置。因
此，空间受限的隔离设计凭借该器件无需单独使用隔离
式电源。
– 可提供用于功能安全系统设计的文档
• 稳健可靠的隔离栅：
– 在1 kVRMS 工作电压下预计寿命超过100 年
– 隔离等级高达5000 VRMS
– 浪涌抗扰度高达10 kVPK
– ±100 kV/µs 最低CMTI
• 集成式高效直流/直流转换器与片上变压器
• 3V 至5.5V 宽电源电压范围
• 5V 或3.3V 稳压输出
器件信息1
封装
封装尺寸（标称值）
器件型号
ISOW7841A-Q1
SOIC (16)
10.30mm × 7.50mm
• 高达0.65W 的输出功率
• 5V 至5V；5V 至3.3V：可用负载电流≥130 mA
• 3.3V 至3.3V：可用负载电流≥75mA；3.3V 至
5V：可用负载电流≥40 mA
1. 如需了解所有可用封装，请参阅数据表末尾的可订
购产品附录。
Isolation Transformer
• 软启动可限制浪涌电流
• 过载和短路保护
• 热关断
DC-DC
Primary
DC-DC
Secondary
VCC
VISO
• 默认输出：高电平和低电平选项
• 低传播延迟：13 ns（典型值，5V 电源）
• 优异的电磁兼容性(EMC)
VSI
VSO
Isolation Capacitors
INx
OUTx
– 系统级ESD、EFT 和浪涌抗扰性
– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放
电保护
GNDI
GNDO
1. VCC 是以GND1 为基准的主电源电压。VISO 是以
GND2 为基准的隔离式电源电压。
2. VSI 和VSO 可以是VCC 或VISO，具体取决于通道
方向。
– 低干扰(EMI)
• 16 引脚宽体SOIC 封装
• 安全相关认证：
– 符合DIN V VDE V 0884-11:2017-01 标准的
7071VPK 增强型隔离
3. VSI 是以GNDI 为基准的输入侧电源电压，而VSO
是以GNDO 为基准的输出侧电源电压。
– 符合UL 1577 标准且长达1 分钟的5000VRMS
隔离
简化原理图
– 符合IEC 60950-1、IEC 62368-1 和IEC
60601-1 终端设备标准的CSA 认证
– 符合GB4943.1-2011 标准的CQC 认证
– 符合EN 60950-1 和EN 61010-1 标准的TUV
认证
– 所有认证已列入计划
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFG1
ISOW7841A-Q1
ZHCSKT4B –FEBRUARY 2020 –REVISED DECEMBER 2020
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description Continued ...................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Power Ratings.............................................................6
7.6 Insulation Specifications............................................. 6
7.7 Safety-Related Certifications...................................... 7
7.8 Safety Limiting Values.................................................7
7.9 Electrical Characteristics—5-V Input, 5-V Output.......8
7.10 Supply Current Characteristics—5-V Input, 5-V
Output............................................................................9
7.11 Electrical Characteristics—3.3-V Input, 5-V
Output............................................................................9
7.12 Supply Current Characteristics—3.3-V Input, 5-
V Output...................................................................... 10
7.13 Electrical Characteristics—5-V Input, 3.3-V
Output..........................................................................10
7.14 Supply Current Characteristics—5-V Input, 3.3-
V Output...................................................................... 11
7.15 Electrical Characteristics—3.3-V Input, 3.3-V
7.17 Switching Characteristics—5-V Input, 5-V Output.. 12
7.18 Switching Characteristics—3.3-V Input, 5-V
Output..........................................................................13
7.19 Switching Characteristics—5-V Input, 3.3-V
Output..........................................................................13
7.20 Switching Characteristics—3.3-V Input, 3.3-V
Output..........................................................................13
7.21 Insulation Characteristics Curves........................... 14
7.22 Typical Characteristics............................................14
8 Parameter Measurement Information..........................19
9 Detailed Description......................................................20
9.1 Overview...................................................................20
9.2 Functional Block Diagram.........................................20
9.3 Feature Description...................................................21
9.4 Device Functional Modes..........................................22
10 Application and Implementation................................24
10.1 Application Information........................................... 24
10.2 Typical Application ................................................. 24
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 Device Support....................................................... 31
12.2 Documentation Support.......................................... 31
12.3 Receiving Notification of Documentation Updates..31
12.4 Community Resources............................................31
12.5 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Output..........................................................................11
7.16 Supply Current Characteristics—3.3-V Input,
Information.................................................................... 32
3.3-V Output................................................................12
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2020) to Revision B (December 2020)
Page
• 向“特性”中添加了功能安全要点......................................................................................................................1
Changes from Revision * (February 2020) to Revision A (June 2020)
Page
• 将器件状态更新为“量产数据”.........................................................................................................................1
• Changed the maximum limit for output signal rise and fall times from 3 to 4 ns in the //Switching
Characteristics—5-V Input, 3.3-V Output// table...............................................................................................13
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English Data Sheet: SLLSFG1
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5 Description Continued
The ISOW7841A-Q1 device provides high electromagnetic immunity and low emissions while isolating CMOS or
LVCMOS digital I/Os. The signal-isolation channel has a logic input and output buffer separated by a double
capacitive silicon dioxide (SiO2) insulation barrier, whereas, power isolation uses on-chip transformers separated
by thin film polymer as insulating material. If the input signal is lost, the default output is high for the
ISOW7841A-Q1 without the F suffix and low for the device with the F suffix.
These devices help prevent noise currents on data buses, such as CAN, or other circuits from entering the local
ground and interfering with or damaging sensitive circuitry. Through innovative chip design and layout
techniques, electromagnetic compatibility of the device has been significantly enhanced to ease system-level
ESD, EFT, surge and emissions compliance. The high-efficiency of the power converter allows operation at a
higher ambient temperature. The device is available in a 16-pin SOIC wide-body (SOIC-WB) DWE package.
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6 Pin Configuration and Functions
VCC
1
16 VISO
GND1
INA
2
3
15 GND2
14 OUTA
INB
INC
4
5
13 OUTB
12 OUTC
OUTD
NC
6
7
11
10 SEL
IND
GND1
8
9 GND2
ISOW7841A-Q1 DWE Package. 16-Pin SOIC-WB. Top View.
表6-1. Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
GND1
ISOW7841A-Q1
2, 8
9, 15
3
Ground connection for VCC
Ground connection for VISO
Input channel A
—
GND2
INA
—
I
I
I
I
INB
4
Input channel B
INC
5
Input channel C
IND
11
7
Input channel D
NC
Not connected
—
O
O
O
O
OUTA
OUTB
OUTC
OUTD
14
13
12
6
Output channel A
Output channel B
Output channel C
Output channel D
VISO selection pin. VISO = 5 V when SEL shorted to VISO. VISO = 3.3 V,
when SEL shorted to GND2 or when left floating. For more information see
节9.4.
SEL
10
I
VCC
1
Supply voltage
—
—
VISO
16
Isolated supply voltage determined by SEL pin
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7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2)
MIN
–0.5
–0.5
MAX
UNIT
V
VCC
Supply voltage
6
6
VISO
Isolated supply voltage
V
VCC + 0.5,
VIO
Voltage at INx, OUTx, SEL pins
V
VISO + 0.5(3)
–0.5
–15
IO
Maximum output current through data channels
Junction temperature
15
150
150
mA
°C
TJ
Tstg
Storage temperature
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2) and are peak voltage
values.
(3) This value depends on whether the pin is located on the VCC or VISO side. The maximum voltage at the I/O pins should not exceed 6 V.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
Contact discharge per IEC 61000-4-2(2)
Isolation barrier withstand test
V(ESD)
±1000
±8000
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
7.3 Recommended Operating Conditions
See 1
MIN
3
NOM
MAX
UNIT
VCC
IOH
Supply voltage
5.5
V
VSO = 5 V
VSO = 3.3 V
VSO = 5 V
VSO = 3.3 V
–4
–2
High level output current 2
mA
mA
4
2
IOL
Low level output current 2
VIH
VIL
DR
TA
High-level input voltage
Low-level input voltage
Data rate
0.7 × VSI
0
VSI
V
V
0.3 × VSI
100
Mbps
°C
Ambient temperature
125
–40
1. VSI is the input side supply, VSO is the output side supply
2. This current is for data output channel.
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7.4 Thermal Information
ISOW7841A-Q1
DWE (SOIC)
16 PINS
56.8
THERMAL METRIC1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
15.6
28.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.4
ΨJT
28.5
ΨJB
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.02
0.51
0.51
UNIT
W
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
VCC = 5.5 V, IISO = 110 mA, TJ = 150°C,
TA ≤80°C, CL = 15 pF, input a 50-MHz
50% duty-cycle square wave
PD1
PD2
W
W
7.6 Insulation Specifications
PARAMETER
GENERAL
TEST CONDITIONS
VALUE
UNIT
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
>8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
External creepage(1)
Minimum internal gap (internal clearance –capacitive
signal isolation)
> 21
DTI
CTI
Distance through the insulation
µm
V
Minimum internal gap (internal clearance –
transformer power isolation)
>120
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 600
I
I-IV
I-IV
I-III
Rated mains voltage ≤300 VRMS
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category per IEC 60664-1
DIN V VDE 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM
AC voltage (bipolar)
1414
VPK
voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test ; See 图10-5
1000
1414
7071
VRMS
VDC
VPK
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM; t = 60 s (qualification);
VTEST = 1.2 × VIOTM; t = 1 s (100% production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK(qualification)
6250
VPK
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PARAMETER
TEST CONDITIONS
VALUE
UNIT
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and
preconditioning (type test),
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance(5)
~3.5
> 1012
> 1011
> 109
pF
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V, TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100%
production)
VISO(UL) Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Plan to certify according to Plan to certify according to IEC Plan to certify under
Plan to certify according to
EN 61010-1:2010 and EN
60950- 1:2006/A2:2013
Plan to certify according
to GB 4943.1-2011
DIN V VDE V
60950-1, IEC 62368-1, and IEC UL 1577 Component
0884-11:2017-01
60601-1
Recognition Program
Reinforced insulation per CSA
60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2, CSA
62368-1-14 and IEC 62368-1
2nd Ed., 800 VRMS maximum
working voltage (pollution
Reinforced insulation;
Maximum transient
isolation voltage, 7071
5000 VRMS Reinforced
insulation per EN 61010-
1:2010 up to working
Reinforced Insulation,
Altitude ≤5000 m,
Tropical Climate, 700
VRMS maximum working
voltage;
VPK
;
degree 2, material group I);
voltage of 600 VRMS;
Single protection, 5000
VRMS
Maximum repetitive peak 2 MOPP (Means of Patient
5000 VRMS Reinforced
insulation per EN 60950-
1:2006/A2:2013 up to
working voltage of 800
VRMS
isolation voltage, 1414
VPK
Protection) per CSA 60601-1:14
and IEC 60601-1 Ed. 3+A1, 250
Maximum surge isolation VRMS maximum working voltage;
;
voltage, 6250 VPK
Temperature rating is 90°C for
reinforced insulation and 125°C
for basic insulation; see
certificate for details.
Certification planned
Certification planned
Certification planned
Certification planned
Certification planned
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output
circuitry.
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 56.8°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C, see Thermal Derating Curve
for Safety Limiting Current per VDE
400
611
IS
Safety input, output, or supply current(1)
mA
R
θJA = 56.8°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C, see Thermal Derating Curve
for Safety Limiting Current per VDE
R
θJA = 56.8°C/W, TJ = 150°C, TA = 25°C,
PS
TS
Safety input, output, or total power(1)
Maximum safety temperature(1)
see Thermal Derating Curve for Safety
Limiting Power per VDE
2200
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use the following equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
7.9 Electrical Characteristics—5-V Input, 5-V Output
VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
External IISO = 0 to 50 mA
MIN
4.75
4.5
TYP
5.07
5.07
2
MAX
5.43
5.43
UNIT
V
VISO
Isolated supply voltage
External IISO = 0 to 130 mA
IISO = 50 mA, VCC = 4.5 V to 5.5 V
IISO = 0 to 130 mA
VISO(LINE)
VISO(LOAD)
DC line regulation
DC load regulation
mV/V
1%
IISO = 130 mA, CLOAD = 0.1 µF || 10 µF;
VI = VSI (ISOW7841A-Q1); VI =0 V
(ISOW7841A-Q1 with F suffix)
Efficiency at maximum load
current
EFF
53%
Positive-going UVLO threshold
on VCC, VISO
VCC+(UVLO)
VCC–(UVLO)
VHYS (UVLO)
2.7
0.7
V
V
V
Negative-going UVLO threshold
on VCC, VISO
2.1
UVLO threshold hysteresis on
VCC, VISO
0.2
VITH
VITL
Input pin rising threshold
Input pin falling threshold
VSI
VSI
0.3
0.1
Input pin threshold hysteresis
(INx)
VI(HYS)
VSI
IIL
Low level input current
High level input current
VIL = 0 at INx or SEL
µA
µA
–10
IIH
VIH = VSI>(1) at INx or SEL
10
(1)
VSO
–
0.4
VSO –
VOH
VOL
High level output voltage
Low level output voltage
V
V
IO = –4 mA, see 图8-1
0.2
0.2
0.4
IO = 4 mA, see 图8-1
Common mode transient
immunity
CMTI
100
kV/us
VI = VSI or 0 V, VCM = 1000 V; see 图8-2
DC current from supply under
short circuit on VISO
ICC_SC
VISO shorted to GND2
137
100
mA
mV
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,
(pk-pk) IISO = 130 mA
VISO(RIP)
(1) VSI = input side supply; VSO = output side supply
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7.10 Supply Current Characteristics—5-V Input, 5-V Output
VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
No external ILOAD; VI = 0 V (ISOW7841A-Q1);
(1)
23
(
VI = VSI ) (ISOW7841A-Q1 with F suffix)
No external ILOAD; VI = VSI (ISOW7841A-Q1);
VI = 0V (ISOW7841A-Q1 with F suffix)
17
20
24
54
Current drawn from
supply
All channels switching with square wave clock input of 1 Mbps;
CL = 15 pF, No external ILOAD
ICC
mA
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF, No external ILOAD
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF, No external ILOAD
VI = 0 V (ISOW7841A-Q1); VI = VSI (ISOW7841A-Q1 with F suffix)
VI = VSI (ISOW7841A-Q1); VI = 0V (ISOW7841A-Q1 with F suffix)
128
130
All channels switching with square wave clock input of 1 Mbps;
CL = 15 pF
128
127
112
(2) Current available to
(
)
IISO(OUT)
mA
isolated supply
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF
(1) VSI = input side supply; VSO = output side supply
(2) Current available to load should be derated by 2 mA/°C for TA > 80°C.
7.11 Electrical Characteristics—3.3-V Input, 5-V Output
VCC = 3.3 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
External IISO = 0 to 40 mA
MIN
TYP
5.07
2
MAX
UNIT
V
VISO
Isolated supply voltage
DC line regulation
DC load regulation
4.5
5.43
VISO(LINE)
VISO(LOAD)
IISO = 20 mA, VCC = 4.5 V to 5.5 V
IISO = 0 to 40 mA
mV/V
1%
IISO = 40 mA, CLOAD = 0.1 µF || 10 µF;
VI = VSI (ISOW7841A-Q1); VI =0 V
(ISOW7841A-Q1 with F suffix)
Efficiency at maximum load
current
EFF
42%
Positive-going UVLO threshold
on VCC, VISO
VCC+(UVLO)
VCC–(UVLO)
VHYS (UVLO)
2.7
0.7
V
V
V
Negative-going UVLO threshold
on VCC, VISO
2.1
UVLO threshold hysteresis on
VCC, VISO
0.2
VITH
VITL
Input pin rising threshold
Input pin falling threshold
VSI
VSI
0.3
0.1
Input pin threshold hysteresis
(INx)
VI(HYS)
VSI
IIL
Low level input current
High level input current
VIL = 0 at INx or SEL
µA
µA
–10
IIH
VIH = VSI (1) at INx or SEL
10
(1)
VSO
–
0.4
VSO –
VOH
VOL
High level output voltage
Low level output voltage
V
V
IO = –4 mA, see 图8-1
0.2
0.2
0.4
IO = 4 mA, see 图8-1
Common mode transient
immunity
CMTI
100
kV/us
VI = VSI or 0 V, VCM = 1000 V; see 图8-2
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC current from supply under
ICC_SC
VISO shorted to GND2
137
mA
short circuit on VISO
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,
(pk-pk) IISO = 40 mA
VISO(RIP)
90
mV
(1) VSI = input side supply; VSO = output side supply
7.12 Supply Current Characteristics—3.3-V Input, 5-V Output
VCC = 3.3 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
No external ILOAD; VI = 0 V (ISOW7841A-Q1);
(1)
31
(
VI = VSI ) (ISOW7841A-Q1 with F suffix)
No external ILOAD; VI = VSI (ISOW7841A-Q1);
VI = 0V (ISOW7841A-Q1 with F suffix)
24
28
33
80
Current drawn from
supply
All channels switching with square wave clock input of 1 Mbps;
CL = 15 pF, No external ILOAD
ICC
mA
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF, No external ILOAD
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF, No external ILOAD
VI = 0 V (ISOW7841A-Q1); VI = VSI (ISOW7841A-Q1 with F suffix)
VI = VSI (ISOW7841A-Q1); VI = 0V (ISOW7841A-Q1 with F suffix)
38
40
All channels switching with square wave clock input of 1 Mbps;
CL = 15 pF
38
37
22
(2) Current available to
(
)
IISO(OUT)
mA
isolated supply
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF
(1) VSI = input side supply; VSO = output side supply
(2) Current available to load should be derated by 2 mA/°C for TA > 80°C.
7.13 Electrical Characteristics—5-V Input, 3.3-V Output
VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
External IISO = 0 to 50 mA
MIN
3.13
3
TYP
3.34
3.34
2
MAX
3.56
3.56
UNIT
V
VISO
Isolated supply voltage
External IISO = 0 to 130 mA
IISO = 50 mA, VCC = 4.5 V to 5.5 V
IISO = 10 to 130 mA
VISO(LINE)
VISO(LOAD)
DC line regulation
DC load regulation
mV/V
1%
IISO = 130 mA, CLOAD = 0.1 µF || 10 µF;
VI = VSI (ISOW7841A-Q1); VI = 0 V
(ISOW7841A-Q1 with F suffix)
Efficiency at maximum load
current
EFF
48%
Positive-going UVLO threshold
on VCC, VISO
VCC+(UVLO)
VCC–(UVLO)
VHYS (UVLO)
2.7
0.7
V
V
V
Negative-going UVLO threshold
on VCC, VISO
2.1
UVLO threshold hysteresis on
VCC, VISO
0.2
VITH
VITL
Input pin rising threshold
Input pin falling threshold
VSI
VSI
0.3
0.1
Input pin threshold hysteresis
(INx)
VI(HYS)
VSI
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PARAMETER
TEST CONDITIONS
VIL = 0 at INx or SEL
MIN
TYP
MAX
UNIT
µA
IIL
Low level input current
High level input current
–10
IIH
VIH = VSI (1) at INx or SEL
10
µA
(1)
VSO
–
0.3
VSO –
VOH
VOL
High level output voltage
Low level output voltage
V
V
IO = –2 mA, see 图8-1
0.1
0.1
0.3
IO = 2 mA, see 图8-1
Common mode transient
immunity
CMTI
100
kV/us
VI = VSI or 0 V, VCM = 1000 V; see 图8-2
DC current from supply under
short circuit on VISO
ICC_SC
VISO shorted to GND2
137
100
mA
mV
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,
(pk-pk) IISO = 130 mA
VISO(RIP)
(1) VSI = input side supply; VSO = output side supply
7.14 Supply Current Characteristics—5-V Input, 3.3-V Output
VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
No external ILOAD; VI = 0 V (ISOW7841A-Q1);
(1)
20
(
VI = VSI ) (ISOW7841A-Q1 with F suffix)
No external ILOAD; VI = VSI (ISOW7841A-Q1);
VI = 0 V (ISOW7841A-Q1 with F suffix)
14
17
20
40
Current drawn from
supply
All channels switching with square wave clock input of 1 Mbps;
CL = 15 pF, No external ILOAD
ICC
mA
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF, No external ILOAD
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF, No external ILOAD
VI = 0 V (ISOW7841A-Q1); VI = VSI (ISOW7841A-Q1 with F suffix)
VI = VSI (ISOW7841A-Q1); VI = 0 V (ISOW7841A-Q1 with F suffix)
128
130
All channels switching with square wave clock input of 1 Mbps;
CL= 15 pF
129
128
118
(2) Current available to
(
)
IISO(OUT)
mA
isolated supply
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF
(1) VSI = input side supply; VSO = output side supply
(2) Current available to load should be derated by 2 mA/°C for TA > 105°C.
7.15 Electrical Characteristics—3.3-V Input, 3.3-V Output
VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
External IISO = 0 to 30 mA
MIN
3.13
3
TYP
3.34
3.34
2
MAX
3.58
3.58
UNIT
V
VISO
Isolated supply voltage
External IISO = 0 to 75 mA
IISO = 30 mA, VCC = 3 V to 3.6 V
IISO = 0 to 75 mA
VISO(LINE)
DC line regulation
mV/V
VISO(LOAD) DC load regulation
1%
IISO = 75 mA, CLOAD = 0.1 µF || 10 µF;
VI = VSI (ISOW7841A-Q1); VI = 0 V
(ISOW7841A-Q1 with F suffix)
Efficiency at maximum load
current
EFF
47%
Positive-going UVLO threshold
on VCC, VISO
VCC+(UVLO)
2.7
V
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Negative-going UVLO threshold
on VCC, VISO
VCC–(UVLO)
2.1
V
UVLO threshold hysteresis on
VCC, VISO
VHYS (UVLO)
0.2
V
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7
VSI
VSI
0.3
0.1
Input pin threshold hysteresis
(INx)
VI(HYS)
VSI
IIL
Low level input current
High level input current
VIL = 0 at INx or SEL
µA
µA
–10
IIH
VIH = VSI (1) at INx or SEL
10
(1)
VSO
VSO –
VOH
VOL
High level output voltage
Low level output voltage
V
V
IO = –2 mA, see 图8-1
–0.3
0.1
0.1
0.3
IO = 2 mA, see 图8-1
Common mode transient
immunity
CMTI
100
kV/us
VI = VSI or 0 V, VCM = 1000 V; see 图8-2
DC current from supply under
short circuit on VISO
ICC_SC
VISO shorted to GND2
143
90
mA
mV
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF, IISO
(pk-pk) = 75 mA
VISO(RIP)
(1) VSI= input side supply; VSO = output side supply
7.16 Supply Current Characteristics—3.3-V Input, 3.3-V Output
VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
No external ILOAD; VI = 0 V (ISOW7841A-Q1);
(1)
26
(
VI = VSI ) (ISOW7841A-Q1 with F suffix)
No external ILOAD; VI = VSI (ISOW7841A-Q1);
VI = 0 V (ISOW7841A-Q1 with F suffix)
20
23
26
53
Current drawn from
supply
All channels switching with square wave clock input of 1 Mbps;
CL = 15 pF, No external ILOAD
ICC
mA
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF, No external ILOAD
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF, No external ILOAD
VI = 0 V (ISOW7841A-Q1);
VI = VSI (ISOW7841A-Q1 with F suffix)
73
75
74
73
61
VI = VSI(ISOW7841A-Q1);
VI = 0V (ISOW7841A-Q1 with F suffix)
(2) Current available to
All channels switching with square wave clock input of 1 Mbps;
CL = 15 pF
(
)
IISO(OUT)
mA
isolated supply
All channels switching with square wave clock input of 10 Mbps;
CL = 15 pF
All channels switching with square wave clock input of 100 Mbps;
CL = 15 pF
(1) VSI = input side supply; VSO = output side supply
(2) Current available to load should be derated by 2 mA/°C for TA > 115°C.
7.17 Switching Characteristics—5-V Input, 5-V Output
VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
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PARAMETER
TEST CONDITIONS
See 图8-1
MIN
TYP
13
MAX
17.6
4.7
2.5
4.5
4
UNIT
ns
tPLH, tPHL Propagation delay time
PWD
Pulse width distortion1 |tPHL –tPLH
|
0.6
ns
tSK(o)
tSK(p-p)
tr, tf
Channel-channel output skew time2
Part-part skew time3
Same-direction channels
ns
ns
Output signal rise and fall times
2
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.18 Switching Characteristics—3.3-V Input, 5-V Output
VCC = 3.3 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
See 图8-1
MIN
TYP
13.5
0.6
MAX
19.6
4.7
2.5
4.5
4
UNIT
ns
tPLH, tPHL Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
|
PWD
tSK(o)
tSK(p-p)
tr, tf
ns
Channel-channel output skew time(2)
Part-part skew time(3)
Same-direction channels
ns
ns
Output signal rise and fall times
2
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.19 Switching Characteristics—5-V Input, 3.3-V Output
VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
tPLH, tPHL Propagation delay time
PWD
TEST CONDITIONS
See 图8-1
MIN
TYP
14
MAX
19.7
4.4
2
UNIT
ns
Pulse width distortion1 |tPHL –tPLH
|
0.6
ns
tSK(o)
tSK(p-p)
tr, tf
Channel-channel output skew time2
Part-part skew time3
Same-direction channels
ns
4.5
4
ns
Output signal rise and fall times
1
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.20 Switching Characteristics—3.3-V Input, 3.3-V Output
VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
tPLH, tPHL Propagation delay time
PWD
TEST CONDITIONS
See 图8-1
MIN
TYP
14.5
0.6
MAX
20.2
4.4
UNIT
ns
Pulse width distortion1 |tPHL –tPLH
|
ns
tSK(o)
Channel-channel output skew time2
Part-part skew time3
Same-direction channels
2.2
ns
tSK(p-p)
4.5
ns
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr, tf
Output signal rise and fall times
1
3
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.21 Insulation Characteristics Curves
700
600
500
400
300
200
100
0
2500
2000
1500
1000
500
VCC = 3.6 V
VCC = 5.5 V
0
0
50
100
Ambient Temperature (°C)
150
200
0
20
40
60
80
100
Ambient Temperature (°C)
120
140
160
图7-2. Thermal Derating Curve for Safety Limiting
图7-1. Thermal Derating Curve for Safety Limiting
Power per VDE
Current per VDE
7.22 Typical Characteristics
5.2
5.15
5.1
5.05
5
0
20
40
60
80
Load Current (mA)
100
120
140
VISO = 3.3 V
TA = 25°C
VISO = 5 V
TA = 25°C
图7-3. Isolated Supply Voltage (VISO) vs Load
Current (IISO
图7-4. Isolated Supply Voltage (VISO) vs Load
Current (IISO
)
)
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300
275
250
225
200
175
150
125
100
75
100
90
80
70
60
50
40
30
20
10
0
VCC = 3.3 V, VISO = 3.3 V
VCC = 5 V, VISO = 3.3 V
VCC = 5 V, VISO = 5 V
VCC = 3.3 V, VISO = 5 V
VCC = 3.3 V, VISO = 3.3 V
VCC = 5 V, VISO = 3.3 V
VCC = 5 V, VISO = 5 V
VCC = 3.3 V, VISO = 5 V
50
25
0
0
20
40
60
Load Current (mA)
80
100
120
140
160
0
20
40
60 80
Load Current (mA)
100
120
140
TA = 25°C
TA = 25°C
图7-5. ISOW7841 Supply Current (ICC) vs Load
图7-6. ISOW7841 Efficiency vs Load Current (IISO)
Current (IISO
)
3.4
640
560
480
400
320
240
160
80
VCC = 3.3 V, VISO = 3.3 V
VCC = 5 V, VISO = 3.3 V
VCC = 5 V, VISO = 5 V
VCC = 3.3 V, VISO = 5 V
3.35
3.3
3.25
3.2
-40
0
-20
0
20
40
60
Free-Air Temperature (°C)
80
100
120
0
20
40
60 80
Load Current (mA)
100
120
140
No IISO load
VCC = 5 V
VISO = 3.3 V
TA = 25°C
图7-8. 3.3-V Isolated Supply Voltage (VISO) vs Free-
图7-7. ISOW7841 Power Dissipation vs Load
Air Temperature
Current (IISO
)
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130
125
120
115
110
105
100
95
800
700
600
500
400
300
200
100
5.14
5.09
5.04
4.99
4.94
Short-circuit Supply Current
Short-circuit Power
90
0
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
Input Supply Voltage (V)
5
5.2 5.4
-40
-20
0
20
40
60
80
100
120
Free-Air Temperature (èC)
VISO shorted to GND2
TA = 25°C
No IISO load
VCC = 5 V
VISO = 5 V
图7-10. Short-Circuit Supply Current (ICC) and
Power (P) vs Supply Voltage (VCC
)
图7-9. 5-V Isolated Supply Voltage (VISO) vs Free-
Air Temperature
120
80
70
60
50
40
30
20
10
0
ICC (mA) at VCC = 5 V, VISO = 5 V
110
ICC (mA) at VCC = 5 V, VISO = 3.3 V
100
ICC (mA) at VCC = 5 V, VISO = 5 V
ICC (mA) at VCC = 5 V, VISO = 3.3 V
ICC (mA) at VCC = 3.3 V, VISO = 3.3 V
ICC (mA) at VCC = 3.3 V, VISO = 5 V
ICC (mA) at VCC = 3.3 V, VISO = 3.3 V
ICC (mA) at VCC = 3.3 V, VISO = 5 V
90
80
70
60
50
40
30
20
10
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
CL = 15 pF
TA = 25°C
No IISO load
CL = no load
TA = 25°C
No IISO load
图7-11. ISOW7841A-Q1 Supply Current vs Data
图7-12. ISOW7841A-Q1 Supply Current vs Data
Rate
Rate
2.6
2.5
2.4
2.3
2.2
20
18
16
14
12
tPLH(ns) at VCC = 5 V, VISO = 5 V
tPHL(ns) at VCC = 5 V, VISO = 5 V
tPLH(ns) at VCC = 5 V, VISO = 3.3 V
tPHL(ns) at VCC = 5 V, VISO = 3.3 V
tPLH(ns) at VCC = 3.3 V, VISO = 3.3 V
tPHL(ns) at VCC = 3.3 V, VISO = 3.3 V
tPLH(ns) at VCC = 3.3 V, VISO = 5 V
tPHL(ns) at VCC = 3.3 V, VISO = 5 V
10
8
6
2.1
4
VCC Rising
VCC Falling
2
-40
-20
0
20
40
60
Free Air Temperature (°C)
80
100 120 140
2
-40
-20
0
20
40
60
80
100 120
Free-Air Temperature (èC)
图7-14. Propagation Delay Time vs Free-Air
图7-13. Power-Supply Undervoltage Threshold vs
Temperature
Free Air Temperature
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6
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4
3
2
1
VSO = 3.3 V
VSO = 5 V
VSO = 3.3 V
VSO = 5 V
0
0
5
10
Low-Level Output Current (mA)
15
-15
-10 -5
High-Level Output Current (mA)
0
TA = 25°C
TA = 25°C
图7-16. Low-Level Output Voltage vs Low-Level
图7-15. High-Level Output Voltage vs High-Level
Output Current
Output Current
VISO = 3.3 V (50 mV/div)(1)
ICC (40 mA/div)
IISO
110 mA
VISO = 3.3 V (1 V/div)
10 mA
10 mA
2
100 µs/div
2 ms/div
VCC = 5 V
VISO = 3.3 V
VCC = 5 V
VISO = 3.3 V
Negligible undershoot and overshoot because of load transient
Current spike is because of charging the input supply capacitor
图7-17. 10-mA to 110-mA Load Transient
图7-18. Soft Start at 10-mA Load
Response
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ICC (40 mA/div)
ICC (40 mA/div)
VISO = 5 V (1 V/div)
VISO = 3.3 V (1 V/div)
2 ms/div
2 ms/div
VCC = 5 V
VISO = 5 V
VCC = 5 V
VISO = 3.3 V
Input current spike is because of charging the input supply
decoupling capacitor
Input current spike is because of charging the input supply
decoupling capacitor
图7-20. Soft Start at 10-mA Load
图7-19. Soft Start at 120-mA Load
ICC (40 mA/div)
VISO = 5 V (20 mV/div)
VISO = 5 V (1 V/div)
5 µs/div
2 ms/div
VCC = 5 V
VISO = 5 V
VCC = 5 V
VISO = 5 V
Input current spike is because of charging the input supply
decoupling capacitor
图7-22. VISO Ripple Voltage at 130 mA
图7-21. Soft Start at 130-mA Load
VISO = 3.3 V (20 mV/div)
5 µs/div
VCC = 5 V
VISO = 3.3 V
图7-23. VISO Ripple Voltage at 130 mA
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8 Parameter Measurement Information
V
SI
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
O
50 ꢀ
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
1. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty
cycle, tr ≤3 ns, tf ≤3 ns, ZO = 50 Ω. At the input, 50-Ωresistor is required to terminate the input generator
signal. The resistor is not required in the actual application.
2. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图8-1. Switching Characteristics Test Circuit and Voltage Waveforms
5 V
5 V
V
SO
V
SI
10 …F || 0.1 µF
C3
C4
10 …F
0.1 …F
GNDI
IN
OUT
C
L
GNDI
GNDO
+
œ
V
CM
1. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
2. Pass-fail criteria: Outputs must remain stable.
图8-2. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISOW7841A-Q1 has a high-efficiency, low-emissions isolated DC-DC converter, and four high-speed
isolated data channels. Block Diagram shows the functional block diagram of the ISOW7841A-Q1.
The integrated DC-DC converter uses switched mode operation and proprietary circuit techniques to reduce
power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of a high-Q
on-chip transformer provide high efficiency and low radiated emissions. The integrated transformer uses thin film
polymer as the insulation barrier.
The VCC supply is provided to the primary power controller that switches the power stage connected to the
integrated transformer. Power is transferred to the secondary side, rectified and regulated to either 3.3 V or 5 V,
depending on the SEL pin. The output voltage, VISO, is monitored and feedback information is conveyed to the
primary side through a dedicated isolation channel. The duty cycle of the primary switching stage is adjusted
accordingly. The fast feedback control loop of the power converter ensures low overshoots and undershoots
during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VCC and VISO supplies
which ensures robust system performance under noisy conditions. An integrated soft-start mechanism ensures
controlled inrush current and avoids any overshoot on the output during power up.
The integrated signal-isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across
the barrier to represent one state and sends no signal to represent the other state. The receiver demodulates the
signal after signal conditioning and produces the output through a buffer stage. The signal-isolation channels
incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions from the high frequency carrier and IO buffer switching. 图 9-2 shows a functional block diagram of a
typical signal isolation channel.
The ISOW7841A-Q1 is suitable for applications that have limited board space and require more integration. This
device is also suitable for very-high voltage applications, where power transformers meeting the required
isolation specifications are bulky and expensive.
9.2 Functional Block Diagram
Transformer
V
CC
V
ISO
Power
Controller
Transformer
Driver
Rectifier
UVLO, Soft-start
Thermal
Shutdown,
UVLO, Soft-start
FB Channel (Tx)
FB Controller
I/O Channels
FB Channel (Rx)
V
ref
I/O Channels
Data Channels
(4)
Data Channels
(4)
Isolation Barrier
图9-1. Block Diagram
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Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
图9-2. Conceptual Block Diagram of a Capacitive Data Channel
图9-3 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图9-3. On-Off Keying (OOK) Based Modulation Scheme
9.3 Feature Description
表9-1 shows an overview of the device features.
表9-1. Device Features
DEFAULT OUTPUT
STATE
PART NUMBER(1)
CHANNEL DIRECTION
MAXIMUM DATA RATE
RATED ISOLATION(2)
ISOW7841A-Q1
ISOW7841FA-Q1
High
Low
3 forward, 1 reverse
100 Mbps
5 kVRMS / 7071 VPK
(1) The F suffix is part of the orderable part number. See the section for the full orderable part number.
(2) For detailed isolation ratings, see the table.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
The ISOW7841A-Q1 uses emissions reduction schemes for the internal oscillator and advanced internal layout
scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
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performance and reliability depends, to a large extent, on the application board design and layout, the
ISOW7841A-Q1 incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
9.3.2 Power-Up and Power-Down Behavior
The ISOW7841A-Q1 has built-in UVLO on the VCC and VISO supplies with positive-going and negative-going
thresholds and hysteresis. When the VCC voltage crosses the positive-going UVLO threshold during power-up,
the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-
start scheme limits primary peak currents drawn from the VCC supply and charges the VISO output in a controlled
manner, avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VCC or
VISO voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on
the secondary side VISO pin, the feedback data channel starts providing feedback to the primary controller. The
regulation loop takes over and the isolated data channels go to the normal state defined by the respective input
channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load
capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.
When VCC power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached.
The VISO capacitor then discharges depending on the external load. The isolated data outputs on the VISO side
are returned to the default state for the brief time that the VISO voltage takes to discharge to zero.
9.3.3 Current Limit, Thermal Overload Protection
The ISOW7841A-Q1 is protected against output overload and short circuit. Output voltage starts dropping when
the power converter is not able to deliver the current demanded during overload conditions. For a VISO short-
circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
Thermal protection is also integrated to help prevent the device from getting damaged during overload and
short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to increase.
When the temperature goes above 180°C, thermal shutdown activates and the primary controller turns off which
removes the energy supplied to the VISO load, which causes the device to cool off. When the junction
temperature goes below 150°C, the device starts to function normally. If an overload or output short-circuit
condition prevails, this protection cycle is repeated. Care should be taken in the design to prevent the device
junction temperatures from reaching such high values.
9.4 Device Functional Modes
表9-2 lists the supply configurations for these devices.
表9-2. Supply Configurations
SEL INPUT
VCC
5 V
VISO
5 V
Shorted to VISO
Shorted to VISO
3.3 V
5 V
5 V
Shorted to GND2 or floating
Shorted to GND2 or floating
3.3 V
3.3 V(1)
3.3 V
(1) The SEL pin has a weak pulldown internally. Therefore for VISO = 3.3 V, the SEL pin should be
strongly connected to the GND2 pin in noisy system scenarios.
表9-3 lists the functional modes for ISOW7841A-Q1.
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表9-3. Function Table
INPUT SUPPLY
INPUT
(INx)
OUTPUT
(OUTx)
COMMENTS
(VCC
)
H
L
H
Output channel assumes the logic state of its input
L
PU
Default mode(1): When INx is open, the corresponding
output channel assumes logic based on default output
mode of selected version
Open
X
Default
PD
Undetermined(2)
(1) In the default condition, the output is high for ISOW7841A-Q1 and low for ISOW7841A-Q1 with the F suffix.
(2) The outputs are in an undetermined state when VCC < 2.1 V.
9.4.1 Device I/O Schematics
Input (Device without F suffix)
Input (Device with F suffix)
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
SEL Pin
Output
V
ISO
V
V
V
ISO
ISO
ISO
~20 ꢀ
1970 ꢀ
OUTx
SEL
2 Mꢀ
图9-4. Device I/O Schematics
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The device is a high-performance, quad channel digital isolator with integrated DC-DC converter. Typically digital
isolators require two power supplies isolated from each other to power up both sides of device. Due to the
integrated DC-DC converter in the device, the isolated supply is generated inside the device that can be used to
power isolated side of the device and peripherals on isolated side, thus saving board space. The device uses
single-ended CMOS-logic switching technology. When designing with digital isolators, keep in mind that because
of the single-ended design structure, digital isolators do not conform to any specific interface standard and are
only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between
the data controller (that is Microcontroller or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
The device is suitable for applications that have limited board space and desire more integration. The device is
also suitable for very high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
10.2 Typical Application
图 10-1 shows the typical schematic for SPI isolation. Typically, an ADC is used to monitor HV battery to chassis
insulation resistance.
Reference
0.1 …F
22 …F
22 …F
0.1 …F
3.3VIN
VISO
SEL
VCC
3.3VOUT
DVCC
MCU
DVSS
AVDD
DVDD
REF
CS
CS
INA
INB
OUTA
ISOW7841A-Q1
HV+ to Chassis
HV- to Chassis
SCLK
SCLK
OUTB
ADC
SDI
SDO
SDI
INC
OUTC
IND
SDO
OUTD
AGND
DGND
GND1
GND2
图10-1. Isolated Power and SPI for Automotive BMS Insulation monitoring Application with ISOW7841A-
Q1
10.2.1 Design Requirements
To design with this device, use the parameters listed in 表10-1.
表10-1. Design Parameters
PARAMETER
VALUE
Input voltage
3 V to 5.5 V
Decoupling capacitor between VCC and GND1
Decoupling capacitor between VISO and GND2
0.1 µF to 10 µF
0.1 µF to 10 µF
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Because of very-high current flowing through the ISOW7841A-Q1 device VCC and VISO supplies, higher
decoupling capacitors typically provide better noise and ripple performance. Although a 10-µF capacitor is
adequate, higher decoupling capacitors (such as 22 µF or 47 µF) on both the VCC and VISO pins to the
respective grounds are strongly recommended to achieve the best performance.
10.2.2 Detailed Design Procedure
The devices requires only external bypass capacitors to operate. These low-ESR ceramic bypass capacitors
must be placed as close to the chip pads as possible.
10 ꢀF
10 ꢀF
2 mm Maximum
from Vcc
2 mm Maximum
from VISO
0.1 ꢀF
0.1 ꢀF
VCC
VISO
1
16
GND1
2
3
15
14
GND2
INA
INB
OUTA
OUTB
4
13
INC
5
6
12
11
OUTC
IND
OUTD
7
8
10
9
SEL
GND1
GND2
图10-2. Typical ISOW7841A-Q1 Circuit Hook-Up
The VCC power-supply input provides power to isolated data channels and to the isolated DC-DC converter. Use
方程式1 to calculate the total power budget on the primary side.
ICC = (VISO × IISO) / (η× VCC) + Iinpx
(1)
where
• ICC is the total current required by the primary supply.
• VISO is the isolated supply voltage.
• IISO is the external load on the isolated supply voltage.
• ηis the efficiency.
• VCC is the supply voltage.
• Iinpx is the total current drawn for the isolated data channels and power converter when data channels are
toggling at a specific data rate. This data is shown in the 节7.9 table.
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10.2.3 Application Curve
ICC (40 mA/div)
VISO (600 mV/div)
VCC = 3.3 V
IISO = 70 mA
Input current spike is because of charging the input supply decoupling capacitor
图10-3. Soft-Start Waveform
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 10-4 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 10-5 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图10-4. Test Setup for Insulation Lifetime Measurement
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图10-5. Insulation Lifetime Projection Data
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Power Supply Recommendations
To help make sure that operation is reliable at data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. The input supply (VCC) must have an appropriate current
rating to support output load and switching at the maximum data rate required by the end application. For more
information, refer to the Detailed Design Procedure section.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low-EMI PCB design (see 图 11-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Keep decoupling capacitors as close as possible to the VCC and VISO pins.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective
GND pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature
of the device from rising to unacceptable levels.
The integrated signal and power isolation device simplifies system design and reduces board area. The use of
low-inductance micro-transformers in the device necessitates the use of high frequency switching, resulting in
higher radiated emissions compared to discrete solutions. The device uses on-chip circuit techniques to reduce
emissions compared to competing solutions. For further reduction in radiated emissions at system level, refer to
the Low-Emission Designs With ISOW7841 Integrated Signal and Power Isolator application report.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
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11.2 Layout Example
Solid supply islands reduce
inductance because large peak
currents flow into the VCC pin
2 mm
maximum
from VCC
2 mm
maximum
from VISO
VCC
VISO
1
16
0.1 …F
GND2
10 …F
0.1 …F
10 …F
GND1
2
3
15
14
4
13
5
6
12
11
SEL
7
8
10
9
GND2
GND1
Solid ground islands help
dissipate heat through PCB
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, refer to:
• 8-ch Isolated High Voltage Analog Input Module with ISOW7841 Reference Design
• Isolated CAN Module With Integrated Power Reference Design
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, ISOW784x Quad-Channel Digital Isolator With Integrated DC-DC Converter Evaluation
Module user's guide
• Texas Instruments, Low-Emission Designs With ISOW7841 Integrated Signal and Power Isolator application
report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI ™E2E Online
Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among
engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas
and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DWE0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4223098/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: ISOW7841A-Q1
English Data Sheet: SLLSFG1
ISOW7841A-Q1
ZHCSKT4B –FEBRUARY 2020 –REVISED DECEMBER 2020
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
16X (0.6)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
9
8
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223098/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFG1
34
Submit Document Feedback
Product Folder Links: ISOW7841A-Q1
ISOW7841A-Q1
ZHCSKT4B –FEBRUARY 2020 –REVISED DECEMBER 2020
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4223098/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: ISOW7841A-Q1
English Data Sheet: SLLSFG1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOW7841AQDWEQ1
ISOW7841AQDWERQ1
ISOW7841FAQDWEQ1
ISOW7841FAQDWERQ1
ACTIVE
SOIC
SOIC
SOIC
SOIC
DWE
16
16
16
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
W7841A
Q1
ACTIVE
ACTIVE
ACTIVE
DWE
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
W7841A
Q1
DWE
W7841FA
Q1
DWE
W7841FA
Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DWE0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4223098/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
9
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223098/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
8
9
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4223098/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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