IWR1443FQAGABLR [TI]
集成 MCU 和硬件加速器的 76GHz 至 81GHz 单芯片毫米波传感器 | ABL | 161 | -40 to 105;
| 型号： | IWR1443FQAGABLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 集成 MCU 和硬件加速器的 76GHz 至 81GHz 单芯片毫米波传感器 | ABL | 161 | -40 to 105 传感器 |
| 文件： | 总74页 (文件大小：1716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
IWR1443 单芯片 76 至 81GHz 毫米波传感器
1 器件概述
1.1 特性
1
– I2C（支持主模式和从模式）
• FMCW 收发器
– 两个 SPI 端口
– CAN 端口
– 多达六个通用 ADC 端口
– 集成式 PLL、发送器、接收器、基带和 A2D
– 76 至 81GHz 覆盖范围，具有 4GHz 的连续带宽
– 四个接收通道
• 支持分布式 应用
• 主机接口
– 三个发送通道（可以同时使用两个通道）
– 基于分数 N PLL 的超精确线性调频脉冲引擎
– TX 功率：12dBm
– 通过 SPI 与外部处理器进行控制连接
– 通过 MIPI D-PHY 和 CSI2 V1.1 与外部处理器进
行数据连接
– RX 噪声系数：
– 14dB（76 至 77GHz）
– 用于故障报告的中断
• IWR1443 高级 特性
– 嵌入式自监控，无需使用主机处理器
– 复基带架构
– 嵌入式干扰检测功能
• 电源管理
– 内置的 LDO 网络，可增强 PSRR
– I/O 支持双电压 3.3V/1.8V
• 时钟源
– 15dB（77 至 81GHz）
– 1MHz 时的相位噪声：
– –95dBc/Hz（76 至 77GHz）
– –93dBc/Hz（77 至 81GHz）
• 内置的校准和自检
– ARM® Cortex®基于 ARM® Cortex®-R4F 的无线
电控制系统
– 内置的固件 (ROM)
– 针对频率和温度进行自校准的系统
• 适用于嵌入式用户应用的片上可编程内核
– 支持频率为 40MHz 的外部振荡器
– 支持外部驱动、频率为 40MHz 的时钟（方波/正
弦波）
– 计时频率为 200MHz 的集成 Cortex®-R4F 微控
制器
• 轻松的硬件设计
– 片上引导加载程序支持自主模式（从 QSPI 闪存
加载用户应用）
– 0.65mm 间距、161 引脚 10.4mm × 10.4mm 覆
晶 BGA 封装，可实现轻松组装和低成本 PCB 设
计
– 集成外设
– 具有 ECC 的内部存储器
– 雷达硬件加速器（FFT、对数幅度计算等）
– 集成计时器（看门狗以及多达四个 32 位计时
器或两个 64 位计时器）
– 小尺寸解决方案
• 运行条件
– 结温范围:–40°C 至 105°C
1.2 应用
•
•
•
•
•
用于测量距离、速度和角度的工业传感器
•
•
•
•
接近和位置感应
安全和监控
液箱液位探测雷达
位移感应
工厂自动化
现场发送器
交通监控
安全防护装置
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWRS211
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
Stored
Program
40 Mhz
Crystal
QSPI
Flash
Rx1
Control and Data
SPI
Communication
Interface
Rx2
Rx3
Control and Data
Communication
Interface
UART
CAN
Rx4
Radar
Front
End
R4F ARM
Control and Computation Processor
Hardware Accelerator, and Peripherals
Control and Data
Communication
Interface
Tx1
Tx2
High Speed
Data Interface
LVDS or
CSI-2
LVDS
Tx3
CSI-2
DC Power
and Power
Management
图 1-1. 适用于工业应用的自主 传感器
1.3 说明
IWR1443 器件是一款能够在 76 至 81GHz 频带中运行且基于 FMCW 雷达技术的集成式单芯片毫米波传感
器，具有高达 4GHz 的连续线性调频脉冲。该器件采用 TI 的低功耗 45nm RFCMOS 工艺进行构建，并且此
解决方案在极小的封装中实现了前所未有的集成度。IWR1443 是适用于工业 应用 （如楼宇自动化、工厂自
动化、无人机、物料处理、交通监控和监视）中的低功耗、自监控、超精确雷达系统的理想解决方案。
IWR1443 器件是一种自包含单芯片解决方案，能够简化 76 至 81GHz 频带中的毫米波传感器实施。
IWR1443 包含一个具有内置 PLL 和模数转换器的单片实施 3TX、4RX 系统。该器件包含一个支持复数 FFT
和 CFAR 检测且完全可配置的硬件加速器。此外，该器件还包含两个基于 ARM R4F 的处理器子系统：一个
处理器子系统用于主控制和其他算法；另一个处理器子系统负责前端配置、控制和校准。简单编程模型更改
可支持各种传感器实施，并且能够进行动态重新配置，从而实现多模式传感器。此外，该器件作为完整的平
台解决方案进行提供，该解决方案包括硬件参考设计、软件驱动程序、样例配置、API 指南、培训以及用户
文档。
器件信息(1)
封装
器件编号
IWR1443FQAGABLR（卷带）
IWR1443FQAGABL（托盘）
封装尺寸
FCBGA (161)
10.4mm × 10.4mm
(1) 更多信息请参见 节 9，机械封装和可订购产品信息。
2
器件概述
版权 © 2017–2018, Texas Instruments Incorporated
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
1.4 功能框图
Rx1
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Cortex R4F
@ 200MHz
Rx2
Digital Front-
end
LNA
(User programmable)
Rx3
(Decimation
filter chain)
LNA
Prog
RAM
Data
RAM (*) ROM
Boot
Rx4
LNA
QSPI Flash
interface
QSPI
SPI
Hardware
Accelerator
(**)
ADC Buffer
(**)
External MCU
interface
Tx1
PA
BPM
BPM
BPM
RF/Analog sub-system
DMA
SPI / I2C
DCAN
PMIC control
Tx2
Optional communicatio
interface
PA
Master sub-system
(Customer programmed)
Ramp
Generator
Control UART,
And Debug UART
Debug
UARTs
Synth
Tx3
x4
PA
(20 GHz)
Radar Data
Memory (*)
(L3)
Test/
Debug
JTAG for debug/
development
Temp
6
RF Control
BIST
Mailbox
GPADC
High-speed Rx or
process
Data for recording or
External DSP
LVDS/
CSI-2
Osc.
(*) Total RAM available in Master subsystem is divided into ARM-Data RAM, Tightly Coupled Memory, Radar Data Memory, Patch Memory
(**) Shared Memory for ADC Buffer and Hardware Accelerator
版权 © 2017–2018, Texas Instruments Incorporated
器件概述
3
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 7
3.1 Related Products ..................................... 8
Terminal Configuration and Functions.............. 9
4.1 Pin Diagram .......................................... 9
4.2 Signal Descriptions.................................. 13
4.3 Pin Multiplexing ..................................... 16
Specifications ........................................... 21
5.1 Absolute Maximum Ratings......................... 21
5.2 ESD Ratings ........................................ 21
5.3 Power-On Hours (POH)............................. 21
5.4 Recommended Operating Conditions............... 22
5.5 Power Supply Specifications........................ 22
5.6 Power Consumption Summary...................... 23
5.7 RF Specification..................................... 24
6.1 Overview ............................................ 51
6.2 Functional Block Diagram........................... 51
6.3 External Interfaces .................................. 52
6.4 Subsystems ......................................... 52
6.5 Accelerators and Coprocessors..................... 57
6.6 Other Subsystems................................... 58
6.7 Identification ......................................... 62
6.8 Boot Modes.......................................... 62
Applications, Implementation, and Layout........ 65
7.1 Application Information.............................. 65
7.2 Reference Schematic ............................... 65
7.3 Layout ............................................... 66
Device and Documentation Support ............... 67
8.1 Device Nomenclature ............................... 67
8.2 Tools and Software ................................. 68
8.3 Documentation Support ............................. 68
8.4 Community Resources.............................. 69
8.5 商标.................................................. 69
8.6 静电放电警告 ........................................ 69
8.7 Export Control Notice ............................... 69
8.8 Glossary ............................................. 69
2
3
4
7
8
5
5.8
Thermal Resistance Characteristics for FCBGA
Package [ABL0161] ................................. 25
9
Mechanical, Packaging, and Orderable
5.9 Timing and Switching Characteristics............... 25
Information .............................................. 70
9.1 Packaging Information .............................. 70
6
Detailed Description ................................... 51
4
内容
版权 © 2017–2018, Texas Instruments Incorporated
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from February 20, 2018 to October 31, 2018 (from B Revision (February 2018) to C Revision)
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
将 RX 噪声系数从“15dB（76 至 77GHz）”更新成了“14dB（76 至 77GHz）”................................................ 1
将 RX 噪声系数从“16dB（77 至 81GHz）”更新成了“15dB（77 至 81GHz）”................................................ 1
将 1MHz 时的相位噪声从“–94dBc/Hz（76 至 77GHz）”更新成了“–95dBc/Hz（76 至 77GHz）” ......................... 1
将 1MHz 时的相位噪声从“–91dBc/Hz（77 至 81GHz）”更新成了“–93dBc/Hz（77 至 81GHz）” ......................... 1
从“...的高速数据接口”项目中删除了“（即中间数据）”............................................................................ 1
从外部驱动振荡器和外部驱动时钟中删除了 50MHz.............................................................................. 1
更新了“器件信息”...................................................................................................................... 2
从功能方框图 中删除了“VMON”框.................................................................................................. 3
Added table note to "Number of transmitters" in Device Features Comparison.............................................. 7
Updated IWR1443 and IWR1642 Product status from AI to PD ............................................................... 7
Updated OSC_CLKOUT ........................................................................................................... 13
Updated P7 from "Open Drain" to "Pull Up'...................................................................................... 13
Updated B10 DESCRIPTION...................................................................................................... 14
Updated A10, A13, A2, and B2 DESCRIPTION ................................................................................ 14
Removed footnote from Flash programming and RS232 UART.............................................................. 15
Updated ESD Ratings .............................................................................................................. 21
Updated/Changed Power-On Hours (POH) ..................................................................................... 21
Updated VIOIN in Recommended Operating Conditions ...................................................................... 22
Updated VIL 1.8V MAX from "3*VIOIN" to "0.3*VIOIN"......................................................................... 22
Updated VOH in Recommended Operating Conditions ......................................................................... 22
Updated VOH in Recommended Operating Conditions ......................................................................... 22
Updated Recommended Operating Conditions ................................................................................. 22
Added "VNWA" to 1.2 V Supply in Power Supply Rails Characteristics ..................................................... 22
Completely updated Ripple Specifications table ................................................................................ 23
Updated Receiver Noise figure values in RF Specification.................................................................... 24
Updated Receiver 1-dB compression point value from "–5" to "–8".......................................................... 24
Updated "IQ gain mismatch" to "Image Rejection Ratio (IMRR)"............................................................. 24
Removed IQ phase mismatch from RF Specification .......................................................................... 24
Updated RF Specification table ................................................................................................... 24
Updated footnote in RF Specification............................................................................................. 25
Removed 1v4 signal from Device Wakeup ..................................................................................... 26
Updated Device Wake-up Sequence ............................................................................................. 26
Updated Synchronized Frame Triggering text .................................................................................. 27
Added Synchronized Frame Triggering subsection............................................................................. 27
Removed TLag from Frame Trigger Timing table ............................................................................... 27
Updated Crystal Implementation note ............................................................................................ 28
Updated/Changed fP Parallel resonance crystal frequency from " 40, 50" to "40".......................................... 28
Completely updated External Clock Mode Specifications ..................................................................... 29
Updated SPI Slave Mode Timing Requirements................................................................................ 35
Added LVDS Interface Configuration ............................................................................................. 38
Updated LVDS Interface Lane Config image.................................................................................... 38
Updated Timing Parameters....................................................................................................... 38
Updated LVDS Electrical Characteristics ....................................................................................... 39
Updated Timing Requirements for QSPI Input (Read) Timings............................................................... 44
Added Q12, Q13, Q14, and Q15 to QSPI Switching Characteristics ........................................................ 45
Updated Data bit rate from 900 Mbps to 600 Mbps ............................................................................ 48
Removed TCLK-SETTLE and THS-SETTLE............................................................................................... 48
Updated Clock Subsystem diagram .............................................................................................. 53
Updated/Changed Transmit Subsystem (Per Channel)........................................................................ 54
Removed Master System Memory Map.......................................................................................... 56
Updated Host Interface............................................................................................................. 57
Updated text in "A2D Data Format Over CSI2 Interface"...................................................................... 58
Updated text in ADC Channels (Service) for User Application................................................................ 60
Completely updated GP-ADC Parameter table ................................................................................. 60
Copyright © 2017–2018, Texas Instruments Incorporated
修订历史记录
5
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
•
•
•
Updated text in Functional Mode.................................................................................................. 64
Updated Application Information .................................................................................................. 65
Updated Device Nomenclature.................................................................................................... 68
6
修订历史记录
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
3 Device Comparison
Table 3-1. Device Features Comparison
FUNCTION
IWR1443
4
IWR1642
Number of receivers
Number of transmitters
On-chip memory
4
2
3
576KB
15
1.5MB
5
Max I/F (Intermediate Frequency) (MHz)
Max real sampling rate (Msps)
Max complex sampling rate (Msps)
Processor
37.5
18.75
12.5
6.25
MCU (R4F)
Yes
—
Yes
Yes
DSP (C674x)
Peripherals
Serial Peripheral Interface (SPI) ports
Quad Serial Peripheral Interface (QSPI)
Inter-Integrated Circuit (I2C) interface
Controller Area Network (DCAN) interface
Trace
1
2
Yes
1
Yes
1
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
—
PWM
—
Hardware In Loop (HIL/DMM)
GPADC
—
Yes
Yes
Yes
Yes
Yes
Yes
LVDS/Debug
CSI2
Hardware accelerator
1-V bypass mode
—
Yes
Yes
JTAG
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product status
PD(1)
PD(1)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2017–2018, Texas Instruments Incorporated
Device Comparison
7
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
3.1 Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with
less power using the smallest footprint mmWave sensor portfolio for industrial applications.
mmWave IWR The Texas Instruments IWR1xxx family of mmWave Sensors are highly integrated and
built on RFCMOS technology operating in 76- to 81-GHz frequency band. The devices have
a closed-loop PLL for precise and linear chirp synthesis, includes a built-in radio processor
(BIST) for RF calibration and safety monitoring. The devices have a very small-form factor,
low power consumption, and are highly accurate. Industrial applications from long range to
ultra short range can be realized using these devices.
Companion Products for IWR1443 Review products that are frequently purchased or used in
conjunction with this product.
IWR1443 Reference Designs The IWR1443 TI Designs Reference Design Library is a robust reference
design library spanning analog, embedded processor and connectivity. Created by TI experts
to help you jump-start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
Power Optimization for IWR1443 77GHz-Level Transmitter Reference Design
The
TIDEP-0091
highlights strategies for power optimization of a IWR1443 76- to 81-GHz mmWave sensor in
tank level-probing applications, displacement sensors, 4- to 20-mA sensors, and other low-
power applications for detecting range with high accuracy in minimal power envelope.
8
Device Comparison
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the pin locations for the 161-pin FCBGA package. Figure 4-2, Figure 4-3, Figure 4-4,
and Figure 4-5 show the same pins, but split into four quadrants.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VOUT
_14APLL
VOUT
_14SYNTH
OSC
_CLKOUT
A
B
C
D
E
F
VSSA
VOUT_PA
VSSA
VSSA
VSSA
VSSA
VSSA
VIN
_18CLK
VIN
_18VCO
RESERVED
RESERVED
VOUT_PA
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VSSA
VSSA
VBGAP
VSSA
VSSA
VIN
_13RF2
ANAMUX/
GPADC5
VSENSE/
GPADC6
VSSA
RESERVED
VSSA
VSSA
VSSA
VSSA
VSSA
RESERVED
VSSA
VIN
_13RF2
VIOIN
_18DIFF
VSSA
RX4
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VDDIN
Reserved
TDI
CLKP
CLKM
VIN_18BB
VSS
VSS
VSS
VIN
_13RF1
CSI2
_TXM[0]
CSI2
_TXP[0]
G
H
J
VSSA
VSSA
VSSA
VSSA
VSSA
RX3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VIN
_13RF1
CSI2
_TXM[1]
CSI2
_TXP[1]
VSS
VIN
_13RF1
VSSA
RX2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TDO
CSI2_CLKM
CSI2_CLKP
CSI2
_TXM[2]
CSI2
_TXP[2]
K
L
VIN_18BB
VSS
VIOIN_18
CSI2
_TXM[3]
CSI2
_TXP[3]
VSSA
RX1
VSS
VSS
TMS
HS_M
_Debug1
HS_P
_Debug1
M
N
P
R
TCK
WARM
_RESET
HS_M
_Debug2
HS_P
_Debug2
VSSA
GPIO[0]
Reserved
Reserved
RS232_RX
RS232_TX
GPIO[1]
NERROR_OUTMCU_CLK_OUT
Sync_in
QSPI[3]
VDDIN
Sync_out
QSPI[0]
GPIO[2]
Analog Test 1/ Analog Test 2/ Analog Test 3/
GPADC3
MISO_1 SPI_HOST_INTR_NERROR_IN
QSPI_CS
MOSI_1
QSPI[1]
NRESET PMIC_CLK_OUT
VNWA
VDDIN
GPADC1
GPADC2
Analog Test 4/
GPADC4
VSSA
Reserved
Reserved
VDDIN
SPI_CS_1
SPI_CLK_1
QSPI_CLK
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
Figure 4-1. Pin Diagram
Copyright © 2017–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
9
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
1
2
3
4
5
6
7
8
A
B
C
D
E
F
VSSA
VOUT_PA
VOUT_PA
VSSA
VSSA
VSSA
RESERVED
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VIN
_13RF2
RESERVED
VSSA
VSSA
RX4
VSSA
VSSA
VSSA
VSS
VSS
VSS
VIN_18BB
VIN
_13RF1
G
VSSA
VSSA
VSS
VSS
VSS
Not to scale
1
2
4
3
Figure 4-2. Top Left Quadrant
9
10
11
12
13
14
15
VOUT
_14APLL
VOUT
_14SYNTH
OSC
_CLKOUT
A
VSSA
VSSA
VIN
_18CLK
VIN
_18VCO
RESERVED
B
C
D
E
F
VSSA
VSSA
VBGAP
VSSA
VSSA
ANAMUX/
GPADC5
VSENSE/
GPADC6
VSSA
RESERVED
VSSA
VIOIN
_18DIFF
VSS
VSS
VSS
VSSA
VDDIN
CLKP
CLKM
VSS
CSI2
_TXM[0]
CSI2
_TXP[0]
G
VSS
Reserved
Not to scale
1
3
2
4
Figure 4-3. Top Right Quadrant
10
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
1
2
3
4
5
6
7
8
VIN
_13RF1
H
RX3
VSSA
VSS
VIN
_13RF1
J
VSSA
VSSA
RX2
VSSA
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
K
L
VIN_18BB
VSSA
VSSA
RX1
VSS
VSS
M
N
P
R
VSSA
VSSA
GPIO[0]
Reserved
Reserved
RS232_RX
RS232_TX
GPIO[1]
NERROR_OUT
Analog Test 1/ Analog Test 2/ Analog Test 3/
GPADC3
MISO_1 SPI_HOST_INTR_NERROR_IN
QSPI_CS
GPADC1
GPADC2
Analog Test 4/
GPADC4
VSSA
Reserved
Reserved
VDDIN
SPI_CS_1
MOSI_1
Not to scale
1
3
2
4
Figure 4-4. Bottom Left Quadrant
Copyright © 2017–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
11
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
9
10
11
12
13
14
15
CSI2
_TXM[1]
CSI2
_TXP[1]
H
J
VSS
VSS
TDI
VSS
VSS
VSS
TDO
VIOIN_18
TMS
CSI2_CLKM
CSI2_CLKP
CSI2
_TXM[2]
CSI2
_TXP[2]
K
L
VSS
VSS
CSI2
_TXM[3]
CSI2
_TXP[3]
HS_M
_Debug1
HS_P
_Debug1
M
N
P
R
TCK
WARM
_RESET
HS_M
_Debug2
HS_P
_Debug2
MCU_CLK_OUT
Sync_in
QSPI[3]
VDDIN
Sync_out
QSPI[0]
GPIO[2]
QSPI[1]
NRESET PMIC_CLK_OUT
VNWA
VDDIN
SPI_CLK_1
QSPI_CLK
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
1
3
2
4
Figure 4-5. Bottom Right Quadrant
12
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
4.2 Signal Descriptions
Table 4-1. Signal Descriptions
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS(1)
FUNCTION
SIGNAL NAME
DESCRIPTION
TX1
B4
B6
O
O
O
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Single-ended transmitter1 o/p
Single-ended transmitter2 o/p
Single-ended transmitter3 o/p
Single-ended receiver1 i/p
Single-ended receiver2 i/p
Single-ended receiver3 i/p
Single-ended receiver4 i/p
Transmitters
TX2
TX3
B8
RX1
M2
RX2
K2
I
Receivers
RX3
H2
I
RX4
F2
I
CSI2_TXP[0]
CSI2_TXM[0]
CSI2_CLKP
CSI2_CLKM
CSI2_TXP[1]
CSI2_TXM[1]
CSI2_TXP[2]
CSI2_TXM[2]
CSI2_TXP[3]
CSI2_TXM[3]
HS_DEBUG1_P
HS_DEBUG1_M
HS_DEBUG2_P
HS_DEBUG2_M
G15
G14
J15
J14
H15
H14
K15
K14
L15
L14
M15
M14
N15
N14
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Differential data Out – Lane 0
Differential clock Out
Differential data Out – Lane 1
Differential data Out – Lane 2
Differential data Out – Lane 3
Differential debug port 1
CSI2 TX/LVDS
TX
Differential debug port 2
B1, B15,
D1, D15
RESERVED
—
—
Reference clock output from clocking subsystem
after cleanup PLL.
Reference clock OSC_CLKOUT
A14
P11
O
O
Low-frequency frame synchronization signal output.
Can be used by slave chip in multichip cascading
SYNC_OUT
Pull Down
System
synchronization
SYNC_IN
N10
R7
R9
R8
P5
I
I
Pull Down
Pull Up
Low-frequency frame synchronization signal input.
SPI_CS_1
SPI_CLK_1
MOSI_1
SPI chip select
SPI clock
SPI control
interface from
external MCU
(default slave
mode)
I
Pull Down
Pull Up
I
SPI data input
SPI data output
SPI interrupt to host
MISO_1
O
O
Pull Up
SPI_HOST_INTR_1
P6
Pull Down
R3, R4, R5,
P4
RESERVED
NRESET
—
P12
I
Open Drain
Power on reset for chip. Active low
Open-drain fail-safe warm reset signal. Can be
driven from PMIC for diagnostic or can be used as
status signal that the device is going through reset.
Reset
Safety
WARM_RESET
N12
IO
Open Drain
Open-drain fail-safe output signal. Connected to
PMIC/Processor/MCU to indicate that some severe
criticality fault has happened. Recovery would be
through reset.
NERROR_OUT
N8
P7
O
I
Open Drain
Fail-safe input to the device. Error output from any
other device can be concentrated in the error
signaling monitor module inside the device and
appropriate action can be taken by firmware
NERROR_IN
Pull Up
(1) Status of PULL structures associated with the IO after device POWER UP.
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Terminal Configuration and Functions
13
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
Table 4-1. Signal Descriptions (continued)
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS(1)
FUNCTION
SIGNAL NAME
DESCRIPTION
TMS
TCK
TDI
L13
M13
H13
J13
I
I
Pull Up
Pull Down
Pull Up
—
JTAG
JTAG port for standard boundary scan
I
TDO
CLKP
O
I
E14
—
In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input
reference clock port (Output CLKM is grounded in
this case)
Reference
oscillator
CLKM
F14
B10
O
—
Band-gap
voltage
VBGAP
VDDIN
O
—
—
Internal voltage reference 0.9V
1.2-V digital power supply
F13,N11,P1
5,R6
POW
VIN_SRAM
VNWA
R14
P14
POW
POW
—
—
1.2-V power rail for internal SRAM
1.2-V power rail for SRAM array back bias
I/O supply (3.3-V or 1.8-V): All CMOS I/Os would
operate on this supply.
VIOIN
R13
POW
—
VIOIN_18
K13
B11
POW
POW
POW
POW
POW
—
—
—
—
—
1.8-V supply for CMOS IO
1.8-V supply for clock module
1.8-V supply for CSI2 port
No connect
VIN_18CLK
VIOIN_18DIFF
Reserved
D13
G13
VIN_13RF1
G5,J5,H5
1.3-V Analog and RF supply,VIN_13RF1 and
VIN_13RF2 could be shorted on the board
1.0-V Analog and RF supply input if RFLDO is
bypassed
VIN_13RF2
C2,D2
POW
—
VIN_18BB
K5,F5
B12
POW
POW
—
—
1.8-V Analog baseband power supply
1.8-V RF VCO supply
VIN_18VCO
E5,E6,E8,E
10,E11,F9,F
11,G6,G7,G
8,G10,H7,H
Power supply
VSS
9,H11,J6,J7 GND
,J8,J10,K7,
—
Digital ground
K8,K9,K10,
K11,L5,L6,L
8,L10,R15
A1,A3,A5,A
7,A9,A15,B
3,B5,B7,B9,
B13,B14,C1
,C3,C4,C5,
C6,C7,C8,C
9,C15,E1,E
2,E3,E13,E
VSSA
GND
—
Analog ground
15,F3,G1,G
2,G3,H3,J1,
J2,J3,K3,L1
,L2,L3,
M3,N1,N2,N
3,R1
VOUT_14APLL
VOUT_14SYNTH
VOUT_PA
A10
A13
O
O
O
O
—
—
—
—
1.4V internal regulator
1.4V internal regulator
1.0V internal regulator
Dithered clock input to PMIC
Internal LDO
output/inputs
A2,B2
P13
PMIC_CLK_OUT
External clock
out
Programmable clock given out to external MCU or
the processor
MCU_CLK_OUT
N9
O
—
14
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
FUNCTION
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 4-1. Signal Descriptions (continued)
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS(1)
SIGNAL NAME
DESCRIPTION
GPIO[0]
GPIO[1]
GPIO[2]
N4
N7
IO
IO
IO
Pull Down
Pull Down
Pull Down
General-purpose IO
General-purpose IO
General-purpose IO
General-
purpose I/Os
N13
Chip-select output from the device. Device is a
master connected to serial flash slave.
QSPI_CS
P8
O
O
Pull Up
Clock output from the device. Device is a master
connected to serial flash slave.
QSPI_CLK
R10
Pull Down
QSPI for Serial
Flash
QSPI[0]
QSPI[1]
QSPI[2]
QSPI[3]
RS232_TX
R11
P9
IO
IO
IO
IO
O
Pull Down
Pull Down
Pull Up
Data IN/OUT
Data IN/OUT
Data IN/OUT
Data IN/OUT
R12
P10
N6
Pull Up
Flash
Pull Down
programming
and RS232
UART
UART pins for programming external flash in
preproduction/debug hardware.
RS232_RX
N5
I
Pull Up
Analog Test1 /
GPADC1
P1
P2
P3
R2
IO
IO
IO
IO
—
—
—
—
GP ADC channel 1
GP ADC channel 2
GP ADC channel 3
GP ADC channel 4
Test and Debug
output for
preproduction
phase. Can be
pinned out on
production
Analog Test2 /
GPADC2
Analog Test3 /
GPADC3
Analog Test4 /
GPADC4
hardware for
field debug
ANAMUX / GPADC5
VSENSE / GPADC6
C13
C14
IO
IO
—
—
GP ADC channel 5
GP ADC channel 6
Copyright © 2017–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
15
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
4.3 Pin Multiplexing
Table 4-2. Pin Multiplexing
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
SIGNAL DESCRIPTION
General Purpose IO
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
REGISTER
PIN NAME
PIN
ADDRESS(1)
INTERNAL WEAK
PULL STATE
SIGNAL NAME
GPIO_12
SIGNAL TYPE
STATE
0
1
0
1
2
0
1
IO
O
Hi-Z
Hi-Z
Weak Pull Down
EA00h
GPIO_12
GPIO_0
P6
N4
SPI_HOST1_INTR
GPIO_13
General Purpose IO [IWR14xx]
General Purpose IO
IO
IO
O
Weak Pull Down
Weak Pull Down
EA04h
EA08h
GPIO_0
General Purpose IO
PMIC_CLKOUT
GPIO_16
Dithered Clock Output for PMIC
General Purpose IO
IO
IO
Hi-Z
GPIO_1
General Purpose IO
GPIO_1
N7
Low Frequency Synchronization
Signal output
2
SYNC_OUT
O
0
1
2
0
1
2
0
1
GPIO_19
MOSI_1
General Purpose IO
SPI Channel#1 Data Input
CAN Interface
IO
IO
I
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Weak Pull Up
Weak Pull Up
Weak Pull Up
Weak Pull Up
EA0Ch
EA10h
EA14h
EA18h
EA1Ch
EA20h
MOSI_1
MISO_1
R8
P5
R9
R7
R3
P4
CAN_RX
GPIO_20
MISO_1
General Purpose IO
SPI Channel#1 Data Output
CAN Interface
IO
IO
O
CAN_TX
GPIO_3
General Purpose IO
SPI Channel#1 Clock
IO
IO
O
SPI_CLK_1
SPI_CS_1
MOSI_2
SPI_CLK_1
RCOSC_CLK
GPIO_30
SPI_CS_1
RCOSC_CLK
GPIO_21
MOSI_2
0
1
General Purpose IO
IO
IO
O
SPI Channel#1 Chip Select
0
1
2
0
1
2
General Purpose IO
SPI Channel#2 Data Input
I2C Data
IO
IO
IO
IO
IO
IO
I2C_SDA
GPIO_22
MISO_2
General Purpose IO
SPI Channel#2 Data Output
I2C Clock
MISO_2
I2C_SCL
(1) Register addresses are of the form FFFF XXXXh, where XXXX is listed here.
16 Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 4-2. Pin Multiplexing (continued)
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
REGISTER
PIN NAME
PIN
ADDRESS(1)
INTERNAL WEAK
PULL STATE
SIGNAL NAME
GPIO_5
SIGNAL DESCRIPTION
General Purpose IO
SIGNAL TYPE
STATE
Hi-Z
0
1
IO
IO
IO
O
SPI_CLK_2
MSS_UARTA_RX
MSS_UARTB_TX
BSS_UART_TX
GPIO_4
SPI Channel#2 Clock
EA24h
EA28h
SPI_CLK_2
R5
6
7
0
1
Debug: Firmware Trace
Debug: Firmware Trace
General Purpose IO
O
IO
IO
IO
O
Hi-Z
SPI_CS_2
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
GPIO_8
SPI Channel#2 Chip Select
SPI_CS_2
R4
6
7
0
1
2
0
1
2
0
1
0
1
0
Debug: Firmware Trace
Debug: Firmware Trace
General Purpose IO
QSPI Data IN/OUT
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
Hi-Z
Hi-Z
Weak Pull Down
Weak Pull Down
EA2Ch
EA30h
QSPI[0]
QSPI[1]
R11
P9
QSPI[0]
MISO_2
SPI Channel#1 Data Output
General Purpose IO
QSPI Data IN/OUT
GPIO_9
QSPI[1]
MOSI_2
SPI Channel#2 Data Input
General Purpose IO
QSPI Data IN/OUT
GPIO_10
Hi-Z
Hi-Z
Hi-Z
Weak Pull Down
Weak Pull Down
Weak Pull Down
EA34h
EA38h
QSPI[2]
QSPI[3]
R12
P10
QSPI[2]
GPIO_11
General Purpose IO
QSPI Data IN/OUT
QSPI[3]
GPIO_7
General Purpose IO
IO
QSPI Clock output from the device.
Device operates as a master with
the serial flash being a slave
EA3Ch
EA40h
QSPI_CLK
QSPI_CS
R10
P8
1
QSPI_CLK
O
2
0
SPI_CLK_2
GPIO_6
SPI Channel#2 Clock
General Purpose IO
IO
IO
Hi-Z
Weak Pull Up
QSPI Chip Select output from the
device.
Device operates as a master with
the serial flash being a slave
1
2
QSPI_CS
SPI_CS_2
O
SPI Channel#2 Chip Select
IO
Copyright © 2017–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
17
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
Table 4-2. Pin Multiplexing (continued)
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
REGISTER
PIN NAME
PIN
ADDRESS(1)
INTERNAL WEAK
PULL STATE
SIGNAL NAME
SIGNAL DESCRIPTION
SIGNAL TYPE
STATE
Failsafe input to the device. Nerror
output from any other device can be
concentrated in the error signaling
monitor module inside the device
and appropriate action can be taken
by Firmware
NERROR_IN
P7
NERROR_IN
I
Hi-Z
Open drain fail safe warm reset
signal. Can be driven from PMIC for
diagnostic or can be used as status
signal that the device is going
through reset.
WARM_RESET
NERROR_OUT
N12
N8
WARM_RESET
NERROR_OUT
IO
O
Hi-Z Input
Open Drain
Open drain fail safe output signal.
Connected to PMIC/Processor/MCU
to indicate that some severe
criticality fault has happened.
Recovery would be through reset.
Hi-Z
Hi-Z
Open Drain
0
1
2
6
0
1
2
0
1
GPIO_17
General Purpose IO
JTAG Clock
IO
I
Weak Pull Down
TCK
EA50h
TCK
M13
MSS_UARTB_TX
BSS_UART_RX
GPIO_18
Debug: Firmware Trace
Debug: Firmware Trace
General Purpose IO
JTAG Test Mode Select
Debug: Firmware Trace
General Purpose IO
JTAG Test Data In
O
I
IO
IO
O
IO
I
Hi-Z
Hi-Z
Hi-Z
Weak Pull Up
Weak Pull Up
EA54h
EA58h
TMS
TDI
L13
H13
TMS
BSS_UART_TX
GPIO_23
TDI
MSS_UARTA_RX
GPIO_24
IO
IO
O
IO
O
O
0
1
General Purpose IO
JTAG Test Data Out
TDO
MSS_UARTA_TX
MSS_UARTB_TX
BSS_UART_TX
EA5Ch
TDO
J13
6
7
Debug: Firmware Trace
Debug: Firmware Trace
Sense On Power [Reset] Line
Impacts boot mode
SOP0
I
18
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 4-2. Pin Multiplexing (continued)
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
REGISTER
PIN NAME
PIN
ADDRESS(1)
INTERNAL WEAK
PULL STATE
SIGNAL NAME
GPIO_25
SIGNAL DESCRIPTION
General Purpose IO
SIGNAL TYPE
STATE
Hi-Z
0
1
IO
O
Weak Pull Down
Programmable clock given out to
external MCU or the processor
EA60h
EA64h
MCU_CLKOUT
N9
MCU_CLKOUT
10
0
BSS_UART_RX
GPIO_26
Debug: Firmware Trace
General Purpose IO
I
IO
IO
O
Hi-Z
Weak Pull Down
1
GPIO_2
General Purpose IO
7
MSS_UARTB_TX
BSS_UART_TX
Debug: Firmware Trace
Debug: Firmware Trace
GPIO_2
N13
8
O
Low frequency Synchronization
signal output
9
SYNC_OUT
O
10
0
PMIC_CLKOUT
GPIO_27
Dithered clock input to PMIC
General Purpose IO
O
IO
O
Hi-Z
Hi-Z
Hi-Z
Weak Pull Down
Weak Pull Down
Weak Pull Down
1
PMIC_CLKOUT
Dithered Clock Output for PMIC
EA68h
EA6Ch
PMIC_CLKOUT
SYNC_IN
P13
N10
Sense On Power [Reset] Line
Impacts boot mode
SOP2
I
IO
I
0
1
GPIO_28
SYNC_IN
General Purpose IO
Low frequency Synchronization
signal input
6
0
MSS_UARTB_RX
GPIO_29
Debug: Firmware Trace
General Purpose IO
I
IO
Low frequency Synchronization
signal output
1
SYNC_OUT
RCOSC_CLK
SOP1
O
O
I
EA70h
EA74h
SYNC_OUT
RS232_RX
P11
Sense On Power [Reset] Line
Impacts boot mode
0
1
GPIO_15
General Purpose IO
IO
IO
Hi-Z
Weak Pull Up
RS232_RX
Debug: Firmware load to RAM
FLASH Programming
Bootloader Controlled
N5
2
MSS_UARTA_RX
I
6
7
BSS_UART_TX
Debug: Firmware Trace
Debug: Firmware Trace
O
I
MSS_UARTB_RX
Copyright © 2017–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
19
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
Table 4-2. Pin Multiplexing (continued)
PAD STATE
nReset = 0 [ASSERTED]
FUNCTION
DIGITAL PIN
MUX CONFIG
VALUE [Bits3:0]
REGISTER
PIN NAME
PIN
ADDRESS(1)
INTERNAL WEAK
PULL STATE
SIGNAL NAME
GPIO_14
SIGNAL DESCRIPTION
General Purpose IO
SIGNAL TYPE
STATE
0
1
IO
IO
RS232_TX
Debug: Firmware load to RAM
FLASH Programming
Bootloader Controlled
EA78h
RS232_TX
N6
5
MSS_UARTA_TX
O
6
7
MSS_UARTB_TX
BSS_UART_TX
Debug: Firmware Trace
Debug: Firmware Trace
O
O
20
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
5 Specifications
5.1 Absolute Maximum Ratings(1)(2)
over operating Tj temperature range (unless otherwise noted)
PARAMETERS
MIN
–0.5
–0.5
–0.5
MAX
1.4
UNIT
VDDIN
1.2 V digital power supply
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
1.4
1.4
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
VIOIN
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for CSI2 port
–0.5
–0.5
–0.5
2
2
2
V
V
V
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
VIN_13RF1
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
–0.5
1.45
V
1-V Internal LDO bypass mode. Device supports mode where
external Power Management block can supply 1 V on
VIN_13RF1 and VIN_13RF2 rails. In this configuration, the
internal LDO of the device would be kept bypassed.
–0.5
1.4
V
VIN_13RF2
VIN_18BB
1.8-V Analog baseband power supply
1.8-V RF VCO supply
–0.5
–0.5
2
2
V
V
VIN_18VCO supply
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
–0.3V
VIOIN + 0.3
Input and output
voltage range
V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
VIOIN + 20% up to
20% of signal period
CLKP, CLKM
Clamp current
Input ports for reference crystal
–0.5
2
V
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
–55
105
150
ºC
ºC
TSTG
Storage temperature range after soldered onto PC board
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
5.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM)
V(ESD)
Electrostatic discharge
All other pins
Corner pins
V
Charged-device model (CDM)
±750
5.3 Power-On Hours (POH)(1)
JUNCTION
TEMPERATURE (Tj)
OPERATING
CONDITION
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)
90% at 85ºC Tj
10% at 105ºC Tj
80,000
50% duty cycle
1.2
100% at 85ºC Tj
100,000
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
21
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.4 Recommended Operating Conditions
Tjunction temperature range (unless otherwise noted)
MIN
1.14
1.14
1.14
3.15
1.71
1.71
1.71
1.71
NOM
1.2
1.2
1.2
3.3
1.8
1.8
1.8
1.8
MAX
UNIT
VDDIN
1.2 V digital power supply
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
I/O supply (3.3 V)
1.32
1.32
1.32
3.45
1.89
1.9
V
V
V
VIN_SRAM
VNWA
VIOIN
V
I/O supply (1.8 V)
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for CSI2 port
V
V
V
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
1.9
1.9
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
1.23
1.3
1.36
V
VIN_13RF1
(1-V Internal LDO
bypass mode)
Device supports mode where external Power Management
block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In
this configuration, the internal LDO of the device would be
kept bypassed.
0.95
1
1.05
V
VIN_13RF2
(1-V Internal LDO
bypass mode)
VIN18BB
1.8-V Analog baseband power supply
1.8V RF VCO supply
1.71
1.71
1.17
2.25
1.8
1.8
1.9
1.9
V
V
VIN_18VCO
Voltage Input High (1.8 V mode)
Voltage Input High (3.3 V mode)
Voltage Input Low (1.8 V mode)
Voltage Input Low (3.3 V mode)
High-level output threshold (IOH = 6 mA) (1.8V)
VIH
VIL
V
V
0.3*VIOIN
0.62
85%*VIOIN
VOH
VOL
mV
mV
VIOIN –
450mV
High-level output threshold (IOH = 6 mA) (3.3V)
Low-level output threshold (IOL = 6 mA)
VIL (1.8V Mode)
450
0.2
VIH (1.8V Mode)
0.96
1.57
NRESET
SOP[2:0]
V
VIL (3.3V Mode)
0.3
VIH (3.3V Mode)
5.5 Power Supply Specifications
Table 5-1 describes the four rails from an external power supply block of the IWR1443 device.
Table 5-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, LVDS
1.8 V
1.3 V (or 1 V in internal
LDO bypass mode)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM, VNWA
22
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
The 1.3V (1.0V) and 1.8V power supply ripple specifications mentioned in Table 5-2 are defined to meet a
target spur level of –105dBc (RF Pin = –15dBm) at the RX. The spur and ripple levels have a dB to dB
relationship, for example, a 1dB increase in supply ripple leads to a ~1dB increase in spur level. Values
quoted are rms levels for a sinusoidal input applied at the specified frequency.
Table 5-2. Ripple Specifications
RF RAIL
1.0 V (INTERNAL LDO BYPASS)
VCO/IF RAIL
FREQUENCY (kHz)
1.3 V (µVRMS
)
1.8 V (µVRMS)
(µVRMS
)
137.5
275
744
4
648
76
22
4
83
21
11
6
550
3
1100
2200
4400
6600
2
11
13
22
82
93
117
13
19
29
5.6 Power Consumption Summary
Table 5-3 and Table 5-4 summarize the power consumption at the power terminals.
Table 5-3. Maximum Current Ratings at Power Terminals
PARAMETER
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Total current drawn by
all nodes driven by
1.2V rail
VDDIN, VIN_SRAM, VNWA
500
Total current drawn by
all nodes driven by
1.3V rail
VIN_13RF1, VIN_13RF2
2000
850
50
Current consumption
mA
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by
all nodes driven by
1.8V rail
Total current drawn by
all nodes driven by
3.3V rail
VIOIN
Table 5-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION
DESCRIPTION
MIN
TYP
MAX UNIT
1.0-V internal
LDO bypass
mode
1TX, 4RX
2TX, 4RX
1TX, 4RX
2TX, 4RX
1.73
Sampling: 16.66 MSps complex
Transceiver, 40-ms frame time, 512
chirps, 512 samples/chirp, 8.5-μs
interchirp time (50% duty cycle)
Data Port: MIPI-CSI-2
1.88
1.92
2.1
Average power
consumption
W
1.3-V internal
LDO enabled
mode
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
23
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.7 RF Specification
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
14
15
–8
48
24
2
MAX UNIT
76 to 77 GHz
Noise figure
dB
77 to 81 GHz
1-dB compression point(1)
Maximum gain
dBm
dB
Gain range
dB
Gain step size
dB
Image Rejection Ratio (IMRR)
IF bandwidth(2)
30
dB
15
MHz
A2D sampling rate (real)
A2D sampling rate (complex)
A2D resolution
37.5 Msps
18.75 Msps
Receiver
12
–10
±0.5
±3
Bits
dB
dB
°
Return loss (S11)
Gain mismatch variation (over temperature)
Phase mismatch variation (over temperature)
RX gain = 30dB
IF = 1.5, 2 MHz at
–12 dBFS
In-band IIP2
16
24
dBm
dBm
RX gain = 24dB
IF = 10 kHz at -10dBm,
1.9 MHz at -30 dBm
Out-of-band IIP2
Idle Channel Spurs
Output power
–90
12
dBFS
dBm
Transmitter
Amplitude noise
Frequency range
Ramp rate
–145
dBc/Hz
76
81
GHz
100 MHz/µs
Clock
subsystem
76 to 77 GHz
77 to 81 GHz
–95
–93
Phase noise at 1-MHz offset
dBc/Hz
(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone below the lowest HPF cut-off frequency (50 kHz).
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of
available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1
HPF2
175, 235, 350, 700
350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
•
•
Less than ±0.5 dB pass-band ripple/droop, and
Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
24
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Figure 5-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain
programmed.
15.6
15.3
15
-20
-24
-28
-32
-36
-40
-44
-48
NF (db)
IB P1db (dBm)
14.7
14.4
14.1
13.8
13.5
24 26 28 30 32 34 36 38 40 42 44 46 48
RX Gain (dB)
Figure 5-1. Noise Figure, In-band P1dB vs Receiver Gain
5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161](1)
THERMAL METRICS(2)
°C/W(3) (4)
4.92
RΘJC
RΘJB
RΘJA
RΘJMA
PsiJT
PsiJB
Junction-to-case
Junction-to-board
6.57
Junction-to-free air
Junction-to-moving air
Junction-to-package top
Junction-to-board
22.3
N/A(1)
4.92
6.4
(1) N/A = not applicable
(2) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(3) °C/W = degrees Celsius per watt.
(4) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
A junction temperature of 105ºC is assumed.
5.9 Timing and Switching Characteristics
5.9.1 Power Supply Sequencing and Reset Timing
The IWR1443 device expects all external voltage rails to be stable before reset is deasserted. Figure 5-2
describes the device wake-up sequence.
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
25
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
SOP
Setup
Time
SOP
Hold time to
nRESET
DC power
Stable before
nRESET
MSS
BOOT
START
nRESET
ASSERT
tPGDEL
DC
Power
notOK
DC
Power
OK
QSPI
READ
release
VDDIN,
VIN_SRAM
VNWA
VIOIN_18
VIN18_CLK
VIOIN_18DIFF
VIN18_BB
VIN_13RF1
VIN_13RF2
VIOIN
SOP[2.1.0]
nRESET
Warm reset
delay for crystal
or ext osc
WARMRESET
OUTPUT
VBGAP
OUTPUT
CLKP, CLKM
Using Crystal
MCUCLK
OUTPUT (1)
QSPI_CS
OUTPUT
7ms (XTAL Mode)
500 µs (REFCLK Mode)
(1) MCU_CLK_OUT in autonomous mode, where IWR1443 application is booted from the serial flash, MCU_CLK_OUT is not enabled
by default by the device bootloader.
Figure 5-2. Device Wake-up Sequence
5.9.2 Synchronized Frame Triggering
The IWR1443 device supports a hardware based mechanism to trigger radar frames. An external host can
pulse the SYNC_IN signal to start radar frames. The typical time difference between the rising edge of the
external pulse and the frame transmission on air (Tlag) is about 160 ns. There is also an additional
programmable delay that the user can set to control the frame start time.
26
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Tactive_frame
SYNC_IN
(Hardware
Trigger)
Radar
Frames
Tpulse
Tlag
Frame-2
Frame-1
Figure 5-3. Sync In Hardware Trigger
Table 5-5. Frame Trigger Timing
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
Tactive_frame
Tpulse
Active frame duration
User defined
25
ns
< Tactive_frame
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
27
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.9.3 Input Clocks and Oscillators
5.9.3.1 Clock Specifications
An external crystal is connected to the device pins. Figure 5-4 shows the crystal implementation.
Cf1
XTALP
Cp
40 and 50 MHz
XTALM
Cf2
Figure 5-4. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-4, should be chosen such that Equation 1 is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to
the associated oscillator CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic
capacitances due to PCB routing.
C f2
CL = C f1
´
+CP
C
f1 +C f2
Table 5-6 lists the electrical characteristics of the clock crystal.
Table 5-6. Crystal Electrical Characteristics (Oscillator Mode)
(1)
NAME
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
40
MAX
UNIT
MHz
pF
fP
CL
Crystal load capacitance
Crystal ESR
5
8
12
50
ESR
Ω
Temperature range Expected temperature range of operation
–40
–50
105
ºC
Frequency
tolerance
Crystal frequency tolerance(1)(2)(3)
50
ppm
µW
Drive level
50
200
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
(3) Crystal tolerance affects radar sensor accuracy.
28
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only;
CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally.
Table 5-7 lists the electrical characteristics of the external clock signal.
Table 5-7. External Clock Mode Specifications
SPECIFICATION
PARAMETER
Frequency
UNIT
MIN
TYP
MAX
40
MHz
mV (pp)
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
%
AC-Amplitude
700
1200
–132
–143
–152
–153
65
Phase Noise at 1 kHz
Phase Noise at 10 kHz
Phase Noise at 100 kHz
Phase Noise at 1 MHz
Duty Cycle
Input Clock:
External AC-coupled sine wave or DC-
coupled square wave
Phase Noise referred to 40 MHz
35
Freq Tolerance
–50
50
ppm
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
29
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
5.9.4.1 Peripheral Description
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals
or another microcontroller.
Standard and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
8-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source
(slave mode)
•
•
Each word transferred can have a unique format.
SPI I/Os not used in the communication can be used as digital input/output signals
5.9.4.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
Table 5-9 to assume the operating conditions stated in Table 5-8.
Table 5-8. SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
2
15
pF
30
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 5-9. SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
MIN
25
TYP
MAX
256tc(VCLK)
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M – 10.5
0.5tc(SPC)M – 10.5
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
2(4)
3(4)
4(4)
5(4)
ns
ns
ns
ns
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 0
Setup time CS active until SPICLK high
(clock polarity = 0)
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
CSHOLD = 1
6(5)
tC2TDELAY
ns
ns
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 0
Setup time CS active until SPICLK low
(clock polarity = 1)
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
CSHOLD = 1
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
(T2CDELAY + 1)
*tc(VCLK) – 7
7(5)
tT2CDELAY
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
(T2CDELAY + 1)
*tc(VCLK) – 7
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
5
5
3
3
8(4)
ns
ns
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
9(4)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
(2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
31
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
11
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1
4
5
Master Out Data Is Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-5. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 5-6. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
32
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 5-10. SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
MIN
25
TYP
MAX
256tc(VCLK)
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 4
0.5tc(SPC)M – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M – 10.5
0.5tc(SPC)M – 10.5
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
0.5tc(SPC)M + 4
2(4)
3(4)
4(4)
5(4)
ns
ns
ns
ns
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
CSHOLD = 0
(C2TDELAY +
2)*tc(VCLK) – 7
(C2TDELAY+2) *
tc(VCLK) + 7.5
Setup time CS active until SPICLK high
(clock polarity = 0)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
CSHOLD = 1
CSHOLD = 0
(C2TDELAY +
2)*tc(VCLK) – 7
(C2TDELAY+2) *
tc(VCLK) + 7.5
6(5)
tC2TDELAY
ns
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
(C2TDELAY+2)*tc(
VCLK) – 7
Setup time CS active until SPICLK low
(clock polarity = 1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
CSHOLD = 1
(C2TDELAY+3)*tc(
VCLK) – 7
(C2TDELAY+3) *
tc(VCLK) + 7.5
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
Hold time, SPICLK low until CS inactive (clock polarity = 0)
Hold time, SPICLK high until CS inactive (clock polarity = 1)
7(5)
8(4)
9(4)
tT2CDELAY
ns
ns
ns
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
5
5
3
3
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
(2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
33
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-7. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
6
7
Figure 5-8. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
34
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
5.9.4.3 SPI Slave Mode I/O Timings
Table 5-11. SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)(1)(2)(3)
NO.
PARAMETER
Cycle time, SPICLK(4)
MIN
25
TYP
MAX
UNIT
1
tc(SPC)S
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
10
2(5)
3(5)
ns
ns
10
10
10
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
td(SPCH-SOMI)S
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
10
10
4(5)
ns
ns
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
2
2
5(5)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Setup time, SPISIMO before SPICLK low (clock
polarity = 0; clock phase = 0) OR (clock polarity = 1;
clock phase = 1)
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
th(SPCL-SIMO)S
th(SPCL-SIMO)S
3
3
1
1
6(5)
ns
ns
Setup time, SPISIMO before SPICLK high (clock
polarity = 1; clock phase = 0) OR (clock polarity = 0;
clock phase = 1)
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
7(5)
Hold time, SPISIMO data valid after SPICLK high
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).
(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.
(3) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where
PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
35
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-9. SPI Slave Mode External Timing (CLOCK PHASE = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-10. SPI Slave Mode External Timing (CLOCK PHASE = 1)
36
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
5.9.4.4 Typical Interface Protocol Diagram (Slave Mode)
1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI
clock.
2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
Figure 5-11 shows the SPI communication timing of the typical interface protocol.
2 SPI clocks
CS
CLK
0x4321
0x1234
CRC
0x5678
0x8765
MOSI
MISO
IRQ
0xDCBA
0xABCD
CRC
16 bytes
Figure 5-11. SPI Communication
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
37
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.9.5 LVDS Interface Configuration
The IWR1443 supports seven differential LVDS IOs/Lanes. The lane configuration supported is four Data
lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane
(LVDS_FRCLKP/M), and one HS_DEBUG LVDS pair. The LVDS interface is used for debugging. The
LVDS interface supports the following data rates:
•
•
•
•
•
•
•
900 Mbps (450 MHz DDR Clock)
600 Mbps (300 MHz DDR Clock)
450 Mbps (225 MHz DDR Clock)
400 Mbps (200 MHz DDR Clock)
300 Mbps (150 MHz DDR Clock)
225 Mbps (112.5 MHz DDR Clock)
150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to
data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Figure 5-12. LVDS Interface Lane Configuration And Relative Timings
5.9.5.1 LVDS Interface Timings
Trise
LVDS_CLK
Clock Jitter = 6sigma
LVDS_TXP/M
LVDS_FRCLKP/M
1100 ps
Figure 5-13. Timing Parameters
38
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 5-12. LVDS Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
max 1 pF lumped capacitive load on
LVDS lanes
48%
52%
Duty Cycle Requirements
Output Differential Voltage
peak-to-peak single-ended with 100 Ω
resistive load between differential pairs
250
450
mV
Output Offset Voltage
Trise and Tfall
1125
1275
mV
ps
20%-80%, 900 Mbps
900 Mbps
500
80
Jitter (pk-pk)
ps
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
39
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.9.6 General-Purpose Input/Output
Table 5-13 lists the switching characteristics of output timing relative to load capacitance.
Table 5-13. Switching Characteristics for Output Timing versus Load Capacitance (CL)(1)(2)
PARAMETER
TEST CONDITIONS
CL = 20 pF
VIOIN = 1.8V
VIOIN = 3.3V
UNIT
2.8
6.4
9.4
2.8
6.4
9.4
3.3
6.7
9.6
3.1
6.6
9.6
3.0
6.9
tr
tf
tr
tf
Max rise time
CL = 50 pF
ns
CL = 75 pF
10.2
2.8
Slew control = 0
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
Max fall time
Max rise time
Max fall time
6.6
ns
ns
ns
9.8
3.3
7.2
10.5
3.1
Slew control = 1
6.6
9.6
(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).
(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
40
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
5.9.7 Controller Area Network Interface (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
Mbps. The DCAN is ideal for applications operating in noisy and harsh environments that require reliable
serial communication or multiplexed wiring.
The DCAN has the following features:
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 Mbps
Configurable Message objects
Individual identifier masks for each message object
Programmable FIFO mode for message objects
Suspend mode for debug support
Programmable loop-back modes for self-test operation
Direct access to Message RAM in test mode
Supports two interrupt lines - Level 0 and Level 1
Automatic Message RAM initialization
Table 5-14. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
15
UNIT
ns
td(CAN_tx)
td(CAN_rx)
Delay time, transmit shift register to CAN_tx pin(1)
Delay time, CAN_rx pin to receive shift register(1)
10
ns
(1) These values do not include rise/fall times of the output buffer.
describes the CSI-2 DPHY electrical specifications.
5.9.8 Serial Communication Interface (SCI)
The SCI has the following features:
•
•
•
•
•
•
Standard universal asynchronous receiver-transmitter (UART) communication
Standard non-return to zero (NRZ) format
Double-buffered receive and transmit functions
Asynchronous or iso-synchronous communication modes with no CLK pin
Capability to use Direct Memory Access (DMA) for transmit and receive data
Two external pins: RS232_RX and RS232_TX
Table 5-15. SCI Timing Requirements
MIN
TYP
921.6
MAX
UNIT
kHz
f(baud)
Supported baud rate at 20 pF
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
41
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.9.9 Inter-Integrated Circuit Interface (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface
between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by
an I2C-bus™. This module will support any slave or master I2C compatible device.
The I2C has the following features:
•
Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
–
–
–
–
–
–
–
–
Bit/Byte format transfer
7-bit and 10-bit device addressing modes
General call
START byte
Multi-master transmitter/ slave receiver mode
Multi-master receiver/ slave transmitter mode
Combined master transmit/receive and receive/transmit mode
Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
•
•
•
•
•
•
•
•
•
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
NOTE
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the slave address second
byte every time it sends the slave address first byte)
42
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 5-16. I2C Timing Requirements(1)
STANDARD MODE
FAST MODE
UNIT
MIN
MAX
MIN
MAX
tc(SCL)
Cycle time, SCL
10
2.5
μs
μs
Setup time, SCL high before SDA low
(for a repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low
(for a START and a repeated START condition)
th(SCLL-SDAL)
μs
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
μs
μs
μs
μs
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
th(SCLL-SDA)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
3.45(1)
0.9
Pulse duration, SDA high between STOP and START
conditions
tw(SDAH)
4.7
4
1.3
μs
μs
Setup time, SCL high before SDA high
(for STOP condition)
tsu(SCLH-SDAH)
tw(SP)
0.6
0
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(2)(3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 5-14. I2C Timing Diagram
NOTE
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a
Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tsu(SDA-SCLH)
.
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
43
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.9.10 Quad Serial Peripheral Interface (QSPI)
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or
quad read access to external SPI devices. This module has a memory mapped register interface, which
provides a direct interface for accessing data from external SPI devices and thus simplifying software
requirements. The QSPI works as a master only. The QSPI in the device is primarily intended for fast
booting from quad-SPI flash memories.
The QSPI supports the following features:
•
•
•
•
•
•
•
Programmable clock divider
Six-pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Table 5-18 and Table 5-19 assume the operating conditions stated in Table 5-17.
Table 5-17. QSPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
15
pF
Table 5-18. Timing Requirements for QSPI Input (Read) Timings(1)(2)
MIN
7.3
TYP
MAX
UNIT
ns
tsu(D-SCLK)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling sclk edge
1.5
ns
Setup time, final d[3:0] bit valid before final falling sclk edge
Hold time, final d[3:0] bit valid after final falling sclk edge
7.3 – P(3)
1.5 + P(3)
ns
ns
(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.
(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-
standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Mode 0.
(3) P = SCLK period in ns.
44
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 5-19. QSPI Switching Characteristics
NO.
PARAMETER
Cycle time, sclk
MIN
TYP
MAX
UNIT
ns
Q1
Q2
Q3
tc(SCLK)
tw(SCLKL)
tw(SCLKH)
25
Pulse duration, sclk low
Pulse duration, sclk high
Y*P – 3(1)(2)
Y*P – 3(1)
ns
ns
–M*P +
2.5(1)(3)
Q4
Q5
td(CS-SCLK)
td(SCLK-CS)
Delay time, sclk falling edge to cs active edge
Delay time, sclk falling edge to cs inactive edge
–M*P – 1(1)(3)
N*P – 1(1)(3)
ns
ns
N*P +
2.5(1)(3)
Q6
Q7
Q8
td(SCLK-D1)
tena(CS-D1LZ)
tdis(CS-D1Z)
Delay time, sclk falling edge to d[1] transition
Enable time, cs active edge to d[1] driven (lo-z)
Disable time, cs active edge to d[1] tri-stated (hi-z)
–3.5
–P – 4(3)
–P – 4(3)
7
–P +1(3)
–P +1(3)
ns
ns
ns
Delay time, sclk first falling edge to first d[1] transition
(for PHA = 0 only)
Q9
td(SCLK-D1)
–3.5 – P(3)
7 – P(3)
ns
Q12
Q13
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling sclk edge
7.3
1.5
ns
ns
Setup time, final d[3:0] bit valid before final falling sclk
edge
Q14
Q15
tsu(D-SCLK)
th(SCLK-D)
7.3 — P(3)
1.5 + P(3)
ns
ns
Hold time, final d[3:0] bit valid after final falling sclk
edge
(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle
distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period in ns.
(3) M = QSPI_SPI_DC_REG.DDx + 1, N = 2
PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q12
Q13
Q12 Q13
Read Data
Bit 0
Q6
Q7
Q9
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 1
d[0]
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_02
Figure 5-15. QSPI Read (Clock Mode 0)
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
45
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
PHA=0
cs
Q5
Q4
Q1
Q2
Q3
POL=0
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 5-16. QSPI Write (Clock Mode 0)
46
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
5.9.11 JTAG Interface
Table 5-21 and Table 5-22 assume the operating conditions stated in Table 5-20.
Table 5-20. JTAG Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
2
15
pF
Table 5-21. Timing Requirements for IEEE 1149.1 JTAG
NO.
MIN
TYP
MAX
UNIT
ns
1
tc(TCK)
Cycle time TCK
66.66
26.67
26.67
2.5
1a
1b
tw(TCKH)
Pulse duration TCK high (40% of tc)
Pulse duration TCK low(40% of tc)
Input setup time TDI valid to TCK high
Input setup time TMS valid to TCK high
Input hold time TDI valid from TCK high
Input hold time TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
2.5
ns
18
ns
18
ns
Table 5-22. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
MIN
TYP
MAX
UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
25
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS91v_JTAG_01
Figure 5-17. JTAG Timing
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
47
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
5.9.12 Camera Serial Interface (CSI)
The CSI is a MIPI D-PHY compliant interface for connecting this device to a camera receiver module. This
interface is made of four differential lanes; each lane is configurable for carrying data or clock. The polarity
of each wire of a lane is also configurable. Table 5-23, Figure 5-18, Figure 5-19, and Figure 5-20 describe
the clock and data timing of the CSI.
Table 5-23. CSI Switching Characteristics
over operating Tj temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
HPTX
(1 or 2 data lane PHY)
(4 data lane PHY)
150
150
75
600
600
450
300
HSTXDBR
Data bit rate
Mbps
MHz
(1 or 2 data lane PHY)
(4 data lane PHY)
fCLK
DDR clock frequency
75
Common-level variation from 75 to 450 MHz of CSI2 clock
frequency
ΔVCMTX(LF)
tR and tF
–50
150
50 mVpeak
ns
20% to 80% rise time and fall time
0.3
UI
LPTX DRIVER
tRLP and tFLP
15% to 85% rise time and fall time
25
ns
ns
105 +
12*UI
(1)
tEOT
Time from start of THS-TRAIL period to start of LP-11 state
Slew rate. CLOAD = 0 to 5 pF
Slew rate. CLOAD = 5 to 20 pF
Slew rate. CLOAD = 20 to 70 pF
Load capacitance
500
(2)(3)(4)
δV/δtSR
200 mV/ns
100
(2)
CLOAD
0
70
pF
DATA-CLOCK Timing Specification
Nominal Unit Interval (1, 2, or 3 data lane PHY)
1.11
1.67
13.33
13.33
UINOM
ns
Nominal Unit Interval (4 data lane PHY)
0.975*U
Minimum instantaneous Unit Interval (1, 2, or 3 data lane PHY)
1.033 INOM –
0.05
UIINST,MIN
TSKEW[TX]
ns
Minimum instantaneous Unit Interval (4 data lane PHY)
Data to clock skew measured at transmitter
1.131
UIINST,
MIN
–0.15
0.15
60
CSI2 TIMING SPECIFICATION
Time-out for receiver to detect absence of clock transitions and
TCLK-MISS
ns
ns
disable the clock lane HS-RX.
Time that the transmitter continues to send HS clock after the
last associated data lane has transitioned to lp mode. Interval is
defined as the period from the end of THS-TRAIL to the beginning
60 ns +
52*UI
TCLK-POST
of TCLK-TRAIL
.
Time that the HS clock shall be driven by the transmitter before
any associated data lane beginning the transition from LP to HS
mode.
TCLK-PRE
8
ns
ns
ns
Time that the transmitter drives the clock lane LP-00 line state
immediately before the HS-0 line state starting the HS
transmission.
TCLK-PREPARE
38
95
38
Time for the clock lane receiver to enable the HS line
termination, starting from the time point when Dn crosses
VIL,MAX.
Time for Dn
to reach
VTERM-EN
TCLK-TERM-EN
(1) With an additional load capacitance CCM of 0 to 60 pF on the termination center tap at RX side of the lane
(2) While driving CLOAD. Load capacitance includes 50 pF of transmission line capacitance, and 10 pF each for TX and RX.
(3) When the output voltage is from 15% to 85% of the fully settled LP signal levels
(4) Measured as average across any 50 mV segment of the output signal transition
48
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 5-23. CSI Switching Characteristics (continued)
over operating Tj temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Time that the transmitter drives the HS-0 state after the last
payload clock bit of a HS transmission burst.
TCLK-TRAIL
60
ns
TCLK-PREPARE + time that the transmitter drives the HS-0 state
before starting the clock.
TCLK-PREPARE + TCLK-ZERO
300
ns
ns
Time for the data lane receiver to enable the HS line
termination, starting from the time point when Dn crosses
VIL,MAX.
Time for Dn
to reach
VTERM-EN
35 ns +
4*UI
TD-TERM-EN
105 ns
+
n*12*UI
Transmitted time interval from the start of THS-TRAIL or TCLKTRAIL
to the start of the LP-11 state following a HS burst.
,
TEOT
ns
Time that the transmitter drives the data lane LP-00 line state
immediately before the HS-0 line state starting the HS
transmission
85 +
6*UI
THS-PREPARE
40 + 4*UI
ns
ns
THS-PREPARE + time that the transmitter drives the HS-0 state
prior to transmitting the Sync sequence.
145 ns +
10*UI
THS-PREPARE + THS-ZERO
Time interval during which the HS-RX should ignore any
transitions on the data lane, following a HS burst. The end point
of the interval is defined as the beginning of the LP-11 state
following the HS burst.
55 ns +
4*UI
THS-SKIP
40
ns
THS-EXIT
THS-TRAIL
TLPX
Time that the transmitter drives LP-11 following a HS burst.
100
ns
ns
ns
max(n*8*UI,
60 ns +
Time that the transmitter drives the flipped differential state after
last payload data bit of a HS transmission burst
n*4*UI)(5)(6)
Transmitted length of any low-power state period
50(7)
(5) If a > b then max(a, b) = a, otherwise max(a, b) = b.
(6) Where n = 1 for Forward-direction HS mode and n = 4 for Reverse-direction HS mode
(7) TLPX is an internal state machine timing reference. Externally measured values may differ slightly from the specified values due to
asymmetrical rise and fall times.
CSI2_CLK(P/M)
0.5UI + Tskew
CSI2_TX(P/M)
1 UI
Figure 5-18. Clock and Data Timing in HS Transmission
Copyright © 2017–2018, Texas Instruments Incorporated
Specifications
49
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
Clock
Lane
Data Lane
Dp/Dn
TLPX
THS-ZERO
THS-SYNC
Disconnect
Terminator
VOH
THS-PREPARE
VIH(min)
VIL(max)
VOL
TREOT
Capture
TD-TERM-EN
1st Data Bit
THS-SKIP
TEOT
THS-TRAIL
LP-11
LP-11
LP-01
LP-00
THS-SETTLE
THS-EXIT
LOW-POWER TO
HIGH-SPEED
TRANSITION
START OF
HS-ZERO TRANSMISSION
SEQUENCE
HIGH-SPEED TO
HS-TRAIL LOW-POWER
TRANSITION
HIGH-SPEED DATA
TRANSMISSION
Figure 5-19. High-Speed Data Transmission Burst
Disconnect
Terminator
Clock Lane
Dp/Dn
T
CLK-SETTLE
VIH(min)
VIL(max)
T
LPX
T
T
CLK-PRE
CLK-ZERO
T
CLK-PREPARE
Data Lane
Dp/Dn
T
HS-PREPARE
Disconnect
Terminator
T
LPX
VIH(min)
VIL(max)
T
HS-SKIP
T
HS-SETTLE
(1) The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.
Figure 5-20. Switching the Clock Lane Between Clock Transmission and Low-Power Mode
50
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
6 Detailed Description
6.1 Overview
The IWR1443 device includes the entire Millimeter Wave blocks and analog baseband signal chain for
three transmitters (two usable at the same instance) and four receivers, as well as a customer-
programmable MCU with a hardware accelerator for radar signal processing. This device is applicable as
a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity and application
code size. These could be cost-sensitive industrial radar sensing applications. Examples are:
•
•
•
•
Industrial level sensing
Industrial automation sensor fusion with radar
traffic intersection monitoring with radar
Industrial radar-proximity monitoring.
In terms of scalability, the IWR1443 device could be paired with a low-end external MCU, to address more
complex applications that might require additional memory for larger application software footprint and
faster interfaces. Because the IWR1443 device also provides high speed data interfaces like MIPI-CSI2, it
is suitable for interfacing with more capable external processing blocks. Here system designers can
choose the IWR1443 to provide raw ADC data or use the on-chip Hardware Accelerator for partial
processing viz. first stage Fast Fourier Transform.
6.2 Functional Block Diagram
Rx1
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Cortex R4F
@ 200MHz
Rx2
Rx3
Digital Front-
end
(User programmable)
(Decimation
filter chain)
Prog
RAM
Data
RAM (*) ROM
Boot
Rx4
QSPI Flash
interface
QSPI
SPI
Hardware
Accelerator
(**)
ADC Buffer
(**)
External MCU
interface
Tx1
Tx2
PA
PA
PA
BPM
BPM
BPM
RF/Analog sub-system
DMA
SPI / I2C
DCAN
PMIC control
Optional communicatio
interface
Master sub-system
(Customer programmed)
Ramp
Generator
Control UART,
And Debug UART
Debug
UARTs
Synth
Tx3
x4
(20 GHz)
Radar Data
Memory (*)
(L3)
Test/
Debug
JTAG for debug/
development
Temp
6
RF Control
BIST
Mailbox
GPADC
High-speed Rx or
process
Data for recording or
External DSP
LVDS/
CSI-2
Osc.
(*) Total RAM available in Master subsystem is divided into ARM-Data RAM, Tightly Coupled Memory, Radar Data Memory, Patch Memory
(**) Shared Memory for ADC Buffer and Hardware Accelerator
Copyright © 2017–2018, Texas Instruments Incorporated
Detailed Description
51
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
6.3 External Interfaces
The IWR1443 device provides the following external interfaces:
•
•
Reference Clock – Reference clock available for Host Processor after device wakeup.
Low speed control information
–
–
Up to two 4-line standard SPI interface
One I2C interface (Pin multiplexed with one of the SPI ports)
•
•
One Controller Area Network (CAN) Port for Industrial Interfacing
Data – High-Speed serial port following the MIPI CSI2 format. 4 data and 1 clock lane (all differential).
Data from different receive channels can be multiplexed on a single data lane in order to optimize
board routing. This is a unidirectional interface used for data transfer only.
•
•
Reset – Active Low reset for device wakeup from host General Purpose IOs
Error Signaling – Used for notifying the host in case the Radio Controller detects a fault
The IWR1443 device comprises of three main blocks – Radar (or the Millimeter Wave) System, Master (or
the Control) System and Processing System.
RADAR System
Radar Processing Inter-connect [128 Bit @ 200MHz]
RF/Analog/Monitoring
LVDS/
ADC
BUFFERS
FFT
ACCELERATOR
L3
EDMA
Mipi-CSI-2
RAM
MAILBOX
(384KB)
2x16KB
Master (Control) System Inter-connect [64 Bit @ 200MHz]
CRC
ROM
DMA
JTAG
Integrated MCU
®
Program
RAM
®
ARM Cortex R4F
Data
RAM
Peripheral Inter-connect
SPI
SPI
Timer
UART
QSPI
CAN
I2C
PWM
Figure 6-1. System Interconnect
6.4 Subsystems
6.4.1 RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA,
mixer, IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The
three transmit channels can be operated up to a maximum of two at a time (simultaneously) for transmit
beamforming purpose as required; whereas the four receive channels can all be operated simultaneously.
52
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
6.4.1.1 Clock Subsystem
The IWR1443 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal or
external clock. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit.
The output of the RF synthesizer is then processed by an X4 multiplier to create the required frequency in
the 76 to 81 GHz spectrum. The RF synthesizer output is modulated by the timing engine block to create
the required waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring
the quality of the generated clock.
Figure 6-2 describes the clock subsystem.
Self Test
RF SYNTH
Timing
SYNC_OUT
Engine
Lock Detect
SoC Clock
Clean-
Up PLL
x4
MULT
XO/
Slicer
CLK Detect
40 MHz
Figure 6-2. Clock Subsystem
Copyright © 2017–2018, Texas Instruments Incorporated
Detailed Description
53
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
6.4.1.2 Transmit Subsystem
The IWR1443 transmit subsystem consists of three parallel transmit chains, each with independent phase
and amplitude control. A maximum of 2 transmit chains can be operational at the same time. However all
3 chains can be operated together in a time multiplexed fashion.The device supports binary phase
modulation for MIMO radar and interference mitigation.
Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit
chains also support programmable backoff for system optimization.
Figure 6-3 describes the transmit subsystem.
Self Test
Loopback
Path
PCB
GSG
at 50 W
DF
LO
0 or 180°
(from Timing
Engine)
Figure 6-3. Transmit Subsystem (Per Channel)
6.4.1.3 Receive Subsystem
The IWR1443 receive subsystem consists of four parallel channels. A single receive channel consists of
an LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational
at the same time an individual power-down option is also available for system optimization.
Unlike conventional real-only receivers, the IWR1443 device supports a complex baseband architecture,
which uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each
receiver channel. The IWR1443 is targeted for fast chirp systems. The band-pass IF chain has
configurable lower cutoff frequencies above 175 kHz and can support bandwidths up to 15 MHz.
Figure 6-4 describes the receive subsystem.
Self Test
DAC
Loopback
Path
DSM
PCB
I
RSSI
50 W
GSG
LO
Q
DSM
DAC
Figure 6-4. Receive Subsystem (Per Channel)
54
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
6.4.1.4 Radio Processor Subsystem
The Radio Processor subsystem (also referred to as BIST Subsystem in this document) includes the
digital front-end, the ramp generator and an internal processor for control / configuration of the low-level
RF/analog and ramp generator registers. The Radar Processor also schedules periodic monitoring tasks.
User applications, running on
Master (Control) System, do not have direct access to Radar System; access is based on well-defined API
messages (over a hardware channel) from the master subsystem.
NOTE
This radio processor is programmed by TI and takes care of RF calibration and self-
test/monitoring functions (BIST). This processor is not available directly for customer
use/application.
The digital front-end takes care of filtering and decimating the raw sigma-delta ADC output and provides
the final ADC data samples at a programmable sampling rate.
6.4.2 Master (Control) System
The Master (Control) System includes ARM’s Cortex-R4F processor clocked at 200 MHz, which is user
programmable. User applications executing on this processor control the overall operation of the device,
including Radar Control via well-defined API messages, radar signal processing (assisted by the radar
hardware accelerator) and peripherals for external interface.
The Master (Control) System plays a big role in enabling autonomous operation of IWR1443 as a radar-
on-a-chip sensor. The device includes a quad serial peripheral interface (QSPI) which can be used to
download customer code directly from a serial flash. A (classic) CAN interface is included that can be
used to communicate directly from the device to a CAN bus. An SPI/I2C interface is available for power
management IC (PMIC) control when the IWR1443 is used as an autonomous sensor.
For more complex applications, the device can operate under the control of an external MCU, which can
communicate with IWR1443 device over an SPI interface. In this case, it is possible to use the IWR14xx
as a radar sensor, providing raw detected objects to the external MCU. External MCU could reduce the
application code complexity residing in the device and makes more memory available for radar data cube
inside the IWR1443. This configuration also eliminates the need for a separate serial flash to be
connected to the IWR1443.
Copyright © 2017–2018, Texas Instruments Incorporated
Detailed Description
55
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
The IWR1443 provides for several digital communications outputs; CSI-2 Clk, 4 data formats – can be
connected to a remote processor for additional processing. Note: CSI-2 data is from the digital front end or
accelerator. When the MSS is used for preprocessing / or another MCU is used in industrial settings the
Serial Tx/Rx or CAN bus can provide lower speed communication than CSI-2. The IWR1443 has
additional serial Tx/Rx for HART protocol for industrial sensors, or Modbus serial protocol. The SPI port
can also provide additional communications or IO control. Additional industrial IO can be Industrial
Ethernet or Wifi.
Note that although four interfaces – one CAN, one I2C and two SPI interfaces – are present in the
IWR1443 device for external communication and PMIC control, only two of these interfaces are usable at
any point in time.
The total memory (RAM) available in the master subsystem is 576 KB. This is partitioned between the
R4F program RAM, R4F data RAM and radar data memory. The maximum usable size for R4F is 448 KB
and this is partitioned between the R4F’s tightly coupled interfaces TCMA (320 KB) and TCMB (128 KB).
Although the complete 448 KB is unified memory and can be used for program or data, typical
applications use TCMA as program and TCMB as data memory.
The remaining memory, starting at a minimum of 128 KB, is available to be used as radar data memory
for storing the ‘radar data cube’. It is possible to increase the radar data memory size in 64 KB
increments, at the cost of corresponding reduction in R4F program or data RAM size. The maximum size
of radar data memory possible is 384 KB. A few example configurations supported are listed in Table 6-1.
Table 6-1. R4F RAM(1)
R4F PROGRAM
RAM
R4F DATA
RAM
RADAR DATA
MEMORY
OPTION
1
2
3
4
320KB
256KB
256KB
128KB
128KB
128KB
64KB
128KB
192KB
256KB
384KB
64KB
(1) For IWR1443 ES1.0 and ES2.0, available RAM is 448 KB instead of
576KB.
The Master Subsystem Memory Map is shown in the Technical Reference Manual.
56
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
6.4.3 Host Interface
The IWR1443 device communicates with the host radar processor over the following main interfaces:
•
•
Reference Clock – Reference clock available for host processor after device wakeup
Control – 4-port standard SPI (slave) for host control. Control UART or CAN can be used as a control
interface
. All radio control commands (and response) flow through this interface.
•
Data – High-speed serial port following the MIPI CSI2 format (LVDS format can also be used). Four
data and one clock lane (all differential). Data from different receive channels can be multiplexed on a
single data lane to optimize board routing. This is a unidirectional interface used for data transfer only.
•
•
•
Reset – Active-low reset for device wakeup from host
Out-of-band interrupt
Error – Used for notifying the host in case the radio controller detects a fault
6.5 Accelerators and Coprocessors
The Processing System in the IWR1443 device is an accelerator for FFT operations. The Radar Hardware
Accelerator is an IP that enables off-loading the burden of certain frequently used computations in FMCW
radar signal processing from the main processor. It is well-known that FMCW radar signal processing
involves the use of FFT and Log-Magnitude computations in order to obtain a radar image across the
range, velocity and angle dimensions. Some of the frequently used functions in FMCW radar signal
processing can be done within the Radar Hardware Accelerator, while still retaining the flexibility of
implementing other proprietary algorithms in the Master System processor.
Key features of the Radar Processing Accelerator are:
•
•
FFT computation, with programmable FFT sizes (powers of 2) up to 1024-pt complex FFT
Internal FFT bit-width of 24 bits (each for I and Q) for good SQNR performance, with fully
programmable butterfly scaling at every radix-2 stage for user flexibility
•
Built-in capabilities for simple pre-FFT processing – specifically, programmable windowing, basic
interference zeroing-out and basic BPM removal
•
•
Magnitude (absolute value) and Log-Magnitude computation capability
Flexible data flow and data sample arrangement to support efficient multi-dimensional FFT operations
and transpose accesses as required
•
Chaining and Looping mechanism to sequence a set of accelerator operations one-after-another with
minimal intervention from the main processor
•
•
CFAR-CA detector support (linear and logarithmic)
Miscellaneous other capabilities of the accelerator
–
–
–
Stitching two or four 1024-point FFTs to get the equivalent of 2048-point or 4096-point FFT for
industrial level sensing applications where large FFT sizes are required
Slow DFT mode, with resolution equivalent to 16K size FFT, for FFT peak interpolation (eg. range
interpolation) purpose
Complex Vector Multiplication and Dot product capability for vectors of size up to 512
Copyright © 2017–2018, Texas Instruments Incorporated
Detailed Description
57
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
6.6 Other Subsystems
6.6.1 A2D Data Format Over CSI2 Interface
The IWR1443 device uses MIPI D-PHY / CSI2-based format to transfer the raw A2D samples to the
external MCU. This is shown in Figure 6-5.
•
•
Supports four data lanes
CSI-2 data rate scalable from 150 Mbps to 600
Mbps per lane
•
•
Virtual channel based
CRC generation
Normal Mode
Frame Period
Acquisition Period
Frame
Ramp/Chirp
1
2
3
N
Data Ready
F
L
H
L
L
H
L
L
H
L
L
H
L
F
S
S
S
E
S
S
E
S
S
E
S
S
E
E
Short
Packet
Short
Packet
Long
Packet
Short
Packet
ST SP ET
LPS
ST SP ET
.5μs-.8μs
ST PH
DATA
PF ET LPS
ST SP ET
LPS
LPS
Chirp 1 data
Data rate/Lane should be such that "Chirp + Interchirp" period
should be able to accommodate the data transfer
Copyright © 2017, Texas Instruments Incorporated
Frame Start – CSi2 VSYNC Start Short Packet
Line Start – CSI2 HSYNC Start Short Packet
Line End – CSI2 HSYNC End Short Packet
Frame End – CSi2 VSYNC End Short Packet
Figure 6-5. CSI-2 Transmission Format
58
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
The data payload is constructed with the following three types of information:
•
•
•
Chirp profile information
The actual chirp number
A2D data corresponding to chirps of all four channels
–
Interleaved fashion
•
Chirp quality data (configurable)
The payload is then split across the four physical data lanes and transmitted to the receiving D-PHY. The
data packet packing format is shown in Figure 6-6
First
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CH Chirp
Profile
Channel
Number
NU
NU
NU
NU
Chirp Num
5
1
11
CH Chirp
Profile
Channel
Number
Chirp Num
5
1
11
CH Chirp
Profile
Channel
Number
Chirp Num
5
1
11
CH Chirp
Profile
Channel
Number
Chirp Num
11
Channel 0 Sample 0 i
Channel 1 Sample 0 i
Channel 2 Sample 0 i
Channel 3 Sample 0 i
Channel 0 Sample 1 i
Channel 1 Sample 1 i
Channel 2 Sample 1 i
Channel 3 Sample 1 i
CQ Data [11:0]
Channel 0 Sample 0 q
11
Channel 1 Sample 0 q
11
Channel 2 Sample 0 q
11
Channel 3 Sample 0 q
11
Channel 0 Sample 1 q
11
Channel 1 Sample 1 q
11
Channel 2 Sample 1 q
11
Channel 3 Sample 1 q
Continues till the
last sample. Max 1023
11
CQ Data [23:12]
11
CQ Data [35:24]
CQ Data [47:36]
11
CQ Data [59:48]
NU
CQ Data [63:60]
Last
Figure 6-6. Data Packet Packing Format for 12-Bit Complex Configuration
Copyright © 2017–2018, Texas Instruments Incorporated
Detailed Description
59
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
6.6.2 ADC Channels (Service) for User Application
The IWR1443 device includes provision for an ADC service for user application, where the
GPADC engine present inside the device can be used to measure up to six external voltages. The
GPADC1, GPADC2, GPADC3, GPADC4, GPADC5, and GPADC6 pins are used for this purpose.
•
ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for
customer’s external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST
subsystem. This API could be linked with the user application running on the Master R4.
•
BIST subsystem firmware will internally schedule these measurements along with other RF and Analog
monitoring operations. The API allows configuring the settling time (number of ADC samples to skip)
and number of consecutive samples to take. At the end of a frame, the minimum, maximum and
average of the readings will be reported for each of the monitored voltages.
GPADC Specifications:
•
•
•
•
625 Ksps SAR ADC
0 to 1.8V input range
10-bit resolution
For 5 out of the 6 inputs, an optional internal buffer (0.4-1.3V input range) is available. Without the
buffer, the ADC has a switched capacitor input load modeled with 5pF of sampling capacitance and
12pF parasitic capacitance (ADC channel mapped to C14, the internal buffer is not available).
5
ANALOG TEST 1-4,
GPADC
ANAMUX
5
VSENSE
Figure 6-7. ADC Path
Table 6-2. GP-ADC Parameter
PARAMETER
TYP
1.8
UNIT
V
ADC supply
ADC unbuffered input voltage range
ADC buffered input voltage range(1)
ADC resolution
0 – 1.8
0.4 – 1.3
10
V
V
bits
LSB
LSB
LSB
LSB
Ksps
ns
ADC offset error
±5
ADC gain error
±5
ADC DNL
–1/+2.5
±2.5
625
ADC INL
ADC sample rate(2)
ADC sampling time(2)
ADC internal cap
400
10
pF
ADC buffer input capacitance
2
pF
(1) Outside of given range, the buffer output will become nonlinear.
(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.
60 Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
Table 6-2. GP-ADC Parameter (continued)
PARAMETER
TYP
UNIT
ADC input leakage current
3
uA
Copyright © 2017–2018, Texas Instruments Incorporated
Detailed Description
61
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
6.7 Identification
The JTAG identification code is described in the IWR1443 Errata.
The JTAG interface provides the XDS emulator and boundary scan connectivity to the IWR1443.
Table 6-3. JTAG Interface
Signal
SoC Pin
Name
Type
Function
Free Running clock when used with emulators viz.
Spectrum Digital’s XDS200 or TI’s XDS110
TCK
M13
Test Clock
Input
TMS
TDI
L13
H13
J13
Test Mode Select
Test Data Input
Test Data Output
Input
Directs the next state of the JTAG state machine
Scan Data Input to the device
Input
TDO
Output
Scan Data Output of the device
6.8 Boot Modes
As soon as device reset is de-asserted, the R4F processor of the Master (Control) system starts executing
its bootloader from an on-chip ROM memory.
The bootloader of the Master system operates in two basic modes and these are specified on the user
hardware (Printed Circuit Board) by configuring what are termed as “Sense on Power” (SOP) pins. These
pins on the device boundary are scanned by the bootloader firmware and choice of mode for bootloader
operation is made.
Table 6-4 enumerates the relevant SOP combinations and how these map to bootloader operation.
Table 6-4. SOP Combinations
SOP2 (P13)
SOP1 (P11)
SOP0 (J13)
BOOTLOADER MODE AND OPERATION
Functional Mode
0
0
1
Device Bootloader loads user application from QSPI Serial Flash to
internal RAM and switches the control to it
Flashing Mode
1
0
0
1
1
1
Device Bootloader spins in loop to allow flashing of user application
(or device firmware patch – Supplied by TI) to the serial flash
Debug Mode
Bootloader is bypassed and R4F processor is halted. This allows
user to connect emulator at a known point
62
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
6.8.1 Flashing Mode
In Flashing Mode, the Master System’s bootloader enables the UART driver and expects a data stream
comprising of User Application (Binary Image) and Device Firmware (referred to as Device Firmware
Patch or Service Pack) from an external flashing utility. Figure 6-8 shows the flashing utility executing on a
PC platform, but the protocol can be accomplished on an embedded platform as well.
Serial
FLASH
User Application
And device firmware
Flashing
ROM
UART
FLASHING
UTILITY
Program
RAM
Integrated MCU
ARM Cortex-R4F
Radar
Section
RAM
Data
RAM
Figure 6-8. Figure 5. Bootloader Flashing Mode
Copyright © 2017–2018, Texas Instruments Incorporated
Detailed Description
63
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
6.8.2 Functional Mode
In Functional Mode, the Master System’s bootloader looks for a valid image in the serial flash memory,
interfaced over the QSPI port. If a valid image is found, the bootloader transfers the same to Master
System’s memory subsystem. The image format contains the MSS application code and the radar
subsystem patch code.
If a valid image (or the QSPI Serial Flash is not found), the bootloader initializes the SPI port and awaits
for the image transfer. This operation comes handy for configurations where the IWR1443 is interfaced to
an external processor which has its own nonvolatile storage hence can store the user application and the
IWR1443 device’s firmware image.
User Application is Loaded
Serial
From FLASH to R4F RAM and
Flash
Device Patch to Radar Section
ROM
UART
Data
RAM
Integrated MCU
ARM Cortex-R4F
Radar
Section
RAM
Histogram
RAM
External
Processor
SPI
User Application is Loaded
From FLASH to R4F RAM and
Device Patch to Radar Section
Figure 6-9. Bootloader’s Functional Mode
64
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Application Information
Application information can be found on IWR Application web page.
7.2 Reference Schematic
The reference schematic and power supply information can be found in the IWR1443 EVM
Documentation.
Copyright © 2017–2018, Texas Instruments Incorporated
Applications, Implementation, and Layout
65
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
7.3 Layout
7.3.1 Layout Guidelines
General layout guidelines can be found in the IWR1443 EVM Documentation, IWR1443BOOST Layout
and Design Files, and IWR1443BOOST Schematics, Assembly Files, and BOM.
7.3.2 Layout Example
The IWR1443 EVM, RF layout can be found in the IWR1443BOOST Layout and Design Files and
IWR1443BOOST Schematics, Assembly Files, and BOM.
7.3.3 Stackup Details
Layout Stackup details can be found in the IWR1443BOOST Layout and Design Files and
IWR1443BOOST Schematics, Assembly Files, and BOM.
There are specific RF guidelines for the RF Tx and Rx. There are additional layout guidelines for other
sections in the IWR1443 Checklist for Schematic Review, Layout Review, Bringup/Wakeup.
66
Applications, Implementation, and Layout
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
8 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions follow.
8.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, IWR1443). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ABL0161), the temperature range (for example, blank is the default
commercial temperature range). Figure 8-1 provides a legend for reading the complete device name for
any IWR1443 device.
For orderable part numbers of IWR1443 devices in the ABL0161 package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the IWR1443 Device
Errata.
Copyright © 2017–2018, Texas Instruments Incorporated
Device and Documentation Support
67
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
IWR
4
43
_F_
__
Q
G
ABL
__
A
1
Prefix
IWR = Industrial
Generation
Tray or Tape & Reel
R = Tape & Reel
Blank = Tray
1 = 77 GHz Band
Variant
Increasing digital performance, generation based. Gen 1:
Package
ABL = BGA
Security
G = General
2 = FE
4 = FE + FFT + MCU
6 = FE + MCU + DSP
Num RX / TX Channels
RX = 1, 2, 3, 4
TX = 1, 2, 3
S = Secure
Silicon PG Revision
blank = Rev 2.0
F = Rev 3.0
Temperature (TJ)
A = -40C to 105C
Features
blank = baseline
Safety Level
Q = Quality Manage
Figure 8-1. Device Nomenclature
8.2 Tools and Software
Models
IWR1443 BSDL Model Boundary scan database of testable input and output pins for IEEE 1149.1 of the
specific device.
IWR1443 IBIS Model IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
I\WR1443 Checklist for Schematic Review, Layout Review, Bringup/Wakeup
A
set of steps in
spreadsheet form to select system functions and pinmux options. Specific EVM schematic
and layout notes to apply to customer engineering. A bringup checklist is suggested for
customers.
8.3 Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (IWR1443). In the upper right corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral
follows.
Errata
IWR1443 Device Errata Describes known advisories, limitations, and cautions on silicon and provides
workarounds.
68
Device and Documentation Support
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: IWR1443
IWR1443
www.ti.com.cn
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
8.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.5 商标
E2E is a trademark of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
All other trademarks are the property of their respective owners.
8.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.7 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017–2018, Texas Instruments Incorporated
Device and Documentation Support
69
提交文档反馈意见
产品主页链接: IWR1443
IWR1443
ZHCSHP9C –MAY 2017–REVISED OCTOBER 2018
www.ti.com.cn
9 Mechanical, Packaging, and Orderable Information
9.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
CAUTION
The following package information is subject to change without notice.
70
Mechanical, Packaging, and Orderable Information
版权 © 2017–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: IWR1443
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2023
PACKAGING INFORMATION
Orderable Device
IWR1443FQAGABL
IWR1443FQAGABLR
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 105
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
FCCSP
FCCSP
ABL
161
161
176
RoHS & Green
Call TI | SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
IWR1443
Samples
Samples
QG
964FC
ACTIVE
ABL
1000 RoHS & Green
Call TI | SNAGCU
-40 to 105
IWR1443
QG
964FC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
ABL 161
10.4 x 10.4, 0.65 mm pitch
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225978/A
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明