JFE150DBVT [TI]
超低噪声、低栅极电流、音频、N 沟道 JFET | DBV | 5 | -40 to 125;
| 型号： | JFE150DBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超低噪声、低栅极电流、音频、N 沟道 JFET | DBV | 5 | -40 to 125 栅 栅极 |
| 文件： | 总30页 (文件大小：2091K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JFE150
ZHCSLR8B –JUNE 2021 –REVISED APRIL 2023
JFE150 超低噪音、低栅极电流、音频、N 通道JFET
设置，并为 50μA 至 20mA 的电流提供出色的噪声性
能。当偏置电流为5mA 时，该器件会产生0.8nV/√Hz
的输入参考噪声，从而以极高的输入阻抗 (> 1TΩ) 提
供超低噪声性能。JFE150 还具有连接到独立钳位节点
的集成二极管，无需添加高泄漏、非线性外部二极管即
可提供保护。
1 特性
• 超低噪声：
– 电压噪声：
• 1kHz 时为0.8nV/√Hz，IDS = 5mA
• 1kHz 时为0.9nV/√Hz，IDS = 2mA
– 电流噪声：1 kHz 时为1.8fA/√Hz
• 低栅极电流：10 pA（最大值）
• 低输入电容：VDS = 5V 时为24pF
• 高栅漏电压和栅源击穿电压：-40 V
• 高跨导：68mS
JFE150 可承受 40V 的高漏源电压，以及低至 –40V
的栅源电压和栅漏电压。该器件额定工作温度范围为
–40°C 至 + 125°C，并采用 5 引脚 SOT-23 和 SC70
封装。
封装信息
封装(1)
• 封装：小型SC70 和SOT-23
封装尺寸（标称值）
2.90mm × 1.60mm
2.00mm × 1.25mm
器件型号
JFE150
2 应用
DBV（SOT-23，5)
DCK（SC70，5）
• 麦克风输入
• 水听器和船用设备
• DJ 控制器、混频器和其他DJ 设备
• 专业音频混合器或控制平面
• 吉他放大器和其他乐器放大器
• 状态监控传感器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
器件概要
参数
栅源击穿电压
漏源击穿电压
输入电容
值
VGSS
VDSS
CISS
TJ
-40 V
±40V
24pF
3 说明
JFE150 是使用德州仪器 (TI) 的现代高性能模拟双极工
艺构建的 Burr-Brown™ 分立式 JFET。JFE150 具有以
前较旧的分立式 JFET 技术所不具备的性能。JFE150
提供出色的噪声功率效率和灵活性，静态电流可由用户
–40°C 至+125°C
结温
IDSS
35mA
漏源饱和电流
D
VCH
G
VCL
S
功能方框图
超低输入电压噪声
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS732
JFE150
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ZHCSLR8B –JUNE 2021 –REVISED APRIL 2023
Table of Contents
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 14
9.3 Power Supply Recommendations.............................17
9.4 Layout....................................................................... 17
10 Device and Documentation Support..........................18
10.1 Device Support....................................................... 18
10.2 Documentation Support.......................................... 19
10.3 接收文档更新通知................................................... 19
10.4 支持资源..................................................................19
10.5 Trademarks.............................................................19
10.6 静电放电警告.......................................................... 19
10.7 术语表..................................................................... 19
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................6
7 Parameter Measurement Information............................8
7.1 AC Measurement Configurations................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
Information.................................................................... 19
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (November 2021) to Revision B (April 2023)
Page
• 将DBV 封装（SOT-23，5）从预发布更改为量产数据（正在供货）并添加了相关内容.................................... 1
• 将器件概要表中的参数说明从“栅源电压”更改为“栅源击穿电压”，并从“漏源电压”更改为“漏源击穿电
压”，以便与电气特性 保持一致........................................................................................................................1
• 将器件概要表中的“漏源饱和电流”值从36mA 更改为35mA，以便与电气特性保持一致.............................1
• Changed VCH and VCL pin type and description in Pin Functions to reflect optional nature of diode clamps....
............................................................................................................................................................................3
• Changed Figure 6-2, Drain-to-Source Current vs Drain-to-Source Voltage, to show correct VGS values.......... 6
• Changed Figure 8-1, VDS vs IDS, to show correct VGS values and improve image resolution..........................10
• Added JFE150EVM user's guide and JFE150 Ultra-Low-Noise Pre-Amp application note to Related
Documentation .................................................................................................................................................19
Changes from Revision * (June 2021) to Revision A (November 2021)
Page
• Changed VGS minimum from –1.1 V to –1.3 V (100 µA), –0.9 V to –1.1 V (2 mA) ..................................... 5
• Changed Figure 6-3, Drain-to-Source Current vs Drain-to-Source Voltage, to show correct VGS values.......... 6
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English Data Sheet: SLPS732
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5 Pin Configuration and Functions
VCH
VCL
G
1
2
3
5
D
S
4
Not to scale
图5-1. DBV, 5-Pin SOT-23 and DCK, 5-Pin SC70 Packages (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
D
NO.
5
Output
Input
Output
—
Drain
Gate
G
3
S
4
Source
VCH
VCL
1
Positive diode clamp voltage. Float this pin if clamp diodes are not used.
Negative diode clamp voltage. Float this pin if clamp diodes are not used.
2
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–40
–40
MAX
UNIT
VDS
Drain-to-source voltage
40
0.9
40
V
V
V
VGS, VGD
VVCH
Gate-to-source, gate-to-drain voltage
Voltage between VCH to D, G, or S
Voltage between VCL to D, G, or S
VVCL
–40
DC
20
200
50
IVCL, IVCH
Clamp diode current
mA
50-ms pulse(2)
IDS
Drain-to-source current
Gate-to-source, gate-to-drain current
Ambient temperature
mA
mA
°C
–50
–20
–55
–55
–55
IGS, IGD
TA
20
150
150
175
TJ
Junction temperature
°C
Tstg
Storage temperature
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Maximum diode current pulse specified for 50 ms at 1% duty cycle.
6.2 ESD Ratings
VALUE
±2500
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.02
0
NOM
MAX
IDSS
UNIT
IDS
VGS
TA
Drain-to-source current
Gate-to-source voltage
Specified temperature
mA
V
–1.2
125
°C
–40
6.4 Thermal Information
JFE150
THERMAL METRIC(1)
DCK (SC70)
DBV (SOT-23)
UNIT
5 PINS
197.1
93.7
5 PINS
183.8
83.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44.8
51.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
16.7
24.9
ψJT
44.6
51.4
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, IDS = 2 mA, and VDS = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE
f = 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
IDS = 100 µA
IDS = 2 mA
IDS = 5 mA
3
2
IDS = 100 µA , VDS = 5 V
IDS = 2 mA, VDS = 5 V
IDS = 5 mA, VDS = 5 V
1.6
0.9
1.8
0.8
0.19
0.09
0.13
1.8
en
Input-referred voltage noise density
nV/√Hz
f = 0.1 Hz to 10 Hz,
VDS = 5 V
Input-referred voltage noise
Input current noise
µVPP
ei
f = 1 kHz, VDS = 5 V
fA/√Hz
INPUT CURRENT
0.2
0.2
±10
VDS = 2 V, VGS = –0.7 V, VVCH = 5 V, VVCL = –5 V
IG
Input gate current
pA
±2000
TA = –40°C to +85°C
TA = –40°C to +125°C
VDS = 0 V, VGS = –30 V
±10000
INPUT VOLTAGE
VGSS
VGSC
Gate-to-source breakdown voltage
VDS = 0 V, |IG| < 100 µA
VDS = 10 V, IDS = 0.1 µA
IDS = 100 µA
V
V
−40
−0.9
Gate-to-source cutoff voltage
−1.5
–1.3
–1.1
−1.2
–0.7
–0.5
VGS
Gate-to-source voltage
V
IDS = 2 mA
INPUT IMPEDANCE
RIN
Gate input resistance
1
30
24
7
VGS = –5 V to 0 V, VDS = 0 V
VDS = 0 V
TΩ
CISS
Input capacitance
VDS = 5 V
pF
CRSS
Reverse transfer capacitance
VDS = 0 V
OUTPUT
24
22
35
46
57
IDSS
gm
Drain-to-source saturation current
Transconductance
VDS = 10 V, VGS = 0 V
mA
mS
TA = –40°C to +125°C
IDS = 100 µA
3
18
68
IDS = 2 mA
GFS
Full conduction transconductance
Drain-to-source breakdown voltage
Output capacitance
VDS = 10 V, VGS = 0 V
|IDS| < 100 µA, VGS = –2 V
VDS = 5 V
55
40
80
mS
V
VDSS
COSS
8
pF
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6.6 Typical Characteristics
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 5 V (unless otherwise noted)
45
VGS = 0 V
VGS = −0.1 V
VGS = −0.2 V
VGS = −0.3 V
VGS = −0.4 V
40
35
30
25
20
15
10
5
0
5
10
15
20
25
30
35
40
Drain-to-Source Voltage (V)
图6-1. Drain-to-Source Current vs Gate-to-Source Voltage
图6-2. Drain-to-Source Current vs Drain-to-Source Voltage
图6-3. Drain-to-Source Current vs Drain-to-Source Voltage
图6-4. Common Source Transconductance vs Drain-to-Source
Current
图6-6. Gate Current vs Gate-to-Source Voltage
图6-5. Gate Current vs Drain-to-Source Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 5 V (unless otherwise noted)
VDS = 5 V
图6-7. Gate-to-Source Voltage vs Temperature
图6-8. IDSS vs Drain-to-Source Voltage
f = 1 kHz
图6-9. Input-Referred Noise Density vs Frequency
图6-10. Noise Density Contributors vs Input Gate Resistance
f = 1 kHz
图6-11. Input-Referred Noise Spectral Density
vs Drain‑to‑Source Current
图6-12. Input, Output, and Reverse Transfer Capacitance vs
Drain-to-Source Voltage
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7 Parameter Measurement Information
7.1 AC Measurement Configurations
The circuit configuration used for noise measurements is seen in 图7-1. The nominal IDS current is configured in
the schematic by calibrating V–. After IDS is fixed, the VDS voltage is set by calibrating V+. For input-referred
noise data, the gain of the circuit is calibrated from VIN to VOUT and used for the input-referred gain calculation.
V+
100 ꢀ
10 kꢀ
RD
10 kꢀ
49.9 ꢀ
œ
VOUT
+
JFE150
OPA210
1 ꢁF
RG
0 ꢀ
100 kꢀ
+
VIN
RS
œ
3 mF
10 kꢀ
Vœ
图7-1. AC Measurement Reference Schematic
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8 Detailed Description
8.1 Overview
The JFE150 is an ultra-low noise JFET designed to create low-noise gain stages for very high output impedance
sensors or microphones. Advanced processing technology gives the JFE150 extremely low-noise performance,
a high gm/CISS ratio, and ultra-low gate-current performance. Input protection diodes are integrated to clamp
high-voltage spurious input signals without the need for additional input diodes that can add leakage current or
distortion-creating non-linear capacitance. The JFE150 provides a next-generation device to implement low-
noise amplifiers for piezoelectric sensors, transducers, large-area condenser microphones, and hydrophones in
small-package options.
8.2 Functional Block Diagram
D
VCH
G
VCL
S
8.3 Feature Description
8.3.1 Ultra-Low Noise
Junction-gate field-effect transistors (JFETs) are commonly used as an input stage in high-input-impedance, low-
noise designs in audio, SONAR, vibration analysis, and other technologies. The JFE150 is a new generation
JFET device that offers very low noise performance at the lowest possible current consumption in high-input-
impedance amplifier designs. The JFE150 is manufactured on a high-performance analog process technology,
giving tighter process parameter control than a standard JFET.
Designs that feature operational amplifiers (op amps) as the primary gain stage are common, but these designs
are not able to achieve the lowest possible noise as a result of the inherent challenges and tradeoffs required
from a full operational amplifier design. Noise in JFET designs can be evaluated in two separate regions: low-
frequency flicker noise and wideband thermal noise. Flicker, or 1/f noise, is extremely important for systems that
require signal gain at frequencies less that 100 Hz. The JFE150 achieves extremely low 1/f noise in this range.
Thermal noise is noise in the region greater than 1 kHz and depends on the gain, or gm, of the circuit. The gm is
a function of the drain-to-source bias current; therefore, thermal noise is also a function of drain-to-source bias
current. 图 6-9 shows both 1/f and thermal noise with multiple bias conditions measured using the circuit shown
in 图7-1.
Noise is typically modeled as a voltage source (voltage noise) and current source (current noise) on the input.
The 1/f and thermal noise can be represented as voltage noise. Current noise is dominated by current flow into
the gate, and is called shot noise. The JFE150 features extremely low gate current, and therefore, extremely low
current noise. 图 6-10 shows how source impedance on the input is the dominant noise source. In nearly all
cases, noise created as a result of current noise is negligible.
8.3.2 Low Gate Current
The JFE150 features a maximum gate current of 10 pA at room temperature, making the device an excellent
choice for maximizing the gain and dynamic range from extremely high impedance sensors. Additionally, any
noise contributions as a result of gate current are minimized because of the negligible shot noise at low current
levels. As with all JFET devices, when the drain-to-source voltage increases, the gate current also increases.
Keep the drain-to-source voltage to less than 5 V for the lowest gate input current operation.
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8.3.3 Input Protection
The JFE150 features input protection diodes that are used for surge clamping and ESD events. The diodes are
rated to withstand high current surges for short times, steering current from the gate (G) pin to the VCH and VCL
pins. The diodes also feature very low leakage, removing the need for external protection devices that can have
high leakage currents or nonlinear capacitance that degrade the distortion performance.
8.4 Device Functional Modes
The JFE150 functionality is identical to standard N-channel depletion JFET devices. The gate-to-source (VGS
voltage, drain-to-source voltage (VDS) and drain-to-source current (IDS) determine the region of operation.
)
• For VGS < VGSC: JFE150 conduction channel is closed; IDS is only determined by junction leakage current.
• For VGS > VGSC: Two modes of operation can exist depending on VDS. When VDS is less than the linear
(saturation) region threshold (see 图8-1), the device operates in the linear region, meaning that the device
behaves as a resistor connected from drain-to-source with minimal variation from any changes in VGS. When
VDS is greater than the linear (saturation) region threshold, IDS has a strong dependance on VGS, where the
relationship is described by the parameter gm.
图8-1. VDS vs IDS
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Input Protection Diodes
The JFE150 features diodes that are used to help clamp voltage surges that can occur on the input sensor to the
gate. The diodes are connected between the gate and two separate pins, VCL and VCH. The clamping
mechanism works by steering current from the gate into the VCL or VCH nodes when the voltage at the gate is
less than VCL or greater than VCH. 图 9-1 shows an example of a microphone input circuit where a dc blocking
capacitor operates with a large dc voltage. When the microphone input is dropped or shorted, the dc blocking
capacitor discharges into the VCL or VCH nodes, thus helping eliminate large signal transient voltages on the
gate. There are also clamping diodes from the drain and source to VCL and VCH, respectively. The clamping
diodes can withstand high surge currents up to 200 mA for 50 ms; however, limit dc current to less than 20 mA.
48 V
VCH
D
6.8 kΩ
CDC
10 …F
RG
G
JFE150
iG
RB
VCL
S
RL
图9-1. JFE150 Clamping Diode Example
图 9-1 shows an example of configuring the diode clamp to protect the JFET against overvoltage in a phantom-
powered microphone circuit. Phantom power typically delivers 48 V through a 6.8-kΩ pullup resistor to a
microphone or dynamic load. If the microphone is disconnected, dc blocking capacitor CDC can be biased up to
48 V. If the input to the capacitor is then shorted to ground (shown by the switch in 图 9-1), the gate voltage can
exceed the absolute maximum rating for VGS. In this case, the blocking diode is used, along with current limiting
resistors RG and RL, to clamp the gate voltage to a safe level. Be aware that the thermal noise of RG couples
directly into the gate input; therefore, make sure to minimize the resistance of RG.
The clamping diodes are not required for operation. The VGS voltage can withstand –40 V, so clamping is not
required if the VGS voltage is kept greater than this limit. If the diodes are not needed, leave the VCL and VCH
nodes floating.
Most previous-generation JFET devices featured only three pins (gate, source, and drain). For these devices,
the gate pin is in the same physical location as the VCL pin on the JFE150. To test the JFE150 in a three-pin
socket, short pin 2 of the JFE150 (VCL) to pin 3 (G). When the devices are connected with pin 2 shorted to pin 3,
the diode from VCL is shorted out and cannot provide any clamping protection. The input capacitance (CISS) also
increases by 1 pF; see 图6-12.
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9.1.2 Capacitive Transducer Input Stage
Piezoelectric transducers are used for many different applications that require low-noise, high-gain performance.
These transducers exhibit high output impedance (> 10 MΩ), and therefore require very high impedance loading
for subsequent input stages. The JFE150 has ultra-low input gate current (maximum IG = ±10 pA) and low input
capacitance (CISS = 24 pF), which makes the device an excellent choice for transducers with an effective
capacitance of greater than 240 pF. For smaller, lower-capacitance transducers, the CISS can impact the gain of
the front end by attenuating the input signal, thereby reducing the noise performance.
9.1.3 Common-Source Amplifier
The common-source amplifier is a commonly used open-loop gain stage for JFET amplifiers. 图 9-2 shows the
basic circuit.
V+
RD
VOUT
JFE150
RG
+
VIN
RS
œ
图9-2. Common-Source Amplifier
方程式1 shows the equation for gain of the circuit in 图9-2.
V
gm*R
D
1 + gm*R
OUT
= −
(1)
V
IN
S
Generally, higher gain results in improved noise performance. Gain increases as the bias current is increased as
a result of increasing gm (see 图 6-4). As a result, the input-referred noise decreases as bias current is
increased (see 图 6-9). Any JFET design must make a tradeoff between current consumption and noise
performance. The JFE150, however, delivers significantly lower noise performance than most operational
amplifiers at the same current consumption. The bias current (IDS) is set by the value of the source resistor, RS,
and the threshold voltage, VT, of the JFE150. 图9-3 is a graph showing nominal IDS vs RS.
图9-3. Drain-to-Source Current vs RS, VDS = 5 V
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The bias current varies according to the resistor and threshold voltage tolerances. Additionally, thermal noise
associated with RS couples directly into the gain of the circuit, degrading the overall noise performance. To
improve the circuit in 图 9-4, use a current-source biasing scheme. Current-source biasing removes the JFET
threshold variation from the biasing scheme, and allows for lower-value filtering capacitance (CS) for equivalent
filtering due to the high output impedance of current sources.
V+
RD
VOUT
JFE150
RG
+
CS
VIN
œ
IBIAS
Vœ
图9-4. Common-Source Amplifier With Current-Source Biasing
9.1.4 Composite Amplifiers
The JFE150 can be configured to provide a low-noise, high-input impedance front-end stage for a typical op
amp. Open-loop transistor gain stages shown previously suffer from wide gain variations that are dependent on
the forward transcondutance of the JFE150. When precision gain is required, the composite amplifier (JFET
front-end + operational amplifier) achieves excellent results by allowing for a fixed gain determined by external
resistors, and improving the noise and bandwidth of the operational amplifier. The JFE150 gain stage provides a
boost to the open-loop performance of the system, extending the bandwidth beyond what the operational
amplifier alone can provide, and gives a high-input impedance, ultra-low noise input stage to interface with high
source impedance microphones.
图 9-5 shows a generic schematic representation of a current-feedback composite amplifier. The component
requirements and tradeoffs are listed in 表9-1.
CF
VDD
RD
CD
œ
OPA
JFE150
VOUT
VBIASO
+
CB
RG
+
RB
VIN
RS2
œ
RS
CS
图9-5. Low Noise, High Input Impedance Composite Amplifier
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表9-1. Composite Amplifier Component List and Function
COMPONENT
DESCRIPTION
RELATED EQUATION
DC blocking capacitor for input source. Use a dc blocking capacitor if
the dc voltage of the input source is not the same as the gate bias
voltage.
1
f
=
(2)
CB
–3dBDC
2* π*R
R
*C
B1 B2 B1
Bias resistor. Use biasing resistors to set the dc voltage at the gate.
High-value resistors can be used without an impact to noise if the
source impedance and bypass capacitor have sufficiently low
impedance.
RB
See 方程式2
Gate resistor. Can be used to help limit current flow into gate in
overvoltage cases.
RG
RD
RS
CD
Drain resistor. Sets gain of JFET stage in common source biasing,
along with gm and RS.
Source resistor. Used to set bias of JFET; see 图9-3. Resistor
thermal noise directly impacts noise performance.
DC blocking capacitor. Blocks nominal drain voltage so the amplifier
operates at a midsupply bias point.
Feedback capacitor. Along with RF, this capacitor sets the –3‑dB
high-pass cutoff frequency when the amplifier gain-bandwidth product
(GBW) is sufficiently high enough to support the –3‑dB frequency. If
the GBW is not high enough, then the GBW sets the –3-dB
frequency.
1
f
=
(3)
CF
–3dBHP
2*π*R *C
F
F
Feedback resistor. Along with CF, this resistor sets the –3‑dB high-
pass cutoff frequency when the amplifier gain-bandwidth product
(GBW) is sufficiently high enough to support the –3‑dB frequency. If
the GBW is not high enough, then the GBW sets the –3-dB
frequency.
RF
See 方程式3
V
R
F2
Current feedback gain-setting resistor 1. Along with RS2, sets gain
closed-loop.
OUT
RF2
RS2
CS
=
(4)
(5)
V
R
IN
S2
Current feedback gain-setting resistor 2. Along with RS2, sets gain
closed-loop. Resistor thermal noise directly impacts noise
performance.
See 方程式4
1
Current feedback ac-coupling capacitor. This capacitor, along with R2,
sets the low-pass –3-dB frequency.
f
=
–3dBLP
2*π*R *C
S2
S
9.2 Typical Application
The JFE150 can be configured to provide a low-noise, high-input-impedance front-end stage for a typical op
amp. Single-transistor gain stages shown previously suffer from wide gain variations dependent on the forward
transcondutance of the JFE150. When precision gain is required, the composite amplifier (JFET front-end +
operational amplifier) achieves excellent results.
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CF
10 pF
12 V
RD
10 kꢁ
CD
10 ꢀF
œ
JFE150
VOUT
CB
10 ꢀF
6 V
RG
10 ꢁ
+
OPA202
+
RB
1 Mꢁ
RS2
10 ꢁ
VIN
œ
RS
300 ꢁ
CS
470 ꢀF
图9-6. Low-Noise, High-Input-Impedance Composite Amplifier
9.2.1 Design Requirements
PARAMETER
DESIGN GOAL
Gain
60 dB
Frequency response
Noise
60 Hz to 20 kHz
< 1.5 nV/√Hz
< 100 pA
Input current
Output swing
±5 V
9.2.2 Detailed Design Procedure
This design provides 60 dB of gain with extremely high input impedance at a very low frequency response. The
order of design priorities are as follows:
• The JFE150 bias current is set by selecting the desired bias current and noise tradeoff (see 图6-11). The
input-referred noise is dominated by the JFE150 bias current and gain. To set the bias current point, adjust
the source resistance according to 图9-3.
• After the bias current is selected, set the JFET stage gain as high as possible without pushing the device into
the linear region of operation. This is achieved by using the largest drain resistor (RD) possible while
maintaining a minimum of 2 V across the drain to source nodes. Be aware that the amplifier forces the drain
node to match the noninverting amplifier input in normal closed-loop operation. Both ac and dc voltages must
be considered, but generally, only the dc operating point on the drain is considered because the ac voltage
swing is minimal.
• Set the closed gain according to RF2 and RS2, as seen in 方程式4. Thermal noise from RS2 directly couples
into the circuit; therefore, small values for this resistor are required.
• CS is required to block dc voltages from altering the bias point set by source resistor RS. CS also forms the
low-frequency response as described in 方程式5.
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9.2.3 Application Curves
图9-7. Voltage Gain
图9-8. Input-Referred Noise Density
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9.3 Power Supply Recommendations
The JFE150 is a JFET transistor with clamping diodes. There are no specific power-supply connections;
however, take care not to exceed any absolute maximum voltages on any of the pins if system supply voltages
greater than or equal to 40 V are used.
9.4 Layout
9.4.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Reduce parasitic coupling by running the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Keep high impedance input signals away from noisy traces.
• Make sure supply voltages are adequately filtered.
• Minimize distance between source-connected and drain-connected components to the JFE150.
• Consider a driven, low-impedance guard ring around the critical gate traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
9.4.2 Layout Example
VDD
RD
VDD
VSS
VCH
VCL
G
D
S
VSS
RS
VIN
CS
图9-9. JFE150 Layout Example, Common Source Configuration
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
10.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
10.1.1.2 TINA-TI™ 仿真软件（免费下载）
TINA-TI™ 仿真软件是一款简单易用、功能强大且基于 SPICE 引擎的电路仿真程序。TINA-TI 仿真软件是 TINA™
软件的一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 仿
真软件提供所有传统的SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 仿真软件提供全面的后处理能力，便于用户以多种方式获得结果，用户可从设计工具和仿真网页免费下
载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的能力，从而构建一个动态的快速启动工具。
备注
必须安装 TINA 软件或者 TINA-TI 软件后才能使用这些文件。请从 TINA-TI™ 软件文件夹中下载免费的
TINA-TI 仿真软件。
10.1.1.3 TI 参考设计
TI 参考设计是由TI 的精密模拟应用专家创建的模拟解决方案。TI 参考设计提供了许多实用电路的工作原理、组件
选择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。TI 参考设计可在线获
取，网址为https://www.ti.com/reference-designs。
10.1.1.4 滤波器设计工具
滤波器设计工具是一款简单、功能强大且便于使用的有源滤波器设计程序。利用滤波设计器，用户可使用精选 TI
运算放大器和TI 供应商合作伙伴提供的无源器件来打造理想滤波器设计方案。
设计工具和仿真网页以基于网络的工具形式提供滤波设计工具。用户通过该工具可在短时间内完成多级有源滤波
器解决方案的设计、优化和仿真。
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English Data Sheet: SLPS732
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10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, JFE150 Ultra-Low-Noise Pre-Amp application note
• Texas Instruments, JFE150 Evaluation Module user's guide
• Texas Instruments, OPAx202 Precision, Low-Noise, Heavy Capacitive Drive, 36-V Operational Amplifiers
data sheet
• Texas Instruments, OPAx210 2.2-nV/√Hz Precision, Low-Power, 36-V Operational Amplifiers data sheet
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
Burr-Brown™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
JFE150DBVR
JFE150DBVT
JFE150DCKR
JFE150DCKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2GLW
Samples
Samples
Samples
Samples
NIPDAU
SN
2GLW
1IF
SC70
SN
1IF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
JFE150DBVR
JFE150DBVT
JFE150DCKR
JFE150DCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
3000
250
180.0
180.0
178.0
178.0
8.4
8.4
9.0
9.0
3.2
3.2
2.4
2.4
3.2
3.2
2.5
2.5
1.4
1.4
1.2
1.2
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
3000
250
SC70
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
JFE150DBVR
JFE150DBVT
JFE150DCKR
JFE150DCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
5
5
5
5
3000
250
210.0
210.0
180.0
180.0
185.0
185.0
180.0
180.0
35.0
35.0
18.0
18.0
3000
250
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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