JL193BGA [TI]
低功耗低失调电压双路比较器 | LMC | 8 | -55 to 125;
| 型号： | JL193BGA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗低失调电压双路比较器 | LMC | 8 | -55 to 125 放大器 比较器 |
| 文件： | 总17页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM193JAN
www.ti.com
SNOSAN2A –MAY 2005–REVISED MARCH 2013
LM193JAN Low Power Low Offset Voltage Dual Comparators
Check for Samples: LM193JAN
1
FEATURES
DESCRIPTION
The LM193 series consists of two independent
precision voltage comparators with an offset voltage
specification as low as 2.0 mV max for two
comparators which were designed specifically to
operate from a single power supply over a wide range
of voltages. Operation from split power supplies is
also possible and the low power supply current drain
is independent of the magnitude of the power supply
voltage. These comparators also have a unique
characteristic in that the input common-mode voltage
range includes ground, even though operated from a
single power supply voltage.
2
•
Wide Supply
–
–
Voltage Range: 5.0VDC to 36VDC
Single or Dual Supplies: ±2.5VDC to ±18VDC
•
Very Low Supply Current Drain (0.4 mA) —
Independent of Supply Voltage
•
•
•
•
Low Input Biasing Current: 25 nA typ
Low Input Offset Current: ±3 nA typ
Maximum Offset Voltage +5mV Max @ 25°C
Input Common-Mode Voltage Range Includes
Ground
Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave and
time delay generators; wide range VCO; MOS clock
timers; multivibrators and high voltage digital logic
gates. The LM193 series was designed to directly
interface with TTL and CMOS. When operated from
both plus and minus power supplies, the LM193
series will directly interface with MOS logic where
their low power drain is a distinct advantage over
standard comparators.
•
•
•
Differential Input Voltage Range Equal to the
Power Supply Voltage
Low Output Saturation Voltage,: 250 mV at 4
mA typ
Output Voltage Compatible with TTL, DTL,
ECL, MOS and CMOS Logic Systems
ADVANTAGES
•
•
•
•
•
•
High Precision Comparators
Reduced VOS Drift Over Temperature
Eliminates Need for Dual Supplies
Allows Sensing Near Ground
Compatible with all Forms of Logic
Power Drain Suitable for Battery Operation
Squarewave Oscillator
Non-Inverting Comparator with Hysteresis
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM193JAN
SNOSAN2A –MAY 2005–REVISED MARCH 2013
www.ti.com
Schematic and Connection Diagrams
Figure 1. TO-99
Figure 2. CDIP Package
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNOSAN2A –MAY 2005–REVISED MARCH 2013
Absolute Maximum Ratings(1)
Supply Voltage, V+
Differential Input Voltage(2)
36VDC or ±18VDC
36V
Output Voltage
36V
Input Voltage
−0.3VDC to +36VDC
50 mA
(3)
Input Current (VIN< −0.3VDC
)
CDIP
400 mW @ TA = 125°C
330 mW @ TA = 125°C
175°C
Power Dissipation(4)
TO-99
Maximum Junction Temperature (TJmax
Output Short-Circuit to Ground(5)
Operating Temperature Range
Storage Temperature Range
)
Continuous
−55°C ≤ TA ≤ +125°C
−65°C ≤ TA ≤ +150°C
174°C/W
TO-99
CDIP
Metal Can (Still Air)
Metal Can (500LF/Min Air flow)
CERDIP (Still Air)
99°C/W
146°C/W
85°C/W
44°C/W
33°C/W
260°C
θJA
Thermal Resistance
CERDIP (500LF/Min Air flow)
TO-99
CDIP
θJC
Lead Temperature(Soldering, 10 seconds)
ESD Tolerance(6)
500V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
(3) This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go
to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3VDC
.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(5) Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20 mA independent of the magnitude of V+.
(6) Human body model, 1.5KΩ in series with 100pF.
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Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp°C
25
1
2
Static tests at
125
-55
25
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
5
125
-55
25
6
7
8A
8B
9
125
-55
25
10
11
12
13
14
125
-55
25
125
-55
LM193JAN Electrical Characteristics
DC Parameters
Symbol
Parameter
Conditions
Notes
Min Max
Unit
Sub-
groups
VIO
Input Offset Voltage
+VCC = 30V, -VCC = 0V,
VO = 15V
-5.0
-7.0
-5.0
-7.0
-5.0
-7.0
-5.0
-7.0
-25
-75
-25
-75
-25
-75
-25
-75
5.0
7.0
5.0
7.0
5.0
7.0
5.0
7.0
25
mV
mV
mV
mV
mV
mV
mV
mV
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
1
2, 3
1
+VCC = 2V, -VCC = -28V,
VO = -13V
2, 3
1
+VCC = 5V, -VCC = 0V,
VO = 1.4V
2, 3
1
+VCC = 2V, -VCC = -3V,
VO = -1.6V
2, 3
1, 2
3
IIO
Input offset Current
+VCC = 30V, -VCC = 0V,
VO = 15V, RS = 20KΩ
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
See(1)
75
+VCC = 2V, -VCC = -28V,
VO = -13V, RS = 20KΩ
25
1, 2
3
75
+VCC = 5V, -VCC = 0V,
VO = 1.4V, RS = 20KΩ
25
1, 2
3
75
+VCC = 2V, -VCC = -3V,
VO = -1.6V, RS = 20KΩ
25
1, 2
3
75
±IIB
Input Bias Current
+VCC = 30V, -VCC = 0V,
VO = 15V, RS = 20KΩ
-100 +0.1
-200 +0.1
-100 +0.1
-200 +0.1
-100 +0.1
-200 +0.1
-100 +0.1
-200 +0.1
1, 2
3
+VCC = 2V, -VCC = -28V,
VO = -13V, RS = 20KΩ
1, 2
3
+VCC = 5V, -VCC = 0V,
VO = 1.4V, RS = 20KΩ
1, 2
3
+VCC = 2V, -VCC = -3V,
VO = -1.6V, RS = 20KΩ
1, 2
3
(1) S/S RS = 20KΩ, tested with RS = 100KΩ for better resolution
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SNOSAN2A –MAY 2005–REVISED MARCH 2013
LM193JAN Electrical Characteristics
DC Parameters (continued)
Symbol
Parameter
Conditions
Notes
Min Max
Unit
Sub-
groups
CMRR
Input Voltage Common Mode
Rejection
2V ≤ +VCC ≤ 30V,
-28V ≤ -VCC ≤ 0V,
-13V ≤ VO ≤ 15V
76
dB
1, 2, 3
2V ≤ +VCC ≤ 5V,
-3V ≤ -VCC ≤ 0V,
-1.6V ≤ VO ≤ 1.4V
70
dB
µA
nA
1, 2, 3
1, 2, 3
1, 2, 3
ICEX
+IIL
-IIL
Output Leakage Current
Input Leakage Current
Input Leakage Current
Logical "0" Output Voltage
+VCC = 30V, -VCC = 0V,
VO = +30V
1.0
+VCC = 36V, -VCC = 0V,
+VI = 34V, -VI = 0V
-500 500
+VCC = 36V, -VCC = 0V,
+VI = 0V, -VI = 34V
-500 500
0.4
nA
V
1, 2, 3
VOL
+VCC = 4.5V, -VCC = 0V,
IO = 4mA
1
2, 3
1
0.7
V
+VCC = 4.5V, -VCC = 0V,
IO = 8mA
1.5
V
2.0
V
2, 3
1, 2
3
ICC
Power Supply Current
+VCC = 5V, -VCC = 0V,
VID = 15mV
2.0
mA
3.0
mA
+VCC = 30V, -VCC = 0V,
VID = 15mV
3.0
mA
1, 2
3
4.0
mA
ΔIO / ΔT
ΔIIO / ΔT
AVS
Temperature Coefficient of Input
Offset Voltage
25°C ≤ TA ≤ +125°C
-55°C ≤ TA ≤ 25°C
25°C ≤ TA ≤ +125°C
-55°C ≤ TA ≤ 25°C
See(2)
See(2)
See(2)
See(2)
See(3)
-25
-25
25
25
µV/°C
µV/°C
pA/°C
pA/°C
V/mV
2
3
Temperature Coefficient of Input
Offset Current
-300 300
-400 400
50
2
3
Open Loop Voltage Gain
+VCC = 15V, -VCC = 0V,
RL = 15KΩ,
1V ≤ VO ≤ 11V
4
See(3)
25
V/mV
V
5, 6
9
VLat
Voltage Latch (Logical "1" Input)
+VCC = 5V, -VCC = 0V,
VI = 10V, IO = 4mA
0.4
(2) Calculated parameter for ΔVIO / ΔT and ΔIIO / ΔT.
(3) K in datalog is equivalent to V/mV.
AC Parameters
The following conditions apply, unless otherwise specified. +VCC = 5V, −VCC = 0V
Symbol
Parameter
Conditions
Notes
Min Max
Unit
Sub-
groups
tRLH
Response Time
VI = 100mV, RL = 5.1KΩ,
VOD = 5mV
5.0
7.0
0.8
1.2
2.5
3.0
0.8
1.0
µS
µS
µS
µS
µS
µS
µS
µS
7, 8B
8A
VI = 100mV, RL = 5.1KΩ,
VOD = 50mV
7, 8B
8A
tRHL
Response Time
VI = 100mV, RL = 5.1KΩ,
VOD = 5mV
7, 8B
8A
VI = 100mV, RL = 5.1KΩ,
VOD = 50mV
7, 8B
8A
CS
Channel Separation
+VCC = 20V, -VCC = -10V,
A to B
80
80
dB
dB
7
7
+VCC = 20V, -VCC = -10V,
B to A
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Typical Performance Characteristics
Supply Current
Input Current
Figure 3.
Figure 4.
Response Time for Various Input Overdrives—Negative
Transition
Output Saturation Voltage
Figure 5.
Figure 6.
Response Time for Various Input Overdrives—Positive Transition
Figure 7.
6
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SNOSAN2A –MAY 2005–REVISED MARCH 2013
APPLICATION HINTS
The LM193 series are high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the
output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only
during the output voltage transition intervals as the comparator change states. Power supply bypassing is not
required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling.
Reducing the input resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small
amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to
stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-
output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse
waveform, with relatively fast rise and fall times, hysteresis is not required.
All input pins of any unused comparators should be tied to the negative supply.
The bias network of the LM193 series establishes a drain current which is independent of the magnitude of the
power supply voltage over the range of from 2.0 VDC to 30 VDC
.
It is usually unnecessary to use a bypass capacitor across the power supply line.
The differential input voltage may be larger than V+ without damaging the device (1). Protection should be
provided to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input clamp diode
can be used as shown in the applications section.
The output of the LM193 series is the uncommitted collector of a grounded-emitter NPN output transistor. Many
collectors can be tied together to provide an output OR'ing function. An output pull-up resistor can be connected
to any available power supply voltage within the permitted supply voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM193 package. The
output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of
current which the output device can sink is limited by the drive available (which is independent of V+) and the β
of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come
out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the
approximately 60Ω rSAT of the output transistor. The low offset voltage of the output transistor (1.0mV) allows the
output to clamp essentially to ground level for small load currents.
(1) Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
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Typical Applications
(V+=5.0 VDC
)
Basic Comparator
Driving CMOS
Driving TTL
Squarewave Oscillator
Pulse Generator
Crystal Controlled Oscillator
* For large ratios of R1/R2,
D1 can be omitted.
Figure 8. Two-Decade High Frequency VCO
V* = +30 VDC
+250 mVDC ≤ VC ≤ +50 VDC
700Hz ≤ fo ≤ 100kHz
Basic Comparator
Non-Inverting Comparator with Hysteresis
8
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SNOSAN2A –MAY 2005–REVISED MARCH 2013
Inverting Comparator with Hysteresis
Output Strobing
AND Gate
OR Gate
Large Fan-in AND Gate
Limit Comparator
Comparing Input Voltages of Opposite Polarity
ORing the Outputs
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Zero Crossing Detector (Single Power Supply)
One-Shot Multivibrator
Bi-Stable Multivibrator
One-Shot Multivibrator with Input Lock Out
Zero Crossing Detector
Comparator With a Negative Reference
10
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SNOSAN2A –MAY 2005–REVISED MARCH 2013
Figure 9. Time Delay Generator
Split-Supply Applications
(V+=+15 VDC and V−=−15 VDC
)
Figure 10. MOS Clock Driver
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REVISION HISTORY SECTION
Date Released Revision
Section
Originator
Changes
05/09/05
A
New Release. Corporate format
L. Lytle
1 MDS datasheets converted into one Corp.
datasheet format. DC Drift table was deleted
due to no JANS product offerings. MJLM193-X
Rev 1A1 MDS will be archived.
03/26/2013
A
All Sections
Changed layout of National Data Sheet to TI
format
12
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
JL193BGA
ACTIVE
TO-99
TO-99
TO-99
LMC
8
8
8
20
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
JL193BGA
JM38510/11202BGA Q
Samples
ACO
JM38510/11202BGA Q
>T
JM38510/11202BGA
M38510/11202BGA
ACTIVE
ACTIVE
LMC
LMC
20
20
Call TI
Call TI
-55 to 125
-55 to 125
JL193BGA
JM38510/11202BGA Q
Samples
Samples
ACO
JM38510/11202BGA Q
>T
JL193BGA
JM38510/11202BGA Q
ACO
JM38510/11202BGA Q
>T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
JL193BGA
LMC
LMC
LMC
TO-CAN
TO-CAN
TO-CAN
8
8
8
20
20
20
2 X 10
2 X 10
2 X 10
150
150
150
126.49 61.98 8890 11.18 12.95 18.54
126.49 61.98 8890 11.18 12.95 18.54
126.49 61.98 8890 11.18 12.95 18.54
JM38510/11202BGA
M38510/11202BGA
Pack Materials-Page 1
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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