JM38510/50402BRA [TI]
标准高速 PAL
| 型号： | JM38510/50402BRA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 标准高速 PAL |
| 文件： | 总15页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
PAL16L8’
J OR W PACKAGE
•
Choice of Operating Speeds
High-Speed, A Devices . . . 25 MHz Min
Half-Power, A-2 Devices . . . 16 MHz Min
(TOP VIEW)
•
•
Choice of Input/Output Configuration
I
I
I
I
I
I
I
I
I
V
1
2
3
4
5
6
7
8
9
10
20
19
18
CC
Package Options Include Both Ceramic DIP
and Chip Carrier in Addition to Ceramic
Flat Package
O
I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
I/O
PORT
S
I
3-STATE
REGISTERED
Q OUTPUTS
DEVICE
INPUTS O OUTPUTS
PAL16L8
PAL16R4
PAL16R6
PAL16R8
10
8
2
0
0
0
0
6
4
2
0
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
12
11
O
I
8
GND
8
description
PAL16L8’
FK PACKAGE
These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices. They combine Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high-performance substitutes for
(TOP VIEW)
3
2 1 20 19
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
conventional
TTL
logic.
Their
easy
18
17
16
15
14
4
5
6
7
8
programmabilityallowforquickdesignof”custom”
functions and typically results in a more compact
circuit board. In addition, chip carriers are
available for further reduction in board space.
9 10 11 12 13
The Half-Power versions offer a choice of
operating frequency, switching speeds, and
power dissipation. In many cases, these
Half-Power devices can result in significant power
reduction from an overall system level.
The PAL16’ M series is characterized for
operation over the full military temperature range
of –55°C to 125°C.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1992, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
PAL16R4AM, PAL16R4A-2M, PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
PAL16R4’
PAL16R4’
J OR W PACKAGE
FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
CC
I
I
I
I
I
I
I
I
I/O
I/O
Q
Q
Q
3
2
1
20 19
18
I/O
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
Q
Q
Q
Q
13 I/O
12 I/O
11 OE
9 10 11 12 13
GND
PAL16R6’
PAL16R6’
J OR W PACKAGE
FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
CC
I
I
I
I
I
I
I
I
I/O
Q
Q
Q
Q
Q
Q
3
2
1
20 19
18
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
12 I/O
11 OE
GND
PAL16R8’
PAL16R8’
J OR W PACKAGE
FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
CC
I
I
I
I
I
I
I
I
Q
Q
Q
Q
Q
Q
Q
Q
3
2
1
20 19
18
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
11 OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
functional block diagrams (positive logic)
PAL16L8AM
PAL16L8A-2M
≥1
&
EN
O
7
32 X 64
O
7
7
7
7
7
7
7
16 x
I/O
I/O
I/O
I/O
I/O
I/O
10
16
16
I
6
6
PAL16R4AM
PAL16R4A-2M
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
2
32 X 64
1D
8
8
8
16 x
8
16
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
16
7
7
7
4
4
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
functional block diagrams (positive logic)
PAL16R6AM
PAL16R6A-2M
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
2
8
8
8
8
8
8
32 X 64
1D
16 x
8
16
16
I
6
2
≥1
EN
7
7
2
I/O
I/O
6
PAL16R8AM
PAL16R8A-2M
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
32 X 64
1D
8
8
8
8
8
8
8
16 x
8
16
16
I
8
8
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
PAL16L8AM, PAL16L8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
logic diagram (positive logic)
1
I
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I/O
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
12
11
O
I
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PAL16R4AM, PAL16R4A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
First
Fuse
Numbers
0
4
8
12
16
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
I/O
Q
128
160
192
224
2
I
256
288
320
352
384
416
448
480
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
C1
768
800
832
864
896
928
960
992
I = 0
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I/O
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
PAL16R6AM, PAL16R6A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I = 0
1D
Q
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
Q
C1
768
800
832
864
896
928
960
992
I = 0
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 0
1D
Q
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
First
Fuse
Numbers
0
4
8
12
16
20
24
28
31
0
32
64
96
128
160
192
I = 0
1D
19
18
17
16
15
14
13
Q
Q
Q
Q
Q
Q
Q
C1
224
2
I
256
288
320
352
384
416
448
480
I = 0
1D
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
C1
768
800
832
864
896
928
960
992
I = 0
1D
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 0
1D
C1
1792
1824
1856
1888
1920
1952
1984
2016
I = 0
1D
12
11
Q
C1
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
–2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
V
IL
I
I
mA
mA
°C
OH
OL
12
T
A
–55
25
125
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
PAL16L8AM, PAL16R4AM, PAL16R6AM, PAL16R8AM
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –2 mA
= 12 mA
2.4
3.2
OH
OL
OH
OL
I
0.25
0.4
20
Outputs
I/O ports
Outputs
I/O ports
I
V
= 5.5 V,
V
= 2.7 V
= 0.4 V
µA
OZH
CC
O
100
–20
–100
0.2
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
O
µA
mA
µA
OZL
V = 5.5 V
I
I
I/O Ports
All others
OE input
All others
100
25
V = 2.7 V
I
IH
–0.2
–0.1
–250
180
mA
V
= 5.5 V,
V = 0.4 V
I
I
IL
CC
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.5 V
O
–30
mA
mA
OS
CC
V = 0,
I
Outputs open
75
CC
CC
timing requirements
MIN
0
MAX
UNIT
f
t
Clock Frequency
25
MHz
clock
Clock high
Clock low
15
20
25
0
w
Pulse duration (see Note 2)
ns
t
t
Setup time, input or feedback before CLK↑
Hold time, input or feedback after CLK↑
ns
ns
su
h
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f
only for clock high or low, but not for both simultaneously.
. The minimum pulse durations specified are
clock
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
f
t
25
45
15
10
15
10
14
13
MHz
ns
max
pd
I, I/O
O, I/O
30
20
25
25
30
30
t
t
t
t
t
CLK↑
OE↓
OE↑
I, I/O
I, I/O
Q
Q
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 1
ns
pd
en
dis
en
dis
ns
Q
ns
O, I/O
O, I/O
ns
ns
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V at 0.5 V to avoid
test equipment degradation.
O
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
PAL16L8A-2M, PAL16R4A-2M, PAL16R6A-2M, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –2 mA
= 12 mA
2.4
3.2
OH
OL
OH
OL
I
0.25
0.4
20
Outputs
I/O ports
Outputs
I/O ports
I
V
= 5.5 V,
V
= 2.7 V
= 0.4 V
µA
OZH
CC
O
100
–20
–100
0.2
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
O
µA
mA
µA
OZL
V = 5.5 V
I
I
I/O Ports
All others
OE input
All others
100
25
V = 2.7 V
I
IH
–0.2
–0.1
–250
90
mA
V
= 5.5 V,
V = 0.4 V
I
I
IL
CC
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.5 V
O
–30
mA
mA
OS
CC
V = 0,
I
Outputs open
75
CC
CC
timing requirements
MIN
0
MAX
UNIT
f
t
Clock Frequency
16
MHz
clock
Clock high
Clock low
25
25
35
0
w
Pulse duration (see Note 2)
ns
t
t
Setup time, input or feedback before CLK↑
Hold time, input or feedback after CLK↑
ns
ns
su
h
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f
only for clock high or low, but not for both simultaneously.
. The minimum pulse durations specified are
clock
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
f
t
16
25
25
11
20
11
25
25
MHz
ns
max
pd
I, I/O
O, I/O
40
25
25
25
40
35
t
t
t
t
t
CLK↑
OE↓
OE↑
I, I/O
I, I/O
Q
Q
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 1
ns
pd
en
dis
en
dis
ns
Q
ns
O, I/O
O, I/O
ns
ns
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V at 0.5 V to avoid
test equipment degradation.
O
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
3 V
0
Timing
Input
High-Level
1.5 V
1.5 V 1.5 V
Pulse
t
t
w
h
t
su
3 V
0
Data
Input
3 V
0
1.5 V
1.5 V
Low-Level
Pulse
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
3 V
0
Output
Control
(low-level
enabling)
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
0
pd
t
pd
pd
t
en
V
OH
t
dis
In-Phase
Output
1.5 V
1.5 V
1.5 V
≈ 3.3 V
OL
V
OL
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+ 0.5 V
t
pd
t
V
OL
V
OH
OL
t
Out-of-Phase
Output
(see Note D)
dis
1.5 V
t
en
V
V
V
≈ 0 V
OH
Waveform 2
S1 Open
(see Note B)
1.5 V
– 0.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
OH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, t and t ≤ 2 ns, duty cycle = 50%
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
SRPS016
PACKAGE OPTION ADDENDUM
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4-Mar-2005
PACKAGING INFORMATION
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Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
FK
J
81036072A
8103607RA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
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8103608RA
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81036092A
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8103609RA
8103609SA
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FK
J
81036102A
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CDIP
CFP
8103610RA
8103610SA
W
FK
J
81036112A
LCCC
CDIP
CFP
8103611RA
8103611SA
W
FK
J
81036122A
LCCC
CDIP
CFP
8103612RA
8103612SA
W
FK
J
81036132A
LCCC
CDIP
CFP
8103613RA
8103613SA
W
FK
J
81036142A
LCCC
CDIP
CFP
8103614RA
8103614SA
W
FK
J
PAL16L8A-2MFKB
PAL16L8A-2MJ
PAL16L8A-2MJB
PAL16L8A-2MWB
PAL16L8AMFKB
PAL16L8AMJ
PAL16L8AMJB
PAL16L8AMWB
PAL16R4A-2MFKB
PAL16R4A-2MJ
PAL16R4A-2MJB
PAL16R4A-2MWB
PAL16R4AMFKB
PAL16R4AMJ
PAL16R4AMJB
PAL16R4AMWB
PAL16R6A-2MFKB
PAL16R6A-2MJ
LCCC
CDIP
CDIP
CFP
J
W
FK
J
LCCC
CDIP
CDIP
CFP
J
W
FK
J
LCCC
CDIP
CDIP
CFP
J
W
FK
J
LCCC
CDIP
CDIP
CFP
J
W
FK
J
LCCC
CDIP
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PACKAGE OPTION ADDENDUM
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Orderable Device
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Package Package
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Qty
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PAL16R6A-2MJB
PAL16R6A-2MWB
PAL16R6AMFKB
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ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
W
FK
J
20
20
20
20
20
20
20
20
20
20
20
20
20
20
1
1
1
1
1
1
1
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1
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LCCC
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PAL16R6AMJB
PAL16R6AMWB
PAL16R8A-2MFKB
PAL16R8A-2MJ
PAL16R8A-2MJB
PAL16R8A-2MWB
PAL16R8AMFKB
PAL16R8AMJ
J
W
FK
J
LCCC
CDIP
CDIP
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J
W
FK
J
LCCC
CDIP
CDIP
CFP
PAL16R8AMJB
PAL16R8AMWB
J
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
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Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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