JM54AC377BRA-RH [TI]
AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20;
| 型号： | JM54AC377BRA-RH |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1999
54AC377 • 54ACT377
Octal D Flip-Flop with Clock Enable
n Ideal for addressable register applications
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
General Description
The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
n Outputs source/sink 24 mA
n See ’273 for master reset version
n See ’373 for transparent latch version
n See ’374 for TRI-STATE® version
n ’ACT377 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC377: 5962-88702
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n ICC reduced by 50%
— ’ACT377: 5962-87697
Logic Symbols
IEEE/IEC
DS100290-1
DS100290-2
Pin
Description
Names
D0–D7
CE
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Q0–Q7
CP
Clock Pulse Input
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100290
www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100290-4
DS100290-3
Mode Select-Function Table
Operating Mode
Inputs
Outputs
CP
N
N
N
CE
L
Dn
H
L
Qn
Load ‘1’
H
L
Load ‘0’
L
Hold (Do Nothing)
H
H
X
No Change
No Change
X
X
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
N =
LOW-to-HIGH Clock Transition
Logic Diagram
DS100290-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
175˚C
Note 2: See individual datasheets for those devices which differ from the
typical input rise and fall times noted here.
DC Characteristics for ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 3)
=
VIN VIL or VIH
=
IOH −12 mA
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
=
IOH −24 mA
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 3)
=
VIN VIL or VIH
=
IOL 12 mA
3.0
4.5
5.5
5.5
0.50
0.50
0.50
=
IOL 24 mA
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
1.0
µA
VI VCC, GND
3
www.national.com
DC Characteristics for ’AC Family Devices (Continued)
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
50
=
VOLD 1.65V Max
IOLD
(Note 4)
5.5
mA
Minimum Dynamic
Output Current
=
VOHD 3.85V Min
IOHD
ICC
5.5
5.5
−50
mA
µA
=
Maximum Quiescent
Supply Current
80.0
VIN VCC
or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 5:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54AC 25˚C is identical to 74AC 25˚C.
CC
DC Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 6)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 6)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.50
0.50
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum
1.0
µA
mA
mA
VI VCC, GND
=
VI VCC − 2.1V
ICCT
5.5
5.5
1.6
I
CC/Input
=
VOLD 1.65V Max
IOLD
(Note 7)
50
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
=
VOHD 3.85V Min
IOHD
ICC
5.5
5.5
−50
mA
µA
=
80.0
VIN VCC
or GND
*
Note 6: All outputs loaded; thresholds on input associated with output under test.
†
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACT 25˚C is identical to 74ACT 25˚C.
CC
Note 8:
I
www.national.com
4
AC Electrical Characteristics
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 9)
Min
75
Max
fmax
tPLH
tPHL
Maximum Clock
Frequency
3.3
5.0
3.3
5.0
3.3
5.0
MHz
ns
95
Propagation Delay
CP to Qn
1.0
1.5
1.0
1.5
14.0
10.0
15.0
11.0
Propagation Delay
CP to Qn
ns
±
Note 9: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note 10)
CL 50 pF
Guaranteed
Minimum
7.5
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
ns
ns
ns
ns
ns
6.0
th
ts
th
tw
Hold Time, HIGH or LOW
Dn to CP
1.5
2.5
Setup Time, HIGH or LOW
CE to CP
9.5
6.0
Hold Time, HIGH or LOW
CE to CP
1.0
2.0
CP Pulse Width
HIGH or LOW
6.5
5.0
±
Note 10: Voltage Range 3.3 is 3.0V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
54ACT
=
VCC
(V)
TA −55˚C
Fig.
Symbol
Parameter
to +125˚C
Units
No.
=
CL 50 pF
(Note 11)
Min
Max
fmax
tPLH
tPHL
Maximum Clock
Frequency
5.0
5.0
5.0
85
MHz
ns
Propagation Delay
CP to Qn
1.5
1.5
11.0
12.0
Propagation Delay
CP to Qn
ns
±
Note 11: Voltage Range 5.0 is 5.0V 0.5V
5
www.national.com
AC Operating Requirements
54ACT
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note
12)
CL 50 pF
Guaranteed
Minimum
7.0
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
th
ts
th
tw
Hold Time, HIGH or LOW
Dn to CP
1.0
7.0
1.0
5.5
Setup Time, HIGH or LOW
CE to CP
Hold Time, HIGH or LOW
CE to CP
CP Pulse Width
HIGH or LOW
±
Note 12: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
=
VCC 5.0V
CPD
90.0
pF
www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
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Email: support@nsc.com
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Products > Military/Aerospace > Logic > FACT AC > 54AC377
54AC377 Product Folder
Octal D Flip-Flop with Clock Enable
General
Description
Package
& Models
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& Pricing
Features
Datasheet
Datasheet
Title
Size in Kbytes Date
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54AC377 54ACT377 Octal D Flip-
Flop with Clock Enable
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177 Kbytes
15 Kbytes
2-Feb-99
54AC377 Mil-Aero Datasheet
MN54AC377-X
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Package Availability, Models, Samples & Pricing
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Models
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SPICE IBIS
Qty $US each
[logo]¢Z¢S¢4¢A
54AC377
LMQB /Q¢M$E
5962-
rail
of
50
5962-88702012A
(54AC377LMQB)
Full
production
LCC
MSL
20
N/A
N/A
50+ $11.0000
Buy Now
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88702012A
[logo]¢Z¢S¢4¢A$E
54AC377DMQB
/Q¢M
rail
of
20
5962-8870201RA
(54AC377DMQB)
Full
production
CERDIP
CERPACK
LCC
MSL
MSL
MSL
20
20
20
N/A
N/A
N/A
N/A
N/A
N/A
50+ $8.6000
50+ $11.0000
5962-8870201RA
[logo]¢Z¢S¢4¢A$E
54AC377FMQB
Q¢M 5962-
rail
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19
5962-8870201SA
(54AC377FMQB)
Full
production
8870201SA
[logo] JM38510
R75603B2A
27014 QS
rail
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N/A
JM54AC377B2A-
RH
Full
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¢Z¢S¢4¢A$E
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/75603B2A
27014 QS
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rail
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50
Full
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LCC
MSL
MSL
JM38510/75603B2
20
20
N/A
N/A
N/A
N/A
50+ $13.6000
rail [logo]¢Z¢S¢4¢A$E
of JM38510R75603BRA
JM54AC377BRA-
RH
Full
production
CERDIP
N/A
27014 QS
[logo]¢Z¢S¢4¢A$E
JM38510/
rail
of
19
Full
production
CERPACK
CERPACK
MSL
MSL
JM38510/75603BS
R75603BSA
20
20
N/A
N/A
N/A
N/A
50+ $13.6000
50+ $73.0000
75603BSA
27014 QS
[logo]¢Z¢S¢4¢A$E
JM38510R
rail
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19
Full
production
75603BSA
27014 QS
[logo]¢Z¢S¢4¢A
27014 Q$E
JM38510R
rail
of
N/A
JM54AC377S2A-
RH
Full
production
LCC
MSL
MSL
MSL
20
20
20
N/A
N/A
N/A
N/A
N/A
75603S2A
rail [logo]¢Z¢S¢4¢A$E
of JM38510R75603SRA
JM54AC377SRA-
RH
Full
production
CERDIP
CERPACK
N/A
27014 Q
[logo]¢Z¢S¢4¢A$E
RM54AC377
SSA WAFER #
¢R
rail
of
N/A
RM54AC377SSA
Preliminary N/A
rail [logo]¢Z¢S¢4¢A$E
Full
N/A
CERPACK
CERPACK
MSL
MSL
JM38510/75603SS
JM38510R75603SS
20
20
N/A
N/A
50+ $138.0000 of
19
27014 JM38510/
75603SSA Q
production
rail [logo]¢Z¢S¢4¢A$E
Full
N/A
50+ $138.0000 of
19
27014 JM38510R
75603SSA Q
production
General Description
The 'AC/'ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The
common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one
setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Features
●
ICC reduced by 50%
●
●
●
●
●
●
●
●
●
●
Ideal for addressable register applications
Clock enable for address and data synchronization applications
Eight edge-triggered D flip-flops
Buffered common clock
Outputs source/sink 24 mA
See '273 for master reset version
See '373 for transparent latch version
See '374 for TRI-STATE version
'ACT377 has TTL-compatible inputs
Standard Microcircuit Drawing (SMD) -'AC377: 5962-88702 -'ACT377: 5962-87697
[Information as of 5-Aug-2002]
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