LF442883 [TI]
LF442QML Dual Low Power JFET Input Operational Amplifier; LF442QML双路低功耗JFET输入运算放大器
| 型号： | LF442883 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LF442QML Dual Low Power JFET Input Operational Amplifier |
| 文件： | 总18页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LF442QML
LF442QML Dual Low Power JFET Input Operational Amplifier
Literature Number: SNOSAO8
December 16, 2010
LF442QML
Dual Low Power JFET Input Operational Amplifier
General Description
Features
The LF442 dual low power operational amplifier provides
many of the same AC characteristics as the industry standard
LM1458 while greatly improving the DC characteristics of the
LM1458. The amplifier has the same bandwidth, slew rate,
and gain (10 kΩ load) as the LM1458 and only draws one
tenth the supply current of the LM1458. In addition the well
matched high voltage JFET input devices of the LF442 reduce
the input bias and offset currents by a factor of 10,000 over
the LM1458. A combination of careful layout design and in-
ternal trimming guarantees very low input offset voltage and
voltage drift. The LF442 also has a very low equivalent input
noise voltage for a low power amplifier.
1/10 supply current of a LM1458:ꢀ 400 μA (max)
Low input bias current: 50 pA (Typ)
Low input offset voltage: 1 mV (Typ)
Low input offset voltage drift:ꢀ7 μV/°C (Typ)
High gain bandwidth: 1 MHz (Typ)
High slew rate: 1 V/μs (Typ)
■
■
■
■
■
■
■
■
■
Low noise voltage for low power:
(Typ)
Low input noise current:
(Typ)
High input impedance: 1012Ω
The LF442 is pin compatible with the LM1458 allowing an im-
mediate 10 times reduction in power drain in many applica-
tions. The LF442 should be used where low power dissipation
and good electrical characteristics are the major considera-
tions.
Ordering Information
NS Paart Number
SMD Part Number
NS Package Number
Package Description
LF442MH/883
5962-9763301QGA
H08C
8LD T0–99 Metal Can
Typical Connection
Connection Diagram
Metal Can Package
20149402
Pin 4 connected to case
Top View
See NS Package Number H08C
20149401
BI-FET II™ is a trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
201494
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Simplified Schematic
1/2 Dual
20149403
Detailed Schematic
1/2 Dual
20149416
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2
Absolute Maximum Ratings (Note 1)
Supply Voltage
±18V
±30V
±15V
Differential Input Voltage
Input Voltage Range (Note 3)
Output Short Circuit Duration (Note 4)
Maximum Power Dissipation (Note 2)
TJ max
Continuous
900mW
150°C
Thermal Resistance
ꢀꢀθJA
Still Air
500LF/Min Air flow
161°C/W
87°C/W
33°C/W
ꢀꢀθJC
Operating Temperature Range
−55°C ≤ TA ≤ 125°C
Storage Temperature Range
−65°C ≤ TA ≤ 150°C
Lead Temperature (Soldering, 10 sec.)
260°C
ESD Tolerance (Note 5)
500V
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp (°C)
1
2
+25
+125
-55
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
+125
-55
5
6
7
+25
+125
-55
8A
8B
9
+25
+125
-55
10
11
12
13
14
+25
+125
-55
3
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LF442 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified. VS = ±15V, VCM = 0V, RS = 0Ω
Sub-
groups
Symbol
ICC
Parameter
Supply Current
Conditions
Notes
Min Max
Unit
500
µA
mV
mV
nA
nA
nA
nA
dB
1, 2, 3
-5.0
-7.5
5.0
7.5
0.1
20
1
VIO
±IIB
Input Offset Voltage
Input Bias Current
Input Offset Current
RS = 10KΩ
2, 3
1
2
-0.05 0.05
1
2
IIO
-10
70
10
CMRR
Common Mode Rejection Ratio VCM = ±11V, RS = 10K
VS+ = +15V to +6V,
VS- = -15V
Power Supply Rejection Ratio
VS- = -15V to -6V,
1, 2, 3
70
70
dB
dB
1, 2, 3
1, 2, 3
PSRR
VS+ = +15V
VO = 0V to +10V,
Large Signal Voltage Gain
25
15
25
15
12
V/mV
V/mV
V/mV
V/mV
V
4
+AVS
-AVS
(Note 7)
(Note 7)
RL = 10KΩ
5, 6
VO = 0V to -10V,
Large Signal Voltage Gain
4
RL = 10KΩ
5, 6
+
VO
Output Voltage Swing
Output Voltage Swing
VI = ±11V, RL = 10K
VI = ±11V, RL = 10K
4, 5, 6
4, 5, 6
-
VO
-12
-11
V
Input Common Mode Voltage
Range
VCM
(Note 6)
11
V
4, 5, 6
AC Parameters
The following conditions apply, unless otherwise specified. VS = ±15V, VCM = 0V, RS = 0Ω
Sub-
groups
Symbol
SR+
Parameter
Conditions
Notes
Min Max
Unit
VO = -5V to +5V, AV = 1,
Slew Rate
Slew Rate
0.6
V/µS
7
RL = 2KΩ, CL - 100pF
VO = +5V to -5V,
AV = 1, RL = 2KΩ,
CL - 100pF
SR-
0.6
0.6
V/µS
MHz
7
7
GBW
Gain Band Width
VI = 50mV, ƒ = 20KHz
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction
temperature will be exceeded.
Note 5: Human Body Model, 100pF discharged through 1.5KΩ
Note 6: Parameter tested go-no-go only, guaranteed by CMRR test..
Note 7: V/mV in units column is equivalent to K in datalog.
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4
Typical Performance Characteristics
Input Bias Current
Input Bias Current
20149418
20149417
Supply Current
Positive Common-Mode
Input Voltage Limit
20149419
20149420
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
20149422
20149421
5
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Negative Current Limit
Output Voltage Swing
20149423
20149424
Output Voltage Swing
Gain Bandwidth
20149425
20149426
Bode Plot
Slew Rate
20149427
20149428
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Distortion vs Frequency
Undistorted Output Voltage
Swing
20149429
20149430
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
20149431
20149432
Power Supply Rejection
Ratio
Equivalent Input Noise
Voltage
20149434
20149433
7
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Open Loop Voltage Gain
Output Impedance
20149435
20149436
Inverter Settling Time
20149437
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Pulse Response
RL = 10 kΩ, CL = 10 pF
Small Signal Inverting
Small Signal Non-Inverting
20149407
20149408
Large Signal Inverting
Large Signal Non-Inverting
20149409
20149410
9
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than these may degrade the common-mode rejection and re-
strict the output voltage swing.
Application Hints
This device is a dual low power op amp with internally trimmed
input offset voltages and JFET input devices (BI-FET II).
These JFETs have large reverse breakdown voltages from
gate to source and drain eliminating the need for clamps
across the inputs. Therefore, large differential input voltages
can easily be accommodated without a large increase in input
current. The maximum differential input voltage is indepen-
dent of the supply voltages. However, neither of the input
voltages should be allowed to exceed the negative supply as
this will cause large currents to flow which can result in a de-
stroyed unit.
The amplifiers will drive a 10 kΩ load resistance to ± 10V over
the full temperature range.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead dress,
component placement and supply decoupling in order to en-
sure stability. For example, resistors from the output to an
input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a re-
versal of phase to the output. Exceeding the negative com-
mon-mode limit on both inputs will force the amplifier output
to a high state. In neither case does a latch occur since raising
the input back within the common-mode range again puts the
input stage and thus the amplifier in a normal operating mode.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3 dB
frequency of the closed loop gain and consequenty there is
negligible effect on stability margin. However, if the feedback
pole is less than approximately 6 times the expected 3 dB
frequency a lead capacitor should be placed from the output
to the input of the op amp. The value of the added capacitor
should be such that the RC time constant of this capacitor and
the resistance it parallels is greater than or equal to the orig-
inal feedback pole time constant.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both inputs
exceed the limit, the output of the amplifier will be forced to a
high state.
The amplifiers will operate with a common-mode input voltage
equal to the positive supply; however, the gain bandwidth and
slew rate may be decreased in this condition. When the neg-
ative common-mode voltage swings to within 3V of the neg-
ative supply, an increase in input offset voltage may occur.
Each amplifier is individually biased to allow normal circuit
operation with power supplies of ±3.0V. Supply voltages less
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Typical Applications
Battery Powered Strip Chart Preamplifier
20149411
Runs from 9v batteries (±9V supplies)
Fully settable gain and time constant
Battery powered supply allows direct plug-in interface to strip chart recorder without common-mode problems
“No FET” Low Power V→F Converter
20149412
Trim 1M pot for 1 kHz full-scale output
15 mW power drain
No integrator reset FET required
Mount D1 and D2 in close proximity
1% linearity to 1 kHz
11
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High Efficiency Crystal Oven Controller
20149413
Tcontrol= 75°C
—
—
—
—
—
A1's output represents the amplified difference between the LM335 temperature sensor and the crystal oven's temperature
A2, a free running duty cycle modulator, drives the LM395 to complete a servo loop
Switched mode operation yields high efficiency
1% metal film resistor
Conventional Log Amplifier
20149414
RT = Tel Labs type Q81
Trim 5k for 10 μA through the 5k–120k combination
*1% film resistor
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12
Unconventional Log Amplifier
20149415
Q1, Q2, Q3 are included on LM389 amplifier chip which is temperature-stabilized by the LM389 and Q2-Q3, which act as a heater-sensor pair.
Q1, the logging transistor, is thus immune to ambient temperature variation and requires no temperature compensation at all.
13
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Revision History
Date Released
Revision
Section
Changes
12/16/2010
A
New release to corporate format
1 MDS datasheet converted into one corporate
datasheet format. MNLF442M-X Rev 0A1 will be
archived.
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14
Physical Dimensions inches (millimeters) unless otherwise noted
8 LD TO-99 Metal Can (H)
NS Package Number H08C
15
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