LF442 [TI]
Dual Low Power JFET Input Operational Amplifier;
| 型号： | LF442 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Low Power JFET Input Operational Amplifier |
| 文件： | 总20页 (文件大小：925K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LF442
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
LF442 Dual Low Power JFET Input Operational Amplifier
Check for Samples: LF442
1
FEATURES
DESCRIPTION
The LF442 dual low power operational amplifiers
provide many of the same AC characteristics as the
industry standard LM1458 while greatly improving the
DC characteristics of the LM1458. The amplifiers
have the same bandwidth, slew rate, and gain (10 kΩ
load) as the LM1458 and only draw one tenth the
supply current of the LM1458. In addition the well
matched high voltage JFET input devices of the
LF442 reduce the input bias and offset currents by a
factor of 10,000 over the LM1458. A combination of
careful layout design and internal trimming ensures
very low input offset voltage and voltage drift. The
LF442 also has a very low equivalent input noise
voltage for a low power amplifier.
2
•
•
•
•
•
•
•
•
•
•
1/10 Supply Current of a LM1458: 400 μA (max)
Low Input Bias Current: 50 pA (max)
Low Input Offset Voltage: 1 mV (max)
Low Input Offset Voltage Drift: 10 μV/°C (max)
High Gain Bandwidth: 1 MHz
High Slew Rate: 1 V/μs
Low Noise Voltage for Low Power: 35 nV/√Hz
Low Input Noise Current: 0.01 pA/√Hz
High Input Impedance: 1012Ω
High Gain VO = ±10V, RL = 10k: 50k (min)
The LF442 is pin compatible with the LM1458
allowing an immediate 10 times reduction in power
drain in many applications. The LF442 should be
used where low power dissipation and good electrical
characteristics are the major considerations.
Typical Connection
Connection Diagrams
Pin 4 connected to case
PDIP Package Top View
Package Number P0008E
TO Package Top View
Package Number LMC0008C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LF442
SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
LF442A
±22V
LF442
±18V
Supply Voltage
Differential Input Voltage
Input Voltage Range(3)
Output Short Circuit Duration(4)
±38V
±30V
±19V
±15V
Continuous
Continuous
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) Refer to RETS442X for LF442MH military specifications.
(3) Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
(4) Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the
maximum junction temperature will be exceeded.
ABSOLUTE MAXIMUM RATINGS(1)(2)
LMC0008C Package
150°C
P0008E Package
115°C
Tj max
θJA (Typical)
See(3)
See(4)
65°C/W
114°C/W
165°C/W
152°C/W
θJC (Typical)
21°C/W
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
ESD Tolerance
See(5)(4)
See(5)(4)
−65°C≤TA≤150°C
260°C
−65°C≤TA≤150°C
260°C
Rating to be determined
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) Refer to RETS442X for LF442MH military specifications.
(3) The value given is in 400 linear feet/min air flow.
(4) The value given is in static air.
(5) These devices are available in both the commercial temperature range 0°C ≤ TA ≤ 70°C and the military temperature range −55°C ≤ TA
≤ 125°C. The temperature range is designated by the position just before the package type in the device number. A “C” indicates the
commercial temperature range and an “M” indicates the military temperature range. The military temperature range is available in “H”
package only.
2
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
DC Electrical Characteristics(1)(2)
LF442A
Typ
LF442
Typ
Symbol
VOS
Parameter
Conditions
Units
Min
Max Min
Max
5.0
Input Offset Voltage
RS = 10 kΩ, TA = 25°C
Over Temperature
RS = 10 kΩ
0.5
1.0
1.0
mV
mV
7.5
ΔVOS/ΔT
Average TC of Input Offset
Voltage
7
5
10
7
5
μV/°C
IOS
Input Offset Current
VS = ±15V(1)(3)
VS = ±15V(1)(3)
Tj = 25°C
Tj = 25°C
25
1.5
10
50
3
50
pA
nA
nA
pA
nA
nA
Ω
Tj = 70°C
Tj = 125°C
Tj = 25°C
Tj = 70°C
Tj = 125°C
1.5
IB
Input Bias Current
10
10
100
3
20
RIN
Input Resistance
1012
200
1012
200
AVOL
Large Signal Voltage Gain
VS = ±15V, VO = ±10V,
RL = 10 kΩ, TA = 25°C
50
25
V/mV
Over Temperature
25
200
±13
+18
−17
15
200
±13
+14
−12
V/mV
VO
Output Voltage Swing
Input Common-Mode
Voltage Range
VS = ±15V, RL = 10 kΩ
±12
±16
±12
±11
V
V
V
VCM
CMRR
PSRR
IS
Common-Mode Rejection
Ratio
R
S ≤ 10 kΩ
80
80
100
70
95
dB
Supply Voltage Rejection
Ratio
See(4)
100
300
70
90
dB
Supply Current
400
400
500
μA
(1) Unless otherwise specified, the specifications apply over the full temperature range and for VS = ±20V for the LF442A and for VS = ±15V
for the LF442. VOS, IB, and IOS are measured at VCM = 0.
(2) Refer to RETS442X for LF442MH military specifications.
(3) The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature,
Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the
junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj = TA + θjAPD where θjA is the
thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
(4) Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with
common practice from ±15V to ±5V for the LF442 and ±20V to ±5V for the LF442A.
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Units
AC Electrical Characteristics(1)(2)
LF442A
Typ
LF442
Typ
Symbol
Parameter
Conditions
Min
Max Min
Max
Amplifier to Amplifier Coupling TA = 25°C, f = 1 Hz-20 kHz (Input
Referred)
−120
−120
dB
SR
Slew Rate
VS = ±15V, TA = 25°C
VS = ±15V, TA = 25°C
0.8
0.8
1
1
0.6
0.6
1
1
V/μs
MHz
GBW
en
Gain-Bandwidth Product
Equivalent Input Noise Voltage TA = 25°C, RS = 100Ω, f = 1 kHz
35
0.01
35
0.01
nV/√Hz
pA/√Hz
in
Equivalent Input Noise Current TA = 25°C, f = 1 kHz
(1) Unless otherwise specified, the specifications apply over the full temperature range and for VS = ±20V for the LF442A and for VS = ±15V
for the LF442. VOS, IB, and IOS are measured at VCM = 0.
(2) Refer to RETS442X for LF442MH military specifications.
SIMPLIFIED SCHEMATIC
1/2 Dual
4
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Typical Performance Characteristics
Input Bias Current
Input Bias Current
Figure 1.
Figure 2.
Positive Common-Mode
Input Voltage Limit
Supply Current
Figure 3.
Figure 4.
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
Figure 5.
Figure 6.
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Typical Performance Characteristics (continued)
Negative Current Limit
Output Voltage Swing
Figure 7.
Figure 8.
Output Voltage Swing
Gain Bandwidth
Figure 9.
Figure 10.
Slew Rate
Bode Plot
Figure 11.
Figure 12.
6
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
Typical Performance Characteristics (continued)
Distortion
vs
Frequency
Undistorted Output Voltage
Swing
Figure 13.
Figure 14.
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
Figure 15.
Figure 16.
Power Supply Rejection
Ratio
Equivalent Input Noise
Voltage
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
Open Loop Voltage Gain
Output Impedance
Figure 19.
Figure 20.
Inverter Settling Time
Figure 21.
8
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Typical Performance Characteristics (continued)
Pulse Response
RL = 10 kΩ, CL = 10 pF
Small Signal Inverting
Small Signal Non-Inverting
Figure 22.
Figure 23.
Large Signal Inverting
Large Signal Non-Inverting
Figure 24.
Figure 25.
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
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APPLICATION HINTS
This device is a dual low power op amp with internally trimmed input offset voltages and JFET input devices (BI-
FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need
for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a
large increase in input current. The maximum differential input voltage is independent of the supply voltages.
However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large
currents to flow which can result in a destroyed unit.
Exceeding the negative common-mode limit on either input will force the output to a high state, potentially
causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force
the amplifier output to a high state. In neither case does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if
both inputs exceed the limit, the output of the amplifier will be forced to a high state.
The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain
bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings
to within 3V of the negative supply, an increase in input offset voltage may occur.
Each amplifier is individually biased to allow normal circuit operation with power supplies of ±3.0V. Supply
voltages less than these may degrade the common-mode rejection and restrict the output voltage swing.
The amplifiers will drive a 10 kΩ load resistance to ± 10V over the full temperature range.
Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in
polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through
the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed
unit.
As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the output to an input should be placed with the body close
to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the
capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.
In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed
loop gain and consequenty there is negligible effect on stability margin. However, if the feedback pole is less
than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the
input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor
and the resistance it parallels is greater than or equal to the original feedback pole time constant.
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
Typical Applications
Battery Powered Strip Chart Preamplifier
Runs from 9v batteries (±9V supplies)
Fully settable gain and time constant
Battery powered supply allows direct plug-in interface to strip chart recorder without common-mode problems
“No FET” Low Power V→F Converter
Trim 1M pot for 1 kHz full-scale output
15 mW power drain
No integrator reset FET required
Mount D1 and D2 in close proximity
1% linearity to 1 kHz
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
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High Efficiency Crystal Oven Controller
•
•
Tcontrol= 75°C
A1's output represents the amplified difference between the LM335 temperature sensor and the crystal oven's
temperature
•
•
•
A2, a free running duty cycle modulator, drives the LM395 to complete a servo loop
Switched mode operation yields high efficiency
1% metal film resistor
Conventional Log Amplifier
RT = Tel Labs type Q81
Trim 5k for 10 μA through the 5k–120k combination
*1% film resistor
12
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
Unconventional Log Amplifier
Q1, Q2, Q3 are included on LM389 amplifier chip which is temperature-stabilized by the LM389 and Q2-Q3, which act
as a heater-sensor pair.
Q1, the logging transistor, is thus immune to ambient temperature variation and requires no temperature
compensation at all.
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Detailed Schematic
1/2 Dual
14
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SNOSC03E –APRIL 1999–REVISED OCTOBER 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
Changes from Revision D (March 2013) to Revision E
Page
•
Changed Input Noise Voltage units ...................................................................................................................................... 4
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PACKAGE OPTION ADDENDUM
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27-Mar-2014
PACKAGING INFORMATION
Orderable Device
LF442ACN
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LIFEBUY
PDIP
PDIP
P
8
8
40
TBD
Call TI
Call TI
LF
442ACN
LF442ACN/NOPB
ACTIVE
P
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LF
442ACN
LF442AMH
ACTIVE
ACTIVE
TO-99
TO-99
LMC
LMC
8
8
500
500
TBD
Call TI
Call TI
-55 to 125
-55 to 125
LF442AMH
LF442AMH/NOPB
Green (RoHS
& no Sb/Br)
POST-PLATE
Level-1-NA-UNLIM
LF442AMH
LF442CN
LIFEBUY
ACTIVE
PDIP
PDIP
P
P
8
8
40
40
TBD
Call TI
CU SN
Call TI
0 to 70
0 to 70
LF
442CN
LF442CN/NOPB
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
LF
442CN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Mar-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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