LM10503SQX/S7002727 [TI]
LM10503 Triple Buck Converter Energy Management Unit (EMU) with PowerWise® 2.0 Adaptive Voltage Scaling (AVS) and ADC; LM10503三联降压转换器的能源管理单元（ EMU）与PowerWise® 2.0自适应电压调节（ AVS ）和ADC
| 型号： | LM10503SQX/S7002727 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM10503 Triple Buck Converter Energy Management Unit (EMU) with PowerWise® 2.0 Adaptive Voltage Scaling (AVS) and ADC |
| 文件： | 总43页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM10503
LM10503 Triple Buck Converter Energy Management Unit (EMU) with PowerWise®
2.0 Adaptive Voltage Scaling (AVS) and ADC
Literature Number: SNVS644
December 1, 2011
LM10503
Triple Buck Converter Energy Management Unit (EMU) with
PowerWise® 2.0 Adaptive Voltage Scaling (AVS) and ADC
General Description
Features
LM10503 is an advanced EMU containing three configurable,
high-efficiency bucks for supplying variable voltages to a di-
verse range of applications. The device is ideal for supporting
ASIC and SOC designs which use voltage scaling for reduc-
ing power consumption.
Three high-efficiency programmable bucks:
■
Integrated FETs with low RDSON
—
—
Bucks operate at 120° phase to reduce the input
current ripple and capacitor size
Input Under Voltage Lock-out
—
—
—
The device is digitally controlled via the PWI® 2.0 open-stan-
dard interface. LM10503 operates cooperatively with a Pow-
erWise® technology-compatible ASIC to optimize the supply
voltage adaptively (AVS - Adaptive Voltage Scaling) over pro-
cess and temperature variations. It also supports dynamic
voltage-scaling (DVS) using frequency/voltage pairs from
pre-characterized look-up tables.
Enable pin and internal soft start
Current overload and thermal shutdown
4-Channel Multi-Function Port (MFP) that includes:
■
8-bit ADC with integrated reference
—
—
—
Comparator Input/General Purpose Output
Interrupt request output with multiple sources
PWI® 2.0 Open-Standard Interface
■
■
■
Key Specifications
Power-On Reset (POR) open-drain output with delay
LM10503-1 with start-up sequence option
Single input rail with wide range: 3.0V - 5.5V
■
■
■
■
■
■
■
Buck 1 (AVS): Programmable output: 0.7V - 1.2V, 2A
Bucks 2 & 3: Adjustable output: 1.0V - 3.5V, 1A
Applications
The LM10503 and LM10503-1 are suitable for applications
that require multiple supplies in the range of 0.7 to 3.5V and
up to 2A:
±2% Feedback voltage accuracy
Up to 96% peak efficiency buck regulators
2MHz switching frequency for smaller inductor size
LLP-36 package (36 pins, 6mm x 6mm x 0.8mm, 0.5mm
Point of Load Regulation for ASICs
■
■
■
■
■
■
pitch)
NVM Memory drives (HDD or FLASH)
Servers and Networking Cards
PCI cards, Set-Top-Box Processors
Video Processors and Graphic Cards
High-Performance Medical and Industrial Processors
Typical Application Circuit
30112101
© 2011 Texas Instruments Incorporated
301121
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Overview
The device contains three buck converters. The table below
lists the output characteristics of the three converters.
SUPPLY SPECIFICATIONS
Output Voltage
Range (V)
Output Voltage Programming
Resolution (mV)
Maximum Output
Current (A)
Supply
Typical Application
VSW1
0.700 to 1.208
1.000 to 3.500
4
2
1
Core Voltage Scaling Domain
I/O, aux voltage
VSW2,3
N/A
Connection Diagrams and Package Mark Information
30112107
FIGURE 1. LLP-36 Package Number SQA36A
36 Pins, 6x6x0.8mm, 0.5mm pitch
Note: The actual physical placement of the package marking will vary from part to part.
DATE CODE: UZXYTT format: 'U' - wafer fab code; 'Z' - assembly plant code; 'XY' - 2-digit date code; and 'TT' - die run code. See
http://www.national.com/quality/marking_conventions.html for more information on marking conventions.
Ordering Information
Order Number
Ordering Spec
Package Marking
LM10503
Supplied As
LM10503SQE/NOPB
LM10503SQ/NOPB
LM10503SQX/NOPB
LM10503SQ/S7002726
LM10503SQX/S7002727
250 units Tape and Reel
1000 units Tape and Reel
2500 units Tape and Reel
1000 units Tape and Reel
2500 units Tape and Reel
NOPB
LM10503
LM10503
S7002726
S7002727
10503-1
10503-1
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2
Pin Descriptions
Pin #
1
Pin Name
AGND
AVDD
VDDL
GNDL
SA0
I/O
G
P
Type
G
Functional Description
Analog ground for Bucks 1, 2 and 3
2
P
Analog power for Bucks 1, 2 and 3
3
P
P
Power for logic block
4
G
I
G
Ground for logic block
5
D
PWI Slave Address Bit 0. Tie to ground or VPWI for '0' or '1, respectively.
PWI Slave Address Bit 1. Tie to ground or VPWI for '0' or '1, respectively.
Interrupt request. This open drain output is asserted low on an interrupt event.
Power On Reset. This open drain output is asserted low on reset.
PowerWise Interface (PWI) bi-directional data
PowerWise Interface (PWI) clock input
6
SA1
I
D
7
IRQ
O
O
I/O
I
OD
OD
D
8
POR
9
SPWI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SCLK
D
VPWI
P
P
Power supply voltage input for PWI and logic interfaces
Power supply voltage input for power stage PFET
Power supply voltage input for power stage PFET
Switching node, connect to inductor
PVIN1A
PVIN1B
SW1A
SW1B
PGND1A
PGND1B
VFB1
P
P
P
P
O
O
G
G
I
O
O
Switching node, connect to inductor
Power ground, connect to system ground.
Power ground, connect to system ground.
Feedback input
Buck #1
G
G
A
VDDMFP
MFP0
MFP1
MFP2
MFP3
GNDADC
VDDADC
DVDD
DSGND
PVIN3
SW3
P
P
Power supply voltage input for the multifunction pins, GPO mode.
Multifunction pin, ADC input, comparator input, GPO, channel 0
Multifunction pin, ADC input, comparator input, GPO, channel 1
Multifunction pin, ADC input, comparator input, GPO, channel 2
Multifunction pin, ADC input, comparator input, GPO, channel 3
Ground for ADC. Connect to system Ground.
I/O
I/O
I/O
I/O
G
P
A/D
A/D
A/D
A/D
G
P
Power for ADC
P
P
Power for digital block of Bucks 1, 2 and 3
G
P
G
Ground for digital block of Bucks 1, 2 and 3
P
Power supply voltage input for power stage PFET
Switching node, connect to inductor.
O
G
I
O
Buck #3
PGND3
VFB3
G
Power ground, connect to system ground.
Feedback input
A
EN
I
D
Enable input. Set this digital input high for normal operation.
Feedback input
VFB2
I
A
PGND2
SW2
G
O
P
G
Power ground, connect to system ground.
Switching node, connect to inductor.
Power supply voltage input for power stage PFET
Exposed pad, connect to system ground
Buck #2
O
PVIN2
PAD
P
G
G
A: Analog Pin
I: Input Pin
D: Digital Pin
G: Ground Pin
O: Output Pin
P: Power Pin
I/O: Input/Output Pin
OD: Open Drain Output Pin
3
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30112102
FIGURE 2. Simplfied Block Diagram
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4
5
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Absolute Maximum Ratings (Note 1, Note
Recommended Operating Ratings
2, Note 3, Note 4, Note 5)
(Note 2, Note 3, Note 4, Note 5)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
VIN
VPWI (Note 6)
3.0V to 5.5V
1.62V to 3.63V but not over
VIN
VDDMFP (Note 6)
VFB1,2,3
EN
MFP0-3
1.62V to VIN
0 to VOUT1,2,3
0 to VIN
0 to VDDMFP
0 to VPWI
Any supply pin (VIN) to GND, Note
3.
Any signal pin, VPWI, VDDMFP
-0.3 to +6.5V
-0.3 to +(VIN
+0.3V) but not over
6.5V
SPWI, SCLK, SA0-1, POR, IRQ
Between any GND pins (Note 4)
-0.3 to +0.3V
+150°C
-65°C to +150°C
Junction Temperature (TJ-MAX
Storage Temperature Range
)
Junction Temperature (TJ)
Range
Ambient Temperature (TA)
Range (Note 8, Note 9, Note 10,
Note 11)
Maximum Continuous Power
Dissipation (PD-MAX) (Note 8,
Note 9, Note 10, Note 11)
-40°C to +105°C
-40°C to +70°C
1.33W
Maximum Lead Temperature
(Soldering 4 sec)
+260°C
ESD Ratings (Note 7)
Human Body Model
2000V
200V
Machine Model
Thermal Properties
(Note 8, Note 9, Note 10, Note 11)
Junction-to-Case Thermal Resistance
(θJC
Junction-to-Board Thermal Resistance
(θJA
Junction-to-Ambient Thermal
Resistance (θJA
)
2.2°C/W
12.4°C/W
27.0°C/W
)
)
General Electrical Characteristics (Note 2, Note 3)
Unless otherwise noted, VIN= 5.0V where: VIN=AVDD=VDDL=VDDADC=DVDD=VDDMFP=PVIN1A=PVIN1B=PVIN2=PVIN3, ex-
cept VPWI=2.5V. The application circuit used is the one shown in Figure 3. Limits in standard type apply for TJ = 25°C. Limits
appearing in boldface type apply over the full operating junction temperature range −40°C ≤ TJ≤ +105°C.
Symbol
Parameter
Conditions
Min
TYP
Max
20
Units
IQ-VIN-SD
Quiescent supply current of Device is shut down by:
all VIN supply pins
a) driving EN pin low or
2
µA
combined; part is shut down
b) issuing the Shutdown Command
IQ-VIN-NO-LOAD
Quiescent supply current of Switching in forced PWM, ADC
all VIN supply pins
combined; part is enabled,
but not loaded
disabled, MFP pins set as inputs, driven
LOW
16
25
1
mA
µA
IQ-VPWI-SD
Quiescent supply current of Device is shut down by:
VPWI supply pin; part is shut
down
a) driving EN pin low or
b) issuing the Shutdown Command
0.1
0.1
IQ-VPWI-IDLE
Quiescent supply current of Device is enabled, PWI bus is idle (no
VPWI supply pin; part is
enabled, PWI bus is idle
load on SPWI, SCLK)
1
FSW
Switching Frequency of all 3 PWM-mode measured at SW1, 2, 3
1.75
2.00
53
2.30
MHz
ms
bucks
pins, 120° out of phase (by design)
All 3 bucks are unloaded
TPOR-DELAY
Delay from EN-pin rising
edge to POR-pin rising edge
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6
Symbol
EN, FB PINS
TEN_LOW
VIL-EN
Parameter
Conditions
Min
TYP
Max
Units
EN pin minimum low pulse To trigger a startup sequence
100
nS
V
EN pin logic low input
VIN = 5V
0.2
+1
VIH-EN
EN pin logic high input
2.0
IIH-EN
EN pin input current, driven V_EN = VIN
high
+0.1
−0.1
µA
V
IIL-EN
EN pin input current, driven V_EN = 0.0V
low
−1
VIL_UVLO-AVDD
VIH_UVLO-AVDD
UVLO falling threshold
2.4
2.6
2.8
Measured on AVDD pin ramping,
monitored at POR pin.
UVLO rising threshold
2.9
VHYST_UVLO-AVDD UVLO hysteresis window
0.24
VPOR-L
POR pin is asserted when
target voltage of Buck1 or 2
or 3 is lower than this level
85
94
Percentage values with respect to
target values of VFB1,2,3 monitored at the
respective buck outputs
%
VPOR-H
POR pin is de-asserted when
target voltage of Buck1 and 2
and 3 is higher than this level
SPWI, SCLK, SA1-0, IRQ, POR PINS
(These pins are powered from VPWI.)
VIL
VIH
IIL
Logic Input Low
Logic Input High
30%
SPWI, SCLK, SA1-0 pins
VPWI
µA
70%
−2
Input Current, pin driven low SPWI, SCLK, SA1-0 pins
SA1-0 pins
+2
+5
Input current, pin driven high
(VPWI)
IIH
µA
SPWI & SCLK have internal pulldown
0.2
20%
VOL
VOH
Logic Output Low
SPWI, IRQ, POR for ISINK ≤ 2mA
VPWI
µA
Logic Output High
80%
−2
SPWI for ISOURCE ≤ 2mA
IRQ, POR pins when open drain
IOZ
Output Leakage Current
+2
MFP0-3 PINS
(Pins used in General Purpose Outputs (GPO) or comparator inputs; these pins are powered from VDDMFP)
IIL
Input current, pin driven low
−2
Open drain or comparator input mode
µA
V
IIH
Input current, pin driven high
(VDDMFP)
+2
VOL
VOH
Logic Output Low
Logic Output High
0.2
Pin in GPO mode, ISINK ≤ 1mA
VDDMFP-
0.2
Pin in GPO mode, ISOURCE ≤ 1mA
THERMAL SHUTDOWN
TSD
Thermal Shutdown
Temperature
160
20
°C
TSD-HYST
Thermal Shutdown
Hysteresis
7
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Buck 1 Electrical Characteristics (Note 1, Note 2, Note 3)
Unless otherwise noted, VIN= 5.0V where: VIN=AVDD=VDDL=VDDADC=DVDD=VDDMFP=PVIN1A=PVIN1B=PVIN2=PVIN3, ex-
cept VPWI=2.5V. The application circuit used is the one shown in Figure 3. Limits in standard type apply for TJ = 25°C. Limits
appearing in boldface type apply over the full operating junction temperature range −40°C ≤ TJ≤ +105°C.
Symbol
Parameter
Conditions
Min
Typ
Max
3
Unit
Quiescent supply current of
PVIN1A and PVIN1B pins
combined
Buck 1 is enabled, but not loaded,
VOUT1 = 1.05V, switching in PWM
IQ-NO-LOAD
1
mA
Buck 1 is enabled, VOUT1 = 1.05V,
switching in PWM*
Continuous maximum load
current
IOUT-MAX
IPEAK
2
A
Buck 1 is enabled, VOUT1 = 1.05V,
switching in PWM
Peak switching current limit
Efficiency peak
2.33
2.75
92%
3.90
VIN = 3.3V, VOUT = 1.05V, IOUT = 0.2A
VIN = 5V, VOUT = 1.05V, IOUT = 1A
ηSW1-3V
ηSW1-5V
CIN
%
82%
10
Input Capacitor
7
14
0
µF
Output Filter Capacitor
Output Filter Capacitor ESR
Output Filter Inductance
22
100
20
COUT
0mA ≤ IOUT ≤ IOUT-MAX
mΩ
µH
L
1
Output voltage top range,
with Register R0 = 7Fh
VOUT-TOP
1.208
V
%
V
Feedback pin connected to VOUT
VOUT = VOUT-TOP, IOUT = 0.1*IOUT-MAX
Feedback pin voltage
tolerance
VFB-TOP- TOL
-2%
-2%
+2.5
+2
Output voltage, power-up
default
VOUT-DEFAULT
VFB-DEFAULT-TOL
Feedback pin connected to VOUT
1.05
0.7
VOUT = VOUT-DEFAULT, IOUT = 0.1*IOUT-
Feedback pin voltage
tolerance
%
MAX
Output voltage bottom
range, with Register R0 =
00h
VOUT-BOTTOM
Feedback pin connected to VOUT
V
VOUT = VOUT-BOTTOM, IOUT = 0.1*IOUT-
Feedback pin voltage
tolerance
MAX
VFB- BOTTOM-TOL
-2%
+2.5
%
3V ≤ VIN ≤ 5V, VOUT = VOUT-DEFAULT
,
DC Line regulation
DC Load regulation
0.2
0.1
%/V
IOUT = 0.5 * IOUT-MAX
ΔVOUT
VIN = 5V, VOUT = VOUT-DEFAULT, 0.1 *
%/A
µA
IOUT-MAX ≤ IOUT ≤ IOUT-MAX
VFB = 1.208V ; (pin has internal
Feedback pin input bias
current
IFB
2.3
50
65
25
5
resistor divider)
High Side Switch On
Resistance
RDS-ON-HS
RDS-ON-LS
TSCALING
105
100
Measured pin-to-pin
mΩ
Low Side Switch On
Resistance
100 mV steps on VSW1
COUT-TOTAL = 22 µF
,
VOUT Scaling Step Time
µS
ms
STARTUP
TSTART
Internal soft-start (turn on time)
0.5
* Specification guaranteed by design. Not tested during production.
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8
Bucks 2 and 3 Electrical Characteristics (Note 1, Note 2, Note 3)
Unless otherwise noted, VIN= 5.0V where: VIN=AVDD=VDDL=VDDADC=DVDD=VDDMFP=PVIN1A=PVIN1B=PVIN2=PVIN3, ex-
cept VPWI=2.5V. The application circuit used is the one shown in Figure 3. Limits in standard type apply for TJ = 25°C. Limits
appearing in boldface type apply over the full operating junction temperature range −40°C ≤ TJ≤ +105°C.
Symbol
Parameter
Conditions
Min
Typ
Max
8
Unit
Quiescent supply current
off PVIN2 pin
Buck 2 is enabled, but not loaded,
switching in PWM
IQ-NO-LOAD-2
3
mA
Quiescent supply current of Buck 3 is enabled, but not loaded,
PVIN3 pin switching in PWM
Continuous maximum load Bucks 2 and 3 are enabled, switching
IQ-NO-LOAD-3
IOUT-MAX
IPEAK
3
8
1
current
in PWM*
A
Bucks 2 and 3 are enabled, switching
in PWM
Peak switching current limit
1.25
1.5
1.75
IOUT = 0.4A, VIN = 5.0V
IOUT = 0.2A, VIN = 3.3V
IOUT = 0.3A, VIN = 5.0V
IOUT = 0.2A, VIN = 3.3V
ηSW2-5V
ηSW2-3.3V
ηSW3-5V
ηSW3-3.3V
CIN
92%
93%
94%
Efficiency peak, Buck 2
Efficiency peak, Buck 3
%
%
97%
10
Input Capacitor
7
14
0
µF
Output Filter Capacitor
Output Filter Capacitor ESR
Output Filter Inductance
Feedback voltage
22
100
20
COUT
0mA ≤ IOUT ≤ IOUT-MAX
mΩ
µH
V
L
1
VFB
0.5
IOUT = 0.1*IOUT-MAX
,
Output voltage set using external
resistor divider to 1.0V...3.5V
Feedback pin voltage
tolerance
VFB-TOL
-2%
+2
%
Output voltage highest
setting using external
resistor divider
All supplies = 4.2 - 5.5V, IOUT = 0 -
IOUT-MAX
VOUT-TOP
3.5
1.0
V
Output voltage lowest
setting using external
resistor divider
All supplies = 3.0 - 5.5V,
IOUT = 0 - IOUT-MAX
VOUT-BOTTOM
3.3V ≤ VIN ≤ 5V,
DC Line regulation
DC Load regulation
0.2
0.3
%/V
IOUT = IOUT-MAX
ΔVOUT
VIN = 5V,
%/A
µA
0.1 * IOUT-MAX ≤ IOUT ≤ IOUT-MIN
Feedback pin input bias
current
IFB
VFB = 0.5V
0.1
170
125
1
High Side Switch On
Resistance
RDS-ON-HS
300
190
Measured pin-to-pin
mΩ
Low Side Switch On
Resistance
RDS-ON-LS
STARTUP
TSTART
Start up from shutdown, VOUT = 0V, no load, LC = recommended
circuit, using software enable to VOUT = 95% of final value
0.5
ms
* Specification guaranteed by design. Not tested during production.
9
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ADC and Comparators Electrical
Characteristics (Note 1, Note 2, Note 3)
Unless otherwise noted, VIN= 5.0V where: VIN=AVDD=VDDL=VDDADC=DVDD=VDDMFP=PVIN1A=PVIN1B=PVIN2=PVIN3, ex-
cept VPWI=2.5V. The application circuit used is the one shown in Figure 3. Limits in standard type apply for TJ = 25°C. Limits
appearing in boldface type apply over the full operating junction temperature range −40°C ≤ TJ ≤ +105°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VDDADC pin quiescent
current, part disabled
IQSC-ADC-0
EN pin LOW
0.1
10
VDDADC pin quiescent
current, part enabled but
ADC not enabled
IQSC-ADC-1
EN pin HIGH, ADCEN=0
45
µA
VDDADC pin operating
current with ADC enabled
but not converting
EN pin HIGH, ADCEN=1,
ADCSTART=0
IADC-0
260
150
VDDADC pin operating
current with ADC enabled
and converting
EN pin HIGH, ADCEN=1,
ADCSTART=1
IADC-1
T = 25°C
1.220
1.225
1.225
1.230
VREF
Internal Reference Voltage
V
LSB
LSB
V
T= 0 to 105°C
1.200
1.250
Core ADC integral non-
linearity
VREF = 1.225*
VREF = 1.225*
INL
-2
+2
Core ADC differential non-
linearity
DNL
-0.5
0.5
ADC input voltage range,
top
VADC_IN_TOP
VADC_IN_BOTTOM
2 * VREF
VREF
ADC input voltage range,
bottom
V
tCONV
tWARM-REF
tu
Conversion time
5
1
ms
ms
ms
Warm-up time of reference After EN pin high (Note 1)
Warm-up time of ADC After enabling the ADC (Note 1)
2
2
COMPARATOR (The comparators use the same reference as the ADC.)
Quiescent current of
VDDMFP pin
MFP pins are configured as
comparator inputs, all grounded
IQ-VDDMFP
V_comp_rise
V_comp_fall
V_comp_rise
V_comp_fall
0.1
VREF
µA
V
Comparator rising edge
trigger level
Hysteresis window bits CMPxHYS
are 0.
Comparator falling edge
trigger level
VREF-0.08
VREF
Comparator rising edge
trigger level
Hysteresis window bits CMPxHYS
are 1.
V
Comparator falling edge
trigger level
VREF-0.05
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10
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: VIN refers to these power pins connected together: AVDD = VDDL = VDDADC = DVDD = PVIN1A = PVIN1B = PVIN2 = PVIN3
Note 4: GND Pins means all ground pins must be connected together: AGND = GNDL = PGND1A = PGND1B = GNDADC = DSGND = PGND3 = PGND2 =
PAD.
Note 5: Signal pins include SW1-3, SA0-1, IRQ, POR, SPWI, SCLK, FB1-3, MFP0-3 and EN.
Note 6: VPWI, VDDMFP sequencing requirements: voltage on VPWI and VDDMFP must be less than, or equal to, VIN, including during ramp up and ramp down
of power supplies.
Note 7: Applies to all pins. The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin (MIL-STD-883 3015.7). The
Machine Model (MM) is a 200 pF capacitor discharged directly into each pin (EAIJ).
Note 8: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187 Leadless Leadframe Package (LLP)
http://www.national.com/an/AN/AN-1187.pdf.
Note 9: The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula:
P = (TJ–TA)/θJA, (1) where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. θJA is highly
application and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.)
Note 10: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 105°C), the maximum power
dissipation of the device in the application (PD-MAX) and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Note 11: θJC refers to the bottom metal surface of the LLP as the CASE. θJB is the junction-to-board thermal resistance. Junction-to-ambient thermal resistance
(θJA) is taken from a thermal modeling result and is based on a power dissipation of 1.33W, using a 4-layer FR-4 standard JEDEC thermal test board (4LJEDEC):
4"x3" (102 mm x 76 mm x 1.6 mm) in size. Ambient temperature in simulation is 22°C, under stationary airflow condition. The board has 2 internal copper layers
which cover roughly the same size as the board. The copper thickness for the four layers, starting from the top one are: 36/18/18/36 [µm] (2/1/1/2 [oz]). A minimum
number of 9 thermal vias are placed between the pad on the top side and the 2nd copper layer. Detailed description of the board can be found in JEDEC standard
JESD 51-7 (High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages) and JESD51-5 (Extension of Thermal Test Board Standards
for Packages with Direct Thermal Attachment Mechanisms). The junction-to-ambient thermal resistance (θJA) is highly dependent on application and board layout.
The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum
power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to
Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
11
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LM10503 - Typical Performance Characteristics
Power Up Sequence: LM10503-1
Power Up Sequence: LM10503
30112112
30112113
POR Pin Operation: LM10503
SW1, SW2 SW3 Phase Order
30112114
30112166
Switching Frequency vs. VIN
Normalized to 2MHz
IAVDD vs. VIN
30112168
30112167
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IVDDL vs. VIN
IDVDD vs. VIN
30112169
30112170
IVDDADC vs. VIN
30112171
13
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Typical Performance Characteristics Buck1
TA = 25°C unless otherwise noted.
Efficiency: VOUT = 1.05V
Line Transient: VIN = 3.2V - 3.4V Step,
VOUT = 1.05V, IOUT = 1A
30112173
30112172
Load Transient: VIN = 5.0V, VOUT = 1.05V
IOUT_step = 0.5A...1.5A
Startup, VOUT = 1.05V, IOUT = 2A
30112176
30112174
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14
VOUT Step-up Response to
R0 MSB Change, VIN = 5.0V, IOUT = 2A
VOUT Step-down Response to
R0 MSB Change, VIN = 5.0V, IOUT = 2A
30112178
30112179
Typical Performance Characteristics, Buck 2
Efficiency: VOUT = 1.8V
Line Transient: VIN = 3.2V - 3.4V Step,
VOUT = 1.8V, IOUT = 1A
30112181
30112180
Load Transient: VIN = 5.0V, VOUT = 1.8V
IOUT_step = 0A...1.0A
Startup, VOUT = 1.5V
30112183
30112182
15
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Typical Performance Characteristics, Buck 3
Efficiency: VOUT = 2.5V
Line Transient: VIN = 3.2V - 3.4V Step,
VOUT = 2.5V, IOUT = 1A
30112158
30112157
Load Transient: VIN = 5.0V, VOUT = 2.5V
IOUT_step = 0A...1.0A
Startup, VOUT = 2.5V, IOUT = 1A
30112160
30112159
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16
The device incorporates three high-efficiency synchronous
buck regulators that deliver three output voltages from a sin-
gle power source. The device also includes a Multifunctional
Block that comprises a 4-channel ADC, comparators and
GPOs.
LM10503 General Description
LM10503 is a PWI 2.0 compliant Energy Management Unit
for reducing power consumption of the digital core of Sys-
tems-on-a-Chip (SoCs), ASICs, and processors. It operates
cooperatively with processors that incorporate National
Semiconductor’s Advanced Power Controller (APC) to pro-
vide Adaptive or Dynamic Voltage Scaling (AVS or DVS)
which significantly improves the system efficiency when com-
pared to fixed output voltage implementations.
The following table summarizes the key features of the de-
vice:
TABLE 1. Feature Summary
Functionality
Power on output voltage default
Output voltage, range minimum
Output voltage, range maximum
Output voltage programming resolution
Output voltage register
BUCK1
1.05V
0.7
BUCK2
BUCK3
Configurable using an external resistor divider
1
1
1.2
3.5
N/A
N/A
3.5
N/A
N/A
4mV
R0
Output voltage change with external resistor
divider
No
Yes
1A
Yes
1A
Maximum output current
Operation mode
2A
PWM Only
PWM or PWM/PFM
Enable pin LOW
All bucks disabled, FB pins pulled low with a 22 kΩ internal resistor.
Enable pin HIGH
Enable Bit
All bucks are enabled.
N/A
BUCK2EN
BUCK3EN
SHUTDOWN Command
RESET Command
SLEEP Command
WAKEUP Command
Turns off all bucks
Turns on all bucks and brings all registers to their power on default values
Turns off this buck
Turns on this buck
No effect
No effect
DIGITALLY ASSISTED VOLTAGE SCALING
caused by the power routing from the AVS regulator all the
way to the internal circuitry of the powered device. As a
result, maximum power savings are achieved.
The device is designed to be used in a voltage scaling system
to lower the power dissipation by scaling the supply voltage
with the clock frequency. Buck 1 supports two modes of volt-
age scaling: Dynamic Voltage Scaling (DVS) and Adaptive
Voltage Scaling (AVS).
The device delivers fast and controlled voltage scaling tran-
sients with the help of a digital state machine. The state
machine automatically optimizes the control loop of the buck
regulator to provide large voltage steps with minimal over-
and undershoot. This is an important characteristic for voltage
scaling systems that rely on minimal over- and undershoot to
set voltages as low as possible in order to maximize the en-
ergy savings.
•
DVS mode: the voltage changes are initiated by the
system firmware as a result of changes in the operating
frequency of the system. Pre-characterized voltage - clock
frequency pairs are used. This is an open loop system
because it does not adapt to temperature changes or other
factors.
DATA INTEFACE
•
• AVS mode: the voltage changes are initiated by the
Advanced Power Controller (APC, residing in the powered
IC) as a result of changes in the operating performance of
the monitored system. Pre-characterized voltage - clock
frequency pairs are not needed. AVS is a closed loop
system that provides an automatic process and
The device is programmable via the low power, 2-wire Pow-
erWise® Interface (PWI). The signals associated with this
interface are SPWI and SCLK. Through this interface, the us-
er can enable/disable the device as well as select between
DVS and AVS modes. By accessing the registers in the de-
vice through this interface, the user can get access and
control the operation of the buck controllers, ADC, compara-
tors and GPOs in the device. For maximum flexibility, the logic
levels of these signals can be matched with the host by sup-
plying the corresponding I/O voltage level to the VPWI pin as
shown in the figure below.
temperature compensation such that for any given
process, temperature, or clock frequency, the minimum
supply voltage is delivered. AVS systems continuously
track the system’s performance and immediately optimize
the supply voltage to the required lowest value. An added
benefit is the automatic compensation for voltage drops
17
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30112105
FIGURE 4. PowerWise Interface
The device supports the full command set as described in
PWI 2.0 specification:
•
Authenticate
Please see the PWI 2.0 specification for a complete descrip-
tion located at http://www.pwistandard.org.
•
•
•
•
•
•
•
Core Voltage Adjust
Reset
Sleep
Shutdown
Wakeup
BUCK REGULATORS OPERATION
buck converter contains a control block, a switching PFET
connected between input and output, a synchronous rectify-
ing NFET connected between the output and ground and a
feedback path. The following figure shows the block diagram
of each of the three buck regulators integrated in the device.
Register Read
Register Write
30112110
FIGURE 5. Buck Functional Diagram
During the first portion of each switching cycle, the control
block turns on the internal PFET switch. This allows current
to flow from the input through the inductor to the output filter
capacitor and load. The inductor limits the current to a ramp
with a slope of (VIN –VOUT)/L by storing energy in a magnetic
field. During the second portion of each cycle, the control
block turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The
inductor draws current from ground through the NFET to the
output filter capacitor and load, which ramps the inductor cur-
rent down with a slope of –VOUT/L. The output filter stores
charge when the inductor current is high, and releases it when
low, smoothing the voltage across the load. The output volt-
age is regulated by modulating the PFET switch on time to
control the average current sent to the load. The effect is
identical to sending a duty-cycle modulated rectangular wave
formed by the switch and synchronous rectifier at the SW pin
to a low-pass filter formed by the inductor and output filter
capacitor. The output voltage is equal to the average voltage
at the SW pin.
BUCK REGULATORS DESCRIPTION
The device incorporates three high efficiency synchronous
switching buck regulators that deliver various voltages from a
single DC input voltage. They include many advanced fea-
tures to achieve excellent voltage regulation, high efficiency
and fast transient response time. The bucks feature voltage
mode architecture with synchronous rectification. Each of the
switching regulators is specially designed for high efficiency
operation throughout the load range. With a 2MHz typical
switching frequency, the external L-C filter can be small and
still provide very low output voltage ripple. The bucks are in-
ternally compensated to be stable with the recommended
external inductors and capacitors as detailed in the applica-
tion diagram. Synchronous rectification yields high efficiency
for low voltage and high output currents. All bucks can operate
up to a 100% duty cycle allowing for the lowest possible input
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18
voltage that still maintains the regulation of the output. The
lowest input to output dropout voltage is achieved by keeping
the PMOS switch on. Additional features include soft-start,
under-voltage lock-out, and current and thermal overload pro-
tection. To reduce the input current ripple, the device employs
a control circuit that operates the 3 bucks at 120° phase.
ternal resistor divider can be calculated using the following
equations.
Buck 1 (AVS)
This buck can deliver up to 2A at voltages in the range of
0.700 -1.208V in 127 steps of 4mV resolution and features
Adaptive and Dynamic Voltage Scaling (AVS and DVS). It
operates in PWM mode only. Its output voltage can be pro-
grammed via the CORE VOLTAGE ADJUST command as
described in the PWI Standard. The voltage setting is held in
register R0 (see PWI register map). Alternately, the voltage
output of Buck 1 can also be programmed by directly access-
ing the same R0 register.
The recommended value for R2 is 2kΩ. For a desired value
of VOUT, the value of R1 is:
Bucks 2 and 3
These two bucks are identical in performance and mode of
operation. They can deliver up to 1A and operate in FPWM
(forced PWM), or automatic mode (PWM/PFM).
In FPWM Mode the bucks always operate in PWM mode re-
gardless of the output current.
In Automatic Mode, if the output current is lower than 70 mA,
the bucks automatically transition into PFM (Pulse Frequency
Modulation) operation to reduce the current consumption,
while at higher than 70 mA they operate in PWM mode. This
increases the efficiency at lower output currents. To configure
this mode, the user needs to set BK2FPWM or BK3FPWM
bits located in the Buck Control Register to 0.
30112108
FIGURE 6. Bucks2/3 VOUT Adjust
The following table shows the value of R1 resistor for output
voltages in the range of 1.0V to 3.5V.
The internal reference is fixed to 0.5V. An external resistor
divider sets the output voltage to the desired value. The ex-
TABLE 2. Bucks 2/3 VOUT Adjust Resistor Values
VOUT (V)
1
VOUT Actual (V)
1
VOUT Error (%)
0.00%
0.00%
0.00%
0.77%
0.00%
0.33%
0.31%
-0.74%
0.42%
0.00%
0.50%
-0.71%
0.00%
-0.54%
0.83%
0.60%
0.48%
0.65%
-0.89%
-0.60%
0.00%
0.81%
-0.78%
R1 (kΩ)
2
R1 Standard 1% (kΩ)
2
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
2.4
2.8
3.2
3.6
4
2.4
1.1
2.8
1.2
3.24
3.6
1.31
1.4
4.02
4.42
4.75
5.23
5.6
1.505
1.605
1.6875
1.8075
1.9
4.4
4.8
5.2
5.6
6
6.04
6.34
6.8
2.01
6.4
6.8
7.2
7.6
8.0
8.4
8.8
9.2
9.6
10.0
10.4
10.8
2.085
2.2
7.15
7.68
8.06
8.45
8.87
9.1
2.2875
2.42
2.515
2.6125
2.7175
2.775
2.8825
3.000
3.125
3.175
9.53
10.00
10.5
10.7
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VOUT (V)
3.3
VOUT Actual (V)
VOUT Error (%)
0.76%
R1 (kΩ)
11.2
11.6
12
R1 Standard 1% (kΩ)
11.3
11.5
12
3.325
3.375
3.5
3.4
-0.74%
3.5
0.00%
DEFAULT STARTUP SEQUENCE
converters are turned off. An internal 22 kΩ resistor (±30%)
attached to the FB pin is activated to discharge any residual
charge present in the output circuitry.
The 3 buck regulators are staggered during startup to avoid
large inrush currents. There are 8 "starting times" with a Td =
2ms resolution. The first voltage starts to come up only after
the internal circuitry has reached steady state. The default
start sequence is shown in the table and Figure 7 below.
STARTUP SEQUENCE
The device incorporates an advanced startup circuit that en-
sures correct system boot.
Start Time Slot
The designer must ensure that VPWI and VDDMFP are al-
ways lower or equal to VIN, including during the initial power
up of the device. If VDDMFP and VPWI are supplied from VIN
or from one of the output voltages generated by the 3 bucks,
than this requirement is automatically satisfied. Note the lim-
itation of VPWI maximum supply is 3.63V. The VIN input
voltage can ramp-up as fast as 25 µs and as slow as 10 ms,
but it should not have a dip larger than 0.1V, while all 3 outputs
are loaded at their maximum rated current.
LM10503
LM10503-1
(ms)
SW3
SW2
SW1
SW1
SW2
SW3
2
4
6
POWER-ON DEFAULT AND DEVICE ENABLE
The device can be enabled/disabled by driving the ENABLE
pin high/low. Once enabled, the device engages the power-
up sequence and the 3 output voltages settle to their default
values. After the power up sequence is completed, and after
an additional delay, the POR pin goes high. While the device
is enabled, Buck2 and 3 can be individually disabled by ac-
cessing their corresponding BKEN bits in register R10 (BUCK
CONTROL).
When the input power supply reaches the UVLO level (which
is sensed on the AVDD pin), and after a delay of about 15 ms
±30%, the internal sequencer will start counting. The 3 bucks
can be enabled at any 2ms discrete points within the 16 ms
maximum sequencer delay.
After the last power supply is up and running, a fixed delay of
32 ms is added after which the POR pin (reset output) is de-
asserted (pin goes in tri-state). This 32 ms delay allows a
processor to stabilize its internal clocks, PLLs or other support
circuits before its reset input driven from POR is released.
BUCK1 can only be turned off by issuing a SLEEP COM-
MAND. All three bucks can be turned off at once by using the
SHUTDOWN COMMAND from PWI. To re-enable the part,
either the ENABLE pin must be toggled (high – low – high),
or a RESET COMMAND must be used. The part will then en-
ter the power-up sequence and all voltages will return to their
default values. The ENABLE pin resets all the previously pro-
grammed bits in the register set to their power-on default. The
ENABLE pin provides flexibility for system control. In larger
systems, it can be advantageous to enable/disable a subsys-
tem independently. For example, the device may be powering
an application processor, in which case the system controller
can disable the application processor via the ENABLE pin, but
leave other subsystems on. If the ENABLE pin function is not
required (i.e., all the power states are controlled through the
PWI bus), the pin should be tied to VIN. If the ENABLE pin is
tied low, the part is disabled and the PWI interface is also
disabled, and the access to PWI registers is not possible.
After the last buck is enabled, the internal sequencer waits a
maximum of 8ms for all 3 bucks to fully start (as reflected by
their respective BUCK#-OK bit). If at least one of the bucks is
not starting up within 8ms (for example because of an over-
load), the device enters an “output fault” state, all 3 bucks are
immediately shut down, and a 200 ms time delay is added
before the sequencer will restart. The 200 ms delay is needed
to allow all output capacitors to fully discharge, such that the
next startup will not be under bias.
The sequencing timer is restarted and the 3 bucks are en-
abled according to the sequencer configuration. If the cause
of the fault is still present, the 3 bucks will be shut down again,
and the process repeats indefinitely. The power supply will be
in a “hiccup” mode with a repetition period of about 214 ms.
Of these 214 ms, the bucks are on for about 8 to 12 ms, so
the duty cycle is about 3.7% to 5.6%, and this reduces the risk
of damage to the system. The device will stay in this hiccup
mode till the condition that caused the overload is removed.
SHUTDOWN MODE
During shutdown the PFET and the NFET switches, the in-
ternal reference, and the control and bias circuitry of the
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20
30112106
FIGURE 7. Startup Sequence
SOFT START
different from the previous one (large voltage step up or
down), the output voltage may overshoot or undershoot. To
prevent this, the user should increment the output voltage of
SW1 in small enough steps.
Each of the buck converters has an internal soft-start circuit
that limits the in-rush current during startup. This allows the
converters to gradually reach the steady state operating point,
thus reducing start-up stresses and surges. During startup,
the switch current limit is increased in steps. Soft start is ac-
tivated only if EN goes from logic low to logic high, after VIN
is higher than the UVLO trip point.
Alternately, this can be done automatically by the logic inside
the device by setting BK1RAMPEN bit of register R10 (Buck
Control) to 1. In this case, the user has two options to select
from: SLOW-RAMP and FAST-RAMP which can be selected
by programming the BK1RAMPMOD bit (Buck 1 Ramp Mode)
of the same register.
For Buck 1 the soft start is implemented as a linear output
voltage ramp that takes about 500 µs. This soft start time in
general doesn't vary with VOUT level or the allowed COUT
range (22 µF - 44 µF). During soft start, the load is expected
to be light, or resistive, for example, if the final voltage is 1V
at 2A, the buck expects the load at VOUT = 0.1V to be about
200 mA.
SLOW-RAMP: set BK1RAMPMOD to 0. In this case the volt-
age code is stepped up/down every 8µs.
FAST-RAMP: set BK1RAMPMOD to 1. In this case the volt-
age code is stepped up/down every 4µs (reset delay).
In both SLOW-RAMP and FAST-RAMP modes, the operation
is as follows
For Bucks 2 and 3 the soft start is implemented by increasing
the switch current limit in steps that are gradually higher: 180
mA, 300 mA, and 720 mA. The startup time depends on the
output capacitor size, load current and output voltage. Typical
startup time with the recommended output capacitor of 22 µF
is 0.2 - 1ms.
•
Ramp up will have a maximum of 8 voltage codes per step
(4mV/code * 8 codes = 32 mV), but will have less voltage
codes (4 or 2 or 1) if within 8 voltage codes of the target
level. A full ramp-up from 7’h00 to 7’h7F will take ~144 µs
for ramp mode 0 and 72 µs mode 1.
•
Ramp down will have a maximum of 4 voltage codes per
step (4mV/code * 4 codes = 16 mV), but will have a single
voltage code if within 4 voltage codes of the target level.
A full ramp-down from 7’h7F to 7’h00 will take ~272 µs for
ramp mode 0 and 136 µs mode 1.
BUCK 1 DIGITALLY ASSISTED RAMP CONTROL
The slew rate of the Buck 1 output can be configured by set-
ting the bits BK1RAMPMOD and BK1RAMPEN in the Buck
Control register R10.
If BK1RAMPEN bit of register R10 (Buck Control) is 0, a new
voltage setting in the R0 register will be immediately trans-
ferred to the Buck 1 analog circuitry. If the new voltage is very
21
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UNDER VOLTAGE LOCK OUT (UVLO)
Bucks 2 and 3 will automatically transition into PFM mode
when either of two conditions occurs for a duration of 32 or
more clock cycles:
The AVDD pin is monitored for a supply under voltage con-
dition, for which the operation of the device can not be guar-
anteed. The part will automatically be disabled if the supply
voltage is insufficient. To prevent unstable operation, the UV-
LO has a hysteresis window of about 200 mV. An under
voltage lockout (UVLO) will force the device into the RESET
state. Once the supply voltage is above the UVLO hysteresis,
the device will initiate a power-up sequence and then enter
the ACTIVE state.
1. The inductor current becomes discontinuous, or
2. The peak PMOS switch current drops below the IMODE
level. (Typically:
During PFM operation, the converter positions the output volt-
age slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The PFM
comparators sense the output voltage via the feedback pin
and control the switching of the output FETs such that the
output voltage ramps between 0.8% and 1.6% (typical) above
the nominal PWM output voltage. If the output voltage is be-
low the ‘high’ PFM comparator threshold, the PMOS power
switch is turned on. It remains on until the output voltage ex-
ceeds the ‘high’ PFM threshold or the peak current exceeds
the I_PFM level set for PFM mode. The typical peak current
in PFM mode is:
THERMAL SHUTDOWN (TSD)
The temperature of the silicon die is monitored for an over-
temperature condition, for which the operation of the device
can not be guaranteed. The part will automatically be disabled
if the temperature is too high. The thermal shutdown (TSD)
will force the device into the RESET state. To prevent unsta-
ble operation, the TSD has a hysteresis window of about
20°C. Once the temperature has decreased below the TSD
hysteresis, the device will initiate a power-up sequence and
then enter the ACTIVE state.
POWER ON RESET (POR)
The device contains a voltage monitor on its input and output
voltages and will assert POR pin whenever the voltages are
too low. The pin is an open-drain type output, therefore it must
be pulled-up via an external resistor. The device continues to
assert this pin for about 32 ms after all output voltages are
good, to ensure that the powered devices are properly reset.
The POR pin remains asserted for as long as the error con-
dition persists.
Once the PMOS power switch is turned off, the NMOS power
switch is turned on until the inductor current ramps to zero.
When the NMOS zero-current condition is detected, the
NMOS power switch is turned off. If the output voltage is be-
low the ‘high’ PFM comparator threshold (see figure below)
the PMOS switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output
reaches the ‘high’ PFM threshold, the NMOS switch is turned
on briefly to ramp the inductor current to zero and then both
output switches are turned off and the part enters an ex-
tremely low power mode. Quiescent supply current during this
‘sleep’ mode is less than 30 µA, which allows the part to
achieve high efficiencies under extremely light load condi-
tions. When the output drops below the ‘low’ PFM threshold,
the cycle repeats to restore the output voltage to ~1.6% above
the nominal PWM output voltage.
CURRENT LIMITING
A current limit feature protects the device and any external
components during overload conditions. In PWM mode the
current limiting is implemented by using an internal compara-
tor that trips at current levels according to the buck capability.
If the output is shorted to ground the device enters a timed
current limit mode where the NFET is turned on for a longer
duration until the inductor current falls below a low threshold,
ensuring inductor current has more time to decay, thereby
preventing runaway.
PWM OPERATION
While in PWM mode, the bucks use an internal NFET as a
synchronous rectifier to reduce the rectifier forward voltage
drop and the associated power loss. Synchronous rectifica-
tion provides a significant improvement in efficiency whenev-
er the output voltage is relatively low compared to the voltage
drop across an ordinary rectifier diode.
If the load current should increase during PFM mode causing
the output voltage to fall below the ‘low2’ PFM threshold, the
part will automatically transition into fixed-frequency PWM
mode.
PFM OPERATION (BUCKS 2 and 3)
At very light loads, Buck 2 and Buck 3 enter PFM mode and
operate with reduced switching frequency and supply current
to maintain high efficiency.
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30112111
FIGURE 8. PFM vs. PWM Operation
PWM/PFM OPERATION AND SETTINGS (REGISTER R10)
[BUCKS 2 and 3]
The PWM-to-PFM transition occurs when the DC output cur-
rent is equal to the ripple current:
The switching converters in the device have two modes of
operation: pulse width modulation (PWM) and pulse frequen-
cy modulation (PFM).
By default, the device stays in PWM mode. This register pro-
vides the ability to enable the automatic transition between
PFM or PWM operation.
where L is the output inductance and fS is the switching fre-
quency.
In PWM the converter switches at a fixed frequency deter-
mined by the frequency of the internal clock. Each period can
be split into two cycles. During the first cycle, the high-side
switch is on and the low-side switch is off, therefore the in-
ductor current is rising. In the second cycle, the high-side
switch is off and the low-side switch is on causing the inductor
current to decrease. The output ripple voltage is lowest in
PWM mode. As the load current decreases, the converter ef-
ficiency becomes worse due to the increased percentage of
overhead current needed to operate in PWM mode.
The converter will transition into PFM mode when the output
switch current is negative for 4 consecutive clock cycles.
If the load current increases during PFM mode causing the
output voltage to fall below the PFM threshold ( ∼1% above
VOUT nominal) - the part will automatically transition into fixed-
frequency PWM mode.
LOW DROPOUT OPERATION
The device can operate at 100% duty cycle (no switching;
PMOS switch completely on) for low drop out support. In this
way the output voltage will be controlled down to the lowest
possible input voltage. When the device operates near 100%
duty cycle, output voltage ripple is approximately 25 mV.
At light load current the converter can enter PFM operation if
R10 register BKxFPWM bit is zero, in which case the output
stage operates alternately between tristate and the nominal
PWM switching frequency. This mode of operation maintains
high efficiency even at light load current.
The minimum input voltage needed to support the output volt-
age: VIN_MIN = VOUT + ILOAD x (RDSON_PFET + RIND), where:
In PFM mode, the converter begins to ramp up the output
voltage after the output voltage falls below the PFM threshold
( ∼1% above VOUT nominal). When the output voltage has
reached VOUT nominal and the load current is still light, the
converter tristates the output stage. The average output volt-
age in PFM mode is, therefore, slightly higher than VOUT
nominal.
•
•
ILOAD = Load Current
RDSON_PFET = Drain to source resistance of PFET (high
side) switch in the triode region
•
RIND = Inductor resistance
EXTERNAL COMPONENTS SELECTION
All three switchers require an input capacitor, and an output
inductor-capacitor filter. These components are critical to the
performance of the device. All three switchers are internally
compensated and do not require external components to
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achieve stable operation. The output voltage of Buck 1 can
be programmed through the PWI pins. The output voltages of
Bucks 2 and 3 can be modified using external resistor dividers
connected from the output voltage to the FB pin.
ISAT
:
Inductor saturation current at operating tempera-
ture
ILPEAK
:
Peak inductor current during worst case conditions
IOUTMAX: Maximum average inductor current
IRIPPLE
:
Peak-to-Peak inductor current
Output voltage
OUTPUT INDUCTORS & CAPACITORS SELECTION
There are several design considerations related to the selec-
tion of output inductors and capacitors:
VOUT
VIN:
L:
:
Input voltage
•
•
•
•
•
Load transient response
Stability
Efficiency
Output ripple voltage
Over current ruggedness
Inductor value in Henries at IOUTMAX
Switching frequency, Hertz
Estimated duty factor
F:
D:
EFF:
Estimated power supply efficiency
The device has been optimized for use with nominal LC val-
ues as shown in the Figure 3.
Suggested Inductors and Their Suppliers
The designer should choose the inductors that best match the
system requirements. A very wide range of inductors are
available as regarding physical size, height, maximum current
(thermally limited, and inductance loss limited), series resis-
tance, maximum operating frequency, losses, etc. In general,
smaller physical size inductors will have higher series resis-
tance (DCR) and implicitly lower overall efficiency is
achieved. Very low profile inductors may have even higher
series resistance. The designer should try to find the best
compromise between system performance and cost.
INDUCTOR SELECTION
The recommended inductor values are shown in Figure 3. It
is important to guarantee the inductor core does not saturate
during any foreseeable operational situation. The inductor
should be rated to handle the peak load current plus the ripple
current:
Care should be taken when reviewing the different saturation
current ratings that are specified by different manufacturers.
Saturation current ratings are typically specified at 25°C, so
ratings at maximum ambient temperature of the application
should be requested from the manufacturer.
OUTPUT AND INPUT CAPACITORS CHARACTERISTICS
Special attention should be paid when selecting these com-
ponents. As shown in the following figure, the DC bias of these
capacitors can result in a capacitance value that falls below
the minimum value given in the recommended capacitor
specifications table. Note that the graph shows the capaci-
tance out of spec for the 0402 case size capacitor at higher
bias voltages. It is therefore recommended that the capacitor
manufacturers’ specifications for the nominal value capacitor
are consulted for all conditions, as some capacitor sizes (e.g.
0402) may not be suitable in the actual application.
There are two methods to choose the inductor saturation cur-
rent rating:
Recommended Method:
The best way to guarantee the inductor does not saturate is
to choose an inductor that has saturation current rating
greater than the maximum device current limit, as specified
in the Electrical Characteristics. In this case the device will
prevent inductor saturation by going into current limit before
the saturation level is reached.
Alternate Method:
If the recommended approach cannot be used care must be
taken to guarantee that the saturation current is greater than
the peak inductor current:
30112115
FIGURE 9. Typical Variation in Capacitance vs.
DC Bias
The ceramic capacitor’s capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a temper-
ature range of −55°C to +125°C, will only vary the capacitance
to within ±15%. The capacitor type X5R has a similar toler-
ance over a reduced temperature range of −55°C to +85°C.
Many large value ceramic capacitors, larger than 1 μF are
manufactured with Z5U or Y5V temperature characteristics.
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24
Their capacitance can drop by more than 50% as the tem-
perature varies from 25°C to 85°C. Therefore X7R is recom-
mended over Z5U and Y5V in applications where the ambient
temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
0.47 µF to 44 µF range. Another important consideration is
that tantalum capacitors have higher ESR values than equiv-
alent size ceramics. This means that while it may be possible
to find a tantalum capacitor with an ESR value within the sta-
ble range, it would have to be larger in capacitance (which
means bigger and more costly) than a ceramic capacitor with
the same ESR value. It should also be noted that the ESR of
a typical tantalum will increase about 2:1 as the temperature
goes from 25°C down to −40°C, so some guard band must
be allowed.
30112116
FIGURE 10. COUT ESR
The output-filter capacitor smooths out the current flow from
the inductor to the load and helps maintain a steady output
voltage during transient load changes. It also reduces output
voltage ripple. These capacitors must be selected with suffi-
cient capacitance and low enough ESR to perform these
functions.
OUTPUT CAPACITOR SELECTION
Note that the output voltage ripple increases with the inductor
current ripple and the Equivalent Series Resistance of the
output capacitor (ESRCOUT). Also note that the actual value
of the capacitor’s ESRCOUT is frequency and temperature de-
pendent, as specified by its manufacturer. The ESR should
be calculated at the applicable switching frequency and am-
bient temperature.
The output capacitor of a switching converter absorbs the AC
ripple current from the inductor and provides the initial re-
sponse to a load transient. The ripple voltage at the output of
the converter is the product of the ripple current flowing
through the output capacitor and the impedance of the ca-
pacitor. The impedance of the capacitor can be dominated by
capacitive, resistive, or inductive elements within the capaci-
tor, depending on the frequency of the ripple current. Ceramic
capacitors have very low ESR and remain capacitive up to
high frequencies. Their inductive component can be usually
neglected at the frequency ranges the switcher operates.
30112126
Output ripple can be estimated from the vector sum of the
reactive (capacitance) voltage component and the real (ESR)
voltage component of the output capacitor where:
VROUT
VCOUT
:
estimated real output ripple,
estimated real output ripple.
The device is designed to be used with ceramic capacitors on
the outputs of the buck regulators. The recommended dielec-
tric type of these capacitors is X5R, X7R, or of comparable
material to maintain proper tolerances over voltage and tem-
perature. The recommended value for the output capacitors
is 22 μF, 6.3V with an ESR of 2mΩ or less. The output ca-
pacitors need to be mounted as close as possible to the
output/ground pins of the device.
where:
VOUT-RIPPLE-PP
:
estimated output ripple,
TABLE 3. Recommended Output Capacitors
Type
Vendor
Model
Vendor
Voltage Rating
Case Size
08056D226MAT2A
C0805L226M9PACTU
ECJ-2FB0J226M
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
AVX Corporation
Kemet
6.3V
6.3V
6.3V
6.3V
6.3V
0805, (2012)
0805, (2012)
0805, (2012)
0603, (1608)
0603, (1608)
Panasonic - ECG
Taiyo Yuden
JMK212BJ226MG-T
C2012X5R0J226M
TDK Corporation
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INPUT CAPACITOR SELECTION
A simplified “worst case” assumption is that all of the PFET
current is supplied by the input capacitor. This will result in
conservative estimates of input ripple voltage and capacitor
RMS current.
The input capacitors should be located as close as possible
to their corresponding PVINx and PGNDx pins, where x des-
ignates the buck 1,2 or 3. The 3 buck regulators operate at
120° out of phase, which means that is they switch on at
equally spaced intervals, in order to reduce the input power
rail ripple. It is recommended to connect all the supply/ground
pins of the buck regulators, PVIN1, 2 and 3 to two solid inter-
nal planes located under the device. In this way, the 3 input
capacitors work together and further reduce the input current
ripple. A larger tantalum capacitor can also be located in the
proximity of the device. The input capacitor supplies the AC
switching current drawn from the switching action of the in-
ternal power FETs. The input current of a buck converter is
discontinuous, so the ripple current supplied by the input ca-
pacitor is large. The input capacitor must be rated to handle
both the RMS current and the dissipated power.
Input ripple voltage is estimated as follows:
where:
VPPIN
:
estimated input ripple voltage,
Input capacitor value
CIN:
ESRCIN
:
input capacitor ESR.
This capacitor is exposed to significant RMS current, so it is
important to select a capacitor with an adequate RMS current
rating. Capacitor RMS current estimated as follows:
The input capacitor must be rated to handle this current:
The power dissipated in the input capacitor is given by:
IRMSCIN
:
estimated input capacitor RMS current.
LARGE SIGNAL TRANSIENT
The switching converters in the device are designed to work
in a voltage scaling system. This requires that the converters
have a well controlled large signal transient response. Specif-
ically, the under- and over-shoots have to be minimal or zero
while maintaining settling times less than 0.1 msec. Typical
response plots are shown in section Typical Performance
Characteristics.
The device is designed to be used with ceramic capacitors on
the inputs of the buck regulators. The recommended dielectric
type of these capacitors is X5R, X7R, or of comparable ma-
terial to maintain proper tolerances over voltage and temper-
ature. The minimum recommended value for the input
capacitor is 10 µF with an ESR of 10 mΩ or less. The input
capacitors need to be mounted as close as possible to the
power/ground input pins of the device.
LM10503 OPERATIONAL STATE DIAGRAM
The device has four operating states: Startup, Active, Sleep
and Standby; see next figure. The figure assumes that sup-
ply voltages are in the valid range.
The input power source supplies the average current contin-
uously. During the PFET switch on-time, however, the de-
manded di/dt is higher than can be typically supplied by the
input power source. This delta is supplied by the input capac-
itor.
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26
30112117
FIGURE 11. LM10503 State Diagram
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The Startup State is the default state of the device after pow-
er is applied. All bucks are off and POR output is ‘0’. This state
is entered when the external enable input pin is pulled low. It
is a temporary state because the startup sequence is auto-
matically executed initiated, and upon its completion, the
device transfers into the Active State. It is possible to issue a
Reset Command while still in Startup state, in which case the
startup sequence will be re-started.
Input Voltage is Too Low
If the input voltage is too low to guarantee accurate operation
of the device, a UVLO detector will disable the device. When
this error condition occurs, the internal logic goes into reset
state and stays in reset for as long as the error condition is
still active. When the error condition is removed, the device
enters the startup sequencing.
Output Voltage is Too Low
In Active State all bucks are on at their default voltages and
If any of the output voltages are too low compared with the
expected voltage, for example due to a short circuit, the de-
vice will enter a hiccup mode (will continuously try to restart).
When any of the buck ready signals of the enabled bucks drop
from high to low for more than 1ms, a restart is triggered. The
external POR is asserted, and all bucks are disabled and re-
enabled again sequentially after a wait time of 200 ms.
the POR-output pin is high. From Active State the device can:
•
•
•
Go back to Start-up State by setting the ENABLE pin low
or by issuing the Reset Command.
Go into Sleep State by issuing the Sleep Command over
the PWI bus.
Go into Shutdown State by issuing the Shutdown
Command over the PWI bus.
Startup Takes Too Long
In Sleep State, only the Buck 1 output voltage is off, but the
POR output is still high. The other two bucks, Bucks 2 and 3,
may be used to provide auxiliary voltages that need to be
maintained during Sleep State. From the Sleep State, the de-
vice can:
During startup, after the bucks are enabled, a 8ms timeout
counter is initialized. If any of the enabled bucks fails to return
the OK signal within 8ms, it triggers a shutdown of all bucks.
All bucks are disabled for 200 ms and re-enabled again se-
quentially.
•
Be re-activated (go into Active State), by using the Wake-
up Command. This resumes the power on default state
configuration and voltages may need to be changed by
firmware.
Output Voltage is Too Low
If any of the output voltages are too low compared with the
expected voltage, for example due to a short circuit, the de-
vice will enter a hiccup mode (will continuously try to restart).
•
•
Go into Shutdown State by issuing the Shutdown
Command over the PWI bus.
Go into to Start-up State by setting the ENABLE pin low or
by issuing the Reset Command.
When any of the buck ready signals of the enabled bucks drop
from high to low for more than 1ms, a restart is triggered. The
external POR is asserted, and all bucks are disabled and re-
enabled again sequentially after a wait time of 200 ms.
In Shutdown State, all buck regulators are off, and POR is
low. This state has the lowest power consumption. The device
can enter the Shutdown State by using the Shutdown Com-
mand, or by setting ENABLE to ‘0’. The device can exit the
Shutdown State and go into Startup State by:
Die Temperature is Too High
If the die junction temperature is too high, the device is auto-
matically disabled to prevent damage. When this error con-
dition occurs, the internal logic goes into reset state and stays
in reset for as long as the error condition is still active. When
the error condition is removed, the device enters the startup
sequencing.
•
•
Toggling the ENABLE pin high, or
Issuing the Reset Command over the PWI bus.
FAULT CONDITIONS
The device incorporates several advanced features that pro-
tect itself and the system from the following fault conditions.
TABLE 4. LM10503 Fault Condition Management
Fault Type
Buck action
POR Pin
UVLO on AVDD input pin
Low
Buck SW pins are tri-stated and a ~22 kΩ pulldown
resistor is activated on FB pins.
Output Under-voltage
Over-temperature
Continues to try to regulate; enters hiccup mode
Low as long as voltage level goes
out of the range
Buck is tri-stated and restarts when the die has cooled Low until buck starts up again
down
Although the device is protected against these conditions, the
system designer should not allow these conditions to occur.
system’s requirements. Any combination of functions is pos-
sible, including the change of the function during runtime.
MULTI FUNCTION PORT
Function Selection
The Multi-Function Pins (MFP3-0) can be configured to op-
erate as
•
ADC: The ADC path is enabled unless MFP3:0 pin is
configured as General Purpose Output pin. The pin
connected to the ADC’s input is the one selected by the
ADCSEL1:0 field in register R11.
COMPARATOR: The MFP3:0 pins can be configured as
comparator inputs by setting the Comparator Enable Bits
CMPxEN in register R15
•
•
•
ADC inputs
Comparator inputs
General Purpose Outputs (GPOs) in either push-pull
mode or open-drain mode.
•
•
This architecture offers the system designer the necessary
flexibility to allocate the device resources according to
GPO: The MFP3:0 pins can be configured as GPO outputs
by setting the GPO Enable Bits GPOxEN in register R15.
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28
This setting supersedes the other two functions
associated with the same pin.
disabled in order to use the Multi-Function Pin as a compara-
tor input pin. For accurate ADC measurements, a pin should
only be configured as ADC input. The following figure shows
a simplified block diagram of the Multi Function Port.
Limitation: the same MFP pin should not simultaneously be
configured as comparator and GPO, in which case the later
takes precedence. In other words, the GPO function must be
30112118
FIGURE 12. MFP Block Diagram
The comparator can generate an “edge” type interrupt, not a
“level” interrupt. The comparator can not be used to immedi-
ately determine if the signal presented on the input is higher
or lower than the VREF. It requires the input signal to change
in time, i.e. to increase/decrease above/below the VREF, as
configured by the polarity bit in R17. The comparator function
is best used for a very slow changing event as for example
the charging or discharging of a battery or supercapacitor, in
which case an interrupt will be generated when the compara-
tor trips. This method is more efficient than a continuous
polling of a comparator or of an ADC. If the system designer
needs to know the value of voltage presented on one of the
MFP pins, it should use the ADC function to do an actual ADC
measurement.
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ternal reference voltage. After an initial 2ms warm-up for the
first activation of the ADC enable bit, the dual-slope converter
integrates the input signal during the first phase for approxi-
mately 2 ms, followed by a second phase that integrates
VREF for 0 ms to 2 ms depending on the level of the input
signal. As a result the total conversion time varies from 2 ms
to 4 ms.
Analog-to-Digital Converter
The device is equipped with an 8-bit dual-slope integrating
analog to digital converter. A dual-slope converter does not
require a sample and hold stage and provides an effective
filtering of the input signal noise components that are outside
the range of 125 kHz to 500 kHz. The ADC digitizes the input
signal ranging from VREF to 2*VREF, where VREF is the in-
30112120
FIGURE 13. Simplified ADC Block Diagram
The ADC has a 4-channel multiplexer on the input that allows
the system designer to assign any of the MFP0-3 pins as ADC
inputs.
the correct ADC source before a conversion is started. The
ADC will set bit 4 of R11 (DATARDY) upon the completion of
a conversion, which is 2-4ms after the start of the conversion.
At the same time, an interrupt request will be generated. (See
Interrupt Request Register).
The voltage applied on MFP0-3 pins must match the input
working voltage of the ADC: VREF to 2VREF. This can be
accomplished by using external resistor dividers. To allow
maximum flexibility, there are no internal resistor dividers.
To save power, disable the ADC by setting bit 2 of R11 to 0
(ADCEN). To initiate the start of a new conversion, or to make
repetitive starts, set bit 3 of R11 (ADCSTART) to 0 then to 1.
The interrupt driven protocol between the part and the system
processor is the most efficient way to acquire data from suc-
cessive measurements, as shown in the following flowchart.
The ADC block includes its own reference which is enabled
when the EN pin is high. This allows a quick startup time of
the ADC after the ADCEN bit was set. The power consump-
tion of the reference is about 50uA typical as it can be moni-
tored on the VDDADC pin. This current can be reduced to a
few uA by disabling the part either by driving EN low or by
executing a SHUTDOWN command. Please note that AD-
CEN bit must be set to zero prior to executing a SHUTDOWN
command.
The input impedance of the ADC is about 3MΩ, therefore the
external resistor divider must be designed accordingly in or-
der to reduce the error it can cause.
The system designer can use these ADC inputs for general
purpose applications such as power rail measurements, re-
sistive keyboard matrix scanning, temperature measure-
ments, load currents, etc. The source selection and the
access to the conversion results are established through the
registers described in the Register Map section.
The power-up default of the ADC is disabled in order to min-
imize current consumption. It needs to be enabled by setting
the ADCEN bit (register R11). Writing a logic 1 to bit 3 of R11
(ADCSTART) will initiate a conversion. It is advised to select
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30112121
FIGURE 14. ADC Operation
INTERRUPT REQUEST OUTPUT
logic low level upon the following 8 events, as described in
register R14, Interrupt Request Register:
The part has the ability to interrupt the system processor
through the open drain IRQ pin, which transitions to an active
7
6
VOUTUV
At least one of the 3 switchers has an output in under-voltage condition.
PWIUCMD
PWIPERR
ADCDONE
COMP3:0
PWI undefined command.
5
PWI parity error
4
ADC conversion done, data ready
3:0
MFP3:0 pin, if configured as comparator, will generate an interrupt if this bit is set 1.
All interrupt sources can be masked by the Interrupt Mask
Register R13. Masking the interrupt prevents the interrupt
event from asserting the IRQ pin, yet the event will still be
captured in the IRQ register, which allows the processor to
poll the interrupt sources. After an active low IRQ has been
detected by the system processor, the latter services the in-
terrupt and will access the IRQ register to determine which
source(s) was (were) responsible for the interrupt request. To
clear the IRQ register, a logic 1 must be written to the same
location. Writing a logic 0 is disregarded. The interrupts are
not hardware prioritized. In case more than one Interrupt Re-
quest is set, the priority must be determined by the system
firmware.
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The figure below provides a better approximation of the θJA
for a given PCB copper area. The PCB heatsink area consists
of 2oz. copper located on the bottom layer of the PCB directly
under the exposed pad. The bottom copper area is connected
to the exposed pad by means of a 4 x 4 array of 12 mil thermal
vias.
Thermal Considerations
The thermal characteristics of the device are specified using
the parameter θJA, which relates the junction temperature to
the ambient temperature. Although the value of θJA is depen-
dent on many variables, it still can be used to approximate the
operating junction temperature of the device. To obtain an
estimate of the device junction temperature, one may use the
following relationship:
TJ = PD x θJA + TA where:
PD is the total power dissipation of the device;
TJ is the junction temperature in °C;
ꢀθJA is the junction-to-ambient thermal resistance for the de-
vice;
TA is the ambient temperature in °C.
It is important to always keep the operating junction temper-
ature (TJ) below 105°C for reliable operation. If the junction
temperature exceeds 160°C the device will cycle in and out
of thermal shutdown. If thermal shutdown occurs it is a sign
of inadequate heat sinking or excessive power dissipation in
the device.
30112145
FIGURE 15. Thermal Resistance vs. PCB Area
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PCB LAYOUT CONSIDERATIONS
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
30112148
FIGURE 16. Schematic of LM10503 Highlighting Layout
Sensitive Nodes
1. Minimize area of switched current loops. In a buck
regulator there are two loops where currents are
close to the FB pin and not to the output capacitor to
improve noise immunity.
switched rapidly. The first loop starts from the CIN input
capacitor, to the regulator PVIN pin, to the regulator SW
pin, to the inductor then out to the output capacitor
COUT and load. The second loop starts from the output
capacitor ground, to the regulator PGND pins, to the
inductor and then out to COUT and the load (see figure
above). To minimize both loop areas the input capacitor
should be placed as close as possible to the PVIN pin.
Grounding for both the input and output capacitors
should consist of a small localized top side plane that
connects to PGND and the die attach pad (DAP). The
inductor should be placed as close as possible to the SW
pin and output capacitor.
5. Make input and output bus connections as wide as
possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If
voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so will
correct for voltage drops at the load and provide the best
output accuracy.
6. Provide adequate device heat sinking. Use as many vias
as possible to connect the DAP to the power plane(s)
heat sink. A recommended arrangement is a 4x4 via
array with a minimum via diameter of 12 mils. See the
Thermal Considerations section to make sure enough
copper heat sinking area is used to keep the junction
temperature below 105°C.
2. Minimize the copper area of the switch node. The SW
pins should be directly connected with a trace that runs
on top side directly to the inductor. To minimize IR losses
this trace should be as short as possible and with a
sufficient width. However, a trace that is wider than 100
mils will increase the copper area and cause too much
capacitive loading on the SW pin. The inductors should
be placed as close as possible to the SW pins to further
minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds
located under the DAP. The ground connections for the
feedback and external ADC components should be
connected together then routed to the AGND pin of the
device. The AGND pin should connect to PGND under
the DAP. This prevents any switched or load currents
from flowing in the analog ground plane. If not properly
handled, poor grounding can result in degraded load
regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. Since the feedback
node can have high impedance, the trace from the output
resistor divider to FB pin should be as short as possible.
This is most important when high value resistors are used
to set the output voltage. The feedback trace should be
routed away from the SW pin and inductor to avoid
contaminating the feedback signal with switch noise.
Locate the two resistors of the feedback resistor divider
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R0 - Core Voltage Buck 1 Register
Bit
7
Field Name
Unused
Description or Comment
Any data written into this bit is ignored.
Core voltage value with no external feedback resistor divider.
6:0
Voltage
Voltage Data Code
Voltage Value (V)
7h'00
7h'xx
7h7F
0.7
Linear scaling of 127 steps of 4mV
1.208
R3 - Status Register
Bit
Field Name
Description or Comment
Reserved
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Buck2 OK
Buck3 OK
Reserved
Buck1 OK
Reserved
Reserved
Reserved
Buck 2 is operating correctly
Buck 3 is operating correctly
Reserved
Buck 1 is operating correctly
R4 - Device Capability Register
Bit
7:3
2:0
Field Name
Reserved
Version
Description or Comment
Reserved
Read transaction return '010' indicating PWI 2.0 specification.
Write transactions to this register are ignored.
R10 - Buck Control Register
Bit
Field Name
Description
7
6
Reserved
Reserved
BK1RAMPMOD
Buck1 Ramp control Mode select
If bit 5, BK1RAMPEN, is 1, the voltage code is stepped up/down every:
0: SLOW-RAMP. Ramp step is 8us
1: FAST-RAMP. Ramp step is 4us (reset default)
In both SLOW-RAMP and FAST-RAMP modes, the operation is as follows:
Ramp-up will have a maximum of 8 voltage codes per step (4mV/code * 8 codes
—
= 32mV), but will have less voltage codes (4 or 2 or 1) if within 8 voltage codes of
the target level. A full ramp-up from 7'h00 to 7'h7F will take ~144 µs for ramp mode
0 and 72 µs mode 1.
Ramp-down will have a maximum of 4 voltage codes per step (4mV/code * 4 codes
—
= 16 mV), but will have a single voltage code if within 4 voltage codes of the target
level. A full ramp-down from 7'h7F to 7'h00 will take ~272 µs for ramp mode 0 and
136 µs mode 1.
5
BK1RAMPEN
Buck 1 Ramp Control Enable.
If set, enables stepping control for voltage going up/down, as described in bit 6 above.
4
3
2
1
0
Buck 3 forced to be always in PWM mode.
Buck 2 forced to be always in PWM mode.
Reserved
Buck 3 Enable
Buck 2 Enable
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36
R11 - ADC Control Register
Bit
7:6
5
Field Name
Reserved
ADCOVF
Description or Comment
Reserved
ADC Overflow indicator (status), input is higher than 2*VREF, read only:
0: no overflow
1: overflow
The overflow bit is cleared on the next conversion cycle start.
4
3
DATARDY
ADC Data Ready indicator (status), read only
0: data not ready
1: data ready
The ADC will set bit 4 upon the completion of a conversion. At the same time, the
ADCDONE bit in R14 Interrupt Request Register will be set, and an interrupt request
will be generated if the ADCDONE bit is un-masked in the Interrupt Mask Register.
ADCSTART
Start ADC conversion
0: default
1: start conversion: writing 1 to this bit will initiate the conversion. It must be toggled in
order to start a conversion. Once the bit is set, it will remain set. To start a new
conversion the bit must be reset to zero and than to a one. Make sure to set ADC
source before setting this bit.
2
ADCEN
ADC Enable
0: ADC disabled
1: ADC enabled
1:0
ADCSEL
ADC source selection:
0: MFP0 pin
1: MFP1 pin
2: MFP2 pin
3: MFP3 pin
Make sure the same pin is not used as a GPO (bit GPOEN3:0 are not set).
R12 - ADC Data Register
This register holds the last ADC conversion value.
Bit
Field Name
Description or Comment
7:0
ADC DATA
This register holds the last conversion value. A value of 00 corresponds to VREF
voltage. A value of FF corresponds to 2*VREF voltage.
R13 - Interrupt Mask Register
Bit
7
Field Name
VOUTUV
Description
Any of the 3 bucks has an output under-voltage event
A PWI undefined command was received.
A PWI parity error was detected.
1. enable the respective interrupt
source to pull the IRQ pin low
0. the respective interrupt source
will be masked (no interrupt will be
generated).
6
PWIUCMD
PWIPERR
ADCDONE
5
4
ADC conversion is done, data ready.
MFP3:0 pin, if configured as comparator, generated
a comparator trigger.
3:0
COMP3:0
R14 - Interrupt Request Register
Bit
7
Field Name
VOUTUV
Description
Any of the 3 bucks has an output under-voltage event
PWI undefined command.
PWI parity error
reading high indicate the
respective source was the
cause of that interrupt
1.
2.
6
PWIUCMD
PWIPERR
ADCDONE
5
4
ADC conversion done, data ready
reading low indicate the
respective source was not the
cause of that interrupt.
Comparator 3:0 tripped for the respective MFP3:0
pin, if that pins was configured as a comparator input
in register R15.
3:0
COMP3:0
37
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R15 - Comparator Control 1 Register
This register controls the operation of the 4 MFP pins when configured as comparator input pins.
Bit
7
Field Name
CMP3DGL
Description
Comparator deglitching circuit for MFP3 pin. 1: four consecutive samples spaced at
intervals defined in register R16, must all
return the same value before the
comparator data in corresponding
COMP3:0 bit is updated (register R14).
0: four consecutive samples spaced at ~1µs
interval, must all return the same value
before the comparator data in
6
CMP2DGL
Comparator deglitching circuit for MFP2 pin.
5
CMP1DGL
Comparator deglitching circuit for MFP1 pin.
corresponding COMP3:0 bit is updated
(register R14).
4
3
2
1
0
CMP0DGL
CMP3EN
CMP2EN
CMP1EN
CMP0EN
Comparator deglitching circuit for MFP0 pin.
Comparator enable for MFP3 pin.
Comparator enable for MFP2 pin.
Comparator enable for MFP1 pin.
Comparator enable for MFP0 pin.
The comparator is an edge triggered comparator, i.e. it
checks for the input transition crossing the reference voltage
level. The direction of the transition can be configured by the
polarity bits in register R17. When a transition crossing the
reference is detected, the corresponding comparator tripped
bit in the R14 Interrupt Status Register is set. Once the com-
parator is tripped, the Comparator Enable bit must be set to
‘0’ to reset the comparator logic, and then set to ‘1’ to re-arm
for the next compare.
A number of 4 consecutive samples are required to validate
the tripping after the comparator output changes state. The
sampling interval is configured by the select bits in register
R16. The GPO function must be disabled in order to use the
Multi-Function Pin as a comparator input pin.
R16 - Comparator Control 2 Register
Bit
Field Name
Description
Comparator 3 deglitching sampling
interval select
7:6
CMP3DM1:0
This register controls the deglitching sampling
interval used for filtering out spurious interrupts
generated by the comparators:
00: 1ms
01: 2ms
10: 4ms
11: 8ms
Comparator 2 deglitching sampling
interval select
5:4
3:2
1:0
CMP2DM1:0
CMP1DM1:0
CMP0DM1:0
Comparator 1 deglitching sampling
interval select
Comparator 0 deglitching sampling
interval select
R17 - Comparator Control 3 Register
This register controls the hysteresis and polarity of the 4 MFP pins when configured as comparator input pins.
Bit
7
Field Name
CMP3HYS
Description
Comparator 3
Comparator 2
Comparator 1
Comparator 0
Comparator 3
Comparator 2
Comparator 1
Hysteresis window select:
1: 60 mV
0: 100 mV
6
CMP2HYS
CMP1HYS
CMP0HYS
CMP3PL
5
4
3
Polarity select bit:
1: Compare on going up
0: Compare on going down
2
CMP2PL
1
CMP1PL
In both polarity modes the comparator works as an
edge detector: the corresponding input signal must
rise above or fall below the trigger level in order the
activate the interrupt. Once the comparator is
tripped, the enable bit must be set to '0' to reset the
comparator logic, and then set to '1' to re-arm for the
next compare.
0
CMP0PL
Comparator 0
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38
R18 - GPO Control Register
This register controls the operation of the 4 MFP pins when configured as GPO output pins.
Bit
7
Field Name
GPO3OD
Description
GPO3 Open Drain
GPO2 Open Drain
GPO1 Open Drain
GPO0 Open Drain
GPO3 Enable
6
GPO2OD
GPO1OD
GPO0OD
GPO3EN
GPO2EN
GPO1EN
1: GPO pin is open drain
0: GPO pin is push-pull
5
4
3
1: Enable the corresponding Multi-Function Pin to be
GPO
0: Disable the corresponding Multi-Function Pin to be
GPO and allow the pin to be used as ADC or
Comparator input pin.
2
GPO2 Enable
1
GPO1 Enable
0
GPO0EN
GPO0 Enable
R19 - GPO Data Register
This register controls the output value of the 4 MFP pins when configured as GPO output pins and according to the settings defined
in R18.
Bit
7:4
3
Field Name
Description
Unused
Return zero.
GPO3D
GPO3 Data Output
GPO2 Data Output
GPO1 Data Output
Write to this register to change the corresponding MFP pin
state:
1: Enable the corresponding Multi-Function Pin to be GPO
0: Disable the corresponding Multi-Function Pin to be GPO
and allow the pin to be used as ADC or Comparator input pin.
2
GPO2D
GPO1D
1
0
GPO0D
GPO0 Data Output
39
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Physical Dimensions inches (millimeters) unless otherwise noted
LLP Package SQA36B
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40
41
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