LM111J-8RLQMLV [TI]
电压比较器 | NAB | 8 | -55 to 125;
| 型号： | LM111J-8RLQMLV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 电压比较器 | NAB | 8 | -55 to 125 放大器 比较器 |
| 文件： | 总47页 (文件大小：1410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM111QML
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LM111QML Voltage Comparator
Check for Samples: LM111QML
1
FEATURES
DESCRIPTION
The LM111 is a voltage comparator that has input
currents nearly a thousand times lower than devices
such as the LM106 or LM710. It is also designed to
operate over a wider range of supply voltages: from
standard ±15V op amp supplies down to the single
5V supply used for IC logic. The output is compatible
with RTL, DTL and TTL as well as MOS circuits.
Further, it can drive lamps or relays, switching
voltages up to 50V at currents as high as 50 mA.
2
•
Available with radiation ensured
–
–
High Dose Rate 50 krad(Si)
Low Dose and ELDRS Free 100 krad(Si)
•
•
•
•
•
•
•
•
Operates from single 5V supply
Input current: 200 nA max. over temperature
Offset current: 20 nA max. over temperature
Differential input voltage range: ±30V
Power consumption: 135 mW at ±15V
Power supply voltage, single 5V to ±15V
Offset voltage null capability
Both the inputs and the output of the LM111 can be
isolated from system ground, and the output can
drive loads referred to ground, the positive supply or
the negative supply. Offset balancing and strobe
capability are provided and outputs can be wire
OR'ed. Although slower than the LM106 and LM710
(200 ns response time vs 40 ns) the device is also
much less prone to spurious oscillations. The LM111
has the same pin configuration as the LM106 and
LM710.
Strobe capability
Connection Diagrams
TO-99 Package
Note: Pin 4 connected to case
Figure 1. Top View
Package Number LMC0008C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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CDIP Package
CDIP Package
Figure 2. Top View
Package Number NAB008A
Figure 3. Top View
Package Number J0014A
N/C
3
GND
2
N/C
1
V+
20
N/C
19
N/C
IN+
N/C
IN-
4
5
6
7
8
18
17
16
15
14
N/C
OUTPUT
N/C
BALANCE/
STROBE
N/C
N/C
9
10
V-
11
12
13
N/C
N/C BALANCE N/C
Figure 4. Top View
Package Number NAC0010A, NAD0010A
Figure 5. Top View
Package Number NAJ0020A
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Schematic Diagram
Pin connections shown on schematic diagram are for LMC0008C package.
Figure 6.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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(1)
Absolute Maximum Ratings
Positive Supply Voltage
Negative Supply Voltage
Total Supply Voltage
+30.0V
-30.0V
36V
Output to Negative Supply Voltage
GND to Negative Supply Voltage
Differential Input Voltage
Sink Current
50V
30V
±30V
50mA
±15V
(2)
Input Voltage
(3)
Power Dissipation
8 LD CDIP
400mW at 25°C
330mW at 25°C
330mW at 25°C
330mW at 25°C
500mW at 25°C
10 seconds
8 LD TO-99
10 LD CLGA
10 LD CLGA
20 LD LCCC
Output Short Circuit Duration
Maximum Strobe Current
Operating Temperature Range
Thermal Resistance
10mA
-55°C ≤ TA ≤ 125°C
θJA
8 LD CDIP (Still Air at 0.5W)
8 LD CDIP (500LF/Min Air flow at 0.5W)
8 LD TO-99 (Still Air at 0.5W)
8 LD TO-99 (500LF/Min Air flow at 0.5W)
10 LD CLGA (Still Air at 0.5W)
10 LD CLGA (500LF/Min Air flow at 0.5W)
10 LD CLGA (Still Air at 0.5W)
10 LD CLGA (500LF/Min Air flow at 0.5W)
14 LD CDIP(Still Air at 0.5W)
14 LD CDIP (500LF/Min Air flow at 0.5W)
20 LD LCCC (Still Air at 0.5W)
20 LD LCCC (500LF/Min Air flow at 0.5W)
θJC
134°C/W
76°C/W
162°C/W
92°C/W
231°C/W
153°C/W
231°C/W
153°C/W
97°C/W
65°C/W
90°C/W
65°C/W
8 LD CDIP
21°C/W
50°C/W
24°C/W
24°C/W
20°C/W
21°C/W
8 LD TO-99
10 LD CLGA
10 LD CLGA
14 LD CDIP
20 LD LCCC
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical
Characteristics tables. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when
the device is not operated under the listed test conditions.
(2) This rating applies for ±15V supplies. The positive input voltage limits is 30 V above the negative supply. The negative input voltage
limits is equal to the negative supply voltage or 30V below the positive supply, whichever is less.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
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Absolute Maximum Ratings (1) (continued)
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature (Soldering, 60 seconds)
Voltage at Strobe Pin
-65°C ≤ TA ≤ 150°C
175°C
300°C
V+ = -5V
Package Weight (Typical)
8 LD TO-99
965mg
1100mg
250mg
225mg
TBD
8 LD CDIP
10 LD CLGA
10 LD CLGA
14 LD CDIP
20 LD LCCC
TBD
(4)
ESD Rating
300V
(4) Human body model, 1.5 kΩ in series with 100 pF.
Recommended Operating Conditions
Supply Voltage
VCC = ±15VDC
Operating Temperature Range
-55°C ≤ TA ≤ 125°C
Quality Conformance Inspection
Table 1. Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temperature (°C)
1
2
+25
+125
-55
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
+125
-55
5
6
7
+25
+125
-55
8A
8B
9
+25
+125
-55
10
11
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LM111/883 Electrical Characteristics DC Parameters(1)
The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC
(2)
The pin assignments are based on the 8 pin package configuration.
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min
Max Unit
IIO
Input Offset Current
VCM = 13.5V, RS = 50KΩ
-10
-20
10
20
nA
nA
1
2, 3
VCM = 13.5V, V85 = V86 = 0V, RS
50KΩ
=
(2)
-30
30
nA
1
VCM = -14.5V, RS= 50KΩ
-10
-20
10
20
nA
nA
1
2, 3
VCM = -14.5V, V85 = V86 = 0V, RS=
50KΩ
(2)
(2)
-30
30
nA
1
RS = 50KΩ
-10
-20
-30
10
20
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
V
1
2, 3
1
V85 = V86 = 0V, RS = 50KΩ
VCM = 13.5V, RS = 50KΩ
30
IIB
Input Bias Current
100
150
100
150
100
150
10
1
2, 3
1
VCM = -14.5V, RS = 50KΩ
RS = 50KΩ
2, 3
1
2, 3
1
(2)
(2)
(2)
(2)
(2)
(2)
IOL
Output Leakage Current
Ground Leakage Current
Saturation Voltage
VCC = ± 18V, I5 + I6 = 5mA,
VO = 35V WRT -VCC
500
25
2, 3
1
IGL
VCC = ± 18V, I5 + I6 = 5mA,
VO = 50V WRT -VCC
500
1.5
0.4
2
VSat
-ICC
+ICC
IL1
VI = -5mV, I7 = 50mA
VI = -6mV, I7 = 8mA
1, 2, 3
1, 2, 3
1, 2
3
V
Negative Supply Current
Positive Supply Current
Input Leakage Current
5.0
15
6.0
15
10
mA
mA
mA
mA
nA
1, 2
3
(2)
(2)
(2)
(2)
VCC = ± 18V, V28 = 1V,
V38 = 30V, I5 + I6 = 5mA
VO = 50V WRT -VCC
1
30
10
30
nA
nA
nA
2
1
2
IL2
Input Leakage Current
VCC = ± 18V, V38 = 1V,
V28 = 30V, I5 + I6 = 5mA
VO = 50V WRT -VCC
VOSt
Collector Output Voltage (Strobe)
14
14
V
V
1
1
ISt = 3mA
(1) Calculated parameter.
(2) Pin names based on an 8 pin package configuration. When using higher pin count packages then: Pin 2 & 3 are Inputs, Pin 5 is
Balance, Pin 6 is Balance /Strobe, Pin 7 is Output, and Pin 8 is V+. For example: V56 is the Voltage between the Balance and Balance /
Strobe pins.
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LM111/883 Electrical Characteristics DC Parameters(1) (continued)
The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC
The pin assignments are based on the 8 pin package configuration. (2)
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min
Max Unit
mV
VIO
Input Offset Voltage
VCM = 13.5V
-3.0
-4.0
-3.0
-3.0
-4.0
-3.0
-3.0
-4.0
-3.0
-5.0
-6.0
-3.0
-4.0
-5.0
-6.0
-3.0
-4.0
40
3.0
4.0
3.0
3.0
4.0
3.0
3.0
4.0
3.0
5.0
6.0
3.0
4.0
5.0
6.0
3.0
4.0
1
2, 3
1
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
V/mV
V/mV
(2)
VCM = 13.5V, V85 = V86= 0V
VCM = -14.5V
1
2, 3
1
(2)
(2)
VCM = -14.5V, V85 = V86 = 0V
1
2, 3
1
V85 = V86 = 0V
VO = 0.4V, +VCC = 4.5V,
-VCC = 0V, VCM = 3V
1
2, 3
1
VO = 4.5V, +VCC = 4.5V,
-VCC = 0V, VCM = 3V
2, 3
1
VO = 0.4V, +VCC = 4.5V,
-VCC = 0V, VCM = 0.5V
2, 3
1
VO = 4.5V, +VCC = 4.5V,
-VCC = 0V, VCM = 0.5V
2, 3
4
(3)
(3)
AVS
Large Signal Gain
-12V ≤ VO ≤ 35V, RL = 1KΩ
30
5, 6
(3) Datalog reading in K=V/mV.
LM111/883 Electrical Characteristics AC Parameters(1)
The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC
(2)
The pin assignments are based on the 8 pin package configuration.
Notes
Min
Max Unit
400 nS
Sub-
groups
Symbol
Parameter
Conditions
tR
Response Time
7
(1) Calculated parameter.
(2) Pin names based on an 8 pin package configuration. When using higher pin count packages then: Pin 2 & 3 are Inputs, Pin 5 is
Balance, Pin 6 is Balance /Strobe, Pin 7 is Output, and Pin 8 is V+. For example: V56 is the Voltage between the Balance and Balance /
Strobe pins.
LM111-SMD Electrical Characteristics SMD 5962-8687701 DC Parameters(1)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
VIO
Parameter
Conditions
VI = 0V, RS = 50Ω
Notes
Min
Max Unit
Input Offset Voltage
-3.0
-4.0
-3.0
+3.0 mV
+4.0 mV
+3.0 mV
1
2, 3
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-4.0
-3.0
-4.0
-3.0
-4.0
+4.0 mV
+3.0 mV
+4.0 mV
+3.0 mV
+4.0 mV
2, 3
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
2, 3
1
+VCC = +2.5V, -VCC = -2.5V,
VI = 0V,
RS = 50Ω
2, 3
(1) Calculated parameter.
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LM111-SMD Electrical Characteristics SMD 5962-8687701 DC Parameters(1) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
VIO
Parameter
Conditions
VI = 0V, RS = 50Ω
Notes
Min
Max Unit
R
Raised Input Offset Voltage
-3.0
-4.5
-3
+3.0 mV
+4.5 mV
1
(2)
2, 3
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
+3
mV
(2)
(2)
-4.5
+4.5 mV
2, 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V, RS = 50Ω
-3.0
-4.5
-10
-20
-10
+3.0 mV
+4.5 mV
1
2, 3
1, 2
3
IIO
Input Offset Current
VI = 0V, RS = 50KΩ
+10
+20
+10
nA
nA
nA
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
1, 2
-20
-10
-20
+20
+10
+20
nA
nA
nA
3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
1, 2
3
IIO
R
Raised Input Offset Current
Input Bias Current
VI = 0V, RS = 50KΩ
-25
-50
+25
+50
nA
nA
nA
nA
nA
1, 2
3
(2)
±IIB
VI = 0V, RS = 50KΩ
-100 0.1
-150 0.1
-150 0.1
1, 2
3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
1, 2
-200 0.1
-150 0.1
nA
nA
nA
3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
1, 2
3
-200 0.1
(3)(4)
VOSt
Collector Output Voltage (Strobe) +VI = Gnd, -VI = 15V,
V
1, 2, 3
1, 2, 3
ISt = -3mA, RS = 50Ω
14
CMRR
Common Mode Rejection Ratio
Low Level Output Voltage
-28V ≤ -VCC ≤ -0.5V, RS = 50Ω, 2V
≤ +VCC ≤ 29.5V, RS = 50Ω, -14.5V
≤ VCM ≤ 13V, RS = 50Ω
80
dB
VOL
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 0.71V,
VID = -6mV
0.4
0.4
V
V
1, 2, 3
1, 2, 3
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = −1.75V,
VID = -6mV
IO = 50mA, ±VI = 13V,
VID = -5mV
1.5
1.5
V
V
1, 2, 3
1, 2, 3
IO = 50mA, ±Vl= -14V,
VID = -5mV
ICEX
Output Leakage Current
Input Leakage Current
+VCC = 18V, -VCC = -18V,
VO = 32V
-1.0
-1.0
10
nA
nA
1
2
500
IL
+VCC = 18V, -VCC = -18V,
+VI = +12V, -VI = -17V
(5)
(5)
-5.0
-5.0
500
500
nA
nA
1, 2, 3
1, 2, 3
+VCC = 18V, -VCC = -18V,
+VI = -17V, -VI = +12V
+ICC
Power Supply Current
6.0
7.0
mA
mA
1, 2
3
(2) Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +VCC
.
(3) IST = −2mA at −55°C
(4) Group A sample ONLY
(5) VID is voltage difference between inputs.
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LM111-SMD Electrical Characteristics SMD 5962-8687701 DC Parameters(1) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
-ICC
Parameter
Conditions
Notes
Min
Max Unit
Power Supply Current
-5.0
-6.0
-25
-25
mA
mA
1, 2
3
(5) (4)
(5) (4)
(5) (4)
(5) (4)
(6)
Δ VIO / ΔT
Δ IIO / ΔT
IOS
Temperature Coefficient Input
Offset Voltage
25°C ≤ T ≤ 125°C
25
25
µV/°C
2
-55°C ≤ T ≤ 25°C
25°C ≤ T ≤ 125°C
-55°C ≤ T ≤ 25°C
µV/°C
pA/°C
pA/°C
mA
3
Temperature Coefficient Input
Offset Current
-100 100
-200 200
200
2
3
Short Circuit Current
VO = 5V, t ≤ 10mS, -VI = 0.1V, +VI
1
= 0V
(6)
150
mA
2
(6)
250
mA
3
+VIO adj.
-VIO adj.
±AVE
Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω
Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω
5.0
mV
1
-5.0 mV
1
(7)
(7)
Voltage Gain (Emitter)
RL = 600Ω
10
V/mV
V/mV
4
8.0
5, 6
(6) Actual min. limit used is 5mA due to test setup.
(7) Datalog reading in K=V/mV.
LM111-SMD Electrical Characteristics SMD 5962-8687701 AC Parameters(1)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
tRLHC
Parameter
Conditions
Notes
Min Max
Unit
(2)
(2)
(2)
(2)
Response Time (Collector Output) VOD(Overdrive) = -5mV,
CL = 50pF, VI = -100mV
300
640
300
500
nS
nS
nS
nS
7, 8B
8A
tRHLC
Response Time (Collector Output) VOD(Overdrive) = 5mV,
CL = 50pF, VI = 100mV
7, 8B
8A
(1) Calculated parameter.
(2) Group A sample ONLY
LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC Parameters(1)(2)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
VIO
Parameter
Conditions
VI = 0V, RS = 50Ω
Notes
Min
Max Unit
Input Offset Voltage
-3.0
-4.0
-3.0
+3.0 mV
+4.0 mV
+3.0 mV
1
2, 3
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-4.0
-3.0
-4.0
+4.0 mV
+3.0 mV
+4.0 mV
2, 3
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
2, 3
+VCC = +2.5V, -VCC = -2.5V,
VI = 0V, RS = 50Ω
-3.0
-4.0
+3.0 mV
+4.0 mV
1
2, 3
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019,
Condition A.
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LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC Parameters(1)(2) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
VIO
Parameter
Conditions
VI = 0V, RS = 50Ω
Notes
Min
Max Unit
R
Raised Input Offset Voltage
-3.0
-4.5
-3.0
+3.0 mV
+4.5 mV
+3.0 mV
1
(3)
2, 3
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
(3)
(3)
-4.5
-3.0
-4.5
+4.5 mV
+3.0 mV
+4.5 mV
2, 3
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
2, 3
IIO
Input Offset Current
VI = 0V, RS = 50KΩ
-10
-20
-10
+10
+20
+10
nA
nA
nA
1, 2
3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
1, 2
-20
-10
-20
+20
+10
+20
nA
nA
nA
3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
1, 2
3
IIO
R
Raised Input Offset Current
Input Bias Current
VI = 0V, RS = 50KΩ
-25
-50
+25
+50
nA
nA
nA
nA
nA
1, 2
3
(3)
±IIB
VI = 0V, RS = 50KΩ
-100 0.1
-150 0.1
-150 0.1
1, 2
3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
1, 2
-200 0.1
-150 0.1
nA
nA
nA
3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
1, 2
3
-200 0.1
(4)(5)
VOSt
Collector Output Voltage (Strobe) +VI = Gnd, -VI = 15V,
V
1, 2, 3
1, 2, 3
ISt = -3mA, RS = 50Ω
14
CMRR
Common Mode Rejection Ratio
Low Level Output Voltage
-28V ≤ -VCC ≤ -0.5V, RS = 50Ω, 2V
≤ +VCC ≤ 29.5V, RS = 50Ω, -14.5V
≤ VCM ≤ 13V, RS = 50Ω
80
dB
VOL
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 0.5V,
VID = -6mV
0.4
0.4
V
V
1, 2, 3
1, 2, 3
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 3V,
VID = -6mV
IO = 50mA, ±VI = 13V,
VID = -5mV
1.5
1.5
V
V
1, 2, 3
1, 2, 3
IO = 50mA, ±VI = -14V,
VID = -5mV
ICEX
Output Leakage Current
Input Leakage Current
+VCC = 18V, -VCC = -18V,
VO = 32V
-1.0
-1.0
10
nA
nA
1
2
500
IL
+VCC = 18V, -VCC = -18V,
+VI = +12V, -VI = -17V
(6)
(6)
-5.0
-5.0
500
500
nA
nA
1, 2, 3
1, 2, 3
+VCC = 18V, -VCC = -18V,
+VI = -17V, -VI = +12V
+ICC
Power Supply Current
6.0
7.0
mA
mA
1, 2
3
(3) Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +VCC
.
(4) IST = −2mA at −55°C
(5) Group A sample ONLY
(6) VID is voltage difference between inputs.
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LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC Parameters(1)(2) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
-ICC
Parameter
Conditions
Notes
Min
Max Unit
Power Supply Current
-5.0
-6.0
-25
-25
mA
mA
1, 2
3
ΔVIO / ΔT
Δ IIO / ΔT
IOS
Temperature Coefficient Input
Offset Voltage
25°C ≤ T ≤ 125°C
25
25
µV/°C
2
-55°C ≤ T ≤ 25°C
25°C ≤ T ≤ 125°C
-55°C ≤ T ≤ 25°C
µV/°C
pA/°C
pA/°C
mA
3
Temperature Coefficient Input
Offset Current
-100 100
-200 200
200
2
3
(7)
(7)
(7)
Short Circuit Current
VO = 5V, t ≤ 10mS, -VI = 0.1V, +VI
1
= 0V
150
mA
2
250
mA
3
+VIO adj.
-VIO adj.
±AVE
Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω
Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω
5.0
mV
1
-5.0 mV
1
(8)
(8)
Voltage Gain (Emitter)
RL = 600Ω
10
V/mV
V/mV
4
8.0
5, 6
(7) Actual min. limit used is 5mA due to test setup.
(8) Datalog reading in K=V/mV.
LM111 RADIATION Electrical Characteristics SMD 5962L0052401 AC Parameters(1)(2)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
tRLHC
Parameter
Conditions
Notes
Min Max
Unit
Response Time (Collector Output) VOD(Overdrive) = -5mV,
CL = 50pF, VI = -100mV
300
640
300
500
nS
nS
nS
nS
7, 8B
8A
(3)
tRHLC
Response Time (Collector Output) VOD(Overdrive) = 5mV,
CL = 50pF, VI = 100mV
7, 8B
8A
(3)
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019,
Condition A.
(3) Group A sample ONLY
LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC DELTA Parameters(1)(2)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Delta calculations performed on QMLV devices at group B , subgroup 5.
Sub-
groups
Symbol
VIO
Parameter
Conditions
Notes
Min Max
Unit
Input Offset Voltage
VI = 0V, RS = 50Ω
-0.5
-0.5
0.5
0.5
mV
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
mV
mV
1
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
-0.5
0.5
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019,
Condition A.
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LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC DELTA
Parameters(1)(2) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Delta calculations performed on QMLV devices at group B , subgroup 5.
Sub-
groups
Symbol
±IIB
Parameter
Input Bias Current
Conditions
Notes
Min Max
Unit
VI = 0V, RS = 50KΩ
-12.5 12.5
nA
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-12.5 12.5
-12.5 12.5
nA
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
nA
nA
1
1
ICEX
Output Leakage Current
+VCC = 18V, -VCC = -18V,
VO = 32V
-5.0
5.0
LM111 RADIATION Electrical Characteristics SMD 5962L0052401 Post Radiation Parameters(1)(2)
The following conditions apply, unless otherwise specified
Sub-
groups
Symbol
IIO
Parameter
Input Offset Current
Conditions
Notes
Min Max
Unit
+VCC = 29.5V, −VCC = −0.5V, VI =
0V, VCM = −14.5V,
−50
+50
nA
1
RS = 50KΩ
+VCC = 2V, −VCC = −28V,
−50
+50
nA
1
VI = 0V, VCM = +13V, RS = 50KΩ
±IIB
Input Bias Current
VI = 0V, RS = 50KΩ
−150 0.1
−175 0.1
nA
nA
1
1
+VCC = 29.5V, −VCC = −0.5V, VI =
0V, VCM = −14.5V,
RS = 50KΩ
ICEX
Output Leakage Current
+VCC = 18V, −VCC = −18V,
−25
+25
nA
1
VO = 32V
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect.
Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019,
Condition A.
LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC Parameters(1)(2)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
VIO
Parameter
Conditions
VI = 0V, RS = 50Ω
Notes
Min
Max Unit
Input Offset Voltage
-3.0
-4.0
-3.0
+3.0 mV
+4.0 mV
+3.0 mV
1
2, 3
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-4.0
-3.0
-4.0
+4.0 mV
+3.0 mV
+4.0 mV
2, 3
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
2, 3
+VCC = +2.5V, -VCC = -2.5V,
VI = 0V, RS = 50Ω
-3.0
-4.0
+3.0 mV
+4.0 mV
1
2, 3
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a
wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.
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LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC Parameters(1)(2) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
VIO
Parameter
Conditions
VI = 0V, RS = 50Ω
Notes
Min
Max Unit
R
Raised Input Offset Voltage
-3.0
-4.5
-3.0
+3.0 mV
+4.5 mV
+3.0 mV
1
(2)
2, 3
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
(2)
(2)
-4.5
-3.0
-4.5
+4.5 mV
+3.0 mV
+4.5 mV
2, 3
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
2, 3
IIO
Input Offset Current
VI = 0V, RS = 50KΩ
-10
-20
-10
+10
+20
+10
nA
nA
nA
1, 2
3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
1, 2
-20
-10
-20
+20
+10
+20
nA
nA
nA
3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
1, 2
3
IIO
R
Raised Input Offset Current
Input Bias Current
VI = 0V, RS = 50KΩ
-25
-50
+25
+50
nA
nA
nA
nA
nA
1, 2
3
(2)
±IIB
VI = 0V, RS = 50KΩ
-100 0.1
-150 0.1
-150 0.1
1, 2
3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
1, 2
-200 0.1
-150 0.1
nA
nA
nA
3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
1, 2
3
-200 0.1
(3)(4)
VOSt
Collector Output Voltage (Strobe) +VI = Gnd, -VI = 15V,
V
1, 2, 3
1, 2, 3
ISt = -3mA, RS = 50Ω
14
CMRR
Common Mode Rejection Ratio
Low Level Output Voltage
-28V ≤ -VCC ≤ -0.5V, RS = 50Ω, 2V
≤ +VCC ≤ 29.5V, RS = 50Ω, -14.5V
≤ VCM ≤ 13V, RS = 50Ω
80
dB
VOL
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 0.5V,
VID = -6mV
0.4
0.4
V
V
1, 2, 3
1, 2, 3
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 3V,
VID = -6mV
IO = 50mA, ±VI = 13V,
VID = -5mV
1.5
1.5
V
V
1, 2, 3
1, 2, 3
IO = 50mA, ±VI = -14V,
VID = -5mV
ICEX
Output Leakage Current
Input Leakage Current
+VCC = 18V, -VCC = -18V,
VO = 32V
-1.0
-1.0
10
nA
nA
1
2
500
IL
+VCC = 18V, -VCC = -18V,
+VI = +12V, -VI = -17V
(5)
(5)
-5.0
-5.0
500
500
nA
nA
1, 2, 3
1, 2, 3
+VCC = 18V, -VCC = -18V,
+VI = -17V, -VI = +12V
+ICC
Power Supply Current
Power Supply Current
6.0
7.0
mA
mA
mA
mA
1, 2
3
-ICC
-5.0
-6.0
1, 2
3
(3) IST = −2mA at −55°C
(4) Group A sample ONLY
(5) VID is voltage difference between inputs.
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LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC Parameters(1)(2) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min
Max Unit
ΔVIO / ΔT
Temperature Coefficient Input
Offset Voltage
25°C ≤ T ≤ 125°C
-25
-25
25
25
µV/°C
2
-55°C ≤ T ≤ 25°C
25°C ≤ T ≤ 125°C
-55°C ≤ T ≤ 25°C
µV/°C
pA/°C
pA/°C
mA
3
Δ IIO / ΔT
Temperature Coefficient Input
Offset Current
-100 100
-200 200
200
2
3
(6)
(5)
(5)
IOS
Short Circuit Current
VO = 5V, t ≤ 10mS, -VI = 0.1V, +VI
= 0V
1
150
mA
2
250
mA
3
+VIO adj.
-VIO adj.
±AVE
Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω
Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω
5.0
mV
1
-5.0 mV
1
(7)
(7)
Voltage Gain (Emitter)
RL = 600Ω
10
V/mV
V/mV
4
8.0
5, 6
(6) Actual min. limit used is 5mA due to test setup.
(7) Pin names based on an 8 pin package configuration. When using higher pin count packages then: Pin 2 & 3 are Inputs, Pin 5 is
Balance, Pin 6 is Balance /Strobe, Pin 7 is Output, and Pin 8 is V+. For example: V56 is the Voltage between the Balance and Balance /
Strobe pins.
LM111 RADIATION Electrical Characteristics SMD 5962R0052402 AC Parameters(1)(2)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Sub-
Symbol
tRLHC
Parameter
Conditions
Notes
Min Max
Unit
groups
7, 8B
8A
Response Time (Collector Output) VOD(Overdrive) = -5mV,
CL = 50pF, VI = -100mV
300
640
300
500
nS
nS
nS
nS
(3)
tRHLC
Response Time (Collector Output) VOD(Overdrive) = 5mV,
CL = 50pF, VI = 100mV
7, 8B
8A
(3)
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a
wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.
(3) Group A sample ONLY
LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC DELTA Parameters(1)(2)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Delta calculations performed on QMLV devices at group B , subgroup 5.
Sub-
groups
Symbol
VIO
Parameter
Conditions
Notes
Min Max
Unit
Input Offset Voltage
VI = 0V, RS = 50Ω
-0.5
-0.5
0.5
0.5
mV
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
mV
mV
1
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
-0.5
0.5
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a
wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.
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LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC DELTA
Parameters(1)(2) (continued)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Delta calculations performed on QMLV devices at group B , subgroup 5.
Sub-
groups
Symbol
±IIB
Parameter
Input Bias Current
Conditions
Notes
Min Max
Unit
VI = 0V, RS = 50KΩ
-12.5 12.5
nA
1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-12.5 12.5
-12.5 12.5
nA
1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
nA
nA
1
1
ICEX
Output Leakage Current
+VCC = 18V, -VCC = -18V,
VO = 32V
-5.0
5.0
LM111 RADIATION Electrical Characteristics SMD 5962R0052402 Post Radiation Parameters(1)(2)
The following conditions apply, unless otherwise specified
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Unit
(3)
IIO
R
Raised Input Offset Current
Input Bias Current
VI = 0V, RS = 50KΩ
−100 +100
−180 0.1
−225 0.1
nA
nA
nA
1
1
1
±IIB
VI = 0V, RS = 50KΩ
+VCC = 29.5V, −VCC = −0.5V, VI =
0V, VCM = −14.5V, RS = 50KΩ
ICEX
Output Leakage Current
+VCC = 18V, −VCC = −18V,
−1.0 +25
nA
1
VO = 32V
(1) Calculated parameter.
(2) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a
wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.
(3) Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +VCC
.
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LM111 Typical Performance Characteristics
Input Bias Current
Input Bias Current
Figure 7.
Figure 8.
Input Bias Current
Input Bias Current
Figure 9.
Figure 10.
Input Bias Current
Input Bias Current
Figure 11.
Figure 12.
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LM111 Typical Performance Characteristics (continued)
Input Bias Current
Input Overdrives
Input Bias Current
Input Overdrives
Figure 13.
Figure 14.
Response Time for Various
Input Overdrives
Input Bias Current
Figure 15.
Figure 16.
Response Time for Various
Input Overdrives
Output Limiting Characteristics
Figure 17.
Figure 18.
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LM111 Typical Performance Characteristics (continued)
Supply Current
Supply Current
Figure 19.
Figure 20.
Leakage Currents
Figure 21.
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APPLICATION HINTS
CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS
When a high-speed comparator such as the LM111 is used with fast input signals and low source impedances,
the output response will normally be fast and stable, assuming that the power supplies have been bypassed (with
0.1 μF disc capacitors), and that the output signal is routed well away from the inputs (pins 2 and 3) and also
away from pins 5 and 6.
However, when the input signal is a voltage ramp or a slow sine wave, or if the signal source impedance is high
(1 kΩ to 100 kΩ), the comparator may burst into oscillation near the crossing-point. This is due to the high gain
and wide bandwidth of comparators like the LM111. To avoid oscillation or instability in such a usage, several
precautions are recommended, as shown in Figure 22 below.
1. The trim pins (pins 5 and 6) act as unwanted auxiliary inputs. If these pins are not connected to a trim-pot,
they should be shorted together. If they are connected to a trim-pot, a 0.01 μF capacitor C1 between pins 5
and 6 will minimize the susceptibility to AC coupling. A smaller capacitor is used if pin 5 is used for positive
feedback as in Figure 22.
2. Certain sources will produce a cleaner comparator output waveform if a 100 pF to 1000 pF capacitor C2 is
connected directly across the input pins.
3. When the signal source is applied through a resistive network, RS, it is usually advantageous to choose an
RS′ of substantially the same value, both for DC and for dynamic (AC) considerations. Carbon, tin-oxide, and
metal-film resistors have all been used successfully in comparator input circuitry. Inductive wire wound
resistors are not suitable.
4. When comparator circuits use input resistors (e.g. summing resistors), their value and placement are
particularly important. In all cases the body of the resistor should be close to the device or socket. In other
words there should be very little lead length or printed-circuit foil run between comparator and resistor to
radiate or pick up signals. The same applies to capacitors, pots, etc. For example, if RS=10 kΩ, as little as 5
inches of lead between the resistors and the input pins can result in oscillations that are very hard to damp.
Twisting these input leads tightly is the only (second best) alternative to placing resistors close to the
comparator.
5. Since feedback to almost any pin of a comparator can result in oscillation, the printed-circuit layout should be
engineered thoughtfully. Preferably there should be a ground plane under the LM111 circuitry, for example,
one side of a double-layer circuit card. Ground foil (or, positive supply or negative supply foil) should extend
between the output and the inputs, to act as a guard. The foil connections for the inputs should be as small
and compact as possible, and should be essentially surrounded by ground foil on all sides, to guard against
capacitive coupling from any high-level signals (such as the output). If pins 5 and 6 are not used, they should
be shorted together. If they are connected to a trim-pot, the trim-pot should be located, at most, a few inches
away from the LM111, and the 0.01 μF capacitor should be installed. If this capacitor cannot be used, a
shielding printed-circuit foil may be advisable between pins 6 and 7. The power supply bypass capacitors
should be located within a couple inches of the LM111. (Some other comparators require the power-supply
bypass to be located immediately adjacent to the comparator.)
6. It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation,
and to avoid excessive noise on the output because the comparator is a good amplifier for its own noise. In
the circuit of Figure 23, the feedback from the output to the positive input will cause about 3 mV of
hysteresis. However, if RS is larger than 100Ω, such as 50 kΩ, it would not be reasonable to simply increase
the value of the positive feedback resistor above 510 kΩ. The circuit of Figure 24 could be used, but it is
rather awkward. See the notes in paragraph 7 below.
7. When both inputs of the LM111 are connected to active signals, or if a high-impedance signal is driving the
positive input of the LM111 so that positive feedback would be disruptive, the circuit of Figure 22 is ideal.
The positive feedback is to pin 5 (one of the offset adjustment pins). It is sufficient to cause 1 to 2 mV
hysteresis and sharp transitions with input triangle waves from a few Hz to hundreds of kHz. The positive-
feedback signal across the 82Ω resistor swings 240 mV below the positive supply. This signal is centered
around the nominal voltage at pin 5, so this feedback does not add to the VOS of the comparator. As much as
8 mV of VOS can be trimmed out, using the 5 kΩ pot and 3 kΩ resistor as shown.
8. These application notes apply specifically to the LM111 and are applicable to all high-speed comparators in
general, (with the exception that not all comparators have trim pins).
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Pin connections shown are for LM111H in the LMC0008C package
Figure 22. Improved Positive Feedback
Pin connections shown are for LM111H in the LMC0008C package
Figure 23. Conventional Positive Feedback
Figure 24. Positive Feedback with High Source Resistance
20
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Product Folder Links: LM111QML
LM111QML
www.ti.com
SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
TYPICAL APPLICATIONS
Figure 25. Offset Balancing
Note: Do Not Ground Strobe Pin. Output is turned off when current is pulled from Strobe Pin.
Figure 26. Strobing
Increases typical common mode slew from 7.0V/μs to 18V/μs.
Figure 27. Increasing Input Stage Current
Figure 28. Detector for Magnetic Transducer
Copyright © 2005–2013, Texas Instruments Incorporated
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SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
www.ti.com
Figure 29. Digital Transmission Isolator
*Absorbs inductive kickback of relay and protects IC from severe voltage transients on V++ line.
Note: Do Not Ground Strobe Pin.
Figure 30. Relay Driver with Strobe
Note: Do Not Ground Strobe Pin.
(1) Typical input current is 50 pA with inputs strobed off.
(2) Pin connections shown on schematic diagram and typical applications are for LMC0008C package.
Figure 31. Strobing off Both Input and Output Stages
22
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Product Folder Links: LM111QML
LM111QML
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SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
*Solid tantalum
Figure 32. Positive Peak Detector
Figure 33. Zero Crossing Detector Driving MOS Logic
Copyright © 2005–2013, Texas Instruments Incorporated
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LM111QML
SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
www.ti.com
TYPICAL APPLICATIONS FOR METAL CYLINDER PACKAGE
(Pin numbers refer to LMC0008C package)
Figure 34. Zero Crossing Detector Driving MOS Switch
*TTL or DTL fanout of two
Figure 35. 100 kHz Free Running Multivibrator
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LM111QML
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SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
*Adjust for symmetrical square wave time when VIN = 5 mV
†Minimum capacitance 20 pF Maximum frequency 50 kH
Figure 36. 10 Hz to 10 kHz Voltage Controlled Oscillator
*Input polarity is reversed when using pin 1 as output.
Figure 37. Driving Ground-Referred Load
Figure 38. Using Clamp Diodes to Improve Response
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*Values shown are for a 0 to 30V logic swing and a 15V threshold.
†May be added to control speed and reduce susceptibility to noise spikes.
Figure 39. TTL Interface with High Level Logic
Figure 40. Crystal Oscillator
Figure 41. Comparator and Solenoid Driver
26
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LM111QML
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SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
*Solid tantalum
†Adjust to set clamp level
Figure 42. Precision Squarer
*Solid tantalum
Figure 43. Low Voltage Adjustable Reference Supply
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*Solid tantalum
Figure 44. Positive Peak Detector
Figure 45. Zero Crossing Detector Driving MOS Logic
*Solid tantalum
Figure 46. Negative Peak Detector
28
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Product Folder Links: LM111QML
LM111QML
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SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
*R2 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing leakages by
an order of magnitude.
Figure 47. Precision Photodiode Comparator
Figure 48. Switching Power Amplifier
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Figure 49. Switching Power Amplifier
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LM111QML
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SNOSAJ4C –OCTOBER 2005–REVISED MARCH 2013
Table 2. Revision History
Released
Revision
Section
New Release, Corporate format
Originator
Changes
10/11/05
A
L. Lytle
3 MDS data sheets converted into one Corp.
data sheet format. MNLM111-X Rev 0A0,
MDLM111-X Rev. 0B0, and MRLM111-X-RH
Rev 0E1. The drift table was eliminated from
the 883 section since it did not apply; Note #3
was removed from RH & QML datasheets with
SG verification that it no longer applied. Added
NSID's for 50k Rad and Post Radiation Table.
MDS data sheets will be archived.
12/14/05
B
Ordering Information Table
R. Malone
Removed NSID reference LM111J-8PQMLV,
5962P0052401VPA
30k rd(Si). Reason: NSID on LTB, Inventory
exhausted. Added following NSID's:
LM111HPQMLV, LM111WPQMLV and
LM111WGPQMLV. Reason: Still have
Inventory. LM111QML, Revision A will be
archived.
06/26/08
C
C
Features, Ordering Information Table,
Electrical section Notes.
Larry McGee
Added Radiation reference, ELDRS NSID's and
Note 14 and 15, Low Dose Electrical Table.
Deleted 30k rd(Si) NSID's: LM111HPQMLV,
LM111WPQMLV and LM111WGPQMLV.
Reason: EOL 9/06/05. Revision B will be
archived.
03/26/2013
All Sections
Changed layout of National Data Sheet to TI
format
Copyright © 2005–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962L0052401VGA
ACTIVE
TO-99
CFP
LMC
8
20
Non-RoHS &
Non-Green
Call TI
Call TI
-55 to 125
LM111HLQMLV
5962L0052401VGA Q
Samples
ACO
5962L0052401VGA Q
>T
5962L0052401VHA
ACTIVE
NAD
10
19
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
LM111W
Samples
LQMLV Q
5962L00524
01VHA ACO
01VHA >T
5962L0052401VPA
5962L0052401VZA
ACTIVE
ACTIVE
CDIP
CFP
NAB
NAC
8
40
54
Non-RoHS
& Green
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
-55 to 125
LM111J-8LQV
5962L00524
01VPA Q ACO
01VPA Q >T
Samples
Samples
10
Non-RoHS
& Green
LM111W
GLQMLV Q
5962L00524
01VZA ACO
01VZA >T
5962R0052402VGA
5962R0052402VHA
ACTIVE
ACTIVE
TO-99
CFP
LMC
NAD
8
20
19
Non-RoHS &
Non-Green
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
LM111HRLQV
5962R0052402VGA Q
ACO
5962R0052402VGA Q
>T
Samples
Samples
10
Non-RoHS
& Green
Level-1-NA-UNLIM
LM111W
RLQMLV Q
5962R00524
02VHA ACO
02VHA >T
5962R0052402VPA
5962R0052402VZA
ACTIVE
ACTIVE
CDIP
CFP
NAB
NAC
8
40
54
Non-RoHS
& Green
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
-55 to 125
LM111J-8RLQV
5962R00524
02VPA Q ACO
02VPA Q >T
Samples
Samples
10
Non-RoHS
& Green
LM111W
GRLQMLV Q
5962R00524
02VZA ACO
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
02VZA >T
LM111 MD8
LM111-MDE
LM111H/883
ACTIVE
ACTIVE
ACTIVE
DIESALE
DIESALE
TO-99
Y
Y
0
0
8
300
40
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
-55 to 125
-55 to 125
Samples
Samples
Samples
LMC
20
LM111H/883 Q ACO
LM111H/883 Q >T
LM111HLQMLV
ACTIVE
TO-99
LMC
LMC
8
20
20
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
LM111HLQMLV
5962L0052401VGA Q
ACO
5962L0052401VGA Q
>T
Samples
LM111HRLQMLV
ACTIVE
TO-99
8
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
LM111HRLQV
5962R0052402VGA Q
ACO
Samples
5962R0052402VGA Q
>T
LM111J-8/883
ACTIVE
ACTIVE
CDIP
CDIP
NAB
NAB
8
8
40
40
Non-RoHS
& Green
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
-55 to 125
LM111J-8
/883 Q ACO
/883 Q >T
Samples
Samples
LM111J-8LQMLV
Non-RoHS
& Green
LM111J-8LQV
5962L00524
01VPA Q ACO
01VPA Q >T
LM111J-8RLQMLV
ACTIVE
CDIP
NAB
8
40
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
LM111J-8RLQV
5962R00524
02VPA Q ACO
02VPA Q >T
Samples
LM111J/883
ACTIVE
ACTIVE
CDIP
CFP
J
14
10
25
54
Non-RoHS
& Green
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
-55 to 125
LM111J/883 Q
Samples
Samples
LM111WG/883
NAC
Non-RoHS
& Green
LM111WG
/883 Q ACO
/883 Q >T
LM111WGLQMLV
ACTIVE
CFP
NAC
10
54
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
LM111W
Samples
GLQMLV Q
5962L00524
01VZA ACO
01VZA >T
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM111WGRLQMLV
LM111WLQMLV
ACTIVE
CFP
CFP
CFP
NAC
10
10
10
54
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
LM111W
Samples
GRLQMLV Q
5962R00524
02VZA ACO
02VZA >T
ACTIVE
ACTIVE
NAD
NAD
19
19
Non-RoHS
& Green
Call TI
Call TI
-55 to 125
-55 to 125
LM111W
Samples
Samples
LQMLV Q
5962L00524
01VHA ACO
01VHA >T
LM111WRLQMLV
Non-RoHS
& Green
LM111W
RLQMLV Q
5962R00524
02VHA ACO
02VHA >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM111QML, LM111QML-SP :
Military : LM111QML
•
Space : LM111QML-SP
•
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962L0052401VHA
5962L0052401VPA
5962R0052402VHA
5962R0052402VPA
LM111J-8/883
NAD
NAB
NAD
NAB
NAB
NAB
NAB
J
CFP
CDIP
CFP
10
8
19
40
19
40
40
40
40
25
19
19
502
506.98
502
23
9398
13440
9398
9.78
NA
15.24
23
10
8
9.78
NA
CDIP
CDIP
CDIP
CDIP
CDIP
CFP
506.98
506.98
506.98
506.98
506.98
502
15.24
15.24
15.24
15.24
15.24
23
13440
13440
13440
13440
13440
9398
8
NA
LM111J-8LQMLV
LM111J-8RLQMLV
LM111J/883
8
NA
8
NA
14
10
10
NA
LM111WLQMLV
LM111WRLQMLV
NAD
NAD
9.78
9.78
CFP
502
23
9398
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
5962L0052401VGA
5962L0052401VZA
5962R0052402VGA
5962R0052402VZA
LM111H/883
LMC
NAC
LMC
NAC
LMC
LMC
LMC
NAC
NAC
NAC
TO-CAN
CFP
8
10
8
20
54
20
54
20
20
20
54
54
54
2 X 10
6 X 9
150
100
150
100
150
150
150
100
100
100
126.49 61.98 8890 11.18 12.95 18.54
101.6 101.6 8001 2.78 16.08 16.08
126.49 61.98 8890 11.18 12.95 18.54
101.6 101.6 8001 2.78 16.08 16.08
126.49 61.98 8890 11.18 12.95 18.54
126.49 61.98 8890 11.18 12.95 18.54
126.49 61.98 8890 11.18 12.95 18.54
101.6 101.6 8001 2.78 16.08 16.08
101.6 101.6 8001 2.78 16.08 16.08
101.6 101.6 8001 2.78 16.08 16.08
TO-CAN
CFP
2 X 10
6 X 9
10
8
TO-CAN
TO-CAN
TO-CAN
CFP
2 X 10
2 X 10
2 X 10
6 X 9
LM111HLQMLV
8
LM111HRLQMLV
LM111WG/883
8
10
10
10
LM111WGLQMLV
LM111WGRLQMLV
CFP
6 X 9
CFP
6 X 9
Pack Materials-Page 2
MECHANICAL DATA
NAB0008A
J08A (Rev M)
www.ti.com
PACKAGE OUTLINE
NAC0010A
CFP - 2.33mm max height
S
C
A
L
E
1
.
8
0
0
CERAMIC FLATPACK
LEAD 1 ID
NOTE 3
SUPPLIER OPTION
NOTE 3
.010 .002
[0.25 0.05]
.005 MIN
[0.12]
TYP
10
1
.2410 .0030
[6.121 0.076]
8X .050 .002
[1.27 0.05]
5
6
10X .017 .002
[0.43 0.05]
+.020
-.005
.241
+0.50
-0.12
6.12
[
]
.410 .010
[10.41 0.25]
+.010
.070
-.020
+0.25
SEE DETAIL A
.045 MAX TYP
[1.14]
1.78
[
-0.50
]
.004 [0.1]
.008 .004 TYP
[0.2 0.1]
.006 .002 TYP
[0.15 0.05]
SEATING PLANE
R.015 .002
[0.38 0.05]
.040 .003
[1.02 0.07]
0 -4
DETAIL A
TYPICAL
4215196/D 08/2022
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. For solder thickness and composition, see the "Lead Finish Composition/Thickness" link in the packaging section of the
Texas Instruments website
3. Lead 1 identification shall be:
a) A notch or other mark within this area
b) A tab on lead 1, either side
4. No JEDEC registration as of December 2021
www.ti.com
EXAMPLE BOARD LAYOUT
NAC0010A
CFP - 2.33mm max height
CERAMIC FLATPACK
(10X .090 )
SYMM
[2.29]
(8X .050 )
[1.27]
(10X .027 )
[0.69]
SYMM
(R.002 ) TYP
[0.05]
(.37 )
[9.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 7X
.003 MAX
[0.07]
ALL AROUND
.003 MIN
[0.07]
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
METAL
SOLDERMASK
OPENING
METAL UNDER
SOLDER MASK
SOLDERMASK
OPENING
SOLDERMASK
DEFINED
NON SOLDERMASK
DEFINED
4215196/D 08/2022
www.ti.com
REVISIONS
REV
A
DESCRIPTION
E.C.N.
DATE
BY/APP'D
RELEASE TO DOCUMENT CONTROL
2197877
2198820
2198845
2200915
12/30/2021
02/14/2022
02/18/2022
08/08/2022
DAVID CHIN / ANIS FAUZI
K. SINCERBOX
B
NO CHANGE TO DRAWING; REVISION FOR YODA RELEASE;
CHANGE PIN 1 ID LOCATION ON PIN
C
D. CHIN / K. SINCERBOX
D. CHIN / K. SINCERBOX
D
.2410 .0030 WAS .2700 +.0012/-.0002;
REV
SCALE
SIZE
PAGE
OF
4215196
D
4
4
A
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE
4X .005 MIN
[0.13]
PIN 1 ID
(OPTIONAL)
A
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
.13 MIN TYP
[3.3]
SEATING PLANE
C
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL B
14
SEE DETAIL A
1
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
(
.063)
[1.6]
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
(R.002 ) TYP
[0.05]
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
PACKAGE OUTLINE
NAD0010A
CFP - 2.03 mm max height
S
C
A
L
E
1
.
4
0
0
CERAMIC FLATPACK
.045 MAX
TYP
.010 .002
.27 MAX
GLASS
.005 MIN
TYP
PIN 1 ID
10
1
5
8X .050 .005
.27 MAX
6
10X .017 .002
+.019
.241
5X .32 .01
5X .32 .01
-.003
.005 .001
+.013
.067
-.012
.045
.026
4215191/A 06/2021
NOTES:
1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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