LM1771UMM/NOPB [TI]

具有精密启用和无需外部补偿组件的低压同步降压控制器 | DGK | 8;


型号：	LM1771UMM/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有精密启用和无需外部补偿组件的低压同步降压控制器 \| DGK \| 8 控制器开关
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LM1771

SNVS446D –JUNE 2006–REVISED JANUARY 2016

LM1771 Low-Voltage Synchronous Buck Controller With Precision Enable and No

External Compensation

1 Features

3 Description

The LM1771 device is an efficient synchronous buck

switching controller with a precision enable requiring

no external compensation. The constant ON-time

control scheme provides a simple design free of

•

Input Voltage Range of 2.8 V to 5.5 V

0.8-V Reference Voltage

•

Precision Enable

compensation

components,

allowing

minimal

No Compensation Required

Constant Frequency Across Input Range

Low Quiescent Current of 400 µA

Internal Soft-Start

component count and board space. The precision

enable pin allows flexibility in sequencing multiple

rails and setting UVLO. The LM1771 also

incorporates a unique input feedforward to maintain a

constant frequency independent of the input voltage.

The LM1771 is optimized for a low-voltage input

range of 2.8 V to 5.5 V and can provide an adjustable

output as low as 0.8 V. Driving an external high-side

PFET and low-side NFET, it can provide efficiencies

as high as 95%.

Short Circuit Protection

6-Pin WSON Package and 8-Pin VSSOP Package

2 Applications

•

Simple-to-Design, High-Efficiency, Step-Down

Switching Regulators

Three versions of the LM1771 are available

depending on the switching frequency desired for the

application. Nominal switching frequencies are in the

range of 100 kHz to 1000 kHz.

•

FPGAs, DSPs, and ASIC Power Supplies

Set-Top Boxes

Cable Modems

Device Information⁽¹⁾

Printers

PART NUMBER

LM1771

PACKAGE

WSON (6)

VSSOP (8)

BODY SIZE (NOM)

3.00 mm × 3.00 mm

Digital Video Recorders

Servers

Graphic Cards

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Circuit

VIN

OUT

LM1771

GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM1771

SNVS446D –JUNE 2006–REVISED JANUARY 2016

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Table of Contents

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................. 10

7.4 Device Functional Modes........................................ 12

Application and Implementation ........................ 13

8.1 Application Information............................................ 13

8.2 Typical Applications ................................................ 13

Power Supply Recommendations...................... 20

10 Layout................................................................... 21

10.1 Layout Guidelines ................................................. 21

10.2 Layout Examples................................................... 21

10.3 Thermal Considerations........................................ 22

11 Device and Documentation Support ................. 23

11.1 Device Support .................................................... 23

11.2 Documentation Support ........................................ 23

11.3 Community Resources.......................................... 23

11.4 Trademarks........................................................... 23

11.5 Electrostatic Discharge Caution............................ 23

11.6 Glossary................................................................ 23

12 Mechanical, Packaging, and Orderable

Information ........................................................... 23

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (April 2013) to Revision D

Page

•

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

Changes from Revision B (April 2013) to Revision C

Page

•

Changed layout of National Data Sheet to TI format ........................................................................................................... 22

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5 Pin Configuration and Functions

NGG Package

6-Pin WSON

Top View

GND

VIN

DAP

DGK Package

8-Pin VSSOP

Top View

VIN

GND

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

WSON

VSSOP

Die Attach Pad is internally connected to GND, but it cannot be used as the

primary GND connection

DAP

—

GND

Enable Pin

Feedback Pin

Ground

GND

2, 3

GND

PWR

PFET Gate Drive

NFET Gate Drive

Input Supply

VIN

6, 7

(1) I = Input, A = Analog, GND = Ground, AO = Analog output, PWR = Power

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6 Specifications

6.1 Absolute Maximum Ratings

(1) (2)

See

MIN

–0.3

MAX

UNIT

V_IN

EN, FB, HG, LG

Junction temperature

V_IN

150

260

150

°C

Lead temperature

Soldering, 10 sec

Storage temperature, T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

6.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

MAX UNIT

V_INto GND

2.8

5.5

Junction temperature, T_J

−40

125

°C

6.4 Thermal Information

LM1771

THERMAL METRIC⁽¹⁾

NGG (WSON)

6 PINS

52.8

DGK (VSSOP)

8 PINS

169.2

59.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

51.4

27.2

89.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.7

7.0

ψ_JB

27.3

87.9

R_θJC(bot)

7.4

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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6.5 Electrical Characteristics

Specifications are for T_J= 25°C. All maximum and minimum limits apply over the full junction temperature range (−40°C to

+125°C), unless otherwise specified. Minimum and maximum limits are ensured through test, design or statistical correlation.

Typical values represent the most likely parametric norm at T_J= 25°C and are provided for reference purposes only. Unless

otherwise specified, V_IN= 3.3 V.

PARAMETER

Feedback pin voltage

Quiescent current

TEST CONDITIONS

MIN

TYP

0.8

400

0.5

MAX

0.818

700

0.6

UNIT

V_FB

I_Q

0.782

V_FB= 0.9 V

µA

LM1771S - (500 ns)

LM1771T - (1000 ns)

LM1771U - (2000 ns)

LM1771S - (500 ns)

LM1771T - (1000 ns)

LM1771U - (2000 ns)

0.4

0.8

1.6

T_ON

Switch ON-time

1.2

µs

2.4

150

135

120

250

225

220

T_{OFF_MIN}

Minimum OFF-time

T_D

Gate drive dead-time

V_{IH_EN}

V_{EN_HYS}

I_FB

EN pin rising threshold

EN pin hysteresis

1.15

0.42

1.2

1.25

200

Feedback pin bias current

Undervoltage lockout

V_FB= 0.9 V

V_UVLO

V_{UVLO_HYS}

V_{SC_TH}

V_INRising Edge

2.65

2.8

Undervoltage lockout hysteresis

Feedback pin short circuit latch

threshold

0.55

0.65

R_{DS(ON) 1}

R_{DS(ON) 2}

R_{DS(ON) 3}

R_{DS(ON) 4}

HG FET driver pullup ON-resistance

I_HG= 20 mA

Ω

HG FET driver pulldown ON-resistance I_HG= 20 mA

LG FET driver pullup ON-resistance

LG FET driver pulldown ON-resistance

I_LG= 20 mA

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6.6 Typical Characteristics

All curves taken at VIN = 3.3 V with configuration in typical application circuit shown in Typical Applications. T_J= 25°C, unless

otherwise specified.

Figure 1. T_ONvs V_IN(LM1771S)

Figure 2. T_ONvs V_IN(LM1771T)

Figure 3. T_ONvs V_IN(LM1771U)

Figure 4. T_ONvs Temperature (LM1771S)

Figure 5. T_ONvs Temperature (LM1771T)

Figure 6. T_ONvs Temperature (LM1771U)

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Typical Characteristics (continued)

All curves taken at VIN = 3.3 V with configuration in typical application circuit shown in Typical Applications. T_J= 25°C, unless

otherwise specified.

Figure 7. T_OFFvs Temperature (LM1771S)

Figure 8. T_OFFvs Temperature (LM1771T)

Figure 9. T_OFFvs Temperature (LM1771U)

Figure 10. Feedback Voltage vs Temperature

Figure 11. V_ENThreshold vs Temperature

Figure 12. Short-Circuit Threshold vs Temperature

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Typical Characteristics (continued)

All curves taken at VIN = 3.3 V with configuration in typical application circuit shown in Typical Applications. T_J= 25°C, unless

otherwise specified.

Figure 13. Quiescent Current vs Temperature

Figure 14. Dead-Time vs Temperature

V_IN= 5 V

V_OUT= 1.8 V

F_SW= 545 kHz

V_IN= 5 V

V_OUT= 2.5 V

F_SW= 379 kHz

Figure 15. Efficiency vs I_OUT(LM1771T)

Figure 16. Efficiency vs I_OUT(LM1771U)

V_IN= 5 V

V_OUT= 3.3 V

F_SW= 500 kHz

V_IN= 5 V

V_OUT= 1.2 V

F_SW= 727 kHz

Figure 17. Efficiency vs I_OUT(LM1771U)

Figure 18. Efficiency vs I_OUT(LM1771S)

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7 Detailed Description

7.1 Overview

The LM1771 synchronous buck controller has a control scheme that is referred to as adaptive ON-time control.

This topology relies on a fixed switch ON-time to regulate the output voltage. This ON-time is internally set by

EEPROM and is available with three different set-points to allow for different frequency options. The LM1771

automatically adjusts the ON-time during operation inversely with the input voltage (VIN) to maintain a constant

frequency. Therefore the switching frequency during continuous conduction mode is independent of the inductor

and capacitor size unlike hysteretic switchers.

At the beginning of the cycle, the LM1771 turns on the high-side PFET for a fixed duration. This ON-time is

predetermined (internally set by EEPROM and adjusted by V_IN) and the switch does not turn off until the timer

has completed its period. The PFET then turns off for a minimum predetermined time period. This minimum T_OFF

of 150 ns is internally set and cannot be adjusted. This is to prevent false triggering from occurring on the

comparator due to noise from the SW node transition. After the minimum T_OFFperiod has expired, the PFET

remains off until the comparator trip-point has been reached. Upon passing this trip-point (set at 0.8 V at the

feedback pin), the PFET turns back on and the process repeats, thus regulating the output.

The NFET control is complementary to the PFET control with the exception of a short dead-time to prevent

shoot-through from occurring.

7.2 Functional Block Diagram

LM1771

VIN

ON TIMER

Vin

UVLO

OFF TIMER

High-Side

Driver

Level Shift

and

Shoot

0.8V

Through

Protection

Low-Side

Driver

REGULATION

COMPARATOR

0.55 V

UVLO

SHORT

CIRCUIT

/Soft-Start

PROTECTION

ENABLE

COMPARATOR

1.2 V

GND

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7.3 Feature Description

7.3.1 Timing Opinion

Three versions of the LM1771 are available each with a predetermined T_ONset internally by EEPROM. This T_ON

setting determines the switching frequency for the application. Derivation and calculation of the dependence of

the switching frequency on V_INand T_ONis shown in Equation 1 through Equation 6.

In a PWM buck switcher, Equation 1, Equation 2, and Equation 3 can be manipulated to obtain the switching

frequency. Equation 1 shows the standard duty-cycle equation given by the volts-seconds balance on the

inductor with Equation 2 and Equation 3 defining standard relationships:

V_OUT

V_IN

D =

(1)

(2)

T_ON= D x T_P

f_SW

T_P=

(3)

(4)

Using these equations and solving for duty-cycle for Equation 4:

D = f_SWx T_ON

Frequency can now be expressed in Equation 5:

V_OUT

V_INx T_ON

F =

(5)

Or simply written as Equation 6:

V_OUT

f_SW

where

•

α = V_INx T_ON

(6)

To maintain a set frequency in an application, α is always held constant by varying T_ONinversely with V_IN. The

three versions of the LM1771 are identified by the ON-times at a V_INof 3.3 V for consistency. For clarification,

see Table 1.

Table 1. Timing for All Variants

Product ID

LM1771S

LM1771T

LM1771U

T_ONat 3.3 V

0.5 µs

α (V µs)

1.65

3.3

1.0 µs

2.0 µs

6.6

The variation of T_ONversus V_INcan also be expressed graphically. These graphs can be found in the Typical

Characteristics of the data sheet.

With α being a constant regardless of the version of the LM1771 used, Equation 6 shows that the only

dependent variable remaining is V_OUT. Because V_OUTis a constant in any application, the frequency also remains

constant. The switching frequency at which the application runs depends upon the V_OUTdesired and the LM1771

version chosen. For any V_OUT, three frequency options (LM1771 versions) can be selected. This can be seen

Table 2. The recommended frequency range of operation is 100 kHz to 1000 kHz.

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Table 2. Frequency vs V_OUTfor Variants

(1)

TIMING OPTIONS

V_OUT

500 ns

485

1000 ns

242

2000 ns

121

0.8

606

303

152

1.2

1.5

1.8

2.5

3.3

727

364

182

909

455

227

1091

1515

2000

545

273

758

379

1000

500

(1) Switching Frequency (kHz) of LM1771 based on output voltage and

timing option.

7.3.2 Short-Circuit Protection

The LM1771 has an internal short-circuit comparator that constantly monitors the feedback node (except during

soft-start). If the feedback voltage drops below 0.55 V (equivalent to the output voltage dropping below 68% of

nominal), the comparator trips causing the part to latch off. The LM1771 does not resume switching until the

input voltage is taken below the UVLO threshold and then brought back into its normal operating range, or the

part is disabled then re-enabled through the enable pin. The purpose of this function is to prevent a severe short

circuit from causing damage to the application. Due to the fast transient response of the LM1771 a severe short

on the output causing the feedback to drop would only occur if the load applied had an effective resistance that

approaches the PMOS R_DS(ON)

7.3.3 Precision Enable

The LM1771 features a precision enable circuit. If the voltage on the EN pin is 1.2 V or greater, the part is

enabled and switching occurs. If the enable voltage falls below 1.2 V, the part is placed into a shutdown state

and the drivers is tri-stated. This allows the LM1771 to be easily sequenced using a resistive divider from the

output of another regulator, or the working input voltage range of the LM1771 to be set using a resistive divider

on V_IN. There is no internal pullup connected to the EN pin, so an external signal is required to initiate switching.

NOTE

When power is first applied to the LM1771, there is a slight delay before the enable

comparator is functional. During this delay, typically on the order of 400 µs, the part is

disabled regardless of the voltage on the EN pin. The falling enable threshold features 50

mV of hysteresis

7.3.4 Soft-Start

To limit in-rush current and allow for a controlled start-up the LM1771 incorporates an internal soft-start scheme.

Every time the enable voltage rises above 1.2 V while V_INis greater than the UVLO threshold, the LM1771 goes

through an adaptive soft-start that limits the ON-time and expands the minimum OFF-time. In addition the part

only activates the PMOS allowing a discontinuous mode of operation enabling a prebiased start-up. The time

spent in soft-start depends on the load applied to the output, but is usually close to a set time that is dependent

on the timing option. The approximate soft-start time can be seen in Table 3 for each timing option.

Table 3. Soft-Start Timing for All Variants

PRODUCT ID

LM1771S

TIMING

0.5 µs

1.0 µs

2.0 µs

T_SS

1 ms

LM1771T

1.2 ms

1.8 ms

LM1771U

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Therefore, if the input supply is extremely slow rising such that at the end of soft-start the input voltage is still

near the UVLO threshold, a timing option must be chosen to ensure that maximum duty-cycle permits the output

to meet the minimum condition. TI recommends using the 2000-ns option (LM1771U) in conditions where the

output voltage is 2.5 V or greater to avoid false latch-offs when there is concern regarding the input supply slew

rate.

NOTE

As soon as soft-start terminates the short-circuit protection is enabled. This means that if

the output voltage does not reach at least 68% of its final value the part latches off.

In some situations, the internal soft-start routine can create a slight overshoot on the output voltage. If this must

be avoided, the use of a feedforward capacitor as detailed in the Feedforward Capacitor section.

7.3.5 Jitter

The LM1771 uses an adaptive ON-time control scheme that relies on the output voltage ripple to provide a

consistent switching frequency. Under certain conditions, excessive noise can couple onto the feedback pin

causing the switch node to appear to have a slight amount of jitter. This is not indicative of an unstable design.

The output voltage still regulates to the exact same value. Careful component selection and layout must minimize

any external influence.

In addition to any external noise that can add to the jitter seen on the switch node, the LM1771 always has a

slight amount of switch jitter. This is because the LM1771 makes a small alteration in the reference voltage every

128 cycles to improve its accuracy and long-term performance. This has the effect of causing a change in the

switching frequency at that instant. When viewed on an oscilloscope this can be seen as a jitter in the switch

node. The change in feedback voltage or output voltage, however, is almost indistinguishable.

7.4 Device Functional Modes

The LM1771 has essentially one normal operational mode: in normal operation, the part operates in full

synchronous mode to regulate the FB input to 0.8 V (typical) after soft-start period is over. The EN pin allows the

user to shut down the part. When the part is enabled, the IC enters soft-start for 1 ms to 1.8 ms depending on

the variant of the IC. See Soft-Start for more detail on the soft-start pattern.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers must

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Design Guide details the design procedure to follow for the typical application. Because of the nature of constant

ON-time controller, a certain degree of iteration might be necessary on the sizing of some key components to

achieve optimal response, such as the inductor L1.

8.2 Typical Applications

8.2.1 LM1771 Typical Application

VIN

OUT

LM1771

Q₂

SNS

FB1

C_OUT

FB2

GND

Figure 19. Example Circuit Schematic

8.2.1.1 Design Requirements

The main parameters needed to successfully design an application based on the LM1171 are typical of buck

DC–DC converters. The input and output voltage must be known as well as the worst-case input voltage

operating conditions. The maximum output current helps the designer size the inductor appropriately. In addition,

the designer needs to be aware of the requirement on the output capacitor to achieve stable operation. See

Output Capacitor for details on the output capacitor requirements.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Design Guide

As with any DC–DC converter, numerous trade-offs are possible to optimize the design for efficiency, size, or

performance. These are taken into account and highlighted throughout this discussion.

Equation 7 calculates for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs

and parasitic resistances it can be approximated by:

V_OUT

V_IN

D =

(7)

A more accurate calculation for duty-cycle can be used that takes into account the voltage drops across the

FETs. Equation 8 determines the slight load dependency on switch frequency if needed. Otherwise the simplified

equation works well for component calculation.

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Typical Applications (continued)

V_OUT+ V_{DS_NMOS}

D =

V_IN+ V_{DS_NMOS}+ V_{DS_PMOS}

(8)

8.2.1.2.1.1 Frequency Selection

The LM1771 is available with three preset timing options that select the ON-time and hence determine the

switching frequency of the application. Increasing the switching frequency has the effect of reducing the inductor

size needed for the application while requiring a slight trade-off in efficiency. Table 4 shows the same frequency

table as shown earlier (Table 2) with the exception that the recommended timing option for each V_OUTis

highlighted. TI does not recommend using a high switching frequency with V_OUTequal to or greater than 2.5 V

due to the maximum duty-cycle limitations of the device coupled with the internal start-up.

Table 4. Recommended Switching Frequency vs V_OUT

(1)

TIMING OPTIONS

V_OUT

500 ns

1000 ns

242

303

364

455

545

2000 ns

0.8

485

606

727

909

1.2

1.5

1.8

2.5

3.3

2237

273

379

500

(1) Recommended switching frequency (kHz) based on output voltage

and timing option.

8.2.1.2.1.2 Inductor Selection

The inductor selection is an iterative process likely requiring several passes before settling on a final value. The

reason for this is because it influences the amount of ripple seen at the output, a critical component to ensure

general stability of an adaptive ON-time circuit. For the first pass at inductor selection the value can be obtained

by targeting a maximum peak-to-peak ripple current equal to 30% of the maximum load current. The inductor

current ripple (ΔI_L) can be calculated by Equation 9:

(V_INœ V_OUT) x D

DI_L=

L x f_SW

(9)

Therefore, L can be initially set by applying the 30% rule in Equation 10:

(V_INœ V_OUT) x D

L =

0.3 x f_SWx I_OUT

(10)

The other features of the inductor that can be selected besides inductance value are saturation current and core

material. Because the LM1771 does not have a current limit, TI recommends having a saturation current higher

than the maximum output current to handle any ripple or momentary overcurrent events. The core material also

influences the saturation characteristics as ferrite materials have a hard saturation curve and take care that they

never saturate during normal use. A shielded inductor or low-profile unshielded inductor is recommended to

reduce EMI. This also helps prevent any spurious noise from picking up on the feedback node resulting in

unexpected tripping of the feedback comparator.

8.2.1.2.1.3 Output Capacitor

One of the most important components to select with the LM1771 is the output capacitor. This is because its size

and ESR have a direct effect on the stability of the loop. A constant ON-time control scheme works by sensing

the output voltage ripple and switching the FETs appropriately. The output voltage ripple on a buck converter can

be approximated by stating that the AC inductor ripple flows entirely into the output capacitor and is created by

the ESR of the capacitor. This can be expressed in Equation 11:

ΔV_OUT= ΔI_Lx R_ESR

(11)

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To ensure stability, two constraints need to be met. The first is that there is sufficient ESR to create enough

voltage ripple at the feedback pin. TI recommends having at least 10 mV of ripple seen at the feedback pin. This

can be calculated by multiplying the output voltage ripple by the gain seen through the feedback resistors. This

gain, H, can be calculated in Equation 12:

V_FB

0.8V

H =

V_OUT

(12)

If the output voltage is fairly high, causing significant attenuation through the feedback resistors, a feedforward

capacitor can be used. This is actually recommended for most circuits as it improves performance. See the

Feedforward Capacitor section for more details.

The second criteria is to ensure that there is sufficient ripple at the output that is in-phase with the switch. The

problem exists that there is actually ripple caused by the capacitor charging and discharging, not only the ESR

ripple. Because these are effectively out of phase, problems can exist. To avoid this issue, TI recommends that

the ratio of the two ripples (β) is always greater than 5. To calculate the minimum ESR value needed,

Equation 13 can be used:

DI_L

≈

I_{CIN_RMS}= I_OUT

1 - D +

∆

12 x I_OUT

(13)

In general, the best capacitors to use are chemistries that have a known and consistent ESR across the entire

operating temperature range. Tantalum capacitors or similar chemistries such as Niobium Oxide perform well

along with certain families of Aluminum Electrolytics. Small value POSCAPs and SP CAPs also work as they

have sufficient ESR. When used in conjunction with a low-value inductor it is possible to have an extremely

stable design. The only capacitors that require modification to the circuit are ceramic capacitors. Ceramic

capacitors cause problems meeting both criteria because they have low ESR and low capacitance. Therefore, if

they are to be used, an external ESR resistor (R_SNS) must be added. This can be seen in Figure 20.

VIN

SNS

OUT

LM1771

OUT

FB1

FB2

GND

Figure 20. LM1771 With an External ESR Resistor (R_SNS

)

This circuit uses an additional resistor in series with the inductor to add ripple at the output. It is placed in this

location and used in combination with the feedforward capacitor (C_FF) to provide ripple to the feedback pin,

without adding ripple or a DC offset to the output. The benefit of using a ceramic capacitor is still obtained with

this technique. Because the addition of the resistor results in power loss, this circuit implementation is only

recommended for low currents (2 A and below). The power loss and rating of the resistor must be taken into

account when selecting this component.

This circuit implementation using the feedforward capacitor begins to experience limitations when the output

voltage is small. Previously the circuit relied on the C_FFfor all the ripple at the feedback node by assuming that

the resistor divider was negligible. As V_OUTdecreases this can not be assumed. The resistor divider contributes a

larger amount of ripple which is problematic as it is also out of phase. Therefore the resistor location must be

changed to be in series with the output capacitor. This can be viewed as adding an effective ESR to the output

capacitor. This can be seen in Figure 21.

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VIN

OUT

LM1771

Q₂

SNS

FB1

C_OUT

FB2

GND

Figure 21. LM1771 With ESR Resistor (R_SNS) in Series With Output Capacitor

8.2.1.2.1.4 Feedforward Capacitor

The feedforward capacitor is used across the top feedback resistor to provide a lower impedance path for the

high-frequency ripple without degrading the DC accuracy. Typically the value for this capacitor must be small

enough to prevent load transient errors because of the discharging time, but large enough to prevent attenuation

of the ripple voltage. In general a small ceramic capacitor in the range of 1 nF to 10 nF is sufficient.

If C_FFis used then it can be assumed that the ripple voltage seen at the feedback pin is the same as the ripple

voltage at the output. The attenuation factor H no longer needs to be used. However, in these conditions, TI

recommends having a minimum of 20-mV ripple at the feedback pin. The use of a C_FFcapacitor is recommended

as it improves the regulation and stability of the design. However, its benefit is diminished as V_OUTstarts

approaching V_REF, therefore it is not needed in this situation.

8.2.1.2.1.5 Input Capacitor

The dominating factor that usually sets the size of an input capacitor is the current handling ability. This is usually

determined by the package size and ESR of the capacitor. If these two criteria are met then there usually must

be enough capacitance to prevent impedance interactions with the source. In general, TI recommends using a

ceramic capacitor for the input as they provide a low impedance and small footprint.

NOTE

Use a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better

over temperature performance and also minimize the DC voltage derating that occurs on

Y5V capacitors.

To calculate the input capacitor RMS current, Equation 14 can be used:

DI_L

≈

I_{CIN_RMS}= I_OUT

1 - D +

∆

12 x I_OUT

(14)

(15)

which can be approximated by, Equation 15

I_{CIN_RMS}= I_OUT

D(1 - D)

8.2.1.2.2 MOSFET Selection

The two FETs used in the LM1771 requires attention to selection of parameters to ensure optimal performance of

the power supply. The high-side FET must be a PFET and the low-side an NFET. These can be integrated in

one package or as two separate packages.

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8.2.1.2.2.1 VDS Voltage Rating

The first selection criteria is to select FETs that have sufficient V_DSvoltage ratings to handle the maximum

voltage seen at the input plus any transient spikes that can occur from parasitic ringing. In general most FETs

available for this application have ratings from 8 V to 20 V. If a larger voltage rating is used then the performance

is most likely be degraded because of higher gate capacitance.

8.2.1.2.2.2 RDSON

The R_DS(ON)specification is important as it determines several attributes of the FET and the overall power supply.

The first is that it sets the maximum current of the FET for a given package. A lower R_DS(ON)permits a higher

allowable current and reduce conduction losses, however, it increases the gate capacitance and the switching

losses.

8.2.1.2.2.3 Gate Drive

The next step is to ensure that the FETs are capable of switching at the low V_insupplies used by the LM1771.

The FET must have the Rdson specified at either 1.8 V or 2.5 V to ensure that it can switch effectively as soon

as the LM1771 starts up.

8.2.1.2.2.4 Gate Charge

Because the LM1771 uses a fixed dead-time scheme to prevent cross conduction, the FET transitions must

occur in this time. The rise and fall time of the FETs gate can be influenced by several factors including the gate

capacitance. Therefore the total gate charge of both FETs must be limited to less than 20 nC at 4.5 V V_GS. The

lower the number the faster the FETs must switch and the better the efficiency.

8.2.1.2.2.5 Rise and Fall Times

A better indication of the actual switching times of the FETs can be found in their Electrical Characteristics table.

The rise and fall time must be specified and selected to be at a minimum. This helps improve efficiency and

ensuring that shoot-through does not occur.

8.2.1.2.2.6 Gate Charge Ratio

Another consideration in selecting the FETs is to pay attention to the Qgd / Qgs ratio. The reason for this is that

proper selection can prevent spurious turnon. If we look at the NFET for example, when the FET is turning off,

the gate signal pulls to ground. Conversely the PFET is turning on, causing the SW node to rise towards V_IN. The

gate-to-drain capacitance of the NFET couples the SW node to the gate and causes it to rise. If this voltage is

excessive, then it could weakly turn on the low-side FET causing an efficiency loss. However, this coupling is

mitigated by having a large gate to source capacitance of the FET, which helps to hold the gate voltage down.

Ideally, a very low Qgd / Qgs would be ideal, but in practice it is common to find the number around 1. As a

general rule, the lower the ratio, the better.

If the above selection criteria have been met it is useful to generate a figure of merit to allow comparison

between the FETs. One such method is to multiply the R_DS(ON)of the FET by the total gate charge. This allows

an easy comparison of the different FETs available. Once again, the lower the product, the better.

8.2.1.2.2.7 Feedback Resistors

The feedback resistors are used to scale the output voltage to the internal reference value such that the loop can

be regulated. The feedback resistors must not be made arbitrarily large as this creates a high impedance node at

the feedback pin that is more susceptible to noise. A combined value of 50 kΩ for the two resistors is adequate.

To calculate the resistor values use Equation 16. Typically, the low-side resistor is initially set to a predetermined

value such as 10 kΩ.

≈

∆

^OUT- 1

V_FB

R_FB1= R_FB2

where

•

V_FBis the internal reference voltage that can be found in the Electrical Characteristics table or approximated

by 0.8 V (16)

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The output voltage value can be set in a precise manner by taking into account the fact that the reference

voltage is regulating the bottom of the output ripple as opposed to the average value. This relationship is shown

in Figure 22.

OUT

OUT_ACTUAL

OUT

OUT_SET

Figure 22. Output Voltage Waveform

The average output voltage (V_{OUT_ACTUAL}) is higher than the output voltage (V_{OUT_SET}) that was calculated by the

earlier equation by exactly half the output voltage ripple. The output voltage that is targeted for regulation may

then be appended according to the voltage ripple. This can be seen in Equation 17:

V_{OUT_ACTUAL}= V_{OUT_SET}+ ½ΔV_OUT= V_{OUT_SET}+ ½ΔI_Lx R_ESR

(17)

8.2.1.2.3 Efficiency Calculations

One of the most important parameters to calculate during the design stage is the expected efficiency of the

system. This can help determine optimal FET selection and can be used to calculate expected temperature rise

of the individual components.

8.2.1.2.3.1 Quiescent Current

The quiescent current consumed by the LM1771 is one of the major sources of loss within the controller.

However, from a system standpoint this is usually less than 0.5% of the overall efficiency. Therefore, it could

easily be omitted but is shown for completeness:

P_IQ= V_INx I_Q

(18)

8.2.1.2.3.2 Conduction Loss

There are three losses associated with the external FETs. From the DC standpoint there is the I-squared R loss,

caused by the ON-resistance of the FET. This can be modeled for the PMOS by:

P_{P_COND}= D x R_{DSON_PMOS}x I_OUT

(19)

(20)

and the NMOS by:

P_{N_COND}= (1 - D) x R_{DSON_NMOS}x I_OUT

8.2.1.2.3.3 Switching Loss

The next loss is the switching loss that is caused by the need to charge and discharge the gate capacitance of

the FETs every cycle. This can be approximated by:

P_{P_SWITCH}= V_INx Q_{g_PMOS}x f_SW

(21)

for the PMOS, and the same approach can be adapted for the NMOS:

P_{N_SWITCH}= V_INx Q_{g_NMOS}x f_SW

(22)

8.2.1.2.3.4 Transitional Loss

The last FET power loss is the transitional loss. This is caused by switching the PMOS while it is conducting

current. This approach only models the PMOS transition, the NMOS loss is considered negligible because it has

minimal drain to source voltage when it switches due to the conduction of the body diode. Therefore the

transitional loss of the PMOS can be modeled by:

P_{P_TRANSITIONAL}= 0.5 x V_INx I_OUTx f_SWx (t_r+ t_f)

(23)

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t_rand t_fare the rise and fall times of the FET and can be found in their corresponding datasheet. Typically these

numbers are simulated using a 6-Ω drive, which corresponds well to the LM1771. Given this, no adjustment is

needed.

8.2.1.2.3.5 DCR Loss

The last source of power loss in the system that needs to be calculated is the loss associated with the inductor

resistance (DCR) which can be calculated by Equation 24:

P_DCR= R_DCRx I_OUT

(24)

(25)

8.2.1.2.3.6 Efficiency

The efficiency, η, can then be calculated by summing all the power losses and then using Equation 25:

P_OUT

h =

P_OUT+ P_LOSSES

8.2.1.3 Application Curve

Figure 23. Typical Efficiency 5 V_INto 2.5 V_OUT

8.2.2 Example Application 5 V_INto 1.8 V_OUT

Figure 24 and Table 5 show an application with conversion from 5-V input to 1.8-V output with a switching

frequency of 1.1 MHz and a 2-A maximum output current.

VIN

OUT

LM1771

Q₂

SNS

FB1

C_OUT

FB2

GND

Figure 24. Example Circuit Schematic, 5 V_INto 1.8 V_OUT

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Table 5. Bill of Materials (5-V to 1.8-V Conversion, f_SW= 1090 kHz, I_OUT= 2 A)

DESIGNATOR

DESCRIPTION

LM1771, 500 ns

PART NUMBER

QUANTITY

VENDOR

U₁

Q₁

LM1771S

Si3867DV

Si3460DV

Texas Instruments

Siliconix

Murata

PMOS

Q₂

NMOS

C_IN

C_OUT

R_FB1

R_FB2

C_FF

22-μF Capacitor, 0805

100-μF Capacitor, 6.3 V, 100 mΩ

12.4-kΩ Resistor, 0603

10-kΩ Resistor, 0603

1-nF Capacitor, 0603

3.3-μH Inductor

GRM21BR60J226ME39

TPSY107M006R0100

CRCW06031242F

CRCW06031002F

VJ0603102KXXA

AVX

Vishay

MSS7341-332NLB

Coilcraft

8.2.3 Example Application 5 V_INto 3.3 V_OUT

Figure 25 and Table 6 show an application with conversion from 5-V input to 3.3-V output with a switching

frequency of 500 kHz and a 5-A maximum output current.

VIN

OUT

LM1771

Q₂

SNS

FB1

C_OUT

FB2

GND

Figure 25. Example Circuit Schematic, 5 V_INto 3.3 V_OUT

Table 6. Bill of Materials (5-V to 3.3-V Conversion, f_SW= 500 kHz, I_OUT= 5 A)

DESIGNATOR

DESCRIPTION

LM1771, 200 ns

PART NUMBER

QUANTITY

VENDOR

Texas Instruments

Siliconix

U₁

Q₁

LM1771U

Si9433BDY

Si4894DY

PMOS

Q₂

NMOS

Siliconix

C_IN

C_OUT

R_FB1

R_FB2

C_FF

100-μF Capacitor, 1812

150-μF Capacitor, 6.3 V, 70 mΩ

29.4-kΩ Resistor, 0805

10-kΩ Resistor, 0805

1-nF Capacitor, 0805

2.2-μH Inductor

GRM43SR60J107ME20B

NOSD157M006R0070

CRCW08052942F

CRCW08051002F

VJ0805102KXXA

Murata

AVX

Vishay

DO3316P-222

Coilcraft

9 Power Supply Recommendations

The power line feeding the LM1771 must have low impedance. The input capacitor of the system must be placed

as close to VIN as possible. If the power supply is very noisy, an additional bulk capacitor might be necessary in

the system to ensure that clean power is delivered to the IC.

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10 Layout

10.1 Layout Guidelines

The LM1771, like all switching regulators, requires careful attention to layout to ensure optimal performance. The

following steps must be taken to aid in the layout. For more information refer to Application Note AN-1299

(SNVA074).

1. Ensure that the ground connections of the input capacitor, output capacitor and NMOS are as close as

possible. Ideally these must all be grounded together in close proximity on the component side of the board.

2. Keep the switch node small to minimize EMI without degrading thermal cooling of the FETs.

3. Locate the feedback resistors close to the IC and keep the feedback trace as short as possible. Do not run

any feedback traces near the switch node.

4. Keep the gate traces short and keep them away from the switch node as much as possible.

5. If a small bypass capacitor is used on V_IN(0.1 µF) place it as close to the pin, with the ground connection as

close to the chip ground, as possible.

10.2 Layout Examples

CIN and COUT GND are close together

Keep path of FET’s gate short

Limit surface of switch node

to reduce capacitance

Figure 26. LM1771 Layout Example (Top)

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Layout Examples (continued)

Figure 27. LM1771 Layout Example (Bottom)

10.3 Thermal Considerations

By breaking down the individual power loss in each component it makes it easy to determine the temperature

rise of each component. Generally the expected temperature rise of the LM1771 is extremely low as it is not in

the power path. Therefore the only two items of concern are the PMOS and the NMOS. The power loss in the

PMOS is the sum of the conduction loss and transitional loss, while the NMOS only has conduction loss. It is

assumed that any loss associated with the body diode conduction during the dead-time is negligible.

For completeness of design it is important to watch out for the temperature rise of the inductor. Assuming the

inductor is kept out of saturation the predominant loss is the DC copper resistance. At higher frequencies,

depending on the core material, the core loss could approach or exceed the DCR losses. Consult with the

inductor manufacturer for appropriate temp curves based on current.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

User's Guide, AN-1299 LM5041 Evaluation Board, SNVA074

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM1771SMM/NOPB

LM1771SSD/NOPB

LM1771TMM/NOPB

LM1771UMM/NOPB

LM1771USD/NOPB

ACTIVE

VSSOP

WSON

VSSOP

WSON

DGK

NGG

DGK

NGG

1000 RoHS & Green

Level-1-260C-UNLIM

SNRB

-40 to 125

1771S

SNSB

SNTB

1771U

-40 to 125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM1771SMM/NOPB

LM1771SSD/NOPB

LM1771TMM/NOPB

LM1771UMM/NOPB

LM1771USD/NOPB

VSSOP

WSON

VSSOP

WSON

DGK

NGG

DGK

NGG

1000

178.0

12.4

5.3

3.3

5.3

3.3

3.4

3.3

3.4

3.3

1.4

1.0

1.4

1.0

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM1771SMM/NOPB

LM1771SSD/NOPB

LM1771TMM/NOPB

LM1771UMM/NOPB

LM1771USD/NOPB

VSSOP

WSON

VSSOP

WSON

DGK

NGG

DGK

NGG

1000

210.0

185.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

NGG0006A

SDE06A (Rev A)

www.ti.com

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LM1771UMM/NOPB [TI]

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