LM1882-RP [TI]

SPECIALTY CONSUMER CIRCUIT, PDIP20, PLASTIC, DIP-20;


型号：	LM1882-RP
厂家：	TEXAS INSTRUMENTS
描述：	SPECIALTY CONSUMER CIRCUIT, PDIP20, PLASTIC, DIP-20 光电二极管商用集成电路
文件：	总19页 (文件大小：383K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

December 1998

LM1882•54ACT715

LM1882-R•54ACT715-R Programmable Video Sync

Generator

LM1882-R is mask programmed to default to a Clock En-

abled state. Bit 10 of the Status Register defaults to a logic

General Description

The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin

“1”. Although completely (re)programmable, the ’ACT715-R/

TTL-input compatible devices capable of generating Hori-

LM1882-R version is better suited for applications using the

zontal, Vertical and Composite Sync and Blank signals for

default 14.31818 MHz RS-170 register values. This feature

televisions and monitors. All pulse widths are completely de-

allows power-up directly into operation, following a single

finable by the user. The devices are capable of generating

CLEAR pulse.

signals for both interlaced and noninterlaced modes of op-

eration. Equalization and serration pulses can be introduced

into the Composite Sync signal when needed.

Features

n Maximum Input Clock Frequency 130 MHz

Four additional signals can also be made available when

Composite Sync or Blank are used. These signals can be

used to generate horizontal or vertical gating pulses, cursor

position or vertical Interrupt signal.

n Interlaced and non-interlaced formats available

n Separate or composite horizontal and vertical Sync and

Blank signals available

n Complete control of pulse width via register

programming

n All inputs are TTL compatible

These devices make no assumptions concerning the system

architecture. Line rate and field/frame rate are all a function

of the values programmed into the data registers, the status

n 8 mA drive on all outputs

n Default RS170/NTSC values mask programmed into

registers

n 4 KV minimum ESD immunity

n ’ACT715-R/LM1882-R is mask programmed to default to

a Clock Enable state for easier start-up into

14.31818 MHz RS170 timing

The ’ACT715/LM1882 is mask programmed to default to a

Clock Disable state. Bit 10 of the Status Register, Register 0,

defaults to a logic “0”. This facilitates (re)programming be-

fore operation.

The ’ACT715-R/LM1882-R is the same as the ’ACT715/

LM1882 in all respects except that the ’ACT715-R/

Connection Diagrams

Pin Assignment for

DIP and SOIC

Pin Assignment

for LCC

DS100232-1

DS100232-2

Order Number LM1882CN or LM1882CM

For Default RS-170, Order Number

LM1882-RCN or LM1882-RCM

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

FACT is a trademark of Fairchild Semiconductor Corporation.

DS100232

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Logic Block Diagram

DS100232-3

Pin Description

There are a Total of 13 inputs and 5 outputs on the ’ACT715/

ODD/EVEN: Output that identifies if display is in odd (HIGH)

or even (LOW) field of interlace when device is in interlaced

mode of operation. In noninterlaced mode of operation this

output is always HIGH. Data can be serially scanned out on

this pin during Scan Mode.

LM1882.

Data Inputs D0–D7: The Data Input pins connect to the Ad-

dress Register and the Data Input Register.

ADDR/DATA: The ADDR/DATA signal is latched into the de-

vice on the falling edge of the LOAD signal. The signal deter-

mines if an address (0) or data (1) is present on the data bus.

VCSYNC: Outputs Vertical or Composite Sync signal based

on value of the Status Register. Equalization and Serration

pulses will (if enabled) be output on the VCSYNC signal in

composite mode only.

L/HBYTE: The L/HBYTE signal is latched into the device on

the falling edge of the LOAD signal. The signal determines if

data will be read into the 8 LSB’s (0) or the 4 MSB’s (1) of the

Data Registers. A 1 on this pin when an ADDR/DATA is a 0

enables Auto-Load Mode.

VCBLANK: Outputs Vertical or Composite Blanking signal

based on value of the Status Register.

HBLHDR: Outputs Horizontal Blanking signal, Horizontal

Gating signal or Cursor Position based on value of the Sta-

tus Register.

LOAD: The LOAD control pin loads data into the Address or

Data Registers on the rising edge. ADDR/DATA and

L/HBYTE data is loaded into the device on the falling edge of

the LOAD. The LOAD pin has been implemented as a

Schmitt trigger input for better noise immunity.

HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating

signal or Vertical Interrupt signal based on value of Status

CLOCK: System CLOCK input from which all timing is de-

rived. The clock pin has been implemented as a Schmitt trig-

ger for better noise immunity. The CLOCK and the LOAD

signal are asynchronous and independent. Output state

changes occur on the falling edge of CLOCK.

All of the data registers are 12 bits wide. Width’s of all pulses

are defined by specifying the start count and end count of all

pulses. Horizontal pulses are specified with-respect-to the

number of clock pulses per line and vertical pulses are speci-

fied with-respect-to the number of lines per frame.

CLR: The CLEAR pin is an asynchronous input that initial-

izes the device when it is HIGH. Initialization consists of set-

ting all registers to their mask programmed values, and ini-

tializing all counters, comparators and registers. The CLEAR

pin has been implemented as a Schmitt trigger for better

noise immunity. A CLEAR pulse should be asserted by the

user immediately after power-up to ensure proper initializa-

tion of the registers — even if the user plans to (re)program

the device.

REG0 — STATUS REGISTER

The Status Register controls the mode of operation, the sig-

nals that are output and the polarity of these outputs. The de-

fault value for the Status Register is 0 (000 Hex) for the

’ACT715/LM1882 and is “1024” (400 Hex) for the

’ACT715-R/LM1882-R.

Note: A CLEAR pulse will disable the CLOCK on the ’ACT715/LM1882 and

will enable the CLOCK on the ’ACT715-R/LM1882-R.

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HORIZONTAL INTERVAL REGISTERS

The Horizontal Interval Registers determine the number of

clock cycles per line and the characteristics of the Horizontal

Sync and Blank pulses.

Bits 0–2

B₂

B₁

B₀VCBLANK VCSYNC HBLHDR HSYNVDR

REG1 — Horizontal Front Porch

CBLANK

CSYNC

HGATE

VGATE

REG2 — Horizontal Sync Pulse End Time

REG3 — Horizontal Blanking Width

(DEFAULT)

VBLANK

CBLANK

VBLANK

CBLANK

VBLANK

CBLANK

VBLANK

CSYNC

VSYNC

HBLANK

HGATE

VGATE

HSYNC

VINT

REG4 — Horizontal Interval Width

Line

of Clocks per

HBLANK

CSYNC CURSOR

CSYNC HBLANK

VSYNC CURSOR

VSYNC HBLANK

VERTICAL INTERVAL REGISTERS

VINT

The Vertical Interval Registers determine the number of lines

per frame, and the characteristics of the Vertical Blank and

Sync Pulses.

HSYNC

REG5 — Vertical Front Porch

REG6 — Vertical Sync Pulse End Time

REG7 — Vertical Blanking Width

Bits 3–4

B₄

B₃

Mode of Operation

Interlaced Double Serration and

REG8 — Vertical Interval Width

# of Lines per Frame

EQUALIZATION AND SERRATION PULSE

SPECIFICATION REGISTERS

(DEFAULT) Equalization

Non Interlaced Double Serration

Illegal State

These registers determine the width of equalization and ser-

ration pulses and the vertical interval over which they occur.

Non Interlaced Single Serration and

Equalization

REG 9 — Equalization Pulse Width End Time

REG10 — Serration Pulse Width End Time

REG11 — Equalization/Serration Pulse Vertical

Interval Start Time

Double Equalization and Serration mode will output equal-

ization and serration pulses at twice the HSYNC frequency

(i.e., 2 equalization or serration pulses for every HSYNC

pulse). Single Equalization and Serration mode will output

an equalization or serration pulse for every HSYNC pulse. In

Interlaced mode equalization and serration pulses will be

output during the VBLANK period of every odd and even

field. Interlaced Single Equalization and Serration mode is

not possible with this part.

REG12 — Equalization/Serration Pulse Vertical

Interval End Time

VERTICAL INTERRUPT SPECIFICATION REGISTERS

These Registers determine the width of the Vertical Interrupt

signal if used.

REG13 — Vertical Interrupt Activate Time

REG14 — Vertical Interrupt Deactivate Time

Bits 5–8

Bits 5 through 8 control the polarity of the outputs. A value of

zero in these bit locations indicates an output pulse active

LOW. A value of 1 indicates an active HIGH pulse.

CURSOR LOCATION REGISTERS

These 4 registers determine the cursor position location, or

they generate separate Horizontal and Vertical Gating sig-

nals.

B5 — VCBLANK Polarity

B6 — VCSYNC Polarity

B7 — HBLHDR Polarity

B8 — HSYNVDR Polarity

REG15 — Horizontal Cursor Position Start Time

REG16 — Horizontal Cursor Position End Time

REG17 — Vertical Cursor Position Start Time

REG18 — Vertical Cursor Position End Time

Bits 9–11

Bits 9 through 11 enable several different features of the de-

vice.

Signal Specification

B9 —

Enable Equalization/Serration Pulses (0)

Disable Equalization/Serration Pulses (1)

HORIZONTAL SYNC AND BLANK

SPECIFICATIONS

B10 — Disable System Clock (0)

Enable System Clock (1)

All horizontal signals are defined by a start and end time.

The start and end times are specified in number of clock

cycles per line. The start of the horizontal line is considered

pulse 1 not 0. All values of the horizontal timing registers are

referenced to the falling edge of the Horizontal Blank signal

(see Figure 1). Since the first CLOCK edge, CLOCK #1,

causes the first falling edge of the Horizontal Blank reference

pulse, edges referenced to this first Horizontal edge are n +

1 CLOCKs away, where “n” is the width of the timing in ques-

tion. Registers 1, 2, and 3 are programmed in this manner.

The horizontal counters start at 1 and count until HMAX. The

value of HMAX must be divisible by 2. This limitation is im-

Default values for B10 are “0” in the ’ACT715/

LM1882 and “1” in the ’ACT715-R/LM1882-R.

B11 — Disable Counter Test Mode (0)

Enable Counter Test Mode (1)

This bit is not intended for the user but is for internal

testing only.

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ization pulses at 2 x the horizontal frequency. Horizontal

signals will change on the falling edge of the CLOCK signal.

Signal specifications are shown below.

Signal Specification (Continued)

posed because during interlace operation this value is inter-

nally divided by 2 in order to generate serration and equal-

DS100232-4

FIGURE 1. Horizontal Waveform Specification

Vertical Syncing Width [REG(6) − REG(5)] x hper/n

Horizontal Period (HPER)

Horizontal Blanking Width:

REG(4) x ckper

Vertical Front Porch [REG(5) − 1] x hper/n

[REG(3) − 1] x ckper

[REG(2) − REG(1)] x ckper

[REG(1) − 1] x ckper

Horizontal Sync Width:

Horizontal Front Porch:

where

1 for noninterlaced

2 for interlaced

VERTICAL SYNC AND BLANK SPECIFICATION

COMPOSITE SYNC AND BLANK SPECIFICATION

All vertical signals are defined in terms of number of lines per

frame. This is true in both interlaced and noninterlaced

modes of operation. Care must be taken to not specify the

Vertical Registers in terms of lines per field. Since the first

CLOCK edge, CLOCK #1, causes the first falling edge of the

Vertical Blank (first Horizontal Blank) reference pulse, edges

referenced to this first edge are n + 1 lines away, where “n”

is the width of the timing in question. Registers 5, 6, and 7

are programmed in this manner. Also, in the interlaced

mode, vertical timing is based on half-lines. Therefore regis-

ters 5, 6, and 7 must contain a value twice the total horizontal

Composite Sync and Blank signals are created by logically

ANDing (ORing) the active LOW (HIGH) signals of the corre-

sponding vertical and horizontal components of these sig-

nals. The Composite Sync signal may also include serration

and/or equalization pulses. The Serration pulse interval oc-

curs in place of the Vertical Sync interval. Equalization

pulses occur preceding and/or following the Serration

pulses. The width and location of these pulses can be pro-

grammed through the registers shown below. (See Figure 3.)

Horizontal Equalization PW

[REG(9) − REG(1)] x ckper

REG 9 (HFP) + (HEQP) + 1

(odd and even) plus

(as described above). In

Horizontal Serration PW:

[REG(4)/n

REG(1)

−

non-interlaced mode, all vertical timing is based on

whole-lines. Register 8 is always based on whole-lines and

does not add 1 for the first clock. The vertical counter starts

at the value of 1 and counts until the value of VMAX. No re-

strictions exist on the values placed in the vertical registers.

Vertical Blank will change on the leading edge of HBLANK.

Vertical Sync will change on the leading edge of HSYNC.

(See Figure 2.)

REG(10)] x ckper

REG 10

(HFP)

(HPER/2) − (HSERR) + 1

Where

for noninterlaced single serration/

for noninterlaced double serration/

equalization

Vertical Frame Period (VPER) REG(8) x hper

2 for interlaced operation

Vertical Field Period (VPER/n) REG(8) x hper/n

Vertical Blanking Width [REG(7) − 1] x hper/n

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Signal Specification (Continued)

DS100232-5

FIGURE 2. Vertical Waveform Specification

DS100232-12

FIGURE 3. Equalization/Serration Interval Programming

HORIZONTAL AND VERTICAL GATING SIGNALS

Addressing Logic

Horizontal Drive and Vertical Drive outputs can be utilized as

general purpose Gating Signals. Horizontal and Vertical Gat-

ing Signals are available for use when Composite Sync and

Blank signals are selected and the value of Bit 2 of the Sta-

tus Register is 0. The Vertical Gating signal will change in the

same manner as that specified for the Vertical Blank.

The register addressing logic is composed of two blocks of

logic. The first is the address register and counter (AD-

DRCNTR), and the second is the address decode (AD-

DRDEC).

ADDRCNTR LOGIC

Horizontal Gating Signal Width

[REG(16) − REG(15)] x

ckper

Addresses for the data registers can be generated by one of

two methods. Manual addressing requires that each byte of

each register that needs to be loaded needs to be ad-

dressed. To load both bytes of all 19 registers would require

a total of 57 load cycles (19 address and 38 data cycles).

Auto Addressing requires that only the initial register value

be specified. The Auto Load sequence would require only 39

load cycles to completely program all registers (1 address

and 38 data cycles). In the auto load sequence the low order

byte of the data register will be written first followed by the

high order byte on the next load cycle. At the time the High

Byte is written the address counter is incremented by 1. The

counter has been implemented to loop on the initial value

loaded into the address register. For example: If a value of 0

was written into the address register then the counter would

count from 0 to 18 before resetting back to 0. If a value of 15

was written into the address register then the counter would

count from 15 to 18 before looping back to 15. If a value

greater than or equal to 18 is placed into the address register

the counter will continuously loop on this value. Auto ad-

dressing is initiated on the falling edge of LOAD when AD-

DRDATA is 0 and LHBYTE is 1. Incrementing and loading of

data registers will not commence until the falling edge of

LOAD after ADDRDATA goes to 1. The next rising edge of

Vertical Gating Signal Width:

[REG(18) − REG(17)] x

hper

CURSOR POSITION AND VERTICAL INTERRUPT

The Cursor Position and Vertical Interrupt signal are avail-

able when Composite Sync and Blank signals are selected

and Bit 2 of the Status Register is set to the value of 1. The

Cursor Position generates a single pulse of n clocks wide

during every line that the cursor is specified. The signals are

generated by logically ORing (ANDing) the active LOW

(HIGH) signals specified by the registers used for generating

Horizontal and Vertical Gating signals. The Vertical Interrupt

signal generates a pulse during the vertical interval speci-

fied. The Vertical Interrupt signal will change in the same

manner as that specified for the Vertical Blanking signal.

Horizontal Cursor Width [REG(16) − REG(15)] x ckper

Vertical Cursor Width [REG(18) − REG(17)] x hper

Vertical Interrupt Width [REG(14) − REG(13)] x hper

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Addressing Logic (Continued)

LOAD will load the first byte of data. Auto Incrementing is

disabled on the falling edge of LOAD after ADDRDATA and

LHBYTE goes low.

Manual Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

Load Address m

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Load Lbyte m

Load Hbyte m

Load Address n

Load Lbyte n

Load Hbyte n

DS100232-7

Auto Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

Enable Auto Addressing

Load Start Address n

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Load Lbyte (n)

Load Hbyte (n); Inc Counter

Load Lbyte (n+1)

Load Hbyte (n+1); Inc Counter

Load Address

DS100232-8

ADDRDEC LOGIC

CLOCK is disabled. Clocking the part during a Vectored Re-

start or Vectored Clear state will have no effect on the part.

To resume operation in the new state, or disable the Vec-

tored Restart or Vectored Clear state, another

non-ADDRDEC address must be loaded. Operation will be-

gin in the new state on the rising edge of the non-ADDRDEC

load pulse. It is recommended that an unused address be

loaded following an ADDRDEC operation to prevent data

registers from accidentally being corrupted. The following

Addresses are used by the device.

The ADDRDEC logic decodes the current address and gen-

erates the enable signal for the appropriate register. The en-

able values for the registers and counters change on the fall-

ing edge of LOAD. Two types of ADDRDEC logic is enabled

by 2 pair of addresses, Addresses 22 or 54 (Vectored Re-

start logic) and Addresses 23 or 55 (Vectored Clear logic).

Loading these addresses will enable the appropriate logic

and put the part into either a Restart (all counter registers are

reinitialized with preprogrammed data) or Clear (all registers

are cleared to zero) state. Reloading the same ADDRDEC

address will not cause any change in the state of the part.

The outputs during these states are frozen and the internal

Address 0

Status Register REG0

Address 1–18Data Registers REG1–REG18

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is possible without interruption or data and performance cor-

ruption. If the defaulted 14.31818 MHz RS-170 values are

being used, preconditioning and restarting can be minimized

by using the CLEAR pulse instead of the Vectored Restart

operation. The ’ACT715-R/LM1882-R is better suited for this

application because it eliminates the need to program a 1

into Bit 10 of the Status Register to enable the CLOCK. Gen

Locking to another count location other than the very begin-

ning or separate horizontal/vertical resetting is not possible

with the ’ACT715/LM1882 nor the ’ACT715-R/LM1882-R.

Addressing Logic (Continued)

Address 19–21Unused

Address 22/54Restart Vector (Restarts Device)

Address 23/55Clear Vector (Zeros All Registers)

Address 24–31Unused

Address 32–50Register Scan Addresses

Address 51–53Counter Scan Addresses

Address 56–63Unused

At any given time only one register at most is selected. It is

possible to have no registers selected.

SCAN MODE LOGIC

A scan mode is available in the ACT715/LM1882 that allows

the user to non-destructively verify the contents of the regis-

ters. Scan mode is invoked through reading a scan address

into the address register. The scan address of a given regis-

ter is defined by the Data register address + 32. The internal

Clocking signal is disabled when a scan address is read.

Disabling the clock freezes the device in it’s present state.

Data can then be serially scanned out of the data registers

through the ODD/EVEN Pin. The LSB will be scanned out

first. Since each register is 12 bits wide, completely scanning

out data of the addressed register will require 12 CLOCK

pulses. More than 12 CLOCK pulses on the same register

will only cause the MSB to repeat on the output.

Re-scanning the same register will require that register to be

reloaded. The value of the two horizontal counters and 1 ver-

tical counter can also be scanned out by using address num-

bers 51–53. Note that before the part will scan out the data,

the LOAD signal must be brought back HIGH.

VECTORED RESTART ADDRESS

The function of addresses 22 (16H) or 54 (36H) are similar to

that of the CLR pin except that the preprogramming of the

registers is not affected. It is recommended but not required

that this address is read after the initial device configuration

load sequence. A 1 on the ADDRDATA pin (Auto Addressing

Mode) will not cause this address to automatically incre-

ment. The address will loop back onto itself regardless of the

state of ADDRDATA unless the address on the Data inputs

has been changed with ADDRDATA at 0.

VECTORED CLEAR ADDRESS

Addresses 23 (17H) or 55 (37H) is used to clear all registers

to zero simultaneously. This function may be desirable to use

prior to loading new data into the Data or Status Registers.

This address is read into the device in a similar fashion as all

of the other registers. A 1 on the ADDRDATA pin (Auto Ad-

dressing Mode) will not cause this address to automatically

increment. The address will loop back onto itself regardless

of the state of ADDRDATA unless the address on the Data

inputs has been changed with ADDRDATA at 0.

Normal device operation can be resumed by loading in a

non-scan address. As the scanning of the registers is a

non-destructive scan, the device will resume correct opera-

tion from the point at which it was halted.

RS170 Default Register Values

The tables below show the values programmed for the

RS170 Format (using a 14.31818 MHz clock signal) and

how they compare against the actual EIA RS170 Specifica-

tions. The default signals that will be output are CSYNC,

CBLANK, HDRIVE and VDRIVE. The device initially starts at

the beginning of the odd field of interlace. All signals have

active low pulses and the clock is disabled at power up. Reg-

isters 13 and 14 are not involved in the actual signal informa-

tion. If the Vertical Interrupt was selected so that a pulse in-

dicating the active lines would be output.

DS100232-9

FIGURE 4. ADDRDEC Timing

GEN LOCKING

The ’ACT715/LM1882 and ’ACT715-R/LM1882-R is de-

signed for master SYNC and BLANK signal generation.

However, the devices can be synchronized (slaved) to an ex-

ternal timing signal in a limited sense. Using Vectored Re-

start, the user can reset the counting sequence to a given lo-

cation, the beginning, at a given time, the rising edge of the

LOAD that removes Vector Restart. At this time the next

CLOCK pulse will be CLOCK 1 and the count will restart at

the beginning of the first odd line.

Preconditioning the part during normal operation, before the

desired synchronizing pulse, is necesasry. However, since

LOAD and CLOCK are asynchronous and independent, this

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RS170 Default Register Values (Continued)

Reg

D Value H

REG0

000 Status Register (715/LM1882)

REG0 1024 400 Status Register

(715-R/LM1882-R)

REG1

REG2

REG3

REG4

REG5

REG6

REG7

REG8

REG9

017 HFP End Time

05B HSYNC Pulse End Time

157 09D HBLANK Pulse End Time

910 38E Total Horizontal Clocks

007 VFP End Time

00D VSYNC Pulse End Time

029 VBLANK Pulse End Time

525 20D Total Vertical Lines

57 039 Equalization Pulse End Time

REG10 410 19A Serration Pulse Start Time

REG11

001 Pulse Interval Start Time

013 Pulse Interval End Time

029 Vertical Interrupt Activate Time

REG12 19

REG13 41

REG14 526 20E Vertical Interrupt Deactivate Time

REG15 911 38F Horizontal Drive Start Time

REG16 92

REG17

05C Horizontal Drive End Time

001 Vertical Drive Start Time

015 Vertical Drive End Time

REG18 21

Rate

14.31818 MHz

15.73426 kHz

59.94 Hz

Period

Input Clock

Line Rate

69.841 ns

63.556 µs

16.683 ms

33.367 ms

Field Rate

Frame Rate

29.97 Hz

RS170 Horizontal Data

Signal

HFP

Width

µs

1.536

Specification (µs)

1.5 0.1

22 Clocks

68 Clocks

4.7 0.1

HSYNC Width

HBLANK Width

HDRIVE Width

HEQP Width

HSERR Width

HPER iod

4.749

7.47

17.15

10.00

3.74

7.47

100

10.9 0.2

156 Clocks

91 Clocks

34 Clocks

68 Clocks

910 Clocks

10.895

0.1H 0.005H

6.356

2.3 0.1

2.375

4.749

4.7 0.1

63.556

RS170 Vertical Data

190.67

VFP

3 Lines

6 EQP Pulses

VSYNC Width

VBLANK Width

VDRIVE Width

VEQP Intrvl

190.67

6 Serration Pulses

0.075V 0.005V

20 Lines

11.0 Lines

9 Lines

1271.12

699.12

7.62

4.20

3.63

0.04V 0.006V

9 Lines/Field

16.683 ms/Field

33.367 ms/Frame

VPERiod (field)

VPERiod (frame)

262.5 Lines

525 Lines

16.683 ms

33.367 ms

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Junction Temperature (T_J)

Ceramic

175˚C

140˚C

Plastic

Recommended Operating

Conditions

Supply Voltage (V_CC

)

−0.5V to +7.0V

DC Input Diode Current (I_IK

)

V_I−0.5V

−20 mA

+20 mA

Supply Voltage (V_CC

)

4.5V to 5.5V

0V to V_CC

V_IV_CC+0.5V

Input Voltage (V_I)

DC Input Voltage (V_I)

−0.5V to V_CC+0.5V

Output Voltage (V_O

)

DC Output Diode Current (I_OK

)

Operating Temperature (T_A)

54ACT

V_O−0.5V

−20 mA

+20 mA

−55˚C to +125˚C

V_OV_CC+0.5V

Minimum Input Edge Rate (∆V/∆t)

V_INfrom 0.8V to 2.0V

DC Output Voltage (V_O

DC Output Source

)

−0.5V to V_CC+0.5V

V_CC4.5V, 5.5V

125 mV/ns

or Sink Current (I_O

)

15 mA

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature and output/input loading variables. National does not recom-

mend operation of FACT^®circuits outside databook specifications.

DC V_CCor Ground Current

per Output Pin (I_CCor I_GND

)

20 mA

Storage Temperature (T_STG

)

−65˚C to +150˚C

DC Characteristics

For ’ACT Family Devices over Operating Temperature Range (unless otherwise specified)

LM1882 54ACT/LM1882 LM1882

V_CC

(V)

T_A+25˚C

T_A−55˚C

T_A−40˚C

Symbol

Parameter

C_L50 pF

to +125˚C

to +85˚C

Units

Conditions

C_L50 pF

Typ

Guaranteed Limits

V_OH

Minimum High Level

Output Voltage

4.5

5.5

4.49

5.49

4.4

5.4

4.4

5.4

4.4

5.4

I_OUT−50 µA

(Note 2)

V_INV_IL/V_IH

4.5

5.5

4.5

5.5

3.86

4.86

0.1

3.7

4.7

0.1

3.76

4.76

0.1

I_OH−8 mA

V_OL

Maximum Low Level

Output Voltage

0.001

I_OUT50 µA

0.1

(Note 2)

V_INV_IL/V_IH

4.5

5.5

0.36

0.5

0.44

32.0

I_OH+8 mA

V_OLD1.65V

I_OLD

I_OHD

I_IN

Minimum Dynamic

Output Current

Minimum Dynamic

Output Current

Maximum Input

Leakage Current

Supply Current

Quiescent

32.0

5.5

−32.0

µA

V_OHD3.85V

1.0

0.1

1.0

V_IV_CC, GND

V_INV_CC, GND

I_CC

8.0

160

1.6

µA

V_INV_CC− 2.1V

I_CCT

Maximum I_CC/Input

0.6

1.5

Note 2: All outputs loaded; thresholds on input associated with input under test.

Note 3: Test Load 50 pF, 500Ω to Ground.

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AC Electrical Characteristics

LM1882

54ACT/LM1882

LM1882

V_CC

T_A+25˚C

T_A−55˚C

T_A−40˚C

Symbol

Parameter

(V)

C_L50 pF

to +125˚C

to +85˚C

Units

C_L50 pF

Min

Typ

Max

Min

Max

Min

Max

f_MAXI

Interlaced f_MAX

5.0

170

190

130

145

3.5

3.0

150

175

3.5

3.0

MHz

(HMAX/2 is ODD)

Non-Interlaced f_MAX

(HMAX/2 is EVEN)

Clock to Any Output

f_MAX

190

4.0

4.5

4.0

220

13.0

15.0

11.5

t_PLH1

t_PHL1

t_PLH2

t_PHL2

t_PLH3

15.5

17.0

16.0

19.5

22.0

20.0

18.5

20.5

19.5

Clock to ODDEVEN

(Scan Mode)

Load to Outputs

AC Operating Requirements

LM1882

54ACT/LM1882

LM1882

Symbol

Parameter

V_CC

(V)

T_A+25˚C

T_A−55˚C

T_A−40˚C

Units

to +125˚C

to +85˚C

Typ

Guaranteed Minimums

Control Setup Time

ADDR/DATA to LOAD−

L/HBYTE to LOAD−

Data Setup Time

D7–D0 to LOAD+

Control Hold Time

LOAD− to ADDR/DATA

LOAD− to L/HBYTE

Data Hold Time

t_sc

5.0

3.0

4.0

4.5

t_sc

t_sd

t_hc

5.0

2.0

4.0

4.5

1.0

t_hd

LOAD+ to D7–D0

LOAD+ to CLK (Note 4)

Load Pulse Width

LOW

5.0

1.0

5.5

2.0

7.0

2.0

8.0

2.0

8.0

t_rec

t_wld−

t_wld+

t_wclr

t_wck

5.0

3.0

5.5

2.5

5.5

5.0

6.5

3.0

5.5

7.5

9.5

4.0

5.5

7.5

9.5

3.5

HIGH

CLR Pulse Width HIGH

CLOCK Pulse Width

(HIGH or LOW)

Note 4: Removal of Vectored Reset or Restart to Clock.

Capacitance

Symbol

Parameter

Input Capacitance

Power Dissipation

Capacitance

Typ

7.0

Units

Conditions

V_CC5.0V

C_IN

V_CC5.0V

C_PD

17.0

www.national.com

Capacitance (Continued)

DS100232-6

FIGURE 5. AC Specifications

Additional Applications Information

POWERING UP

PREPROGRAMMING “ON-THE-FLY”

The ’ACT715/LM1882 default value for Bit 10 of the Status

plied and the registers are initialized by loading the default

values the CLOCK is disabled. Before operation can begin,

Bit 10 must be changed to a 1 to enable CLOCK. If the de-

fault values are needed (no other programming is required)

then Figure 6 illustrates a hardwired solution to facilitate the

enabling of the CLOCK after power-up. Should control sig-

nals be difficult to obtain, Figure 7 illustrates a possible solu-

tion to automatically enable the CLOCK upon power-up. Use

of the ’ACT715-R/LM1882-R eliminates the need for most of

this circuitry. Modifications of the Figure 7 circuit can be

made to obtain the lone CLEAR pulse still needed upon

power-up.

Although the ’ACT715/LM1882 and ’ACT715-R/LM1882-R

are completely programmable, certain limitations must be

set as to when and how the parts can be reprogrammed.

Care must be taken when reprogramming any End Time reg-

isters to a new value that is lower than the current value.

Should the reprogramming occur when the counters are at a

count after the new value but before the old value, then the

counters will continue to count up to 4096 before rolling over.

For this reason one of the following two precautions are rec-

ommended when reprogramming “on-the-fly”. The first rec-

ommendation is to reprogram horizontal values during the

horizontal blank interval only and/or vertical values during

the vertical blank interval only. Since this would require deli-

cate timing requirements the second recommendation may

be more appropriate.

Note that, although during a Vectored Restart none of the

preprogrammed registers are affected, some signals are af-

fected for the duration of one frame only. These signals are

the Horizontal and Vertical Drive signals. After a Vectored

Restart the beginning of these signals will occur at the first

CLK. The end of the signals will occur as programmed. At

the completion of the first frame, the signals will resume to

their programmed start and end time.

The second recommendation is to program a Vectored Re-

start as the final step of reprogramming. This will ensure that

all registers are set to the newly programmed values and

that all counters restart at the first CLK position. This will

avoid overrunning the counter end times and will maintain

the video integrity.

www.national.com

Additional Applications Information (Continued)

DS100232-10

FIGURE 6. Default RS170 Hardwire Configuration

DS100232-11

Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND

Components

R1: 4.7k

R2:10k

C1: 10 µF

C2: 50 pF

FIGURE 7. Circuit for Clear and Load Pulse Generation

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Physical Dimensions inches (millimeters) unless otherwise noted

20-Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

20-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Integrated Circuit (S)

NS Package Number M20B

20-Lead Plastic Dual-In-Line Package (P)

NS Package Number N20B

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LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-

VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-

CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, and whose fail-

ure to perform when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 1 80-530 85 85

English Tel: +49 (0) 1 80-532 78 32

Français Tel: +49 (0) 1 80-532 93 58

Italiano Tel: +49 (0) 1 80-534 16 80

Email: sea.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

National Semiconductor Company

Design

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Products > Analog - Display Circuits > Video Communication > 54ACT715

Product Folder

54ACT715

Programmable Video Sync Generator

Contents

Parametric Table

Function

Sync Generator

General Description

Features

Datasheet

Package Availability, Models, Samples

& Pricing

Supply Voltage 5 V

General Description

The 'ACT715/LM1882 and 'ACT715-R/LM1882-R are 20-pin TTL-input compatible

devices capable of generating Horizontal, Vertical and Composite Sync and Blank signals

for televisions and monitors. All pulse widths are completely definable by the user. The

devices are capable of generating signals for both interlaced and noninterlaced modes of

operation. Equalization and serration pulses can be introduced into the Composite Sync

signal when needed.

Four additional signals can also be made available when Composite Sync or Blank are used.

These signals can be used to generate horizontal or vertical gating pulses, cursor position or

vertical Interrupt signal.

These devices make no assumptions concerning the system architecture. Line rate and

field/frame rate are all a function of the values programmed into the data registers, the status

The 'ACT715/LM1882 is mask programmed to default to a Clock Disable state. Bit 10 of

the Status Register, Register 0, defaults to a logic "0". This facilitates (re)programming

before operation.

The 'ACT715-R/LM1882-R is the same as the 'ACT715/LM1882 in all respects except that

the 'ACT715-R/LM1882-R is mask programmed to default to a Clock Enabled state. Bit 10

of the Status Register defaults to a logic "1". Although completely (re)programmable, the

'ACT715-R/LM1882-R version is better suited for applications using the default 14.31818

MHz RS-170 register values. This feature allows power-up directly into operation, following

a single CLEAR pulse.

Features

Maximum Input Clock Frequency > 130 MHz

Interlaced and non-interlaced formats available

Separate or composite horizontal and vertical Sync and Blank signals available

Complete control of pulse width via register programming

All inputs are TTL compatible

8 mA drive on all outputs

Default RS170/NTSC values mask programmed into registers

4 KV minimum ESD immunity

'ACT715-R/LM1882-R is mask programmed to default to a Clock Enable state for

easier start-up into 14.31818 MHz RS170 timing

Datasheet

Size

(in

Kbytes)

Title

Date

Receive via

View

Online

Download

LM1882 54ACT715 LM1882-R 54ACT715-R Programmable Video Sync

Generator

4-Dec-

340 Kbytes

View Online Download Receive via Email

Please use Adobe Acrobat to view PDF file(s).

If you have trouble printing, see Printing Problems.

Package Availability, Models, Samples & Pricing

Samples

Electronic

Orders

Package

Models

Budgetary Pricing

Quantity $US each

Std

Pack

Size

Package

Marking

Part Number

Status

Type # pins

SPICE IBIS

[logo]¢Z¢S¢4¢A

54ACT715-

RLMQB/Q¢M$E

5962-

tube

5962-9309702M2A LCC

20 Full production N/A N/A

50+

$19.8000 of

9309702M2A

[logo]¢Z¢S¢4¢A

54ACT715

tube

Order Parts

5962-9309701M2A LCC

$18.7000 of

LMQB/Q¢M$E

5962-

9309701M2A

tube

[logo]¢Z¢S¢4¢A$E

5962-9309702MRA Cerdip 20 Full production N/A N/A

50+

$14.5000 of 54ACT715-RDMQB /Q¢M

5962-9309702MRA

tube

$15.6000 of

[logo]¢Z¢S¢4¢A$E

54ACT715DMQB /Q¢M

5962-9309701MRA

5962-9309701MRA Cerdip 20 Full production N/A N/A

[Information as of 1-Sep-2000]

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