LM20143 [TI]

具有调频功能的2.95V 至 5.5V、3A、电流模式同步降压稳压器;


型号：	LM20143
厂家：	TEXAS INSTRUMENTS
描述：	具有调频功能的2.95V 至 5.5V、3A、电流模式同步降压稳压器稳压器
文件：	总39页 (文件大小：1268K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LM20143, LM20143-Q1

SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

LM20143/LM20143-Q1 3-A PowerWise™ Adjustable Frequency Synchronous Buck

Regulator

1 Features

3 Description

The LM20143 devices are full featured PowerWise™

adjustable frequency synchronous buck regulators

capable of delivering up to 3 A of continuous output

current. The current mode control loop can be

compensated to be stable with virtually any type of

output capacitor. For most cases, compensating the

device only requires two external components,

providing maximum flexibility and ease of use. The

device is optimized to work over the input voltage

range of 2.95 V to 5.5 V, making it suited for a wide

variety of low voltage systems.

•

Available in AEC-Q100 Temperature Grade 1

Input Voltage Range: 2.95 V to 5.50 V

Accurate Current Limit Minimizes Inductor Size

97% Peak Efficiency

•

Adjustable Output Voltage Down to 0.80 V

Adjustable Switching Frequency (500 kHz to 1.5

MHz)

•

32-mΩ Integrated FET Switches

Starts into Prebiased Loads

The device features internal over voltage protection

(OVP) and over current protection (OCP) circuits for

increased system reliability. A precision enable pin

and integrated UVLO allows the turn-on of the device

to be tightly controlled and sequenced. Start-up

inrush currents are limited by both an internally fixed

and externally adjustable Soft-Start circuit. Fault

detection and supply sequencing is possible with the

integrated power good circuit.

Output Voltage Tracking

Peak Current Mode Control

Adjustable Soft-Start with External Capacitor

Precision Enable Pin with Hysteresis

Integrated OVP, UVLO, Power Good and Thermal

Shutdown

2 Applications

The frequency of this device can be adjusted from

500 kHz to 1.5 MHz by connecting an external

resistor from the RT pin to ground.

•

Simple to Design, High Efficiency Point of Load

Regulation from a 5-V or 3.3-V Bus

High Performance DSPs, FPGAs, ASICs, and

Microprocessors

The LM20143 is designed to work well in multi-rail

power supply architectures. The output voltage of the

device can be configured to track a higher voltage rail

using the SS/TRK pin. If the output of the LM20143 is

pre-biased at startup it will not sink current to pull the

output low until the internal soft-start ramp exceeds

the voltage at the feedback pin.

Broadband, Networking, and Optical

Communications Infrastructure

Device Information⁽¹⁾

PART NUMBER

LM20143

PACKAGE

BODY SIZE (NOM)

HTSSOP (16)

4.40 mm × 5.00 mm

LM20143-Q1

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Circuit

LM20143

OUT

PVIN

FB1

OUT

AVIN

FB2

PGOOD

VCC

COMP

VCC

SS/TRK

PGND AGND

(optional)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM20143, LM20143-Q1

SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

www.ti.com

Table of Contents

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 13

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Applications ................................................ 17

Power Supply Recommendations...................... 27

10 Layout................................................................... 27

10.1 Layout Guidelines ................................................. 27

10.2 Layout Example .................................................... 28

10.3 Thermal Considerations........................................ 29

11 Device and Documentation Support ................. 30

11.1 Device Support...................................................... 30

11.2 Documentation Support ........................................ 30

11.3 Related Links ........................................................ 30

11.4 Trademarks........................................................... 30

11.5 Electrostatic Discharge Caution............................ 30

11.6 Glossary................................................................ 30

12 Mechanical, Packaging, and Orderable

Information ........................................................... 30

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (March 2013) to Revision H

Page

•

Added ESD Ratings table, Feature Descriptionsection, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1

Changes from Revision F (March 2013) to Revision G

Page

•

Changed layout of National Data Sheet to TI format ............................................................................................................. 1

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SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP With Exposed Thermal Pad

Top View

SS/TRK

AGND

AVIN

PGOOD

COMP

Exposed Pad

On Bottom

(EP)

VCC

PGND

PVIN

Pin Functions

NAME

TYPE⁽¹⁾

DESCRIPTION

NO.

Soft-Start or Tracking control input. An internal 5-µA current source charges an external capacitor to set

the Soft-Start ramp rate. If driven by a external source less than 800 mV, this pin overrides the internal

reference that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated.

SS/TRK

Feedback input to the error amplifier from the regulated output. This pin is connected to the inverting

input of the internal transconductance error amplifier. An 800-mV reference connected to the non-

inverting input of the error amplifier sets the closed loop regulation voltage at the FB pin.

Power good output signal. Open drain output indicating the output voltage is regulating within tolerance.

is recommend for most applications.

PGOOD

COMP

External compensation pin. Connect the compensation network to resistor and capacitor to this pin to

compensate the device.

This pin has no internal connection. While this pin may be left open, it is strongly recommended that this

pin be connected to Ground.

Input voltage to the power switches inside the device. These pins should be connected together at the

device. A low ESR capacitor should be placed near these pins to stabilize the input voltage.

PVIN

Switch pin. The PWM output of the internal power switches.

Power ground pin for the internal power switches.

PGND

Precision enable input for the device. An external voltage divider can be used to set the device turn-on

threshold. If not used the EN pin should be connected to PVIN.

VCC

AVIN

Internal 2.7-V sub-regulator. This pin should be bypassed with a 1-µF ceramic capacitor.

Analog input supply that generates the internal bias. Must be connected to VIN through a low pass RC

filter.

AGND

Quiet analog ground for the internal bias circuitry.

Frequency adjust pin. Connecting a resistor on this pin to ground will set the oscillator frequency.

Exposed metal thermal pad on the underside of the package with a weak electrical connection to

ground. It is recommended to connect this pad to the PC board ground plane copper in order to improve

heat dissipation and reduce the package θ_JA. Do not connect to any potential other than Ground.

Exposed Pad

(1) P: Power, I: Input, O: Output, G: Ground

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SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

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6 Specifications

6.1 Absolute Maximum Ratings

(1)

See

MIN

MAX

UNIT

AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, RT

Power Dissipation⁽²⁾

Voltages from indicated pins to GND

–0.3

2.6

Junction Temperature

150

260

150

°C

Lead Temperature (Soldering, 10 sec)

Storage Temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The maximum allowable power dissipation is a function of the maximum junction temperature, T_{J_MAX}, the junctions-to-ambient thermal

resistance, θ_JA, and the ambient temperature, T_A. The maximum allowable power dissipation at any ambient temperature is calculated

using: P_{D_MAX}= (T_{J_MAX}– T_A) / θ_JA. The maximum power dissipations of 2.6 W is determined using T_A= 25°C, θ_JA= 38°C/W, and

T_{J_MAX}= 125°C.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

MAX

5.5

UNIT

PVIN, AVIN to GND

Junction Temperature

2.95

−40

125

°C

6.4 Thermal Information

LM20143

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

16 PINS

39.3

20.3

9.9

(2)

(3)

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JB

9.9

R_θJC(bot)

12.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) On JEDEC 4-Layer test board (JESD 51-7) with eight (8) thermal vias.

(3) θ_JCrefers to center of the Exposed Pad on the bottom of the package as the case.

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SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

6.5 Electrical Characteristics

Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5 V. All Typical limits are for T_J= 25°C only, all

Minimum and Maximum limits apply over the junction temperature (T_J) range of –40°C to 125°C⁽¹⁾. Typical values represent

the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only.

PARAMETER

TEST CONDITIONS

V_IN= 2.95 V to 5.5 V

MIN

TYP

0.8

0.08

4.8

MAX

UNIT

V_FB

Feedback pin voltage

0.788

0.812

ΔV_OUT/ΔI_OUT

I_CL

Load Regulation

I_OUT= 100 mA to 3 A

V_IN= 3.3 V

%/A

Switch Current Limit Threshold

High-Side Switch On Resistance

Low-Side Switch On Resistance

Operating Quiescent Current

Shutdown Quiescent current

VIN Under Voltage Lockout

VIN Under Voltage Lockout Hysteresis

VCC Voltage

4.3

5.3

R_{DS_ON}

I_Q

I_SW= 3.5 A

mΩ

µA

I_SW= 3.5 A

Non-switching, V_FB= V_COMP

V_EN= 0 V

3.5

I_SD

180

2.95

100

2.95

V_UVLO

Rising V_IN

2.45

2.7

V_{UVLO_HYS}

V_VCC

Falling V_IN

I_VCC= 0 µA

2.45

2.7

4.5

I_SS

Soft-Start Pin Source Current

SS/TRK Accuracy, V_SS- V_FB

V_SS/TRK= 0 V

V_SS/TRK= 0.4 V

µA

V_TRACK

OSCILLATOR

F_OSCH

F_OSCL

–10

Oscillator Frequency

Maximum Duty Cycle

Minimum On Time

R_T= 49.9 kΩ

R_T= 249 kΩ

I_LOAD= 0 A

1350

450

1500

510

85%

100

1650

570

kHz

DC_MAX

T_{ON_TIME}

T_{CL_BLANK}

Current Sense Blanking Time

After Rising V_SW

ERROR AMPLIFIER AND MODULATOR

I_FB

Feedback pin bias current

V_FB= 0.8 V

100

600

µA

I_{COMP_SRC}

I_{COMP_SNK}

COMP Output Source Current

COMP Output Sink Current

Error Amplifier Transconductance

Error Amplifier Voltage Gain

V_FB= V_COMP= 0.6 V

V_FB= 1.0 V, V_COMP= 0.6 V

I_COMP= ± 50 µA

100

µA

450

510

µmho

V/V

A_VOL

2000

POWER GOOD

V_OVP

Over Voltage Protection Rising Threshold

Over Voltage Protection Hysteresis

PGOOD Rising Threshold

With respect to V_FB

105%

92%

108%

94%

111%

V_{OVP_HYS}

V_PGTH

96%

V_PGHYS

T_PGOOD

I_OL

PGOOD Falling Hysteresis

PGOOD deglitch time

µs

PGOOD Low Sink Current

V_PGOOD= 0.4 V

V_PGOOD= 5 V

0.6

I_OH

PGOOD High Leakage Current

100

ENABLE

V_{IH_EN}

V_{EN_HYS}

EN Pin turn-on Threshold

EN Pin Hysteresis

V_ENRising

1.08

1.18

1.28

THERMAL SHUTDOWN

T_SD

Thermal Shutdown

Thermal Shutdown Hysteresis

160

°C

T_{SD_HYS}

(1) Minimum and Maximum limits are specified by test, design, or statistical correlation.

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6.6 Typical Characteristics

Unless otherwise specified: C_IN= C_OUT= 100 µF, L = 1.0 µH, V_IN= 5 V, V_OUT= 1.2 V, R_LOAD= 1.2 Ω, f_SW= 1 MHz, T_A= 25°C

for efficiency curves, loop gain plots and waveforms, and T_J= 25°C for all others.

V_IN= 5 V

f_SW= 1.5 MHz

V_IN= 3.3 V

f_SW= 1.5 MHz

Figure 1. Efficiency vs Load Current

Figure 2. Efficiency vs Load Current

V_IN= 3.3 V

f_SW= 1.0 MHz

V_IN= 5 V

f_SW= 1.0 MHz

Figure 4. Efficiency vs Load Current

Figure 3. Efficiency vs Load Current

V_IN= 5.0 V

f_SW500 kHz

V_IN= 3.3 V

f_SW= 500 kHz

Figure 5. Efficiency vs Load Current

Figure 6. Efficiency vs Load Current

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SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

Typical Characteristics (continued)

Unless otherwise specified: C_IN= C_OUT= 100 µF, L = 1.0 µH, V_IN= 5 V, V_OUT= 1.2 V, R_LOAD= 1.2 Ω, f_SW= 1 MHz, T_A= 25°C

for efficiency curves, loop gain plots and waveforms, and T_J= 25°C for all others.

Figure 7. High-Side FET Resistance vs Temperature

Figure 8. Low-Side FET Resistance vs Temperature

Figure 9. Error Amplifier Gain vs Frequency

Figure 10. Line Regulation

Figure 11. Load Regulation

Figure 12. Feedback Pin Voltage vs Temperature

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Typical Characteristics (continued)

Unless otherwise specified: C_IN= C_OUT= 100 µF, L = 1.0 µH, V_IN= 5 V, V_OUT= 1.2 V, R_LOAD= 1.2 Ω, f_SW= 1 MHz, T_A= 25°C

for efficiency curves, loop gain plots and waveforms, and T_J= 25°C for all others.

Figure 13. Switching Frequency vs Temperature

Figure 14. Switching Frequency vs R_T

Figure 15. Quiescent Current vs V_IN(Not Switching)

Figure 16. Shutdown Current vs Temperature

Figure 17. Enable Threshold vs Temperature

Figure 18. UVLO Threshold vs Temperature

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SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

Typical Characteristics (continued)

Unless otherwise specified: C_IN= C_OUT= 100 µF, L = 1.0 µH, V_IN= 5 V, V_OUT= 1.2 V, R_LOAD= 1.2 Ω, f_SW= 1 MHz, T_A= 25°C

for efficiency curves, loop gain plots and waveforms, and T_J= 25°C for all others.

Figure 19. Peak Current Limit vs Temperature

Figure 20. Peak Current Limit vs V_OUT

Figure 22. Load Transient Response

Figure 21. Peak Current Limit vs V_IN

Figure 24. Start Up (Soft-Start)

Figure 23. Line Transient Response

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Typical Characteristics (continued)

Unless otherwise specified: C_IN= C_OUT= 100 µF, L = 1.0 µH, V_IN= 5 V, V_OUT= 1.2 V, R_LOAD= 1.2 Ω, f_SW= 1 MHz, T_A= 25°C

for efficiency curves, loop gain plots and waveforms, and T_J= 25°C for all others.

Figure 25. Start Up (Tracking)

Figure 26. Short Circuit Input Current vs V_IN

Figure 27. Power Down

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SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

7 Detailed Description

7.1 Overview

The LM20143 switching regulator features all of the functions necessary to implement an efficient low voltage

buck regulator using a minimum number of external components. This easy to use regulator features two

integrated switches and is capable of supplying up to 3 A of continuous output current. The regulator utilizes

peak current mode control with nonlinear slope compensation to optimize stability and transient response over

the entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-

cycle current limiting and easy loop compensation. The switching frequency can be varied from 500 kHz to 1.5

MHz with an external resistor to ground. The device can operate at high switching frequency allowing use of a

small inductor while still achieving efficiencies as high as 96%. The precision internal voltage reference allows

the output to be set as low as 0.8 V. Fault protection features include: current limiting, thermal shutdown, over

voltage protection, and shutdown capability. The device is available in the HTSSOP 16-pin package featuring an

exposed pad to aid thermal dissipation. The LM20143 can be used in numerous applications to efficiently step-

down from a 5 V or 3.3 V bus. The typical application circuit for the LM20143 is shown in Figure 32 in the design

guide.

7.2 Functional Block Diagram

+2.7V

REGULATOR

AVIN

VCC

UVLO

2.7V

SLOPE COMP

PVIN

COMP

2.7V

CURRENT SENSE

5 mA

(50 ms)

DISCHARGE

SS/TRK

ERROR AMP

= 510 mmho

DISCHARGE

CURRENT

LIMIT

4.8A

PVIN

VREF

800 mV

PWM COMPARATOR

OVERVOLTAGE

DIODE

EMULATION

864 mV

PG-L

CONTROL

LOGIC

UNDERVOLTAGE

752 mV

PVIN

THERMAL

PROTECTION

1.18V

PGND

PG-L

OSCILLATOR

PGOOD

AGND

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7.3 Feature Description

7.3.1 Peak Current Mode Control

In most cases, the peak current mode control architecture used in the LM20143 only requires two external

components to achieve a stable design. The compensation can be selected to accommodate any capacitor type

or value. The external compensation also allows the user to set the crossover frequency and optimize the

transient performance of the device.

For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to

avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What

makes the LM20143 unique is the amount of slope compensation will change depending on the output voltage.

When operating at high output voltages the device will have more slope compensation than when operating at

lower output voltages. This is accomplished in the LM20143 by using a non-linear parabolic ramp for the slope

compensation. The parabolic slope compensation of the LM20143 is much better than the traditional linear slope

compensation because it optimizes the stability of the device over the entire output voltage range.

7.3.2 Precision Enable

The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.

This pin is a precision analog input that enables the device when the voltage exceeds 1.2 V (typical). The EN pin

has 100 mV of hysteresis and will disable the output when the enable voltage falls below 1.1 V (typical). If the EN

pin is not used, it should be connected to VIN. Since the enable pin has a precise turn-on threshold it can be

used along with an external resistor divider network from V_INto configure the device to turn-on at a precise input

voltage. The precision enable circuitry will remain active even when the device is disabled.

7.3.3 Current Limit

The precise current limit of the LM20143 is set at the factory to be within 10% over the entire operating

temperature range. This enables the device to operate with smaller inductors that have lower saturation currents.

When the peak inductor current reaches the current limit threshold, an over current event is triggered and the

internal high-side FET turns off and the low-side FET turns on allowing the inductor current to ramp down until

the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM

pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events,

while at the same time providing frequency and voltage foldback protection during hard short circuit conditions.

7.3.4 Pre-Bias Start Up Capability

The LM20143 is in a pre-biased state when the device starts up with an output voltage greater than zero. This

often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these

applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.

Even though the LM20143 is a synchronous converter it will not pull the output low when a pre-bias condition

exists. During start up the LM20143 will not sink current until the Soft-Start voltage exceeds the voltage on the

FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if

current is conducted through the parasitic paths of the load.

7.3.5 Soft-Start and Voltage Tracking

The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage

source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground.

The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus

reducing stresses on the input supply and controlling start up current. If no Soft-Start capacitor is used the device

defaults to the internal Soft-Start circuitry resulting in a start up time of approximately 1 ms. For applications that

require a monotonic start up or utilize the PGOOD pin, an external Soft-Start capacitor is recommended. The

SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two

external resistors connected to the SS/TRK pin as shown in Figure 29.

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Feature Description (continued)

7.3.6 Power Good and Overvoltage Fault Handling

The LM20143 has built in under and over voltage comparators that control the power switches. Whenever there

is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn-

on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage

falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output

reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low.

Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient

glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges.

7.3.7 UVLO

The LM20143 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the

input voltage reaches 2.7 V (typical). The UVLO threshold has 45 mV of hysteresis that keeps the device from

responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by

using the precision enable pin and a resistor divider network connected to V_INas shown in Figure 31. in the

design guide.

7.3.8 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum

junction temperature is exceeded. When activated, typically at 160°C, the LM20143 tri-states the power FETs

and resets soft start. After the junction cools to approximately 150°C, the part starts up using the normal start up

routine. This feature is provided to prevent catastrophic failures from accidental device overheating.

7.4 Device Functional Modes

7.4.1 Light Load Operation

The LM20143 offers increased efficiency when operating at light loads. Whenever the load current is reduced to

a point where the peak to peak inductor ripple current is greater than two times the load current, the part will

enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is

the critical conduction boundary and can be calculated by Equation 1

(V_INœ V_OUT) x D

I_BOUNDARY

2 x L x f_SW

(1)

Several diagrams are shown in Figure 28 illustrating continuous conduction mode (CCM), discontinuous

conduction mode, and the boundary condition.

It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will

become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor

and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be

added from the switch node to ground.

At very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively

reducing the switching frequency and further improving light-load efficiency.

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Device Functional Modes (continued)

Continuous Conduction Mode (CCM)

Time (s)

Continuous Conduction Mode (CCM)

AVERAGE

Time (s)

DCM - CCM Boundary

AVERAGE

Time (s)

Discontinuous Conduction Mode (DCM)

Time (s)

Discontinuous Conduction Mode (DCM)

Peak

Time (s)

Figure 28. Modes of Operation for LM20143

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Device Functional Modes (continued)

7.4.2 Tracking an External Supply

By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 29, the

output of the LM20143 can be configured to track an external voltage source to obtain a simultaneous or

ratiometric start up.

External

Power Supply

OUT1

LM20143

OUT2

SS/TRK

Figure 29. Tracking an External Supply

Since the Soft-Start charging current I_SSis always present on the SS/TRK pin, the size of R2 should be less than

10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be

calculated using appropriate equation in Figure 30, to give the desired start up. Figure 30 shows two common

start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates

a ratiometric start up.

SIMULTANEOUS START UP

OUT1

OUT2

≈

’

OUT2

0.8V

∆

-1

R1=

◊

< 0.8 x V

OUT2

OUT1

TIME

RATIOMETRIC START UP

OUT1

(

)

-1

R1=

OUT1

OUT2

TIME

Figure 30. Common Start Up Sequences

A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these

systems the higher voltage, V_OUT1, usually powers the I/O, and the lower voltage, V_OUT2, powers the core. A

simultaneous start up provides a more robust power up for these applications since it avoids turning on any

parasitic conduction paths that may exist between the core and the I/O pins of the processor.

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Device Functional Modes (continued)

The second most common power on behavior is known as a ratiometric start up. This start up is preferred in

applications where both supplies need to be at the final value at the same time.

Similar to the Soft-Start function, the fastest start up possible is 1ms regardless of the rise time of the tracking

voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide

sufficient overdrive and transient immunity.

7.4.3 Using Precision Enable and Power Good

The precision enable (EN) and power good (PGOOD) pins of the LM20143 can be used to address many

sequencing requirements. The turn-on of the LM20143 can be controlled with the precision enable pin by using

two external resistors as shown in Figure 31.

External

Power Supply

OUT1

LM20143

OUT2

Figure 31. Sequencing LM20143 with Precision Enable

The value for resistor R_Bcan be selected by the user to control the current through the divider. Typically this

resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for R_Bis chosen the resistor R_Acan be

solved using Equation 2 to set the desired turn-on voltage.

V_TO

V_{IH_EN}

x R

- 1

R_A

(2)

When designing for a specific turn-on threshold (V_TO) the tolerance on the input supply, enable threshold

(V_{IH_EN}), and external resistors needs to be considered to insure proper turn-on of the device.

The LM20143 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to

provide fault detection. This pin requires an external resistor (R_PG) to pull PGOOD high while when the output is

within the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM20143 is a step down DC/DC converter, typically used for to convert 3.3 V or 5 V rail to lower DC

voltages with a maximum output current of 3 A. The following design procedure can be used to select all the

external components for the LM20143. Alternately, the WEBENCH^®Design Tool may be used to complete the

design. By using this tool the user can optimize the design by using an iterative design procedure and selecting

different components from the extensive component database. Along with this datasheet and WEBENCH, the

user can reference the LM20143 Quickstart Calculator tool as a free download. The Quickstart tool is an excel

sheet summary of the Typical Applications section.

8.2 Typical Applications

Several circuit designs can be created for applications with differing requirements. Three examples

demonstrating this are detailed in this section.

8.2.1 3.3-V or 5-V Supply Rail Design

This section walks the designer through the steps necessary to select the external components to build a fully

functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design

for efficiency, size, or performance. These will be taken into account and highlighted throughout this section. The

circuit shown in Figure 32 may be used as a reference to facilitate component selection. Unless otherwise

indicated all formulas assume units of amps (A) for current, farads (F) for capacitance, henries (H) for inductance

and volts (V) for voltages.

LM20143

PVIN

OUT

FB1

AVIN

OUT

FB2

PGOOD

VCC

R_T

COMP

SS/TRK

PGND GND

VCC

Figure 32. Typical Application Circuit

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

3.3 V to 5 V

1.2 V

Operating frequency

Output current rating

1.5 MHz

3 A

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8.2.1.2 Detailed Design Procedure

Table 2 lists components chosen for a circuit design with the listed specifications. The example calculations in

this section will use values representative of this circuit design.

Table 2. Bill of Materials

Designator

Description

Synchronous Buck Regulator

47 µF, 1210, X5R, 6.3 V

1.2 µH, 17 mΩ

Part Number

Manufacturer

Texas Instruments

Qty

LM20143

C_IN

GRM32ER60J476ME20

DO1813H-122ML

Murata

C_OUT

Murata

Coilcraft

R_PG

R_F

10 kΩ, 0603

CRCW06031002F-e3

CRCW06031R0J-e3

GRM188R71C104KA01

GRM188R60J105KA01

CRCW06031001F-e3

VJ0603Y472KXXA

Vishay-Dale

Murata

1 Ω, 0603

C_F

100 nF, 0603, X7R, 16 V

1 µF, 0603, X5R, 6.3 V

1 kΩ, 0603

C_VCC

R_C1

C_C1

C_SS

R_T

Murata

Vishay-Dale

Vishay-Vitramon

Vishay-Dale

4.7 nF, 0603, X7R, 25 V

33 nF, 0603, X7R, 25 V

49.9 kΩ, 0603

VJ0603Y333KXXA

CRCW06034992F-e3

CRCW06034991F-e3

CRCW06031002F-e3

R_FB1

R_FB2

4.99 kΩ, 0603

10 kΩ, 0603

8.2.1.2.1 Duty Cycle Calculation

The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with

the FETs and parasitic resistances it can be approximated with Equation 3.

V_OUT

D =

V_IN

(3)

The example design the typical duty cycle is calculated to be 66%.

8.2.1.2.2 Inductor Selection (L)

The inductor value is determined based on the operating frequency, load current, ripple current, and duty cycle.

To optimize the performance and prevent the device from entering current limit at maximum load, the inductance

is typically selected such that the ripple current, ΔiL, is between 25% and 50% of the rated output current. In

general, the inductor ripple current, Δi_L, should be greater than 10% of the rated output current to provide

adequate current sense information for the current mode control loop. Figure 33 illustrates the switch and

inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency, and desired ripple

current are known, the minimum value for the inductor can be calculated with Equation 4.

ë_hÜÇ∂(1-5)

f_{í∂0.ꢀ∂L_hÜÇ(max)

ë_hÜÇ∂(1-5)

f_{í∂0.2ꢀ∂L_hÜÇ(max)

Ç[ Ç

(4)

For the example design the calculated inductance is between .405 μH and 0.810 μH.

The inductor selected should have a saturation current rating greater than the peak current limit of the device

listed in the Electrical Characteristics table. Keep in mind the specified current limit does not account for delay of

the current limit comparator, therefore the current limit in the application may be higher than the specified value.

Peak current can be calculated using Equation 5. This value needs to be less than the part current limit

threshold. If needed, slightly smaller value inductors can be used, however, the peak inductor current should be

kept below the peak current limit of the device.

(ë - ë_hÜÇ)∂5

L_[(max)=L_hÜÇ

[∂f_{í

(5)

For the example design the peak inductor current is between 4.563 A and 6.125 A for the selected inductor ripple

current range.

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Due to exceeding current limit and adding flexibility to accommodate the entire output voltage range a inductance

of 1.2 μH was selected, resulting in a peak inductor current of 4.056 A.

Time

= I

OUT

L AVG

Time

Figure 33. Switch and Inductor Current Waveforms

8.2.1.2.3 Output Capacitor Selection (C_OUT

)

The output capacitor, C_OUT, filters the inductor ripple current and provides a source of charge for transient load

conditions. A wide range of output capacitors may be used with the LM20143 that provide excellent performance.

The best performance is typically obtained using ceramic, SP, or OSCON type chemistries. Typical trade-offs are

that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes,

while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading

conditions.

When selecting the value for the output capacitor the two performance characteristics to consider are the output

voltage ripple and transient response. The output voltage ripple can be approximated by using Equation 6.

DV_OUT= Di_Lx

R_ESR

8 x f_SWx C_OUT

where

•

ΔV_OUT(V) is the amount of peak to peak voltage ripple at the power supply output

R_ESR(Ω) is the series resistance of the output capacitor

f_SW(Hz) is the switching frequency

C_OUT(F) is the output capacitance used in the design

(6)

The amount of output ripple that can be tolerated is application specific; however a general recommendation is to

keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes

preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor

the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also

affect the output voltage droop during a load transient. The peak droop on the output voltage during a load

transient is dependent on many factors; however, an approximation of the transient droop ignoring loop

bandwidth can be obtained using Equation 7. Both the tolerance and voltage coefficient of the capacitor needs to

be examined when designing for a specific output ripple or transient drop target.

L x DI_OUTSTEP

V_DROOP= DI_OUTSTEPx R_ESR

C_OUTx (V_IN- V_OUT

)

where

•

C_OUT(F) is the minimum required output capacitance

L (H) is the value of the inductor

V_DROOP(V) is the output voltage drop ignoring loop bandwidth considerations

ΔI_OUTSTEP(A) is the load step change

R_ESR(Ω) is the output capacitor ESR

V_IN(V) is the input voltage

V_OUT(V) is the set regulator output voltage

(7)

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For the example design, a 47-µF ceramic capacitor is selected for the output capacitor to provide good transient

and DC performance in a relatively small package. From the technical specifications of this capacitor, the ESR is

roughly 3 mΩ, and the effective in-circuit capacitance is approximately 32 µF (reduced from 47 µF due to the 1.2

V DC bias). With these values, the peak-to-peak voltage ripple on the output when operating from a 5-V input

can be calculated to be 3 mV. A load transient from 1.5 A to 3 A is calculated to create a 27-mV droop.

8.2.1.2.4 Input Capacitor Selection (C_IN)

Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the

switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they

provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic

capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC

voltage derating that occurs on Y5V capacitors. For most applications, a 22-µF, X5R, 6.3-V input capacitor is

sufficient; however, additional capacitance may be required if the connection to the input supply is far from the

PVIN pins. The input capacitor should be placed as close as possible PVIN and PGND pins of the device.

Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good

approximation for the required ripple current rating is given by Equation 8.

I_IN-RMS= I_OUTD(1 - D)

(8)

As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty

cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output

current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance

capacitors to provide the best input filtering for the device.

For the example design the rated RMS current must be at least 1.5 A. A 47-µF ceramic capacitor provides the

necessary input capacitance for the evaluation board. For improved bypassing, a small 1-µF high frequency

capacitor is placed in parallel with the 47-µF bulk capacitor to filter high frequency noise pulses on the supply.

8.2.1.2.5 Setting the Output Voltage (R_FB1, R_FB2

)

The resistors R_FB1and R_FB2are selected to set the output voltage for the device. For most applications, R_FB1

should be between 4.99 kΩ to 49.9 kΩ.

V_OUT

x R_FB2

- 1

R_FB1

0.8

(9)

For the example design R_FB1= 4 kΩ and R_FB2= 10 kΩ to set the output voltage at 1.2 V.

Table 3 contains common output voltage values for R_FB1and R_FB2

Table 3. Suggested Values for R_FB1and R_FB2

R_FB1(kΩ)

short

4.99

R_FB2(kΩ)

open

V_OUT

0.8

1.2

1.5

1.8

2.5

3.3

8.87

10.2

12.7

10.2

21.5

10.2

31.6

10.2

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8.2.1.2.6 Adjusting the Operating Frequency (R_T)

The LM20143 supports a wide range of switching frequencies from 500 kHz to 1.5 MHz. The operating frequency

of the LM20143 can be adjusted by connecting a resistor from the RT pin to ground. The choice of switching

frequency is usually a compromise between efficiency and the size of the circuit. Lower switching frequency

implies reduced switching losses, usually resulting in higher overall efficiency. However, higher switching

frequency allows use of smaller inductor and output capacitor components, resulting in a smaller design. The

optimal switching frequency is usually a tradeoff in a given application and thus should be determined on a case-

by-case basis. For the design example a relatively high switching frequency was selected to minimize circuit size.

Equation 10 can be used to calculate the value of R_Tfor a given operating frequency.

154750

- 55

R_T=

f_SW

where

•

f_SWis the switching frequency in kHz

R_Tis the frequency adjust resistor in kΩ

(10)

Please refer to the curve Oscillator Frequency verses R_Tin the typical performance characteristics section. If the

R_Tresistor is omitted the device will not operate.

For the example design RT was calculated to be 49.9 kΩ to give a switching frequency of 1.5 MHz.

8.2.1.2.7 AVIN Filtering Components (C_Fand R_F)

To prevent high frequency noise spikes from disturbing the sensitive analog circuitry connected to the AVIN and

AGND pins, a high frequency RC filter is required between PVIN and AVIN. These components are shown in

Figure 32 as C_Fand R_F. The required value for R_Fis 1 Ω. C_Fmust be used. Recommended value of C_Fis 1.0

µF. The filter capacitor, C_Fshould be placed as close to the IC as possible with a direct connection from AVIN to

AGND. A good quality X5R or X7R ceramic capacitor should be used for C_F.

For the example design, R_F1 Ω and C_Fis 1.0 µF, providing greater than 16 dB of attenuation at the set 1.5-MHz

switching frequency.

8.2.1.2.8 Sub-Regulator Bypass Capacitor (C_VCC

)

The capacitor at the VCC pin provides noise filtering and stability for the internal sub-regulator. The

recommended value of C_VCCshould be no smaller than 1 µF and no greater than 10 µF. The capacitor should be

a good quality ceramic X5R or X7R capacitor. In general, a 1-µF ceramic capacitor is recommended for most

applications. In the example design, C_VCCis 1 µF.

8.2.1.2.9 Setting the Start Up Time (C_SS

)

The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will

reach the final regulated value. Larger values for CSS will result in longer start up times. While the Soft-Start

capacitor can be sized to meet many start up requirements, there are limitations to its size. The Soft-Start time

can never be faster than 1 ms due to the internal default 1-ms start up time. When the device is enabled there is

an approximate time interval of 50 μs when the Soft-Start capacitor will be discharged just prior to the Soft-Start

ramp. If the enable pin is rapidly pulsed or the Soft-Start capacitor is large there may not be enough time for CSS

to completely discharge resulting in start up times less than predicted. To aid in discharging of Soft-Start

capacitor during long disable periods an external 1-MΩ resistor from SS/TRK to ground can be used without

greatly affecting the start up time. Equation 11 can be used to calculate the desired soft start time. For the

LM20143, I_SSis nominally 5 µA, that may be found in the electrical characteristics table.

0.8ë∂/_{{

t_{{=

L_{{

(11)

For the example design the start-up time was set to be around 5ms resulting in a 33 nF capacitor.

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Table 4 shows values of C_SSfor some common start up times.

Table 4. Start Up Times for Different Soft-Start Capacitors

Start Up Time (ms)

C_SS(nF)

none

100

120

8.2.1.2.10 Loop Compensation (R_C1, C_C1

)

The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining

adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load, and the device

itself. Table 5 gives values for the compensation network that will result in a stable system when using a 100-µF,

6.3-V ceramic X5R output capacitor and 1-µH inductor.

Table 5. Recommended Compensation for C_OUT= 100 µF, L = 1 µH & f_SW= 1 MHz

V_IN

V_OUT

3.30

2.50

1.80

1.50

1.20

0.80

2.50

1.80

1.50

1.20

0.80

C_C1(nF)

4.7

R_C1(kΩ)

17.8

12.1

7.68

5.9

5.00

3.30

4.7

3.57

1.58

4.7

9.76

6.49

4.64

1.58

4.7

If the desired solution differs from those provided, the loop transfer function should be analyzed to optimize the

loop compensation. The overall loop transfer function is the product of the power stage and the feedback network

transfer functions. For stability purposes, the objective is to have a loop gain slope that is –20 db/decade from a

very low frequency to beyond the crossover frequency. Figure 34 shows the transfer functions for power stage,

feedback/compensation network, and the resulting closed loop system for the LM20143.

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Output Filter Pole, f

P(FIL)

0 dB

Output Filter Zero, f

Z(FIL)

Complex Double Pole, f

P(MOD)

Error Amp Pole, f

P1(EA)

Optional Error Amp

Pole, f

P2(EA)

0 dB

Error Amp Zero, f

Z(EA)

+ A

Error Amp Pole, f

P(EA)

0 dB

Complex Double Pole, f

P(MOD)

FREQUENCY (Hz)

Figure 34. LM20143 Loop Compensation

The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback

transfer function is set by the feedback resistor ratio, error amp gain, and external compensation network.

To achieve a –20 dB/decade slope, the error amplifier zero, located at f_Z(EA), should positioned to cancel the

output filter pole (f_P(FIL)). An additional error amp pole, located at f_P2(EA), can be added to cancel the output filter

zero at f_Z(FIL). Cancellation of the output filter zero is recommended if larger value, non-ceramic output capacitors

are used.

Compensation of the LM20143 is achieved by adding an RC network as shown in Figure 35.

LM20143

COMP

(optional)

Figure 35. Compensation Network for LM20143

A good starting value for C_C1for most applications is 4.7 nF. Once the value of C_C1is chosen the value of RC

should be calculated using Equation 12 to cancel the output filter pole (f_P(FIL)) as shown in Figure 34.

-1

15 x D

V_IN

C_C1

I_OUT

1-D

R_C1

C_OUT

V_OUT

f_SWx L

(12)

A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of

C_C1and recalculating the value of R_C1. Likewise, increasing C_C1and recalculating R_C1will provide additional

phase margin at a lower crossover frequency. As with any attempt to compensate the LM20143 the stability of

the system should be verified for desired transient droop and settling time.

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If the output filter zero, f_Z(FIL)approaches the crossover frequency (F_C), an additional capacitor (C_C2) should be

placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the

crossover frequency will occur before the double pole at f_SW/ 2 degrades the phase margin. The output filter

zero is set by the output capacitor value and ESR as shown in Equation 13.

f_Z(FIL)

2 x p x C_OUTx R_ESR

(13)

If needed, the value for C_C2should be calculated using Equation 14.

C_OUTx R_ESR

C_C2

R_C1

where

•

R_ESRis the output capacitor series resistance

R_C1is the calculated compensation resistance

(14)

For the example design R_C1is 1 kΩ, C_C1is 4.7 nF and C_C2is left open.

8.2.1.3 Application Curves

V_IN= 5 V

V_OUT= 1.2 V

I_OUT= 0.5 A to 3 A

V_IN= 5 V

V_OUT= 1.2 V

I_OUT= 3 A

Time Scale = 200 µs/div

Figure 37. Load Transient

Figure 36. Startup

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8.2.2 5-V Supply Rail Design

LM20143

PVIN

OUT

FB1

AVIN

OUT

FB2

PGOOD

VCC

R_T

COMP

SS/TRK

PGND GND

VCC

Figure 38. Typical Application Circuit

8.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 6 as the input parameters.

Table 6. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

5 V

3.3 V

750 kHz

3 A

Operating frequency

Output current rating

8.2.2.2 Detailed Design Procedure

Table 7 lists a selection of components using the design procedure explained in 3.3-V or 5-V Supply Rail Design

for a circuit design with the listed specifications.

Table 7. Bill of Materials

Designator

Description

Synchronous Buck Regulator

47 µF, 1210, X5R, 6.3 V

100 µF, 1210, X5R, 6.3 V

1.5 µH, 8.1 mΩ

Part Number

Manufacturer

Texas Instruments

Qty

LM20143

C_IN

GRM32ER60J476ME20

GRM32ER60J107ME20

MSS1038-152NL

Murata

C_OUT

Murata

Coilcraft

R_F

1 Ω, 0603

CRCW06031R0J-e3

GRM188R71C104KA01

GRM188R60J105KA01

CRCW06031002F-e3

VJ0603Y332KXXA

Vishay-Dale

Murata

C_F

100 nF, 0603, X7R, 16 V

1 µF, 0603, X5R, 6.3 V

10 kΩ, 0603

C_VCC

R_C1

C_C1

C_SS

R_T

Murata

Vishay-Dale

Vishay-Vitramon

Vishay-Dale

3.3 nF, 0603, X7R, 25 V

33 nF, 0603, X7R, 25 V

150 kΩ, 0603

VJ0603Y333KXXA

CRCW06031503F-e3

CRCW06033162F-e3

CRCW06031022F-e3

R_FB1

R_FB2

31.6 kΩ, 0603

10.2 kΩ, 0603

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8.2.3 3-V Supply Rail Design

LM20143

PVIN

OUT

FB1

AVIN

OUT

FB2

PGOOD

VCC

R_T

COMP

SS/TRK

PGND GND

VCC

Figure 39. Typical Application Circuit

8.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 8 as the input parameters.

Table 8. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

3.3 V

1.2 V

Operating frequency

Output current rating

750 kHz

3 A

8.2.3.2 Detailed Design Procedure

Table 9 lists a selection of components using the design procedure explained in 3.3-V or 5-V Supply Rail Design

for a circuit design with the listed specifications.

Table 9. Bill of Materials

Designator

Description

Synchronous Buck Regulator

47 µF, 1210, X5R, 6.3 V

100 µF, 1210, X5R, 6.3 V

1.2 µH, 17 mΩ

Part Number

Manufacturer

Texas Instruments

Qty

LM20143

C_IN

GRM32ER60J476ME20

GRM32ER60J107ME20

DO1813H-122ML

Murata

C_OUT

Murata

Coilcraft

R_F

1 Ω, 0603

CRCW06031R0J-e3

GRM188R71C104KA01

GRM188R60J105KA01

CRCW06032001F-e3

VJ0603Y472KXXA

Vishay-Dale

Murata

C_F

100 nF, 0603, X7R, 16 V

1 µF, 0603, X5R, 6.3 V

2 kΩ, 0603

C_VCC

R_C1

C_C1

C_SS

R_T

Murata

Vishay-Dale

Vishay-Vitramon

Vishay-Dale

4.7 nF, 0603, X7R, 25 V

33 nF, 0603, X7R, 25 V

150 kΩ, 0603

VJ0603Y333KXXA

CRCW06031503F-e3

CRCW06034991F-e3

CRCW06031002F-e3

R_FB1

R_FB2

4.99 kΩ, 0603

10 kΩ, 0603

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LM20143, LM20143-Q1

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SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

9 Power Supply Recommendations

The LM20143 converter is designed to operate from either a 3.3-V or 5-V rail. The input supply must be

compatible with the Absolute Maximum Ratings and Recommended Operating Conditions. Further more the

input supply must be able to supply the required average input current to the regulated load. The average input

current can be estimated with Equation 15.

C_OUTx R_ESR

C_C2

R_C1

where

•

η is efficiency

(15)

If the regulator is connected to the input supply through long wires or PCB traces with large impedance, special

care is required to achieve good performance. The parasitic inductance and resistance of the input cables may

have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low

ESR ceramic input capacitors, can form an under-damped resonant circuit. This circuit may cause overvoltage

transients at the PVIN pin each time the input supply is cycled on and off. The parasitic resistance causes the

PVIN voltage to dip when the load on the regulator is switched on or exhibits a transient. If the regulator is

operating close to the minimum input voltage, this dip may cause false UVLO fault triggering and system reset.

The best way to solve these types of issues is to reduce the distance from the input supply to the regulator

and/or use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the

electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A value in the

range of 20 μF to 100 μF is usually sufficient to provide input damping and help to hold the input voltage steady

during large load transients.

Sometimes, an EMI input filter is used in front of the regulator. This can lead to instability, as well as some of the

effects mentioned above, unless it is carefully designed. The user guide Simple Success with Conducted EMI for

DC-DC Converters, SNVA489, provides helpful suggestions when designing an input filter for any switching

regulator.

10 Layout

10.1 Layout Guidelines

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched

very fast. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to

the inductor then out to the output capacitor and load. The second loop starts from the output capacitor

ground, to the regulator PGND pins, to the inductor and then out to the load (see Figure 40). To minimize

both loop areas the input capacitor should be placed as close as possible to the PVIN pin. Grounding for

both the input and output capacitor should consist of a small localized top side plane that connects to PGND

and the die attach pad (DAP). The inductor should be placed as close as possible to the SW pin and output

capacitor.

2. Minimize the copper area of the switch node. Since the LM20143 has the SW pins on opposite sides of the

package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each

SW pin. The SW pins should be directly connected with a trace that runs across the bottom of the package.

To minimize IR losses this trace should be no smaller that 50 mils wide, but no larger than 100 mils wide to

keep the copper area to a minimum. In general the SW pins should not be connected on the top layer since it

could block the ground return path for the power ground. The inductor should be placed as close as possible

to one of the SW pins to further minimize the copper area of the switch node.

3. Have a single point ground for all device analog grounds located under the DAP. The ground connections for

the compensation, feedback, and Soft-Start components should be connected together then routed to the

AGND pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any

switched or load currents from flowing in the analog ground plane. If not properly handled poor grounding

can result in degraded load regulation or erratic switching behavior.

Submit Documentation Feedback

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LM20143, LM20143-Q1

SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

www.ti.com

Layout Guidelines (continued)

4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the

output resistor divider to FB pin should be as short as possible. This is most important when high value

resistors are used to set the output voltage. The feedback trace should be routed away from the SW pin and

inductor to avoid contaminating the feedback signal with switch noise.

5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure

feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide

the best output accuracy.

6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power

plane heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See Thermal

Considerations section to insure enough copper heatsinking area is used to keep the junction temperature

below 125°C.

LM20143

PVIN

OUT

PGND

LOOP1

LOOP2

Figure 40. Schematic of LM20143 Highlighting Layout Sensitive Nodes

10.2 Layout Example

AGND

R_T

C_SS

R_FB2

C_C1

C_C2

SS/TRK

R_FB1

AGND

R_F

R_PG

R_C1

C_F

AVIN

VCC

PGOOD

COMP

V_PGOOD

C_VCC

V_IN

V_EN

PVIN

PGND

PVIN

PGND

C_IN

GND

ëia to Db5

ëia to ëhÜÇ

ëia to ꢀDhh5

ëia to {í

C_OUT

GND

V_OUT

Figure 41. Example Layout

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Product Folder Links: LM20143 LM20143-Q1

LM20143, LM20143-Q1

www.ti.com

SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

10.3 Thermal Considerations

The thermal characteristics of the LM20143 are specified using the parameter θ_JA, which relates the junction

temperature to the ambient temperature. Although the value of θ_JAis dependant on many variables, it still can be

used to approximate the operating junction temperature of the device.

To obtain an estimate of the device junction temperature, one may use Equation 16 and Equation 17.

T_J= P_Dθ_JA+ T_A

(16)

P_D= P_INx (1 - Efficiency) - 1.1 x I_OUT2 x DCR

where

•

T_Jis the junction temperature in °C

P_INis the input power in Watts (P_IN= V_INx I_IN)

θ_JAis the junction to ambient thermal resistance for the LM20143

T_Ais the ambient temperature in °C

I_OUTis the output load current

DCR is the inductor series resistance

(17)

It is important to always keep the operating junction temperature (T_J) below 125°C for reliable operation. If the

junction temperature exceeds 160°C the device will cycle in and out of thermal shutdown. If thermal shutdown

occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device.

Figure 42 provides a better approximation of the θ_JAfor a given PCB copper area. The PCB heatsink area

consists of 2 oz. copper located on the bottom layer of the PCB directly under the HTSSOP exposed pad. The

bottom copper area is connected to the HTSSOP exposed pad by means of a 4 x 4 array of 12 mil thermal vias.

Figure 42. Thermal Resistance vs PCB Area

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Product Folder Links: LM20143 LM20143-Q1

LM20143, LM20143-Q1

SNVS528H –OCTOBER 2007–REVISED JANUARY 2016

www.ti.com

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

LM20143 Quickstart Design Tool, http://www.ti.com/tool/lm20143design-calc

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

AN-1691 LM20143 Evaluation Board, SNVA277

AN-2162: Simple Success with Conducted EMI from DC-DC Converters, SNVA489

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 10. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

LM20143

Click here

LM20143-Q1

11.4 Trademarks

PowerWise is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Documentation Feedback

Product Folder Links: LM20143 LM20143-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM20143MH/NOPB

LM20143MHE/NOPB

LM20143MHX/NOPB

LM20143QMH/NOPB

LM20143QMHE/NOPB

LM20143QMHX/NOPB

ACTIVE

HTSSOP

PWP

RoHS & Green

Level-1-260C-UNLIM

-40 to 125

20143

ACTIVE

PWP

250

20143

PWP

2500 RoHS & Green

20143

PWP

RoHS & Green

20143

QMH

PWP

250

20143

QMH

PWP

2500 RoHS & Green

20143

QMH

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM20143, LM20143-Q1 :

Catalog: LM20143

•

Automotive: LM20143-Q1

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM20143MHE/NOPB

LM20143MHX/NOPB

HTSSOP PWP

250

2500

250

178.0

330.0

178.0

330.0

12.4

6.95

5.6

1.6

8.0

12.0

LM20143QMHE/NOPB HTSSOP PWP

LM20143QMHX/NOPB HTSSOP PWP

2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM20143MHE/NOPB

LM20143MHX/NOPB

LM20143QMHE/NOPB

LM20143QMHX/NOPB

HTSSOP

PWP

250

2500

250

210.0

367.0

210.0

367.0

185.0

367.0

185.0

367.0

35.0

2500

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

LM20143MH/NOPB

LM20143QMH/NOPB

PWP

HTSSOP

495

2514.6

4.06

Pack Materials-Page 3

PACKAGE OUTLINE

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

0.1 C

14X 0.65

5.1

4.9

4.55

NOTE 3

0.30

16X

0.19

4.5

4.3

0.1

C A B

(0.15) TYP

SEE DETAIL A

4X 0.166 MAX

NOTE 5

2X 1.34 MAX

NOTE 5

THERMAL

PAD

0.25

GAGE PLANE

3.3

2.7

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

TYPICAL

(1)

3.3

2.7

4214868/A 02/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(3.3)

16X (1.5)

SYMM

SEE DETAILS

16X (0.45)

(1.1)

TYP

SYMM

(3.3)

(5)

NOTE 9

14X (0.65)

(

0.2) TYP

VIA

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-16

4214868/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.3)

BASED ON

0.125 THICK

STENCIL

16X (1.5)

(R0.05) TYP

16X (0.45)

(3.3)

SYMM

BASED ON

0.125 THICK

STENCIL

14X (0.65)

SYMM

(5.8)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.69 X 3.69

3.3 X 3.3 (SHOWN)

3.01 X 3.01

0.125

0.15

0.175

2.79 X 2.79

4214868/A 02/2017

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LM20143 [TI]

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