LM20242 [TI]
4.5-36V 2A 电流模式可调频率同步降压稳压器;
| 型号： | LM20242 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5-36V 2A 电流模式可调频率同步降压稳压器 稳压器 |
| 文件： | 总30页 (文件大小：1264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM20242
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SNVS534E –OCTOBER 2007–REVISED MARCH 2013
LM20242 36V, 2A PowerWise® Adjustable Frequency Synchronous Buck Regulator
Check for Samples: LM20242
1
FEATURES
DESCRIPTION
The LM20242 is a full featured 1MHz capable
synchronous buck regulator capable of delivering up
to 2A of load current. The current mode control loop
is externally compensated with only two external
components, offering both high performance and
ease of use. The device is optimized to work over the
input voltage range of 4.5V to 36V making it well
suited for high voltage systems.
23
•
2A Output Current, 3.7A Peak Current
130 mΩ/110 mΩ Integrated Power MOSFETs
1.5% Output Voltage Accuracy
•
•
•
Current Mode Control, Selectable
Compensation
•
Resistor Programmed, 1MHz Capable
Oscillator
The device features internal Over Voltage Protection
(OVP) and Over Current Protection (OCP) circuits for
increased system reliability. A precision Enable pin
and integrated UVLO allows the turn on of the device
to be tightly controlled and sequenced. Startup inrush
currents are limited by both an internally fixed and
externally adjustable soft-start circuit. Fault detection
and supply sequencing are possible with the
integrated PGOOD circuit.
•
•
•
•
Synchronous Rectifier with Diode Emulation
Adjustable Output Voltage Down to 0.8V
Compatible with Pre-Biased Loads
Programmable Soft-Start With External
Capacitor
•
•
•
Precision Enable Pin with Hysteresis
OVP, UVLO Inputs and PGOOD Output
Internally Protected with Peak Current Limit,
Thermal Shutdown and Restart
The LM20242 is designed to work well in multi-rail
power supply architectures. The output voltage of the
device can be configured to track a higher voltage rail
using the SS/TRK pin. If the output of the LM20242 is
pre-biased at startup it will not sink current to pull the
output low until the internal soft-start ramp exceeds
the voltage at the feedback pin.
•
Accurate Current Limit with Frequency
Foldback
•
•
Non-Linear Current Mode Slope Compensation
HTSSOP Exposed Pad Package
The LM20242 is offered in an exposed pad 20 pin
HTSSOP package that can be soldered to the PCB,
eliminating the need for bulky heatsinks.
APPLICATIONS
•
•
•
Simple to Design, High Efficiency Point of
Load Regulation from a 4.5V to 36V Bus
High Performance DSPs, FPGAs, ASICs and
Microprocessors
Communications Infrastructure, Automotive
Simplified Application Circuit
LM20242
BOOT
L
V
SW
V
IN
VIN
EN
OUT
R
FB1
C
IN
FB
C
OUT
R
FB2
PGOOD
RT
COMP
R
RT
R
C1
SS/TRK
AGND
VCC
GND
C
VCC
C
C1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerWise is a registered trademark of Deere and Company.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LM20242
SNVS534E –OCTOBER 2007–REVISED MARCH 2013
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Connection Diagram
SS/TRK
FB
1
2
3
4
5
6
7
8
9
20 RT
19 EN
PGOOD
COMP
VIN
18 VCC
17 BOOT
16 VIN
15 VIN
14 SW
13 SW
12 AGND
11 GND
EP
VIN
SW
SW
GND
GND 10
Figure 1. Top View
HTSSOP Package
PIN DESCRIPTIONS
Pin(s)
Name
Description
Application Information
1
SS/TRK Soft-Start or Tracking control input
An internal 5 µA current source charges an external capacitor to set the
soft-start rate. The PWM can Track to an external voltage ramp with a
low impedance source. If left open, an internal 1 ms SS ramp is
activated.
2
3
4
FB
Feedback input to the error amplifier
from the regulated output
This pin is connected to the inverting input of the internal
transconductance error amplifier. An 800 mV reference is internally
connected to the non-inverting input of the error amplifier.
PGOOD Power good output signal
Open drain output indicating the output voltage is regulating within
tolerance. A pull-up resistor of 10 kΩ to 100 kΩ is recommended if this
function is used.
COMP
Output of the internal error amplifier and The loop compensation network should be connected between the
input to the Pulse Width Modulator
Input supply voltage
Switch pin
COMP pin and the AGND pin.
5,6,15,16
7,8,13,14
VIN
SW
Nominal operating range: 4.5V to 36V.
The drain terminal of the internal Synchronous Rectifier power
NMOSFET and the source terminal of the internal Control power
NMOSFET.
9,10,11
12
GND
AGND
BOOT
Ground
Internal reference for the power MOSFETs.
Analog ground
Internal reference for the regulator control functions.
17
Boost input for bootstrap capacitor
An internal diode from VCC to BOOT charges an external capacitor
required from SW to BOOT to power the Control MOSFET gate driver.
18
19
VCC
EN
Output of the high voltage linear
regulator. The VCC voltage is regulated to approximately 5.5 Volts. A 0.1 µF to 1 µF ceramic decoupling
to approximately 5.5V.
VCC tracks VIN up to about 7.2V. Above VIN = 7.2V, VCC is regulated
capacitor is required. The VCC pin is an output only.
Enable or UVLO input
An external voltage divider can be used to set the line undervoltage
lockout threshold. If the EN pin is left unconnected, a 2 µA pull-up
current source pulls the EN pin high to enable the regulator.
20
RT
Internal oscillator frequency adjust input Normally biased at 550 mV. An external resistor connected between RT
and AGND sets the internal oscillator frequency.
EP
Exposed Exposed pad
Pad
Exposed metal pad on the underside of the package with a weak
electrical connection to GND. Connect this pad to the PC board ground
plane in order to improve heat dissipation.
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
ABSOLUTE MAXIMUM RATINGS
VIN to GND
-0.3V to +38V
-0.3V to +43V
-0.3V to +7V
BOOT to GND
BOOT to SW
SW to GND
-0.5V to +38V
-1.5V (< 20 ns)
-0.3V to +6V
SW to GND (Transient)
FB, EN, SS/TRK, PGOOD to GND
VCC to GND
-0.3V to +8V
Storage Temperature
-65°C to 150°C
ESD Rating
(2)
Human Body Model
2kV
(1) Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin.
OPERATING RATINGS
VIN to GND
+4.5V to +36V
−40°C to + 125°C
Junction Temperature
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ = 25°C only, limits in
bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C,
and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VFB
Feedback pin voltage
VVIN = 4.5V to 36V
0.788
0.8
0.812
V
VCOMP = 500 mV to 700 mV
RHSW-DS(ON) High-Side MOSFET On-Resistance
ISW = 200 mA
ISW = 200 mA
VVIN = 4.5V to 36V
VEN = 0V
130
110
2
225
190
3
mΩ
mΩ
mA
µA
V
RLSW-DS(ON)
IQ
Low-Side MOSFET On-Resistance
Operating Quiescent Current
Shutdown Quiescent current
VIN Under Voltage Lockout
VIN Under Voltage Lockout Hysteresis
VCC Voltage
ISD
150
3.9
200
5.5
5
180
4.2
400
VUVLO
Rising VVIN
3.65
3
VUVLO(HYS)
VVCC
mV
V
IVCC = -5 mA, VEN = 5V
VSS = 0V
ISS
Soft-Start Pin Source Current
BOOT Diode Leakage
7
µA
nA
V
IBOOT
VBOOT = 4V
10
VF-BOOT
Powergood
VFB(OVP)
BOOT Diode Forward Voltage
IBOOT = -100 mA
0.9
1.1
Over Voltage Protection Rising Threshold
VFB(OVP) / VFB
ΔVFB(OVP) / VFB
VFB(PG) / VFB
ΔVFB(PG) / VFB
107
93
110
2
112
3
%
%
VFB(OVP-HYS) Over Voltage Protection Hysteresis
VFB(PG)
VFB(PG-HYS)
TPGOOD
PGOOD Rising Threshold
PGOOD Hysteresis
95
2
97
3
%
%
PGOOD delay
20
1
µs
mA
nA
IPGOOD(SNK)
IPGOOD(SRC)
PGOOD Low Sink Current
PGOOD High Leakage Current
VPGOOD = 0.5V
VPGOOD = 5V
0.6
5
200
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ = 25°C only, limits in
bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C,
and are provided for reference purposes only.
Symbol
Oscillator
FSW1
Parameter
Conditions
Min
Typ
Max
Units
Switching Frequency 1
Switching Frequency 2
Maximum Duty Cycle
RT pin voltage
RRT = 49.9 kΩ
RRT = 249 kΩ
ILOAD = 0A
675
225
750
250
90
825
325
kHz
kHz
%
FSW2
DMAX
VRT
RRT = 250 kΩ
550
mV
Error Amplifier
IFB
Feedback pin bias current
VFB = 1V
50
nA
µA
ICOMP(SRC)
COMP Output Source Current
VFB = 0V
VCOMP = 0V
200
200
400
400
ICOMP(SNK)
COMP Output Sink Current
VFB = 1V
VCOMP = 0.5V
350
µA
gm
AVOL
Error Amplifier DC Transconductance
Error Amplifier Voltage Gain
ICOMP = -50 µA to +50 µA
COMP pin open
515
2000
7
600
µmho
V/V
GBW
Error Amplifier Gain-Bandwidth Product
COMP pin open
MHz
Current Limit
ILIM
Cycle By Cycle Current Limit
3.1
1.2
3.7
4.65
1.3
A
TILIM
Cycle By Cycle Current Limit Delay
150
ns
Enable
VEN(RISING)
VEN(HYS)
IEN
EN Pin Rising Threshold
EN Pin Hysteresis
1.25
50
2
V
mV
µA
EN Source Current
VEN = 0V, VVIN = 12V
Thermal Shutdown
TSD
Thermal Shutdown
Thermal Shutdown Hysteresis
170
20
°C
°C
TSD(HYS)
Thermal Resistance
θJC
θJA
Junction to Case
Junction to Ambient
5.6
30
°C/W
°C/W
0 LFM airflow
4
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TJ = 25°C, VVIN = 12V.
Efficiency vs. Load Current
fSW = 350 kHz, VOUT = 3.3V
Efficiency vs. Load Current
fSW = 500 kHz, VOUT = 3.3V
Figure 2.
Figure 3.
Error Amplifier Gain
Error Amplifier Phase
Figure 4.
Figure 5.
Line Regulation
VCC vs. VIN
Figure 6.
Figure 7.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, VVIN = 12V.
Non-Switching IQ vs. VIN
Shutdown IQ vs. VIN
PGOOD VOL vs. IPGOOD
EN Threshold and Hysteresis vs. Temperature
EN Current vs. Temperature
Oscillator Frequency vs. RRT
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, VVIN = 12V.
Oscillator Frequency vs. VIN
High-Side FET Resistance vs. Temperature
Low-Side FET Resistance vs. Temperature
Startup with CSS = 0
Load Transient Response
Peak Current Limit vs. Temperature
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, VVIN = 12V.
Startup with CSS = 200 nF
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Block Diagram
BOOT
BOOT
VCC
+5.5V
REGULATOR
VIN
VCC
2.7V
UVLO
+
-
3.9V
+2.7V
REGULATOR
SLOPE COMP
COMP
2.7V
CURRENT SENSE
+
5 mA
DISCHARGE
ERROR AMP
SS/TRK
FB
g
= 515 mmho
m
+
DISCHARGE
CURRENT LIMIT
-
BOOT
+
-
+
3.7A
VREF
800 mV
+
-
+
-
PWM COMPARATOR
DIODE EMULATION
+
+
-
OVERVOLTAGE
PG-L
UNDERVOLTAGE
-
-58 mV
880 mV
CONTROL
LOGIC
SW
740 mV
+
-
VCC
VCC
THERMAL
PROTECTION
2 mA
+
-
1.25V
EN
OSCILLATOR
GND
RT
PGOOD
PG-L
AGND
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OPERATION DESCRIPTION
GENERAL
The LM20242 switching regulator features all of the functions necessary to implement an efficient low voltage
buck regulator using a minimum number of external components. This easy to use regulator features two
integrated switches and is capable of supplying up to 2A of continuous output current. The regulator utilizes peak
current mode control with nonlinear slope compensation to optimize stability and transient response over the
entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-cycle
current limiting and easy loop compensation. The switching frequency can be varied from 100 kHz to 1 MHz with
an external resistor to ground. The device can operate at high switching frequency allowing use of a small
inductor while still achieving efficiencies as high as 93%. The precision internal voltage reference allows the
output to be set as low as 0.8V. Fault protection features include: current limiting, thermal shutdown, over voltage
protection, and shutdown capability. The device is available in the HTSSOP package featuring an exposed pad
to aid thermal dissipation. The typical application circuit for the LM20242 is shown in Figure 9 in the design
guide.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.
This pin is a precision analog input that enables the device when the voltage exceeds 1.25V (typical). The EN pin
has 50 mV of hysteresis and will disable the output when the enable voltage falls below 1.2V (typical). If the EN
pin is not used, it should be disconnected so the internal 2 µA pull-up will default this function to the enabled
condition. Since the enable pin has a precise turn-on threshold it can be used along with an external resistor
divider network from VIN to configure the device to turn-on at a precise input voltage. The precision enable
circuitry will remain active even when the device is disabled.
PEAK CURRENT MODE CONTROL
In most cases, the peak current mode control architecture used in the LM20242 only requires two external
components to achieve a stable design. The compensation can be selected to accommodate any capacitor type
or value. The external compensation also allows the user to set the crossover frequency and optimize the
transient performance of the device.
For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to
avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What
makes the LM20242 unique is the amount of slope compensation will change depending on the output voltage.
When operating at high output voltages the device will have more slope compensation than when operating at
lower output voltages. This is accomplished in the LM20242 by using a non-linear parabolic ramp for the slope
compensation. The parabolic slope compensation of the LM20242 is much better than the traditional linear slope
compensation because it optimizes the stability of the device over the entire output voltage range.
CURRENT LIMIT
The precise current limit enables the device to operate with smaller inductors that have lower saturation currents.
When the peak inductor current reaches the current limit threshold, an over current event is triggered and the
internal high-side FET turns off and the low-side FET turns on, allowing the inductor current to ramp down until
the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM
pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events,
while at the same time providing frequency and voltage foldback protection during hard short circuit conditions.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to set the startup time or track an external voltage
source. The startup or soft-start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground.
The soft-start feature allows the regulator output to gradually reach the steady state operating point, thus
reducing stresses on the input supply and controlling startup current. If no soft-start capacitor is used the device
defaults to the internal soft-start circuitry resulting in a startup time of approximately 1 ms. For applications that
require a monotonic startup or utilize the PGOOD pin, an external soft-start capacitor is recommended. The
SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two
external resistors connected to the SS/TRK pin as shown in Figure 14 in the design guide.
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PRE-BIAS STARTUP CAPABILITY
The LM20242 is in a pre-biased state when it starts up with an output voltage greater than zero. This often
occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the
output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the
LM20242 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. During start
up the LM20242 will not sink current until the soft-start voltage exceeds the voltage on the FB pin. Since the
device cannot sink current, it protects the load from damage that might otherwise occur if current is conducted
through the parasitic paths of the load.
POWER GOOD AND OVER VOLTAGE FAULT HANDLING
The LM20242 has built in under and over voltage comparators that control the power switches. Whenever there
is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn-
on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage
falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output
reaches the UVP threshold the part will continue switching and the PGOOD pin will be deasserted and go low.
Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient
glitches the PGOOD pin has 20 µs of built in deglitch time to both rising and falling edges.
UVLO
The LM20242 has an internal under-voltage lockout protection circuit that keeps the device from switching until
the input voltage reaches 3.9V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device
from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed
by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 13 in the
design guide.
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When activated, typically at 170°C, the LM20242 tri-states the power FETs
and resets soft-start. After the junction cools to approximately 150°C, the part starts up using the normal start up
routine. This feature is provided to prevent catastrophic failures from accidental device overheating.
LIGHT LOAD OPERATION
The LM20242 offers increased efficiency when operating at light loads. Whenever the load current is reduced to
a point where the peak to peak inductor ripple current is greater than two times the load current, the part will
enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is
the critical conduction boundary and can be calculated by Equation 1:
(VIN œ VOUT) x D
IBOUNDARY
=
2 x L x fSW
(1)
Several diagrams are shown in Figure 8 illustrating continuous conduction mode (CCM), discontinuous
conduction mode, and the boundary condition.
It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will
become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor
and the parasitic capacitance. If this ringing is of concern, an additional RC snubber circuit can be added from
the switch node to ground.
At very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively
reducing the switching frequency and further improving light-load efficiency.
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Continuous Conduction Mode (CCM)
V
IN
Time (s)
Continuous Conduction Mode (CCM)
I
AVERAGE
Time (s)
DCM - CCM Boundary
I
AVERAGE
Time (s)
Discontinuous Conduction Mode (DCM)
V
IN
Time (s)
Discontinuous Conduction Mode (DCM)
I
Peak
Time (s)
Figure 8. Modes of Operation for LM20242
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DESIGN GUIDE
This section walks the designer through the steps necessary to select the external components to build a fully
functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design
for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion.
To facilitate component selection discussions the circuit shown in Figure 9 below may be used as a reference.
Unless otherwise indicated all formulas assume units of amps (A) for current, farads (F) for capacitance, henries
(H) for inductance and volts (V) for voltages.
LM20242
BOOT
L
C
BOOT
V
V
IN
SW
VIN
EN
OUT
D2
D1
R
FB1
C
IN
C
OUT
FB
RT
R
FB2
PGOOD
COMP
R
RT
R
C1
VCC
GND
SS/TRK
AGND
C
VCC
C
C1
C
SS
Figure 9. Typical Application Circuit
The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with
the FETs and parasitic resistances it can be approximated by:
VOUT
D =
VIN
(2)
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INDUCTOR SELECTION (L)
The inductor value is determined based on the operating frequency, load current, ripple current and duty cycle.
The inductor selected should have a saturation current rating greater than the peak current limit of the device.
Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the
current limit in the application may be higher than the specified value. To optimize the performance and prevent
the device from entering current limit at maximum load, the inductance is typically selected such that the ripple
current, ΔiL, is not greater than 30% of the rated output current. Figure 10 illustrates the switch and inductor
ripple current waveforms. Once the input voltage, output voltage, operating frequency and desired ripple current
are known, the minimum value for the inductor can be calculated by the formula shown below:
(VIN - VOUT) x D
LMIN
=
DiL x f
SW
(3)
V
SW
V
IN
Time
I
L
I
= I
OUT
DI
L
L AVG
Time
Figure 10. Switch and Inductor Current Waveforms
If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT + ΔiL/2, should
be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be more
than 10% of the rated output current to provide adequate current sense information for the current mode control
loop. If the ripple current in the inductor is too low, the control loop will not have sufficient current sense
information and can be prone to instability.
OUTPUT CAPACITOR SELECTION (COUT
)
The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load
conditions. A wide range of output capacitors may be used with the LM20242 that provide excellent performance.
The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical trade-offs are
that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes,
while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading
conditions.
When selecting the value for the output capacitor, the two performance characteristics to consider are the output
voltage ripple and transient response. The output voltage ripple can be approximated by using the following
formula.
1
DVOUT = DiL x
RESR
+
8 x fSW x COUT
(4)
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Where, ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output, RESR (Ω) is the series
resistance of the output capacitor, fSW(Hz) is the switching frequency, and COUT (F) is the output capacitance
used in the design. The amount of output ripple that can be tolerated is application specific; however a general
recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic
capacitors are sometimes preferred because they have very low ESR; however, depending on package and
voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output
capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output
voltage during a load transient is dependent on many factors; however, an approximation of the transient droop
ignoring loop bandwidth can be obtained using Equation 5.
2
L x DIOUTSTEP
VDROOP = DIOUTSTEP x RESR
+
COUT x (VIN - VOUT
)
(5)
Where, COUT (F) is the minimum required output capacitance, L (H) is the value of the inductor, VDROOP (V) is the
output voltage drop ignoring loop bandwidth considerations, ΔIOUTSTEP (A) is the load step change, RESR (Ω) is
the output capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is the set regulator output voltage. Both the
tolerance and voltage coefficient of the capacitor should be examined when designing for a specific output ripple
or transient droop target.
INPUT CAPACITOR SELECTION
Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the
switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they
provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic
capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC
voltage derating that occurs on Y5V capacitors. The input capacitors should be placed as close as possible to
the VIN and GND pins on both sides of the device.
Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good
approximation for the required ripple current rating is given by the relationship:
IIN-RMS = IOUT D(1 - D)
(6)
As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty
cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output
current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance
capacitors to provide the best input filtering for the device.
SETTING THE OUTPUT VOLTAGE (RFB1, RFB2
)
The resistors RFB1 and RFB2 are selected to set the output voltage for the device. Table 1 provides suggestions
for RFB1 and RFB2 for common output voltages.
Table 1. Suggested Values for RFB1 and RFB2
RFB1(kΩ)
short
4.99
RFB2(kΩ)
open
10
VOUT
0.8
1.2
1.5
1.8
2.5
3.3
8.87
10.2
12.7
10.2
21.5
10.2
31.6
10.2
If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can
be calculated using Equation 7.
VOUT
x RFB2
- 1
RFB1
=
0.8
(7)
15
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ADJUSTING THE OPERATING FREQUENCY (RRT)
The operating frequency of the LM20242 can be adjusted by connecting a resistor from the RT pin to ground.
Equation 8 can be used to calculate the value of RRT for a given operating frequency.
82000
- 56
RRT
=
fSW
(8)
Where, fSW is the switching frequency in kHz, and RRT is the frequency adjust resistor in kΩ. Please refer to the
curve Oscillator Frequency versus RRT in the typical performance characteristics section. If the RRT resistor is
omitted the device will not operate.
LOOP COMPENSATION (RC1, CC1)
The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining
adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load and the device
itself.
The overall loop transfer function is the product of the power stage and the feedback network transfer functions.
For stability purposes, the objective is to have a loop gain slope that is -20db/decade from a very low frequency
to beyond the crossover frequency. Figure 11 shows the transfer functions for power stage,
feedback/compensation network, and the resulting closed loop system for the LM20242.
Output Filter Pole, f
P(FIL)
A
M
0 dB
Output Filter Zero, f
Z(FIL)
Complex Double Pole, f
P(MOD)
Error Amp Pole, f
P1(EA)
A
EA
Optional Error Amp
Pole, f
P2(EA)
0 dB
Error Amp Zero, f
Z(EA)
A
EA
+ A
M
Error Amp Pole, f
P(EA)
0 dB
Complex Double Pole, f
P(MOD)
f
f
/2
C
SW
FREQUENCY (Hz)
Figure 11. LM20242 Loop Compensation
The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback
transfer function is set by the feedback resistor ratio, error amp gain and external compensation network.
To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should be positioned to cancel the
output filter pole (fP(FIL)). An additional error amp pole, located at fP2(EA), can be added to cancel the output filter
zero at fZ(FIL). Cancellation of the output filter zero is recommended if larger value, non-ceramic output capacitors
are used.
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Compensation of the LM20242 is achieved by adding an RC network as shown in Figure 12.
LM20242
COMP
R
C
C1
C
C2
(optional)
C1
Figure 12. Compensation Network for LM20242
A good starting value for CC1 for most applications is 4.7 nF. Once the value of CC1 is chosen the value of RC
should be calculated using Equation 9 to cancel the output filter pole (fP(FIL)) as shown in Figure 11.
-1
2.84 x D
VIN
CC1
IOUT
1-D
x
+
+
RC1
=
COUT
VOUT
fSW x L
(9)
A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of
CC1 and recalculating the value of RC1. Likewise, increasing CC1 and recalculating RC1 will provide additional
phase margin at a lower crossover frequency. As with any attempt to compensate the LM20242 the stability of
the system should be verified for desired transient droop and settling time.
If the output filter zero, fZ(FIL) approaches the crossover frequency (FC), an additional capacitor (CC2) should be
placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the
crossover frequency will occur before the double pole at fSW/2 degrades the phase margin. The output filter zero
is set by the output capacitor value and ESR as shown in Equation 10.
1
fZ(FIL)
=
2 x p x COUT x RESR
(10)
If needed, the value for CC2 should be calculated using Equation 11.
COUT x RESR
CC2
=
RC1
(11)
Where RESR is the output capacitor series resistance and RC1 is the calculated compensation resistance.
BOOT CAPACITOR (CBOOT
)
The LM20242 integrates an N-Channel buck switch and associated floating high voltage level shift / gate driver.
This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1 µF
ceramic capacitor, connected with short traces between the BOOT pin and SW pin, is recommended. During the
off-time of the buck switch, the SW pin voltage is approximately 0V and the bootstrap capacitor is charged from
VCC through the internal bootstrap diode.
SUB-REGULATOR BYPASS CAPACITOR (CVCC
)
The capacitor at the VCC pin provides noise filtering for the internal sub-regulator. The recommended value of
CVCC should be no smaller than 0.1 µF and no greater than 1 µF. The capacitor should be a good quality ceramic
X5R or X7R capacitor. In general, a 1 µF ceramic capacitor is recommended for most applications. The VCC
regulator should not be used for other functions since it isn't protected against short circuit.
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SETTING THE START UP TIME (CSS)
The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will
reach the final regulated value. Larger values for CSS will result in longer start up times. Table 2 provides a list of
soft start capacitors and the corresponding typical start up times.
Table 2. Start Up Times for Different Soft-Start Capacitors
Start Up Time (ms)
CSS (nF)
none
33
1
5
10
15
20
68
100
120
If different start up times are needed Equation 12 can be used to calculate the start up time.
0.8V x CSS
tSS
=
ISS
(12)
As shown above, the start up time is influenced by the value of the soft-start capacitor CSS(F) and the 5 µA soft-
start pin current ISS(A). that may be found in the Electrical Characteristics table.
While the soft-start capacitor can be sized to meet many start up requirements, there are limitations to its size.
The soft-start time can never be faster than 1 ms due to the internal default 1 ms start up time. When the device
is enabled there is an approximate time interval of 50 µs when the soft-start capacitor will be discharged just
prior to the soft-start ramp. If the enable pin is rapidly pulsed or the soft-start capacitor is large there may not be
enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in discharging
of soft-start capacitor during long disable periods an external 1MΩ resistor from SS/TRK to ground can be used
without greatly affecting the start up time.
USING PRECISION ENABLE AND POWER GOOD
The precision enable (EN) and power good (PGOOD) pins of the LM20242 can be used to address many
sequencing requirements. The turn-on of the LM20242 can be controlled with the precision enable pin by using
two external resistors as shown in Figure 13 .
External
Power Supply
V
OUT1
LM20242
R
R
A
V
OUT2
EN
B
Figure 13. Sequencing LM20242 with Precision Enable
The value for resistor RB can be selected by the user to control the current through the divider. Typically this
resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for RB is chosen the resistor RA can be
solved using Equation 13 to set the desired turn-on voltage.
VTO
VIH_EN
x R
- 1
RA =
B
(13)
When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold
(VIH_EN), and external resistors need to be considered to insure proper turn-on of the device.
The LM20242 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to
provide fault detection. This pin requires an external resistor (RPG) to pull PGOOD high when the output is within
the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ.
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TRACKING AN EXTERNAL SUPPLY
By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 14, the
output of the LM20242 can be configured to track an external voltage source to obtain a simultaneous or
ratiometric start up.
External
Power Supply
V
OUT1
LM20242
R1
R2
EN
V
OUT2
SS/TRK
Figure 14. Tracking an External Supply
Since the soft-start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than
10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be
calculated using appropriate equation in Figure 15, to give the desired start up. Figure 15 shows two common
start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates
a ratiometric start up.
SIMULTANEOUS START UP
V
V
OUT1
OUT2
≈
’
V
OUT2
0.8V
∆
∆
÷
x
÷
-1
R1=
V
R2
«
◊
V
EN
< 0.8 x V
OUT2
OUT1
TIME
RATIOMETRIC START UP
V
OUT1
(
)
-1
x
R2
V
R1=
OUT1
V
OUT2
V
EN
TIME
Figure 15. Common Start Up Sequences
A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these
systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core. A
simultaneous start up provides a more robust power up for these applications since it avoids turning on any
parasitic conduction paths that may exist between the core and the I/O pins of the processor.
The second most common power on behavior is known as a ratiometric start up. This start up is preferred in
applications where both supplies need to be at the final value at the same time.
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Similar to the soft-start function, the fastest start up possible is 1ms regardless of the rise time of the tracking
voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide
sufficient overdrive and transient immunity.
BENEFIT OF AN EXTERNAL SCHOTTKY
During dead time, the body diode of the synchronous MOSFET acts as a free-wheeling diode and conducts the
inductor current. The MOSFET is optimized for high breakdown voltage, but this makes an inefficient body diode
reverse recovery charge. The power loss is proportional to load current and switching frequency. The loss
increases at higher input voltages and switching frequencies. One simple solution is to use a small 1A external
Schottky diode between SW and GND as shown in Figure 17, diodes D1 and D2. The external Schottky diode
effectively conducts all inductor current during the dead time, minimizing the current passing through the
synchronous MOSFET body diode and eliminating reverse recovery losses.
The external Schottky conducts currents for a very small portion of the switching cycle, therefore the average
current is low. An external Schottky rated for 1A will improve efficiency by several percent in some applications.
A Schottky rated at a higher current will not significantly improve efficiency and may be worse due to the
increased reverse capacitance. The forward voltage of the synchronous MOSFET body diode is approximately
700 mV, therefore an external Schottky with a forward voltage less than or equal to 700 mV should be selected
to ensure the majority of the dead time current is carried by the Schottky.
THERMAL CONSIDERATIONS
The thermal characteristics of the LM20242 are specified using the parameter θJA, which relates the junction
temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be
used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PD x θJA + TA
(14)
(15)
and
PD = PIN x (1 - Efficiency) - 1.1 x (IOUT)2 x DCR
Where:
TJ is the junction temperature in °C.
PIN is the input power in Watts (PIN = VIN x IIN).
θJA is the junction to ambient thermal resistance for the LM20242.
TA is the ambient temperature in °C.
IOUT is the output load current.
DCR is the inductor series resistance.
It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the
junction temperature exceeds 160°C the device will cycle in and out of thermal shutdown. If thermal shutdown
occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device.
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PCB LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
very fast. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the
inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to
the regulator GND pins, to the inductor and then out to the load (see Figure 16). To minimize both loop areas the
input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output
capacitor should consist of a small localized top side plane that connects to GND and the exposed pad (EP). The
inductor should be placed as close as possible to the SW pin and output capacitor.
2. Minimize the copper area of the switch node. Since the LM20242 has the SW pins on opposite sides of the
package it is recommended that the SW pins should be connected with a trace that runs around the package.
The inductor should be placed at an equal distance from the SW pins using 100 mil wide traces to minimize
capacitive and conductive losses.
3. Have a single point ground for all device grounds located under the EP. The ground connections for the
compensation, feedback, and soft-start components should be connected together then routed to the EP pin of
the device. The AGND pin should connect to GND under the EP. If not properly handled poor grounding can
result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output
resistor divider to FB pin should be as short as possible. This is most important when high value resistors are
used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid
contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure
feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the
best output accuracy.
6. Provide adequate device heatsinking. Use as many vias as is possible to connect the EP to the power plane
heatsink. For best results use a 5x3 via array with a minimum via diameter of 12 mils. "Via tenting" with the
solder mask may be necessary to prevent wicking of the solder paste applied to the EP. See the Thermal
Considerations section to insure enough copper heatsinking area is used to keep the junction temperature below
125°C.
LM20242
L
SW
PVIN
V
OUT
C
IN
C
OUT
PGND
LOOP1
LOOP2
Figure 16. Schematic of LM20242 Highlighting Layout Sensitive Nodes
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V
= 8V œ 36V
IN
J1
C1
C2
C3
C4
4.7 éF
4.7 éF 4.7 éF
0.1 éF
U1
J2
GND
5
6
15
16
VIN
VIN
VIN
VIN
18
C5
1 éF
VCC
R8
49.9k
R1
10k
R7
0
3
17
BOOT
PGOOD
J10
PGOOD
C9
0.1 éF
7
8
13
14
SW
SW
SW
SW
V
= +3.3V
OUT
I
19
20
1
J9
ENABLE
EN
RT
SS
= 2A
OUT
J3
L1
4
2
R9
10.0k
R2
205k
C6
0.1 éF
COMP
FB
C10
100 éF 1 éF
C11
9
10
11
D1
D2
GND
GND
GND
J4
12
AGND
C8
2200 pF
EP
R4
0
C7
120 pF
R3
R5
12.1k
32.1k
R6
10.2k
Figure 17. Typical Application Schematic
Table 3. Bill of Materials
ID
Qty
Part Number
LM20242MH
Size
HTSSOP
MSS1260
1210
Description
Vendor
U1
L1
1
1
3
3
2
1
1
1
2
2
1
1
2
1
1
1
IC, Switching Regulator
15 µH, 4.6A ISAT
4.7 µF, 50V, X7R
0.1 µF
NSC
Coilcraft
Murata
Vishay
Vishay
TDK
MSS1260-153MX
GRM32ER71H475KA88L
VJ0805JY104KXX
VJ0805Y105JXACW1BC
C1608COG1H121J
VJ0805Y222J
C1-3
C4, 6, 9
C5, 11
C7
0805
0805
1 µF
0603
120 pF
C8
0805
2.2 nF
Vishay
Kemet
Fairchild
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
C10
D1, D2
R1,9
R2
C1210C107M9PAC
MBR0540
1210
100 µF
SOD123
0603
0.5A, 40V, Schottky
10 kΩ
CRCW06031002F
CRCW08052053F
CRCW08051212F
CRCW060330000ZOEA
CRCW08053212F
CRCW08051022F
CRCW08054992F
0805
205 kΩ
R3
0805
12.1 kΩ
R4, 7
R5
0603
0 kΩ
0805
32.1 kΩ
R6
0805
10.2 kΩ
R8
0603
49.9 kΩ
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM20242MH/NOPB
LM20242MHE/NOPB
LM20242MHX/NOPB
ACTIVE
HTSSOP
HTSSOP
HTSSOP
PWP
20
20
20
73
RoHS & Green
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
20242
MH
ACTIVE
ACTIVE
PWP
250
SN
SN
20242
MH
PWP
2500 RoHS & Green
20242
MH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM20242MHE/NOPB
LM20242MHX/NOPB
HTSSOP PWP
HTSSOP PWP
20
20
250
178.0
330.0
16.4
16.4
6.95
6.95
7.1
7.1
1.6
1.6
8.0
8.0
16.0
16.0
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM20242MHE/NOPB
LM20242MHX/NOPB
HTSSOP
HTSSOP
PWP
PWP
20
20
250
210.0
367.0
185.0
367.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM20242MH/NOPB
20
73
495
8
2514.6
4.06
Pack Materials-Page 3
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
www.ti.com
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