LM25145RGYT [TI]
具有宽占空比范围的 6V 至 42V 同步降压直流/直流控制器 | RGY | 20 | -40 to 125;型号: | LM25145RGYT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有宽占空比范围的 6V 至 42V 同步降压直流/直流控制器 | RGY | 20 | -40 to 125 控制器 |
文件: | 总61页 (文件大小:1918K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LM25145
ZHCSGD0 –JUNE 2017
具有宽占空比范围的 LM25145 6V 至 42V 同步降压直流/直流控制器
1 特性
2 应用
1
•
多功能同步降压直流/直流控制器
•
•
•
•
电信基础设施
工厂自动化
测试与测量
工业电机驱动
–
–
宽输入电压范围为 6V 至 42V
可调节输出电压范围为 0.8V 至 40V
•
•
•
符合 EN55022/CISPR 22 EMI 标准
无损 RDS(on) 或分流电流感应
3 说明
开关频率范围为 100kHz 至 1MHz
LM25145 42V 同步降压控制器旨在对会发生高压瞬变
的高输入电压源或输入电源轨的电压进行调节,从而最
大限度地减少对外部浪涌抑制组件的需求。40ns 的高
侧开关最短导通时间有助于获得较大的降压比,支持从
24V 标称输入到低电压轨的直接降压转换,从而降低
系统的复杂性并减少解决方案成本。LM25145 在输入
电压突降至 6V 时,仍能根据需要以接近 100% 的占空
比继续工作,因此非常适用于高性能工业控制、机器
人、数据通信和射频功率放大器 应用。
–
同步输入和同步输出能力
•
•
•
•
40ns 最短导通时间,可实现高 VIN/VOUT 比率
140ns 最短关闭时间,以实现低压差
具有 ±1% 反馈精度的 0.8V 基准
适用于标准 VTH MOSFET 的 7.5V 栅极驱动器
–
–
–
14ns 自适应死区时间控制
2.3A 拉电流和 3.5A 灌电流能力
针对预偏置启动的低侧软启动
•
•
可调软启动或可选电压跟踪
快速线路和负载瞬态响应
强制 PWM (FPWM) 模式运行可以消除频率变化以最
大程度地降低 EMI,而用户可选的二极管仿真功能则
可以降低轻负载条件下的电流消耗。逐周期过流保护可
通过测量低侧 MOSFET 上的压降或使用可选电流感应
电阻器来实现。高达 1MHz 的可调开关频率可同步至
外部时钟源,以消除噪声敏感应用中的 拍频。
–
–
具有线路前馈的电压模式控制
高增益带宽误差放大器
•
•
精密使能端输入和漏极开路电源正常指示器(用于
排序和控制)
固有保护 特性 可实现稳健设计
–
–
–
–
间断模式过流保护
器件信息(1)
具有迟滞的输入 UVLO
VCC 和栅极驱动 UVLO 保护
具有迟滞的热关断保护
器件型号
LM25145
封装
VQFN (20)
封装尺寸(标称值)
3.50mm × 4.50mm
(1) 要了解所有可用封装,请参阅数据表末尾的可订购产品附录。
•
•
具有可湿性侧面的 VQFN-20 封装
使用 LM25145 并借助 WEBENCH® 电源设计器创
建定制设计
典型应用电路和效率性能,VOUT = 5V,FSW = 225kHz
VIN
EN
VIN
VOUT
VIN
EN/UVLO
Q1
SYNCIN
SYNC In
HO
BST
SW
LO
RC2
SYNC Out
CC1
SYNCOUT
COMP
FB
RFB1
LF
CBST
CC3
VOUT
RC1
CC2
LM25145
Q2
RT
CIN
COUT
RFB2
VCC
SS/TRK
RRT
CSS
CVCC
AGND
PGND
GND
PGOOD
ILIM
RILIM
PG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSAT9
LM25145
ZHCSGD0 –JUNE 2017
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 25
Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Applications ................................................ 36
1
2
3
4
5
6
特性.......................................................................... 1
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Functions......................... 4
6.1 Wettable Flanks ........................................................ 5
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Switching Characteristics........................................ 10
7.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
10 Power Supply Recommendations ..................... 47
11 Layout................................................................... 48
11.1 Layout Guidelines ................................................. 48
11.2 Layout Example .................................................... 51
12 器件和文档支持 ..................................................... 53
12.1 器件支持 ............................................................... 53
12.2 文档支持................................................................ 53
12.3 相关链接................................................................ 54
12.4 接收文档更新通知 ................................................. 54
12.5 社区资源................................................................ 54
12.6 商标....................................................................... 54
12.7 静电放电警告......................................................... 54
12.8 Glossary................................................................ 54
13 机械、封装和可订购信息....................................... 55
7
8
4 修订历史记录
日期
修订版本
注释
2017 年 6 月
*
最初发布版本
空白
2
版权 © 2017, Texas Instruments Incorporated
LM25145
www.ti.com.cn
ZHCSGD0 –JUNE 2017
5 说明 (续)
LM25145 电压模式控制器使用适用于标准阈值 MOSFET 的可靠的 7.5V 栅极驱动器驱动外部高侧和低侧 N 通道电
源开关。具有 2.3A 拉电流和 3.5A 灌电流能力的自适应定时栅极驱动器可在开关切换期间最大限度地减少体二极管
导通,从而降低在以高输入电压和高频率驱动 MOSFET 时的开关损耗并提高热性能。LM25145 可从开关稳压器的
输出或其他可用的源供电,从而进一步提高效率。
180° 异相时钟输出(相对于内部振荡器的同步输出)非常适用于级联或多通道电源,可降低输入电容器纹波电流和
EMI 滤波器尺寸。其他 的 LM25145 功能还包括可配置软启动、用于故障报告和输出监控的漏极开路电源正常监
控、单调启动至预偏置负载、集成 VCC 偏置电源稳压器和自举二极管、外部电源跟踪、针对可调线路欠压锁定
(UVLO) 且具有迟滞的精密使能端输入、间断模式过载保护和带自动恢复的热关断保护。
LM25145 控制器采用 3.5mm × 4.5mm 热增强型 20 引脚 VQFN 封装,并为高电压引脚和可湿性侧面留出额外间
距,以便对焊锡接点填角焊缝进行光学检测。
版权 © 2017, Texas Instruments Incorporated
3
LM25145
ZHCSGD0 –JUNE 2017
www.ti.com.cn
6 Pin Configuration and Functions
RGY Package
20-Pin VQFN With Wettable Flanks
Top View
RT
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
SW
HO
SS/TRK
BST
NC
COMP
FB
Exposed
Pad
(EP)
AGND
EP
SYNCOUT
VCC
LO
SYNCIN
NC
PGND
Connect Exposed Pad on bottom to AGND and PGND on the PCB.
Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
Enable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the
controller is in the shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V
and less than 1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin
grounded, and no switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK
pin is allowed to ramp and pulse-width modulated gate drive signals are delivered to the HO and LO pins. A
10-μA current source is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO
resistor divider to provide hysteresis. Hysteresis can be adjusted by varying the resistance of the external
divider.
1
EN/UVLO
I
Oscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and
the AGND. The recommended maximum oscillator frequency is 1 MHz. An RT pin resistor is required even
when using the SYNCIN pin to synchronize to an external clock.
2
3
RT
I
I
Soft-start and voltage tracking pin. An external capacitor and an internal 10-μA current source set the ramp
rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the
SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V,
the amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby
and fault conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB
falls due to a load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery
when the fault is removed. Voltage tracking can be implemented by connecting a low impedance reference
between 0 V and 0.8 V to the SS/TRK pin. The 10-µA SS/TRK charging current flows into the reference
and produces a voltage error if the impedance is not low. Connect a minimum capacitance from SS/TRK to
AGND of 2.2 nF.
SS/TRK
Low impedance output of the internal error amplifier. The loop compensation network should be connected
between the COMP pin and the FB pin.
4
5
COMP
FB
O
I
Feedback connection to the inverting input of the internal error amplifier. A resistor divider from the output
to this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V.
(1) P = Power, G = Ground, I = Input, O = Output.
4
Copyright © 2017, Texas Instruments Incorporated
LM25145
www.ti.com.cn
PIN
ZHCSGD0 –JUNE 2017
Pin Functions (continued)
TYPE(1)
DESCRIPTION
NO.
NAME
6
AGND
P
Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.
Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-
side FET gate drive. Connect SYNCOUT of the master LM25145 to the SYNCIN pin of a second LM25145
to operate two controllers at the same frequency with 180° interleaved high-side FET switch turnon
transitions. Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating
from an external clock that is different from the free-running frequency set by the RT resistor.
7
8
SYNCOUT
O
Dual function pin for providing an optional clock input and for enabling diode emulation by the low-side
MOSFET. Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode
emulation by the low-side MOSFET is disabled when the controller is synchronized to an external clock,
and negative inductor current can flow in the low-side MOSFET with light loads. A continuous logic low
state at the SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode
emulation results in DCM operation at light loads, which improves efficiency. A logic high state at the
SYNCIN pin disables diode emulation producing forced-PWM (FPWM) operation. During soft-start when
SYNCIN is high or a clock signal is present, the LM25145 operates in diode emulation mode until the
output is in regulation, then gradually increases the SW zero-cross threshold, resulting in a gradual
transition from DCM to FPWM.
SYNCIN
I
9
NC
—
O
No electrical connection.
Power Good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin
is within a specified tolerance window centered at 0.8 V.
10
PGOOD
Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an
external resistor programs the threshold voltage for valley current limiting. The opposite end of the
threshold adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing
or to a current sense resistor connected to the source of the low-side FET.
11
ILIM
I
Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-
side MOSFET or the ground side of a shunt resistor.
12
13
PGND
LO
P
P
Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through
a short, low inductance path.
Output of the 7.5-V bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as
close to the controller as possible. Controller bias can be supplied from an external supply that is greater
than the internal VCC regulation voltage. Use caution when applying external bias to ensure that the
applied voltage is not greater than the minimum VIN voltage and does not exceed the VCC pin maximum
operating rating, see Recommended Operating Conditions.
14
VCC
O
15
16
EP
NC
—
—
Pin internally connected to exposed pad of the package. Electrically isolated.
No electrical connection.
Bootstrap supply for the high-side gate driver. Connect to the bootstrap capacitor. The bootstrap capacitor
supplies current to the high-side FET gate and should be placed as close to controller as possible. If an
external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the
cathode of the diode to the BST pin and anode to VCC.
17
18
BST
HO
O
P
High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low
inductance path.
Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-
side MOSFET and the drain terminal of the low-side MOSFET using short, low inductance paths.
19
20
—
SW
VIN
EP
P
P
Supply voltage input for the VCC LDO regulator.
Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal
resistance.
—
6.1 Wettable Flanks
100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high
reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins
and terminals that are easily viewed. It is therefore difficult to determine visually whether or not the package is
successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve
the issue of side-lead wetting of leadless packaging. The LM25145 is assembled using a 20-pin VQFN package
with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and
manufacturing costs.
Copyright © 2017, Texas Instruments Incorporated
5
LM25145
ZHCSGD0 –JUNE 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted).(1)
MIN
–0.3
–1
MAX
45
45
45
45
45
14
6
UNIT
VIN
SW
SW (20-ns transient)
ILIM
–5
–1
Input voltages
V
EN/UVLO
–0.3
–0.3
–0.3
–0.3
–0.3
VCC
FB, COMP, SS/TRK, RT
SYNCIN
14
60
45
14
7
BST
BST to VCC
BST to SW
–0.3
Output voltages
V
VCC to BST (20-ns transient)
LO (20-ns transient)
PGOOD
–3
–0.3
14
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6
Copyright © 2017, Texas Instruments Incorporated
LM25145
www.ti.com.cn
ZHCSGD0 –JUNE 2017
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted).(1)
MIN
6
NOM
MAX
42
42
42
13
42
55
42
13
13
1
UNIT
VIN
SW
–1
–1
8
VI
Input voltages
ILIM
V
External VCC bias rail
EN/UVLO
BST
0
–0.3
BST to VCC
BST to SW
PGOOD
SYNCOUT
PGOOD
VO
Output voltages
V
5
–1
ISINK
,
Sink/source currents
mA
°C
ISRC
2
TJ
Operating junction temperature
–40
125
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
7.4 Thermal Information
LM25145
THERMAL METRIC(1)
RGY (VQFN)
20 PINS
36.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
28
11.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
11.7
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Operating input voltage range
Operating input current, not switching VEN/UVLO = 1.5 V, VSS/TRK = 0 V
6
42
2.1
2
V
IQ-RUN
IQ-STBY
IQ-SDN
1.8
1.75
13.5
mA
mA
µA
Standby input current
Shutdown input current
VEN/UVLO = 1 V
VEN/UVLO = 0 V, VVCC < 1 V
16
VCC REGULATOR
VSS/TRK = 0 V, 9 V ≤ VVIN ≤ 42 V,
0 mA < IVCC ≤ 20 mA
VVCC
VCC regulation voltage
7.3
7.5
7.7
V
VVCC-LDO
ISC-LDO
VVCC-UV
VVCC-UVH
VIN to VCC dropout voltage
VCC short-circuit current
VVIN = 6 V, VSS/TRK = 0 V, IVCC = 20 mA
VSS/TRK = 0 V, VVCC = 0 V
VVCC rising
0.25
50
0.63
70
V
mA
V
40
VCC undervoltage threshold
VCC undervoltage hysteresis
4.8
4.93
0.26
5.2
Rising threshold – falling threshold
V
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in Thermal Information.
Copyright © 2017, Texas Instruments Incorporated
7
LM25145
ZHCSGD0 –JUNE 2017
www.ti.com.cn
Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVCC-EXT
IVCC
Minimum external bias supply voltage Voltage required to disable VCC regulator
8
V
External VCC input current, not
VSS/TRK = 0 V, VVCC = 13 V
switching
2.1
mA
ENABLE AND INPUT UVLO
VSDN
Shutdown to standby threshold
VEN/UVLO rising
0.42
50
V
mV
V
VSDN-HYS
VEN
Shutdown threshold hysteresis
Standby to operating threshold
EN/UVLO rising – falling threshold
VEN/UVLO rising
1.164
9
1.2 1.236
Standby to operating hysteresis
current
IEN-HYS
VEN/UVLO = 1.5 V
10
11
µA
ERROR AMPLIFIER
VREF
FB reference voltage
FB input bias current
FB connected to COMP
VFB = 0.8 V
792
800
5
808
0.1
mV
µA
V
IFB-BIAS
–0.1
VCOMP-OH COMP output high voltage
VFB = 0 V, COMP sourcing 1 mA
COMP sinking 1 mA
VCOMP-OL
AVOL
COMP output low voltage
DC gain
0.3
V
94
dB
MHz
GBW
Unity gain bandwidth
6.5
SOFT-START AND VOLTAGE TRACKING
ISS
SS/TRK capacitor charging current
SS/TRK discharge FET resistance
SS/TRK to FB offset
VSS/TRK = 0 V
8.5
10
11
12
15
µA
Ω
RSS
VEN/UVLO = 1 V, VSS/TRK = 0.1 V
VSS-FB
–15
mV
mV
VSS-CLAMP SS/TRK clamp voltage
VSS/TRK – VFB, VFB = 0.8 V
115
POWER GOOD INDICATOR
FB upper threshold for PGOOD high
to low
PGUTH
PGLTH
% of VREF, VFB rising
% of VREF, VFB falling
106%
90%
108% 110%
FB lower threshold for PGOOD high
to low
92%
94%
PGHYS_U
PGHYS_L
TPG-RISE
TPG-FALL
VPG-OL
PGOOD upper threshold hysteresis
PGOOD lower threshold hysteresis
PGOOD rising filter
% of VREF
3%
2%
25
% of VREF
FB to PGOOD rising edge
FB to PGOOD falling edge
VFB = 0.9 V, IPGOOD = 2 mA
VFB = 0.8 V, VPGOOD = 13 V
µs
µs
PGOOD falling filter
25
PGOOD low state output voltage
PGOOD high state leakage current
150
100
mV
nA
IPG-OH
OSCILLATOR
FSW1
FSW2
FSW3
Oscillator Frequency – 1
RRT = 100 kΩ
RRT = 25 kΩ
RRT = 12.5 kΩ
100
400
780
kHz
kHz
kHz
Oscillator Frequency – 2
Oscillator Frequency – 3
380
420
SYNCHRONIZATION INPUT AND OUTPUT
SYNCIN external clock frequency
FSYNC
range
% of nominal frequency set by RRT
–20%
2
+50%
0.8
VSYNC-IH
VSYNC-IL
RSYNCIN
Minimum SYNCIN input logic high
Maximum SYNCIN input logic low
SYNCIN input resistance
V
V
VSYNCIN = 3 V
20
kΩ
ns
V
TSYNCI-PW SYNCIN input minimum pulsewidth
Minimum high state or low state duration
50
3
VSYNCO-OH SYNCOUT high state output voltage ISYNCOUT = –1 mA (sourcing)
VSYNCO-OL SYNCOUT low state output voltage
ISYNCOUT = 1 mA (sinking)
0.4
V
Delay from HO rising to SYNCOUT
leading edge
VSYNCIN = 0 V, TS = 1/FSW
FSW set by RRT
,
TSYNCOUT
TS/2 – 140
ns
8
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Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay from SYNCIN leading edge to
HO rising
TSYNCIN
50% to 50%
150
ns
BOOTSTRAP DIODE AND UNDERVOLTAGE THRESHOLD
VBST-FWD
Diode forward voltage, VCC to BST
VCC to BST, BST pin sourcing 20 mA
0.75
80
0.9
V
BST to SW quiescent current, not
switching
IQ-BST
VSS/TRK = 0 V, VSW = 24 V, VBST = 30 V
µA
VBST-UV
BST to SW undervoltage detection
BST to SW undervoltage hysteresis
VBST – VSW falling
VBST – VSW rising
3.4
V
V
VBST-HYS
0.42
PWM CONTROL
TON(MIN)
TOFF(MIN)
DC100kHz
DC400kHz
Minimum controllable on-time
VBST – VSW = 7 V, HO 50% to 50%
VBST – VSW = 7 V, HO 50% to 50%
FSW = 100 kHz, 6 V ≤ VVIN ≤ 42 V
FSW = 400 kHz, 6 V ≤ VVIN ≤ 42 V
40
140
60
ns
ns
Minimum off-time
200
98%
90%
99%
94%
Maximum duty cycle
Ramp valley voltage (COMP at 0%
duty cycle)
VRAMP(min)
kFF
300
15
mV
V/V
PWM feedforward gain (VIN / VRAMP
)
6 V ≤ VVIN ≤ 42 V
OVERCURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING
IRS
ILIM source current, RSENSE mode
ILIM source current, RDS(on) mode
ILIM current tempco
Low voltage detected at ILIM
SW voltage detected at ILIM, TJ = 25°C
RDS-ON mode
90
100
200
4500
0
110
220
µA
µA
IRDSON
IRSTC
IRDSONTC
VILIM-TH
180
ppm/°C
ppm/°C
mV
ILIM current tempco
RSENSE mode
ILIM comparator threshold at ILIM
–8
–2
3.5
SHORT-CIRCUIT PROTECT (SCP) – DUTY CYCLE CLAMP
Clamp offset voltage – no current
limiting
VCLAMP-OS
CLAMP to COMP steady state offset voltage
0.2 + VVIN/75
V
V
VCLAMP-MIN Minimum clamp voltage
CLAMP voltage with continuous current limiting
0.3 + VVIN/150
HICCUP MODE FAULT PROTECTION
Clock cycles with current limiting before hiccup
off-time activated
CHICC-DEL Hiccup mode activation delay
128
cycles
cycles
Clock cycles with no switching followed by
SS/TRK release
CHICCUP
Hiccup mode off-time after activation
8192
DIODE EMULATION
Zero-cross detect (ZCD) soft-start
ramp
ZCD threshold measured at SW pin
50 clock cycles after first HO pulse
VZCD-SS
0
mV
Zero-cross detect disable threshold
(CCM)
ZCD threshold measured at SW pin
1000 clock cycles after first HO pulse
VZCD-DIS
200
mV
mV
VDEM-TH
Diode emulation zero-cross threshold Measured at SW with VSW rising
–5
0
5
GATE DRIVERS
RHO-UP
HO high-state resistance, HO to BST VBST – VSW = 7 V, IHO = –100 mA
1.5
0.9
1.5
0.9
2.3
3.5
Ω
Ω
Ω
Ω
A
A
RHO-DOWN HO low-state resistance, HO to SW
VBST – VSW = 7 V, IHO = 100 mA
RLO-UP
LO high-state resistance, LO to VCC VBST – VSW = 7 V, ILO = –100 mA
RLO-DOWN LO low-state resistance, LO to PGND VBST – VSW = 7 V, ILO = 100 mA
IHOH, ILOH HO, LO source current
IHOL, ILOL HO, LO sink current
THERMAL SHUTDOWN
VBST – VSW = 7 V, HO = SW, LO = AGND
VBST – VSW = 7 V, HO = BST, LO = VCC
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
175
20
°C
°C
TSD-HYS
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7.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THO-TR
TLO-TR
HO, LO rise times
VBST – VSW = 7 V, CLOAD = 1 nF, 20% to 80%
VBST – VSW = 7 V, CLOAD = 1 nF, 80% to 20%
7
ns
THO-TF
TLO-TF
HO, LO fall times
4
ns
THO-DT
TLO-DT
HO turnon dead time
LO turnon dead time
VBST – VSW = 7 V, LO off to HO on, 50% to 50%
VBST – VSW = 7 V, HO off to LO on, 50% to 50%
14
14
ns
ns
10
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7.7 Typical Characteristics
VVIN = 24 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted).
100
95
90
85
80
75
70
65
100
90
80
70
60
50
40
30
20
VIN = 8V
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 32V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 32V
0
5
10
15
20
0.1
0.5
1
5
10
20
Output Current (A)
Output Current (A)
VOUT = 5 V
VSYNCIN = VVCC
FSW = 500 kHz
VOUT = 5 V
VSYNCIN = 0 V
FSW = 500 kHz
See Figure 46
RRT = 20 kΩ
See Figure 46
RRT = 20 kΩ
Figure 1. Efficiency vs Load, CCM
Figure 2. Efficiency vs Load, DCM
100
95
90
85
80
75
100
90
80
70
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
70
0
60
0.1
2
4
6
8
0.5
1
5
8
Output Current (A)
Output Current (A)
VOUT = 12 V
VSYNCIN = VVCC
FSW = 425 kHz
VOUT = 12 V
VSYNCIN = 0 V
FSW = 425 kHz
See Figure 57
RRT = 23.7 kΩ
See Figure 57
RRT = 23.7 kΩ
Figure 3. Efficiency vs Load, CCM
Figure 4. Efficiency vs Load, DCM
(VOUT Supplies Bias Power to VCC)
0.808
0.806
0.804
0.802
0.8
100
80
60
40
20
0.798
0.796
0.794
0.792
VIN = 6V
VIN = 12V
VIN = 24V
VIN = 36V
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
2
4
6
8
10
Output Current (A)
VOUT = 1.1 V
See Figure 70
FSW = 300 kHz
RRT = 33.2 kΩ
Figure 5. Efficiency vs Load, CCM
Figure 6. FB Voltage vs Junction Temperature
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Typical Characteristics (continued)
VVIN = 24 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted).
160
140
120
100
80
14
12
10
8
6
60
4
40
2
20
TOFF(min)
TON(min)
-40°C
25°C
30
125°C
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
6
12
18
24
36
42
Input Voltage (V)
VSW = 0 V
VEN/UVLO = 0 V
Figure 7. TON(min) and TOFF(min) vs Junction Temperature
Figure 8. IQ-SHD vs Input Voltage
1.8
2
1.9
1.8
1.7
1.6
1.5
1.7
1.6
1.5
1.4
-40°C
25°C
30
125°C
-40°C
25°C
30
125°C
1.3
1.4
6
6
12
18
24
36
42
12
18
24
36
42
Input Voltage (V)
Input Voltage (V)
VSW = 0 V
VEN/UVLO = 1 V
VSW = 0 V
VEN/UVLO = VVIN
VSS/TRK = 0 V
Figure 9. IQ-STANDBY vs Input Voltage
Figure 10. IQ-OPERATING (Nonswitching) vs Input Voltage
0.6
4
3.75
3.5
0.5
0.4
0.3
0.2
0.1
3.25
3
2.75
2.5
-40°C
25°C
30
125°C
VCC = 8V
0
6
12
18
24
36
42
6
12
18
24
30
36
42
Input Voltage (V)
Input Voltage (V)
VSW = 0 V
HO, LO Open
VSW = 0 V
VVCC = VBST = VILIM
VFB = 0 V
Figure 11. IQ-OPERATING (Switching) vs Input Voltage
Figure 12. VIN Quiescent Current With External VCC Applied
12
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Typical Characteristics (continued)
VVIN = 24 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted).
350
300
250
200
150
100
50
25
20
15
10
5
RDS-ON Mode
RSENSE Mode
HO to LO
LO to HO
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
VSW = 0 V
Figure 13. ILIM Current Source vs Junction Temperature
Figure 14. Dead Time vs Junction Temperature
5.2
4
3.8
3.6
3.4
3.2
3
5
4.8
4.6
4.4
Rising
Falling
Rising
Falling
4.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Figure 15. VCC UVLO Thresholds vs Junction Temperature
Figure 16. BST UVLO Thresholds vs Junction Temperature
98
110
96
94
92
90
108
106
104
102
Rising
Rising
Falling
Falling
88
-40 -25 -10
100
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Figure 17. PGOOD UVP Thresholds vs Junction
Temperature
Figure 18. PGOOD OVP Thresholds vs Junction
Temperature
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Typical Characteristics (continued)
VVIN = 24 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted).
1.3
1.25
1.2
0.5
0.45
0.4
1.15
1.1
0.35
0.3
Rising
Falling
1.05
0.25
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Figure 19. EN/UVLO Threshold vs Junction Temperature
Figure 20. EN Standby Thresholds vs Junction Temperature
1000
420
800
600
400
200
0
410
400
390
VIN = 6V
VIN = 48V
VIN = 100V
380
-40 -25 -10
0
10
20
30
40
50
60
70
80
90 100
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
RT Resistance (kW)
VSW = 0 V
Figure 21. Oscillator Frequency vs RT Resistance
Figure 22. Oscillator Frequency vs Junction Temperature
1
0.9
0.8
0.7
0.6
0.5
4
3.5
3
2.5
2
1.5
Source
Sink
VCC = 8V
1
0
10
20
30
40
50
6
7
8
9
10
11
12
13
BST Diode Forward Current (mA)
VCC Voltage (V)
Figure 23. BST Diode Forward Voltage vs Current
Figure 24. Gate Driver Peak Current vs VCC Voltage
14
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Typical Characteristics (continued)
VVIN = 24 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted).
1.6
1.4
1.2
1
1.6
1.4
1.2
1
0.8
0.6
0.8
0.6
High State
Low State
High State
Low State
6
7
8
9
10
11
12
13
6
7
8
9
10
11
12
13
VCC Voltage (V)
VCC Voltage (V)
Figure 25. HO Driver Resistance vs VCC Voltage
Figure 26. LO Driver Resistance vs VCC Voltage
7.75
7.5
7.25
7
7
6
5
4
3
2
1
0
6.75
6.5
6.25
6
-40°C
25°C
125°C
-40°C
25°C
30
125°C
5.75
0
10
20
30
40
50
60
6
12
18
24
36
42
VCC Current (mA)
Input Voltage (V)
VIN = 6 V
VSS/TRK = 0 V
Figure 28. VCC vs ICC Characteristic
Figure 27. VCC Voltage vs Input Voltage
8
7
6
5
4
3
2
1
11
10.8
10.6
10.4
10.2
10
9.8
9.6
9.4
9.2
-40°C
25°C
125°C
0
0
9
10
20
30
40
50
60
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
VCC Current (mA)
VIN = 12 V
Figure 29. VCC vs ICC Characteristic
Figure 30. SS/TRK Current Source vs Junction Temperature
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8 Detailed Description
8.1 Overview
The LM25145 is a 42-V synchronous buck controller that features all of the functions necessary to implement a
high efficiency step-down power supply with output voltage ranging from 0.8 V to 40 V. The voltage-mode control
architecture uses input feedforward for excellent line transient response over a wide VIN range. Voltage-mode
control supports the wide duty cycle range for high input voltage and low dropout applications as well as when a
high voltage conversion ratio (for example, 10-to-1) is required. Current sensing for cycle-by-cycle current limit
can be implemented with either the low-side FET RDS(on) or a current sense resistor. The operating frequency is
programmable from 100 kHz to 1 MHz. The LM25145 drives external high-side and low-side NMOS power
switches with robust 7.5-V gate drivers suitable for standard threshold MOSFETs. Adaptive dead-time control
between the high-side and low-side drivers is designed to minimize body diode conduction during switching
transitions. An external bias supply can be connected to the VCC pin to improve efficiency in high-voltage
applications. A user-selectable diode emulation feature enables discontinuous conduction mode operation for
improved efficiency and lower dissipation at light-load conditions.
8.2 Functional Block Diagram
VIN
VCC
BST
7.5 V LDO
REGULATOR
+
œ
VCC
UVLO
7.5 V
VCC ENABLE
œ
+
VVCC-UV
SHUTDOWN
0.4 V
+
ENABLE
LOGIC
œ
EN/UVLO
BST_UV
œ
+
1.2 V
—1“
D
5 µs
FILTER
+
œ
STANDBY
R
Q
VSW
+
VBST-UV
CL
THERMAL
SHUTDOWN
kFF*VIN
HYSTERESIS
LEVEL
SHIFT
DRIVER
HO
SW
RT
OSCILLATOR &
FEEDFORWARD
RAMP
CLK
SYNCOUT
GENERATOR
ADAPTIVE
DEADTIME
DELAY
kFF*VIN + 0.3 V
RAMP
PWM
LOGIC
PEAK
VCC
PWM
COMPARATOR
DETECT
FILTER
SYNCIN
FPWM
0.3 V
DRIVER
LO
+
œ
COMP
FB
PGND
ERROR
AMP
œ
œ
+
+
115 mV
0.8 V
+
+
œ
+
ZERO CROSS
DETECTION
œ
CLAMP
SS/TRK
PGOOD
COMP
CLAMP
MODULATOR
STANDBY
HICCUP
COUNTERS
CLK
SUPERVISORY
COMPARATORS
ILIM
RDS(on) or
Resistor Sensing
LO
0.8 V + 8%
œ
+
FB
LO
25 µs
delay
OCP
œ
ILIM
œ
AGND
+
0.8 V - 8%
CURRENT LIMIT
COMPARATOR
+
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8.3 Feature Description
8.3.1 Input Range (VIN)
The LM25145 operational input voltage range is from 6 V to 42 V. The device is intended for step-down
conversions from 12-V, 24-V, 28-V and 36-V unregulated, semiregulated, and fully-regulated supply rails. The
application circuit of Figure 31 shows all the necessary components to implement an LM25145-based wide-VIN
step-down regulator using a single supply. The LM25145 uses an internal LDO subregulator to provide a 7.5-V
VCC bias rail for the gate drive and control circuits (assuming the input voltage is higher than 7.5 V plus the
necessary subregulator dropout specification).
RUV2
RUV1
VOUT
VIN
1
20
CBST
RC2
CC3
RRT
Q1
RFB1
EN/UVLO
VIN
RT
2
3
4
5
6
7
17
18
19
BST
HO
SS/TRK
CC1
RC1
CSS
LF
COMP
FB
SW
VOUT
NC 16
EP 15
CC2
LM25145
Q2
AGND
SYNC
out
RFB2
CIN
COUT
SYNCOUT
14
13
12
VCC
LO
8
9
SYNCIN
NC
SYNC
PGND
GND
ILIM
11
PGOOD
optional
10
CVCC
RPG
RILIM
CILIM
PG
Copyright © 2017, Texas Instruments Incorporated
Figure 31. Schematic Diagram for VIN Operating Range of 6 V to 42 V
In high voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 55 V during line or load transient events. Voltage ringing on the VIN pin that exceeds the
Absolute Maximum Ratings can damage the IC. Use high-quality ceramic input capacitors to minimize ringing.
An RC filter from the input rail to the VIN pin (for example, 4.7 Ω and 0.1 µF) provides supplementary filtering at
the VIN pin.
8.3.2 Output Voltage Setpoint and Accuracy (FB)
The reference voltage at the FB pin is set at 0.8 V with a feedback system accuracy over the full junction
temperature range of ±1%. Junction temperature range for the device is –40°C to +125°C. While dependent on
switching frequency and load current levels, the LM25145 is generally capable of providing output voltages in the
range of 0.8 V to a maximum of slightly less than VIN. The DC output voltage setpoint during normal operation is
set by the feedback resistor network, RFB1 and RFB2, connected to the output.
8.3.3 High-Voltage Bias Supply Regulator (VCC)
The LM25145 contains an internal high-voltage VCC regulator that provides a bias supply for the PWM controller
and its gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an input voltage
source up to 42 V. The output of the VCC regulator is set to 7.5 V. However, when the input voltage is below the
VCC setpoint level, the VCC output tracks VIN with a small voltage drop. Connect a ceramic decoupling capacitor
between 1 µF and 5 µF from VCC to AGND for stability.
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Feature Description (continued)
The VCC regulator output has a current limit of 40 mA (minimum). At power up, the regulator sources current into
the capacitor connected to the VCC pin. When the VCC voltage exceeds its rising UVLO threshold of 4.93 V, the
output is enabled (if EN/UVLO is above 1.2 V) and the soft-start sequence begins. The output remain active until
the VCC voltage falls below its falling UVLO threshold of 4.67 V (typical) or if EN/UVLO goes to a standby or
shutdown state.
Internal power dissipation of the VCC regulator can be minimized by connecting the output voltage or an auxiliary
bias supply rail (up to 13 V) to VCC using a diode DVCC as shown in Figure 32. A diode in series with the input
prevents reverse current flow from VCC to VIN if the input voltage falls below the external VCC rail.
LM25145
Required if VIN < VCC(EXT)
DVCC
DVIN
VIN
20 VIN
VCC 14
VCC-EXT
8 V to 13 V
6 V to 42 V
CVIN
CVCC
2.2 mF
0.1 mF
AGND
6
Copyright © 2017, Texas Instruments Incorporated
Figure 32. VCC Bias Supply Connection From VOUT or Auxiliary Supply
Note that a finite bias supply regulator dropout voltage exists and is manifested to a larger extent when driving
high gate charge (QG) power MOSFETs at elevated switching frequencies. For example, at VVIN = 6 V, the VCC
voltage is 5.8 V with a DC operating current, IVCC, of 20 mA. Such a low gate drive voltage may be insufficient to
fully enhance the power MOSFETs. At the very least, MOSFET on-state resistance, RDS(ON), may increase at
such low gate drive voltage.
Here are the main considerations when operating at input voltages below 7.5 V:
•
•
•
Increased MOSFET RDS(on) at lower VGS, leading to Increased conduction losses and reduced OCP setpoint.
Increased switching losses given the slower switching times when operating at lower gate voltages.
Restricted range of suitable power MOSFETs to choose from (MOSFETs with RDS(on) rated at VGS = 4.5 V
become mandatory).
8.3.4 Precision Enable (EN/UVLO)
The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by the
resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a
comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the
EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way to
enable the operation of the LM25145 is to connect EN/UVLO directly to VIN. This allows self start-up of the
LM25145 when VCC is within its valid operating range. However, many applications benefit from using a resistor
divider RUV1 and RUV2 as shown in Figure 33 to establish a precision UVLO level.
Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turnon and turnoff
voltages.
V
- V
IN(off)
IN(on)
RUV1
=
IHYS
(1)
(2)
VEN
- VEN
RUV2 = RUV1
∂
V
IN(on)
18
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Feature Description (continued)
vcc
LM25145
VIN
10 ꢀA
RUV1
EN/UVLO
1.2V
1
RUV2
Enable
Remote
Comparator
Shutdown
Figure 33. Programmable Input Voltage UVLO Turnon and Turnoff
The LM25145 enters a low IQ shutdown mode when EN/UVLO is pulled below approximately 0.4 V. The internal
LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the
LM25145. The LM25145 operates in standby mode when the EN/UVLO voltage is between the hard shutdown
and precision enable (standby) thresholds.
8.3.5 Power Good Monitor (PGOOD)
The LM25145 provides a PGOOD flag pin to indicate when the output voltage is within a regulation window. Use
the PGOOD signal as shown in Figure 34 for start-up sequencing of downstream converters, fault protection, and
output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than
13 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease
the voltage from a higher voltage pullup rail.
VIN(on) = 15 V
VIN(off) = 10 V
VOUT(SLAVE) = 3.3 V
VOUT(MASTER) = 5 V
LM25145
PGOOD 10
LM25145
RUV1
499 kꢀ
PGOOD 10
EN/UVLO
RFB3
RPG
RFB1
20 kꢀ
1
20 kꢀ
1
EN/UVLO
20 kꢀ
RUV2
FB
FB
5
5
0.8 V
0.8 V
43.2 kꢀ
RFB4
RFB2
6.34 kꢀ
3.83 kꢀ
Regulator #1
Regulator #2
Start-up based on
Input Voltage UVLO
Sequential Start-up
based on PGOOD
Copyright © 2017, Texas Instruments Incorporated
Figure 34. Master-Slave Sequencing Implementation Using PGOOD and EN/UVLO
When the FB voltage exceeds 94% of the internal reference VREF, the internal PGOOD switch turns off and
PGOOD can be pulled high by the external pullup. If the FB voltage falls below 92% of VREF, the internal PGOOD
switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. Similarly, when
the FB voltage exceeds 108% of VREF, the internal PGOOD switch turns on, pulling PGOOD low. If the FB
voltage subsequently falls below 105% of VREF, the PGOOD switch is turned off and PGOOD is pulled high.
PGOOD has a built-in deglitch delay of 25 µs.
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Feature Description (continued)
8.3.6 Switching Frequency (RT, SYNCIN)
There are two options for setting the switching frequency, FSW, of the LM25145, thus providing a power supply
designer with a level of flexibility when choosing external components for various applications. To adjust the
frequency, use a resistor from the RT pin to AGND, or synchronize the LM25145 to an external clock signal
through the SYNCIN pin.
8.3.6.1 Frequency Adjust
Adjust the LM25145 free-running switching frequency by using a resistor from the RT pin to AGND. The
switching frequency range is from 100 kHz to 1 MHz. The frequency set resistance, RRT, is governed by
Equation 3. E96 standard-value resistors for common switching frequencies are given in Table 1.
104
RRT kW =
»
ÿ
⁄
FSW kHz
»
ÿ
⁄
(3)
Table 1. Frequency Set Resistors
SWITCHING FREQUENCY
(kHz)
FREQUENCY SET RESISTANCE
(kΩ)
100
200
250
300
400
500
750
1000
100
49.9
40.2
33.2
24.9
20
13.3
10
8.3.6.2 Clock Synchronization
Apply an external clock synchronization signal to the LM25145 to synchronize switching in both frequency and
phase. Requirements for the external clock SYNC signal are:
•
•
•
•
Clock frequency range: 100 kHz to 1 MHz
Clock frequency: –20% to +50% of the free-running frequency set by RRT
Clock maximum voltage amplitude: 13 V
Clock minimum pulse width: 50 ns
VSW 5 V/DIV
VSYNCIN
2 V/DIV
1 ms/DIV
Figure 35. Typical 400-kHz SYNCIN and SW Voltage Waveforms
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Figure 35 shows a clock signal at 400 kHz and the corresponding SW node waveform (VIN = 24 V, VOUT = 5 V,
free-running frequency = 280 kHz). The SW voltage waveform is synchronized with respect to the rising edge of
SYNCIN. The rising edge of the SW voltage is phase delayed relative to SYNCIN by approximately 100 ns.
8.3.7 Configurable Soft-Start (SS/TRK)
After the EN/UVLO pin exceeds its rising threshold of 1.2 V, the LM25145 begins charging the output to the DC
level dictated by the feedback resistor network. The LM25145 features an adjustable soft-start (set by a capacitor
from the SS/TRK pin to GND) that determines the charging time of the output. A 10-µA current source charges
this soft-start capacitor. Soft-start limits inrush current as a result of high output capacitance to avoid an
overcurrent condition. Stress on the input supply rail is also reduced. The soft-start time, tSS, for the output
voltage to ramp to its nominal level is set by Equation 4.
CSS ∂VREF
tSS
=
ISS
where
•
•
•
CSS is the soft-start capacitance
VREF is the 0.8-V reference
ISS is the 10-µA current sourced from the SS/TRK pin.
(4)
(5)
More simply, calculate CSS using Equation 5.
CSS nF = 12.5 ∂ t ms
»
ÿ
»
ÿ
⁄
SS
⁄
The SS/TRK pin is internally clamped to VFB + 115 mV to allow a soft-start recovery from an overload event. The
clamp circuit requires a soft-start capacitance greater than 2 nF for stability and has a current limit of
approximately 2 mA.
8.3.7.1 Tracking
The SS/TRK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This
tracking is achieved by simply dividing down the output voltage of the master with a simple resistor network.
Coincident, ratiometric, and offset tracking modes are possible.
If an external voltage source is connected to the SS/TRK pin, the external soft-start capability of the LM25145 is
effectively disabled. The regulated output voltage level is reached when the SS/TRACK pin reaches the 0.8-V
reference voltage level. It is the responsibility of the system designer to determine if an external soft-start
capacitor is required to keep the device from entering current limit during a start-up event. Likewise, the system
designer must also be aware of how fast the input supply ramps if the tracking feature is enabled.
SS/TRK
160mV/DIV
94% VOUT
92% VOUT
VOUT 1V/DIV
PGOOD
2V/DIV
10 ms/DIV
Figure 36. Typical Output Voltage Tracking and PGOOD Waveforms
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Figure 36 shows a triangular voltage signal directly driving SS/TRK and the corresponding output voltage
tracking response. Nominal output voltage here is 5 V, with oscilloscope channel scaling chosen such that the
waveforms overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 94% (rising) and
92% (falling) of the nominal output voltage setpoint.
Two practical tracking configurations, ratiometric and coincident, are shown in Figure 37. The most common
application is coincident tracking, used in core versus I/O voltage tracking in DSP and FPGA implementations.
Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the
slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the output voltage of the slave
to a fraction of the output voltage of the master during start-up.
VOUTMASTER = 3.3 V
Slave Regulator #1
Ratiometric Tracking
Slave Regulator #2
Coincident Tracking
VOUTSLAVE1 = 1.8 V
VOUTSLAVE2 = 1.2 V
LM25145
LM25145
RTRK1
RTRK3
RFB3
RFB1
26.7 kꢀ
10 kꢀ
10 kꢀ
12.5 kꢀ
SS/TRK
FB
3
3
5
SS/TRK
FB
5
0.8 V
0.8 V
RTRK4
20 kꢀ
RTRK2
CSS2
CSS1
RFB2
10 kꢀ
RFB4
20 kꢀ
10 kꢀ
2.2 nF
2.2 nF
SYNCIN
SYNCIN
8
8
SYNCOUT
from Master
Copyright © 2017, Texas Instruments Incorporated
Figure 37. Tracking Implementation With Master, Ratiometric Slave, and Coincident Slave Rails
For coincident tracking, connect the SS/TRK input of the slave regulator to a resistor divider from the output
voltage of the master that is the same as the divider used on the FB pin of the slave. In other words, simply
select RTRK3 = RFB3 and RTRK4 = RFB4 as shown in . As the master voltage rises, the slave voltage rises
identically (aside from the 80-mV offset from SS/TRK to FB when VFB is below 0.8 V). Eventually, the slave
voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the
SS/TRK input continues to 115 mV above FB, and no longer controls the output voltage.
In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRK voltage being too
close to the 0.8-V reference voltage, the final value of the SS/TRK voltage of the slave should be at least 100 mV
above FB.
8.3.8 Voltage-Mode Control (COMP)
The LM25145 incorporates a voltage-mode control loop implementation with input voltage feedforward to
eliminate the input voltage dependence of the PWM modulator gain. This configuration allows the controller to
maintain stability throughout the entire input voltage operating range and provides for optimal response to input
voltage transient disturbances. The constant gain provided by the controller greatly simplifies loop compensation
design because the loop characteristics remain constant as the input voltage changes, unlike a buck converter
without voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage
amplitude to maintain constant modulator gain. The input voltage feedforward gain, kFF, is 15, equivalent to the
input voltage divided by the ramp amplitude, VIN/VRAMP. See Control Loop Compensation for more detail.
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8.3.9 Gate Drivers (LO, HO)
The LM25145 gate driver impedances are low enough to perform effectively in high output current applications
where large die-size or paralleled MOSFETs with correspondingly large gate charge, QG, are used. Measured at
VVCC = 7.5 V, the low-side driver of the LM25145 has a low impedance pulldown path of 0.9 Ω to minimize the
effect of dv/dt induced turnon, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side
driver has 1.5-Ω and 0.9-Ω pullup and pulldown impedances, respectively, for faster switching transition times,
lower switching loss, and greater efficiency.
The high-side gate driver works in conjunction with an integrated bootstrap diode and external bootstrap
capacitor, CBST. When the low-side MOSFET conducts, the SW voltage is approximately at 0 V and CBST is
charged from VCC through the integrated boot diode. Connect a 0.1-μF or larger ceramic capacitor close to the
BST and SW pins.
Furthermore, there is a proprietary adaptive dead-time control on both switching edges to prevent shoot-through
and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery losses.
8.3.10 Current Sensing and Overcurrent Protection (ILIM)
The LM25145 implements a lossless current sense scheme designed to limit the inductor current during an
overload or short-circuit condition. Figure 38 portrays the popular current sense method using the on-state
resistance of the low-side MOSFET. Meanwhile, Figure 39 shows an alternative implementation with current
shunt resistor, RS. The LM25145 senses the inductor current during the PWM off-time (when LO is high).
VIN
VIN
Q1
Q1
Q2
LF
HO
LO
HO
LF
VOUT
VOUT
SW
SW
RILIM
ILIM
COUT
COUT
ILIM
Q2
RILIM
RS
LO
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
Figure 39. Shunt Resistor Current Sensing
Figure 38. MOSFET RDS(on) Current Sensing
The ILIM pin of the LM25145 sources a reference current that flows in an external resistor, designated RILIM, to
program of the current limit threshold. A current limit comparator on the ILIM pin prevents further SW pulses if
the ILIM pin voltage goes below GND. Figure 40 shows the implementation.
Resistor RILIM is tied to SW to use the RDS(on) of the low-side MOSFET as a sensing element (termed RDS-ON
mode). Alternatively, RILIM is tied to a shunt resistor connected at the source of the low-side MOSFET (termed
RSENSE mode). The LM25145 detects the appropriate mode at start-up and sets the source current amplitude and
temperature coefficient (TC) accordingly.
The ILIM current with RDS-ON sensing is 200 µA at 27°C junction temperature and incorporates a TC of +4500
ppm/°C to generally track the RDS(on) temperature variation of the low-side MOSFET. Conversely, the ILIM
current is a constant 100 µA in RSENSE mode. This controls the valley of the inductor current during a steady-
state overload at the output. Depending on the chosen mode, select the resistance of RILIM using Equation 6.
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I
- DIL
IRDSON
2
2
À OUT
∂RDS(on)Q2, RDS(on) sensing
∂RS, shunt sensing
Œ
Œ
RILIM
=
Ã
I
- DIL
IRS
Œ OUT
Œ
Õ
where
•
•
•
•
•
ΔIL is the peak-to-peak inductor ripple current
RDS(on)Q2 is the on-state resistance of the low-side MOSFET
IRDSON is the ILIM pin current in RDS-ON mode
RS is the resistance of the current-sensing shunt element, and
IRS is the ILIM pin current in RSENSE mode.
(6)
Given the large voltage swings of ILIM in RDS-ON mode, a capacitor designated CILIM connected from ILIM to
PGND is essential to the operation of the valley current limit circuit. Choose this capacitance such that the time
constant RILIM · CILIM is approximately 6 ns.
VIN
S
R
Q
Q
CLK
ValleyPWM
COMP
FB
Q1
PWML
HO
SW
Error Amp
+
IRAMP
LF
S
R
Q
Q
PWM Comp
Gate
VOUT
Driver
VREF
+
PWM
Latch
VRAMP
Q2
LO
COUT
RILIM
ILIM
IRDSON(TJ)
+
œ
300 mV
PWM Aux
CILIM
+
+
COMP
Clamp
ILIM
comparator
PGND
VCLAMP
GND
Modulator
Copyright © 2017, Texas Instruments Incorporated
Figure 40. OCP Setpoint Defined by Current Source IRDSON and Resistor RILIM in RDS-ON Mode
Note that current sensing with a shunt component is typically implemented at lower output current levels to
provide accurate overcurrent protection. Burdened by the unavoidable efficiency penalty, PCB layout, and
additional cost implications, this configuration is not usually implemented in high-current applications (except
where OCP setpoint accuracy and stability over the operating temperature range are critical specifications).
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8.3.11 OCP Duty Cycle Limiter
Short
Applied
CLAMP
COMP
Many
cycles
RAMP
300 mV
ILIM Threshold
Inductor Current
CLK
PWML
ValleyPWM
PWML terminated by
VRAMP > VCOMP
PWML terminated by
VRAMP > VCLAMP
Figure 41. OCP Duty Cycle Limiting Waveforms
In addition to valley current limiting, the LM25145 uses a proprietary duty-cycle limiter circuit to reduce the PWM
on-time during an overcurrent condition. As shown in Figure 40, an auxiliary PWM comparator along with a
modulated CLAMP voltage limits how quickly the on-time increases in response to a large step in the COMP
voltage that typically occurs with a voltage-mode control loop architecture.
As depicted in Figure 41, the CLAMP voltage, VCLAMP, is normally regulated above the COMP voltage to provide
adequate headroom during a response to a load-on transient. If the COMP voltage rises quickly during an
overloaded or shorted output condition, the on-time pulse terminates thereby limiting the on-time and peak
inductor current. Moreover, the CLAMP voltage is reduced if additional valley current limit events occur, further
reducing the average output current.
If the overcurrent condition exists for 128 continuous clock cycles, a hiccup event is triggered and SS is pulled
low for 8192 clock cycles before a soft-start sequence is initiated.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN/UVLO pin provides ON / OFF control for the LM25145. When the EN/UVLO voltage is below 0.37 V
(typical), the device is in shutdown mode. Both the internal bias supply LDO and the switching regulator are off.
The quiescent current in shutdown mode drops to 13.5 μA (typical) at VIN = 24 V. The LM25145 also includes
undervoltage protection of the internal bias LDO. If the internal bias supply voltage is below its UVLO threshold
level, the switching regulator remains off.
8.4.2 Standby Mode
The internal bias supply LDO has a lower enable threshold than the switching regulator. When the EN/UVLO
voltage exceeds 0.42 V (typical) and is below the precision enable threshold (1.2 V typically), the internal LDO is
on and regulating. Switching action and output voltage regulation are disabled in standby mode.
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Device Functional Modes (continued)
8.4.3 Active Mode
The LM25145 is in active mode when the VCC voltage is above its rising UVLO threshold of 5 V and the
EN/UVLO voltage is above the precision EN threshold of 1.2 V. The simplest way to enable the LM25145 is to tie
EN/UVLO to VIN. This allows self start-up of the LM25145 when the input voltage exceeds the VCC threshold
plus the LDO dropout voltage from VIN to VCC.
8.4.4 Diode Emulation Mode
The LM25145 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source)
current flow in the low-side MOSFET. When configured for diode emulation, the low-side MOSFET is switched
off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The
benefit of this configuration is lower power loss at no-load and light-load conditions, the disadvantage being
slower light-load transient response.
The diode emulation feature is configured with the SYNCIN pin. To enable diode emulation and thus achieve
discontinuous conduction mode (DCM) operation at light loads, connect the SYNCIN pin to AGND or leave
SYNCIN floating. If forced PWM (FPWM) continuous conduction mode (CCM) operation is desired, tie SYNCIN
to VCC either directly or using a pullup resistor. Note that diode emulation mode is automatically engaged to
prevent reverse current flow during a prebias start-up. A gradual change from DCM to CCM operation provides
monotonic start-up performance.
8.4.5 Thermal Shutdown
The LM25145 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical),
thermal shutdown occurs.
When entering thermal shutdown, the device:
1. Turns off the low-side and high-side MOSFETs;
2. Pulls SS/TRK and PGOOD low;
3. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of
20°C (typical).
This is a non-latching protection, and, as such, the device will cycle into and out of thermal shutdown if the fault
persists.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Design and Implementation
To expedite the process of designing of a LM25145-based regulator for a given application, please use the
LM25145 Quickstart Calculator available as a free download, as well as numerous LM25145 reference designs
populated in TI Designs™ reference design library, or the designs provided in Typical Applications. The
LM25145 is also WEBENCH® Designer enabled.
9.1.2 Power Train Components
Comprehensive knowledge and understanding of the power train components are key to successfully completing
a synchronous buck regulator design.
9.1.2.1 Inductor
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 40%
of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 7 based on a
peak inductor current given by Equation 8.
≈
’
÷
◊
VOUT V - VOUT
IN
LF =
∂
∆
«
V
DIL ∂FSW
DIL
IN
(7)
(8)
IL(peak) = IOUT
+
2
Check the inductor datasheet to ensure that the saturation current of the inductor is well above the peak inductor
current of a particular design. Ferrite designs have very low core loss and are preferred at high switching
frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core
loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core
materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not
to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally deceases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
9.1.2.2 Output Capacitors
Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series
resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient
response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and
noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact
footprint for transient loading events.
Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by Equation 9.
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Application Information (continued)
DIL
2
COUT
í
2
8 ∂FSW DVOUT - RESR ∂ DIL
(9)
Figure 42 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to
match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of
charge in the output capacitor, which must be replenished as rapidly as possible during and after the load step-
up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current
adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
diL
dt
VOUT
LF
= -
inductor current, iL(t)
DIOUT
DQC
IOUT2
load current,
iOUT(t)
diOUT DIOUT
=
dt
tramp
inductor current, iL(t)
IOUT2
DQC
diL
dt
VIN - VOUT
DIOUT
=
load current, iOUT(t)
LF
IOUT1
tramp
Figure 42. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 24-V input to low output voltage (for example, 5 V), it should be recognized
that the load-off transient represents worst-case. In that case, the steady-state duty cycle is approximately 10%
and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –VOUT/L.
Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The
surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete
this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its
nominal level following the load step. In this scenario, a large output capacitance can be advantageously
employed to absorb the excess charge and limit the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger than
2
LF ∂ DIOUT
COUT
í
2
2
V
+ DVOVERSHOOT - VOUT
OUT
(10)
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors
have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some
parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and
ESL contributions at the switching frequency, and the capacitive impedance component dominates. However,
depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite
significantly with applied DC voltage and operating temperature.
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Application Information (continued)
Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary to
meet the output ripple specification. One to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a
common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the load-off
transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and
ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance
provides low-frequency energy storage to cope with load transient demands.
9.1.2.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-
frequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in
the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and
the source of the low-side MOSFET. The input capacitor RMS current is given by Equation 11.
DIL2
12
≈
’
ICIN,rms = D∂ IOUT2 ∂ 1-D +
∆
÷
÷
◊
(
)
∆
«
(11)
The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the
capacitors should be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT
−
IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by Equation 12.
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(12)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 13.
D∂ 1-D ∂I
(
)
OUT
CIN
í
FSW ∂ DV -RESR ∂IOUT
IN
(13)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with
high-Q ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2-μF 100-V X7R
ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current
rating and operating temperature.
9.1.2.4 Power MOSFETs
The choice of power MOSFETs has significant impact on DC-DC regulator performance. A MOSFET with low on-
state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition
times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate charge and
output charge (QG and QOSS respectively), and vice versa. As a result, the product RDS(on) × QG is commonly
specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power dissipation
does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in an LM25145 application are as follows:
•
•
RDS(on) at VGS = 7.5 V;
Drain-source voltage rating, BVDSS, typically 30 V, 40 V or 60 V, depending on maximum input voltage;
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Application Information (continued)
•
•
•
•
Gate charge parameters at VGS = 7.5 V;
Output charge, QOSS, at the relevant input voltage;
Body diode reverse recovery charge, QRR
Gate threshold voltage, VGS(th), derived from the plateau in the QG vs. VGS plot in the MOSFET data sheet.
With a MOSFET Miller plateau voltage typically in the range of 3 V to 5 V, the 7.5-V gate drive amplitude of
the LM25145 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt shoot-
through when off.
;
The MOSFET-related power losses are summarized by the equations presented in Table 2, where suffixes 1 and
2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple
current is considered, second-order loss modes, such as those related to parasitic inductances and SW node
ringing, are not included. Consult the LM25145 Quickstart Calculator to assist with power loss calculations.
Table 2. Buck Regulator MOSFET Power Losses
POWER LOSS MODE
HIGH-SIDE MOSFET
LOW-SIDE MOSFET
DIL2
12
DIL2
12
≈
’
≈
∆
’
2
2
MOSFET
∆
÷
÷
◊
Å
÷
÷
◊
P
= D∂ IOUT
+
∂RDS(on)1
P
= D ∂ IOUT
+
∂RDS(on)2
Conduction(1)(2)
cond1
cond2
∆
«
∆
«
»
…
ÿ
F Ÿ
⁄
DIL
2
DIL
2
≈
’
≈
’
P
= VIN ∂FSW
I
-
∂ tR + I
∆ OUT
+
∂ t
MOSFET Switching
Negligible
sw1
∆ OUT
÷
◊
÷
◊
«
«
MOSFET Gate Drive(3)
PGate1 = VCC ∂FSW ∂QG1
PCoss = FSW ∂ V ∂Q
PGate2 = VCC ∂FSW ∂QG2
MOSFET Output
Charge(4)
+ Eoss1 -Eoss2
IN
oss2
»
≈
ÿ
dt2 Ÿ
⁄
DIL
2
DIL
2
’
≈
’
Body Diode
Conduction
P
= VF ∂FSW
I
+
∂ tdt1 + I
∆ OUT
-
∂ t
N/A
…
condBD
∆ OUT
÷
◊
÷
◊
«
«
Body Diode
PRR = V ∂FSW ∂QRR2
Reverse Recovery(5)
IN
(1) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance.
(2) D' = 1–D is the duty cycle complement.
(3) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally-added series gate resistance and the
relevant driver resistance of the LM25145.
(4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the
inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance
of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this is offset by the stored energy Eoss2 on Coss2
.
(5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition speed
and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically
incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances
conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of
the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the
net loss attributed to body diode reverse recovery.
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D
interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just
commutates from the channel to the body diode or vice versa during the transition dead-times. The LM25145,
with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such
losses scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM25145 is well suited to drive TI's comprehensive portfolio of NexFET™ power
MOSFETs.
30
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9.1.3 Control Loop Compensation
The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue
dashed rings in the schematic embedded in Table 3.
The compensation network typically employed with voltage-mode control is a Type-III circuit with three poles and
two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation
strategy uses two compensator zeros to counteract the LC double pole, one compensator pole located to nullify
the output capacitor ESR zero, with the remaining compensator pole located at one-half switching frequency to
attenuate high frequency noise. The resistor divider network to FB determines the desired output voltage. Note
that the lower feedback resistor, RFB2, has no impact on the control loop from an AC standpoint because the FB
node is the input to an error amplifier and is effectively at AC ground. Hence, the control loop is designed
irrespective of output voltage level. The proviso here is the necessary output capacitance derating with bias
voltage and temperature.
Table 3. Buck Regulator Poles and Zeros(1)(2)
VIN
Power Stage
Q1
&
&
L
o
D
VOUT
Adaptive
Gate
Driver
LF
&
RESR
ESR
RDAMP
IOUT
RL
Q2
Modulator
COUT
GND
PWM Ramp
VRAMP
Compensator
Error
Amp
VREF
CC3
&
p2 RC2
+
COMP
CC1
+
FB
PWM
Comparator
&
z1
RC1
&
z2
RFB1
RFB2
&
CC2
p1
POWER STAGE POLES
POWER STAGE ZEROS
COMPENSATOR POLES
COMPENSATOR ZEROS
1
1
1
1
wo
=
@
wESR
=
wp1
=
wz1 =
RESR ∂COUT
RC2 ∂CC3
RC1 ∂CC1
≈
∆
«
’
÷
◊
1+ RESR RL
1+ RESR RDAMP
LF ∂COUT
LF
1
1
1
1
wp2
=
@
wz2
=
wL
=
RC1 ∂(CC1 CC2
)
RC1 ∂CC2
(RFB2 + RC2 )∂CC3
RDAMP
LF ∂COUT
(1) RESR represents the ESR of the output capacitor COUT
.
(2) RDAMP = D · RDS(on)high-side + (1–D) · RDS(on) low-side + RDCR, shown as a lumped element in the schematic, represents the effective series
damping resistance.
The small-signal open-loop response of a buck regulator is the product of modulator, power train and
compensator transfer functions. The power stage transfer function can be represented as a complex pole pair
associated with the output LC filter and a zero related to the ESR of the output capacitor. The DC (and low
frequency) gain of the modulator and power stage is VIN/VRAMP. The gain from COMP to the average voltage at
the input of the LC filter is held essentially constant by the PWM line feedforward feature of the LM25145 (15 V/V
or 23.5 dB).
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Complete expressions for small-signal frequency analysis are presented in Table 4. The transfer functions are
denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by
its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio
susceptibility.
Table 4. Buck Regulator Small-Signal Analysis
TRANSFER FUNCTION
EXPRESSION
Ù
Ù
vcomp(s)
Ù
vo(s)
d(s)
Tv (s) =
∂
∂
= Gc (s)∂Gvd(s)∂FM
Open-loop transfer function
Ù
Ù
Ù
vo(s)
vcomp(s)
d(s)
s
1+
Ù
vo(s)
wESR
Gvd(s) =
= V
IN
Duty-cycle-to-output transfer function
Ù
Ù
vin(s)=0
d(s)
s
s2
wo2
Ù
1+
+
io (s)=0
Qowo
≈
∆
«
’
÷
◊
wz1
s
≈
’
s
1+
1+
1+
∆
÷
Ù
vcomp(s)
wz2
«
◊
Compensator transfer function(1)
Modulator transfer function
Gc (s) =
= Kmid
Ù
vo(s)
≈
’≈
’
s
s
1+
∆
∆
«
÷∆
÷∆
◊«
÷
÷
◊
wp1
wp2
Ù
d(s)
1
FM =
=
Ù
vcomp(s) VRAMP
(1) Kmid = RC1/RFB1 is the mid-band gain of the compensator. By expressing one of the compensator zeros in inverted zero format, the mid-
band gain is denoted explicitly.
An illustration of the open-loop response gain and phase is given in Figure 43. The poles and zeros of the
system are marked with x and o symbols, respectively, and a + symbol indicates the crossover frequency. When
plotted on a log (dB) scale, the open-loop gain is effectively the sum of the individual gain components from the
modulator, power stage, and compensator (see Figure 44). The open-loop response of the system is measured
experimentally by breaking the loop, injecting a variable-frequency oscillator signal and recording the ensuing
frequency response using a network analyzer setup.
40
20
0
0
Loop
Gain
Complex
LC Double
Pole
Crossover
Frequency, fc
-45
Compensator
Poles
Loop
Phase
(°)
Loop
Gain
(dB)
Compensator
Zeros
-90
Loop
Phase
NM
-135
-20
-40
Output
Capacitor
ESR Zero
-180
1
10
100
1000
Frequency (kHz)
Figure 43. Typical Buck Regulator Loop Gain and Phase With Voltage-Mode Control
If the pole located at ωp1 cancels the zero located at ωESR and the pole at ωp2 is located well above crossover,
the expression for the loop gain, Tv(s) in Table 4, can be manipulated to yield the simplified expression given in
Equation 14.
32
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V
wo2
s
IN
Tv (s) = RC1 ∂CC3
∂
∂
VRAMP
(14)
Essentially, a multi-order system is reduced to a single-order approximation by judicious choice of compensator
components. A simple solution for the crossover frequency, denoted as fc in Figure 43, with Type-III voltage-
mode compensation is derived as shown in Equation 15 and Equation 16.
V
IN
wc = 2p ∂ fc = wo ∂Kmid ∂
VRAMP
(15)
(16)
fc
RC1
1
Kmid
=
∂
=
fo kFF RFB1
40
20
0
Loop Gain
Modulator
Gain
Compensator
Gain
Gain
(dB)
-20
Filter Gain
-40
fc
1
10
100
1000
Frequency (kHz)
Figure 44. Buck Regulator Constituent Gain Components
The loop crossover frequency is usually selected between one-tenth to one-fifth of switching frequency. Inserting
an appropriate crossover frequency into Equation 15 gives a target for the mid-band gain of the compensator,
Kmid. Given an initial value for RFB1, RFB2 is then selected based on the desired output voltage. Values for RC1
,
RC2, CC1, CC2 and CC3 are calculated from the design expressions listed in Table 5, with the premise that the
compensator poles and zeros are set as follows: ωz1 = 0.5·ωo, ωz2 = ωo, ωp1 = ωESR, ωp2 = ωSW/2.
Table 5. Compensation Component Selection
RESISTORS
CAPACITORS
RFB1
2
RFB2
=
CC1
=
V
VREF -1
wz1 ∂RC1
OUT
1
CC2
=
RC1 = Kmid ∂RFB1
wp2 ∂RC1
1
1
RC2
=
CC3
=
wp1 ∂CC3
w
z2 ∂RFB1
Referring to the bode plot in Figure 43, the phase margin, indicated as φM, is the difference between the loop
phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase
boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole (hence why
CC1 is scaled by a factor of 2 above). This helps mitigate the phase dip associated with the LC filter, particularly
at light loads when the Q-factor is higher and the phase dip becomes especially prominent. The ramification of
low phase in the frequency domain is an under-damped transient response in the time domain.
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The power supply designer now has all the necessary expressions to optimally position the loop crossover
frequency while maintaining adequate phase margin over the required line, load and temperature operating
ranges. The LM25145 Quickstart Calculator is available to expedite these calculations and to adjust the bode plot
as needed.
9.1.4 EMI Filter Design
Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An
underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the
filter output impedance must be less than the absolute value of the converter input impedance.
2
V
IN(min)
ZIN = -
P
IN
(17)
The EMI filter design steps are as follows:
•
•
•
Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the
existing capacitance at the input of the switching converter;
Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a
high current design;
Calculate input filter capacitor CF.
LIN
Q1
VIN
LF
CD
VOUT
CF
CIN
Q2
COUT
RD
GND
GND
Figure 45. Buck Regulator With π-Stage EMI Filter
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by Equation 18.
≈
’
IPEAK
2 ∂FSW ∂CIN
∆
∆
«
÷
Attn = 20log
∂1ꢀV ∂sin
p
∂DMAX - V
(
)
MAX
÷
◊
p
(18)
VMAX is the allowed dBμV noise level for the applicable EMI standard, for example EN55022 Class B. CIN is the
existing input capacitance of the buck regulator, DMAX is the maximum duty cycle, and IPEAK is the peak inductor
current. For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI
filter capacitance CF from Equation 19.
2
Attn
≈
∆
∆
’
÷
÷
40
1
10
CF =
LIN
2p
∂FSW
∆
∆
«
÷
÷
◊
(19)
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop
gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the
filter is given by Equation 20.
34
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1
fres
=
2p
∂ LIN ∂CF
(20)
The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD should
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added damping is
needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and
CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 21.
CD í 4 ∂CIN
(21)
Select the damping resistor RD using Equation 22.
LIN
RD =
CIN
(22)
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9.2 Typical Applications
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of
an LM25145-powered implementation, please refer to TI Designs reference design library.
9.2.1 Design 1 – 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications
Figure 46 shows the schematic diagram of a 5-V, 20-A buck regulator with a switching frequency of 500 kHz. In
this example, the target full-load efficiency is 94% at a nominal input voltage of 24 V that ranges from 6.5 V to as
high as 32 V. The switching frequency is set by means of a synchronization input signal at 500 kHz, and the free-
running switching frequency (in the event that the synchronization signal is removed) is set at 450 kHz by resistor
RRT. In terms of control loop performance, the target loop crossover frequency is 70 kHz with a phase margin
greater than 50°. The output voltage soft-start time is 4 ms.
RUV2
RUV1
11.3 kꢁ
49.9 kꢁ
VIN = 6.5 V to 32 V
CVIN
0.1 ꢀF
VOUT
U1
CBST
0.1 ꢀF
1
20
RRT
RC2
RFB1
23.2 kꢁ
22.1 kꢁ
200 ꢁ
Q1
EN/UVLO
VIN
RT
2
3
4
5
6
7
17
18
19
BST
HO
CC3
560 pF
CSS
47 nF
CC1
3.3 nF
RC1
8.87 kꢁ
SS/TRK
LF
1 ꢀH
VOUT = 5 V
IOUT = 20 A
COMP
FB
SW
NC 16
EP 15
CC2
68 pF
LM25145
Q2
AGND
RFB2
4.42 kꢁ
CIN
7 ì 10 ꢀF
COUT
7 ì 47 ꢀF
SYNC Out
SYNCOUT
14
13
12
VCC
LO
8
9
SYNCIN
NC
SYNC In
500 kHz
PGND
ILIM
11
PGOOD
GND
10
CVCC
2.2 ꢀF
RPG
49.9 kꢁ
RILIM
PGOOD
249 ꢁ
CILIM
22 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 46. Application Circuit #1 With LM25145 24-V to 5-V, 20-A Buck Regulator at 500 kHz
NOTE
This and subsequent design examples are provided herein to showcase the LM25145
controller in several different applications. Depending on the source impedance of the
input supply bus, an electrolytic capacitor may be required at the input to ensure stability,
particularly at low input voltage and high output current operating conditions. See Power
Supply Recommendations for more detail.
36
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LM25145
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9.2.1.1 Design Requirements
The intended input, output, and performance-related parameters pertinent to this design example are shown in
Table 6.
Table 6. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Input transient voltage (peak)
Output voltage and current
VALUE
6.5 V to 32 V
42 V
5 V, 20 A
6.5 V on, 6 V off
500 kHz
Input voltage UVLO thresholds
Switching frequency (SYNC in)
Output voltage regulation
±1%
Load transient peak voltage deviation
< 100 mV
9.2.1.2 Detailed Design Procedure
The design procedure for an LM25145-based regulator for a given application is streamlined by using the
LM25145 Quickstart Calculator available as a free download, or by availing of TI's WEBENCH® Power Designer.
The selected buck converter powertrain components are cited in Table 7, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching
power loss, as discussed in detail in Power MOSFETs.
The current limit setpoint in this design is set at 26 A based on the resistor RILIM and the 2-mΩ RDS(on) of the low-
side MOSFET (typical at TJ = 25°C and VGS = 7.5 V). This design uses a low-DCR, metal-powder inductor and
an all-ceramic output capacitor implementation.
Table 7. List of Materials for Design 1
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
TDK
Murata
C3225X7R1H106M
GRM32ER71H106KA12L
12105C106KAT2A
CIN
7
10 µF, 50 V, X7R, 1210, ceramic
AVX
Kemet
C1210C106K5RACTU
UMK325AB7106MM-T
GRM32ER71A476KE15L
LMK325B7476MM-TR
1210ZC476KAT2A
C1210C476M8RAC7800
CMLE104T-1R0MS2R307
WE HCI 744325120
ETQP5M1R0YLC
Taiyo Yuden
Murata
Taiyo Yuden
AVX
COUT
7
1
47 µF, 10 V, X7R, 1210, ceramic
Kemet
1 µH, 2.3 mΩ, 40 A, 11.15 × 10 × 3.8 mm
1.2 µH, 1.8 mΩ, 25 A, 10.2 × 10.2 × 4.7 mm
1 µH, 2.3 mΩ, 38 A, 10.9 × 10 × 5.0 mm
1 µH, 2.2 mΩ, 36 A, 10.5 × 10 × 6.5 mm
40 V, 3.7 mΩ, high-side MOSFET, SON 5 × 6
40 V, 2 mΩ, low-side MOSFET, SON 5 × 6
Wide VIN synchronous buck controller
Cyntec
Würth Electronik
Panasonic
TDK
LF
SPM10065VT-D
Q1
Q2
U1
1
1
1
Texas Instruments
Texas Instruments
Texas Instruments
CSD18503Q5A
CSD18511Q5A
LM25145RGYR
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9.2.1.3 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25145 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.4 Application Curves
100
95
90
85
80
75
70
65
100
90
80
70
60
50
40
30
20
VIN = 8V
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 32V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 32V
0
5
10
15
20
0.1
0.5
1
5
10
20
Output Current (A)
Output Current (A)
SYNCIN tied to VCC
SYNCIN tied to GND
Figure 47. Efficiency and Power Loss vs IOUT and VIN, CCM
Figure 48. Efficiency and Power Loss vs IOUT and VIN, DCM
VOUT 1V/DIV
VOUT 1V/DIV
VIN 2V/DIV
VIN 5V/DIV
PGOOD 5V/DIV
IOUT 5A/DIV
PGOOD
5V/DIV
IOUT 5A/DIV
400 ms/DIV
1 ms/DIV
VIN step to 24 V
0.25-Ω Load
VIN 24 V to 6 V
0.25-Ω Load
Figure 49. Start-Up, 20-A Resistive Load
Figure 50. Shutdown Through Input UVLO, 20-A Resistive
Load
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VOUT 1V/DIV
IOUT 5A/DIV
VOUT 1V/DIV
ENABLE
1V/DIV
IOUT 5A/DIV
PGOOD
5V/DIV
ENABLE
1V/DIV
PGOOD
5V/DIV
1 ms/DIV
100 ms/DIV
VIN = 24 V
0.25-Ω Load
Figure 51. ENABLE ON, 20-A Resistive Load
VIN = 24 V
0.25-Ω Load
Figure 52. ENABLE OFF, 20-A Resistive Load
VOUT 200m/DIV
VOUT 100m/DIV
IOUT 5A/DIV
IOUT 5A/DIV
40 ms/DIV
40 ms/DIV
VIN = 24 V
VIN = 24 V
Figure 53. Load Transient Response, 10 A to 20 A to 10 A
Figure 54. Load Transient Response, 0 A to 20 A to 0 A
SYNCOUT
SW 5V/DIV
1V/DIV
SW 5V/DIV
400 ns/DIV
1 ms/DIV
VIN = 24 V
IOUT = 0 A
Figure 55. SYNCOUT and SW Node Voltages
VIN = 24 V
IOUT = 20 A
Figure 56. SW Node Voltage
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9.2.2 Design 2 – High Density, 12-V, 8-A Rail With LDO Low-Noise Auxiliary Output for Industrial
Applications
Figure 57 shows the schematic diagram of a 425-kHz, 12-V output, 8-A synchronous buck regulator intended for
RF power applications.
An auxiliary 10-V, 800-mA rail to power noise-sensitive circuits is available using the LP38798 ultra-low noise
LDO as a post-regulator. The internal pullup of the EN pin of the LP38798 facilitates direct connection to the
PGOOD of the LM25145 for sequential start-up control.
RUV2
RUV1
7.5 kꢁ
80.6 kꢁ
VIN = 14.4 V to 36 V
CVIN
VOUT
0.1 ꢀF
U1
1
20
RRT
RC2
RFB1
21 kꢁ
23.7 kꢁ
100 ꢁ
EN/UVLO
VIN
Q1
RT
2
3
4
5
6
7
17
18
19
BST
HO
CC3
CSS
47 nF
RC1
10 kꢁ
CC1
5.6 nF
SS/TRK
820 pF
LF
5.6 ꢀH
VOUT1 = 12 V
IOUT1 = 8 A
CBST
0.1 ꢀF
COMP
FB
SW
NC 16
EP 15
CC2
82 pF
LM25145
Q2
AGND
RFB2
1.5 kꢁ
CIN
COUT
SYNCOUT
SYNC Out
SYNC In
14
13
12
VCC
LO
4 ì 22 ꢀF
4 ì 10 ꢀF
8
9
SYNCIN
NC
PGND
ILIM
11
PGOOD
10
CVCC
GND
2.2 ꢀF
RILIM
499 ꢁ
CILIM
12 pF
U2
VOUT2 = 10V
1
18
17
16
15
14
13
VOUT1
IN
OUT
OUT
2
3
4
5
6
IN
CV2
OUT(FB)
IN(CP)
CP
CLDO_IN
1 ꢀF
RT
CCP
1 ꢀF
73.5 kꢁ
SET
FB
10 nF
RB
EN
10 kꢁ
GND(CP)
GND
LP38798SD-ADJ
Copyright © 2017, Texas Instruments Incorporated
Figure 57. Application Circuit #2 With LM25145 24-V to 12-V Synchronous Buck Regulator at 425 kHz
40
Copyright © 2017, Texas Instruments Incorporated
LM25145
www.ti.com.cn
ZHCSGD0 –JUNE 2017
9.2.2.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in Table 8.
Table 8. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Input transient voltage (peak)
VALUE
14.4 V to 36 V
42 V
Output voltage and current
12 V, 8 A
Input UVLO thresholds
14 V on, 13.2 V off
425 kHz
Switching frequency
Output voltage regulation
±1%
Load transient peak voltage deviation, 4-A load step, 1 A/µs
< 150 mV
9.2.2.2 Detailed Design Procedure
A high power density, high-efficiency regulator solution is realized by using TI NexFET™ Power MOSFETs, such
as CSD18543Q3A (60-V, 8.5-mΩ MOSFET in a SON 3.3-mm × 3.3-mm package), together with a low-DCR
inductor and all-ceramic capacitor design. The design occupies 15 mm × 15 mm on a single-sided PCB. The
overcurrent (OC) setpoint in this design is set at 11 A based on the resistor RILIM and the 8.5-mΩ RDS(on) of the
low-side MOSFET (typical at TJ = 25°C and VGS = 7.5 V). Connecting VCC to either VOUT1 or VOUT2 using a
series diode reduces bias power dissipation and improves efficiency, especially at light loads.
The selected buck converter powertrain components are cited in Table 9, including power MOSFETs, buck
inductor, input and output capacitors, and ICs. Using the LM25145 Quickstart Calculator, compensation
components are selected based on a target loop crossover frequency of 70 kHz and phase margin greater than
55°. The output voltage soft-start time is 4 ms based on the selected soft-start capacitance, CSS, of 47 nF.
Table 9. List of Materials for Design 2
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
TDK
Murata
C3225X7R1H106M
GRM32ER71H106KA12L
12105C106KAT2A
GRM32ER71E226KE15L
TMK325B7226MM-TR
C3225X7R1E226M
CMLS104T-5R6MS
MPT1040-5R6H1
CIN
4
10 µF, 50 V, X7R, 1210, ceramic
AVX
Murata
COUT
4
1
22 µF, 25 V, X7R, 1210, ceramic
Taiyo Yuden
TDK
5.6 µH, 17 mΩ, 18 A, 10.85 × 10 × 3.8 mm
5.6 µH, 20 mΩ, 14 A, 10.85 × 10 × 3.8 mm
5.6 µH, 16 mΩ, 12 A, 10.7 × 10 × 4 mm
5.6 µH, 19.3 mΩ, 16 A, 11 × 10 × 4 mm
6.8 µH, 17.5 mΩ, 14 A, 11 × 10 × 3.8 mm
6.8 µH, 17.9 mΩ, 25 A, 10.5 × 10 × 4 mm
6.8 µH, 18.3 mΩ, 12.1 A, 10.7 × 10 × 4 mm
60 V, 8 mΩ, MOSFET, SON 3 × 3
Cyntec
Delta
Bourns
SRP1040-5R6M
LF
Laird
MGV10045R6M-10
WE-LHMI 74437368068
SPM10040VT-6R8M-D
ETQP4M6R8KVC
Würth Electronik
TDK
Panasonic
Texas Instruments
Texas Instruments
Q1, Q2
U1
2
1
CSD18543Q3A
Wide VIN synchronous buck controller
LM25145RGYR
Ultra-low noise and high-PSRR LDO for RF and
analog circuits, 4-mm × 4-mm 12-pin WSON
U2
1
Texas Instruments
LP38798SD-ADJ
If needed, a 2.2-Ω resistor can be added in series with CBST is used to slow the turn-on transition of the high-side
MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of
Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and
100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate
any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI
and Voltage Stress by Minimizing Inductive Parasitics for more detail.
Copyright © 2017, Texas Instruments Incorporated
41
LM25145
ZHCSGD0 –JUNE 2017
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9.2.2.2.1 Application Curves
100
95
90
85
80
75
70
SYNCOUT
1V/DIV
SW 10V/DIV
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
0
2
4
6
8
1 ms/DIV
Output Current (A)
VIN = 24 V
IOUT = 4 A
Figure 59. SYNCOUT and SW Node Voltages
Figure 58. Efficiency vs IOUT and VIN
VOUT 2V/DIV
VOUT 2V/DIV
VIN 5V/DIV
VIN 5V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
PGOOD 5V/DIV
PGOOD 5V/DIV
1 ms/DIV
100 ms/DIV
VIN step to 24 V
1.5-Ω Load
1.5-Ω Load
Figure 60. Start-Up, 8-A Resistive Load
Figure 61. Shutdown Through Input UVLO, 8-A Resistive
Load
VOUT 2V/DIV
IOUT 2A/DIV
VOUT 2V/DIV
IOUT 2A/DIV
ENABLE
1V/DIV
PGOOD
2V/DIV
ENABLE
1V/DIV
PGOOD 2V/DIV
1 ms/DIV
100 ms/DIV
VIN = 24 V
1.5-Ω Load
Figure 62. ENABLE ON, 8-A Resistive Load
VIN = 24 V
1.5-Ω Load
Figure 63. ENABLE OFF, 8-A Resistive Load
42
Copyright © 2017, Texas Instruments Incorporated
LM25145
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ZHCSGD0 –JUNE 2017
VOUT 2V/DIV
VOUT 20mV/DIV
PGOOD 2V/DIV
EN 1V/DIV
SW 10V/DIV
1 ms/DIV
1 ms/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
IOUT = 0 A
Figure 64. Pre-Biased Start-Up
Figure 65. SW Node and VOUT Ripple
VOUT 200m/DIV
VOUT 200m/DIV
IOUT 2A/DIV
IOUT 2A/DIV
40 ms/DIV
40 ms/DIV
VIN = 24 V
VIN = 24 V
Figure 66. Load Transient Response, 4 A to 8 A to 4 A
Figure 67. Load Transient Response, 0.8 A to 8 A to 0.8 A
VOUT 100mV/DIV
VOUT 100mV/DIV
IOUT 2A/DIV
VIN 10V/DIV
IOUT 2A/DIV
VIN 10V/DIV
200 ms/DIV
200 ms/DIV
IOUT = 8 A
Figure 68. Line Transient Response, 18 V to 36 V
IOUT = 8 A
Figure 69. Line Transient Response, 36 V to 18 V
Copyright © 2017, Texas Instruments Incorporated
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ZHCSGD0 –JUNE 2017
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9.2.3 Design 3 – Powering a Multicore DSP From a 24-V Rail
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's
Power House blog series.
Figure 70 shows the schematic diagram of a 10-A synchronous buck regulator for a DSP core voltage supply.
CVIN
0.1 ꢀF
D1
VIN = 6 V to 36 V
VOUT
U1
CBST
0.1 ꢀF
1
20
RRT
RC2
RFB1
6.81 kꢁ
33.2 kꢁ
100 ꢁ
EN/UVLO
VIN
RT
2
17
BST
HO
CC3
2.7 nF
Q1
CSS
47 nF
RC1 CC1
2.32 kꢁ
SS/TRK
3
4
5
6
7
18
19
10 nF
LF
1 ꢀH
COMP
FB
SW
NC 16
EP 15
CC2
470 pF
LM25145
Core voltage
0.9 V œ 1.1 V
AGND
RFB2
18.2 kꢁ
Q2
SYNC
Out
CIN
3 ì 10 ꢀF
Step resolution
6.4 mV
SYNCOUT
14
13
12
VCC
LO
SYNC
In
8
9
SYNCIN
NC
PGND
ILIM
11
PGOOD
10
VAUX = 8 V to 13 V
COUT
RILIM
249 ꢁ
CILIM
4 x 100 ꢀF
CVCC
22 pF
2.2 ꢀF
U3
DVDD18 CVDD
RPU1:4
U2
1
2
3
4
5
10
9
GND
VIDS
VCNTL[3]
VCNTL[2]
VCNTL[1]
VCNTL[0]
TMS320C667x
VIDC
3.3 V
IDAC_OUT
VDD
KeyStone√
Multicore
DSP
8
VIDB
VIDA
SET
7
EN
MODE
6
GND
RSET
LM10011SD
182 kꢁ
Copyright © 2017, Texas Instruments Incorporated
Figure 70. Application Circuit #3 With LM25145 DSP Core Voltage Supply
44
Copyright © 2017, Texas Instruments Incorporated
LM25145
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ZHCSGD0 –JUNE 2017
9.2.3.1 Design Requirements
For this application example, the intended input, output, and performance parameters are listed in Table 10.
Table 10. Design Parameters
DESIGN PARAMETER
Input voltage range (steady-state)
Input transient voltage (peak)
Output voltage and current
VALUE
6 V to 36 V
42 V
0.9 V to 1.1 V, 10 A
±1%
Output voltage regulation
Load transient peak voltage deviation, 10-A step
Switching frequency
< 120 mV
300 kHz
9.2.3.2 Detailed Design Procedure
The schematic diagram of a 300-kHz, 24-V nominal input, 10-A regulator powering a KeyStone™ DSP is given in
Figure 70. This high step-down ratio design leverages the low 40-ns minimum controllable on-time of the
LM25145 controller to achieve stable, efficient operation at very low duty cycles. 60-V power MOSFETs, such as
TI's CSD18543Q3A and CSD18531Q5A NexFET devices, are used together with a low-DCR, metal-powder
inductor, and ceramic output capacitor implementation. An external rail between 8 V and 13 V powers VCC to
minimize bias power dissipation, and a blocking diode connected to the VIN pin is used as recommended in
Figure 32.
The important components for this design are listed in Table 11.
Table 11. List of Materials for Design 3
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
TDK
Murata
C3225X7R1H106M
GRM32ER71H106KA12L
12105C106KAT2A
GRM32EC70J107ME15L
JMK325AC7107MM-P
GRM31CR60J107ME39K
C3216X5R0J107M
885012108005
CIN
3
10 µF, 50 V, X7R, 1210, ceramic
AVX
Murata
100 µF, 6.3V, X7S, 1210, ceramic
100 µF, 6.3V, X5R, 1206, ceramic
Taiyo Yuden
Murata
COUT
4
TDK
Würth Electronik
Cyntec
1 µH, 5.6 mΩ, 16 A, 6.95 × 6.6 × 2.8 mm
1 µH, 5.5 mΩ, 12 A, 6.65 × 6.45 × 3.0 mm
1 µH, 7.9 mΩ, 16 A, 6.5 × 6.0 × 3.0 mm
1 µH, 6.95 mΩ, 18 A, 6.76 × 6.56 × 3.1 mm
60 V, 8.5 mΩ, high-side MOSFET, SON 3 × 3
60 V, 4 mΩ, low-side MOSFET, SON 5 × 6
Wide VIN synchronous buck controller
6- or 4-bit VID voltage programmer, WSON-10
KeyStone™ DSP
CMLE063T-1R0MS
WE XHMI 74439344010
ETQP3M1R0YFN
XEL6030-102ME
Würth Electronik
Panasonic
LF
1
Coilcraft
Q1
Q2
U1
U2
U3
1
1
1
1
1
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
CSD18543Q3A
CSD18531Q5A
LM25145RGYR
LM10011SD
TMS320C667x
The regulator output current requirements are dependent upon the baseline and activity power consumption of
the DSP in a real-use case. While baseline power is highly dependent on voltage, temperature and DSP
frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To
this end, the IDAC_OUT pin of the LM10011 connects to the LM25145 FB pin to allow continuous optimization of
the core voltage. The SmartReflex-enabled DSP provides 6-bit information using the VCNTL open-drain I/Os to
command the output voltage setpoint with 6.4-mV step resolution.(1)
(1) Refer to Hardware Design Guide for Keystone I Devices (SPRAB12) and How to Optimize Your DSP Power Budget for further detail.
Copyright © 2017, Texas Instruments Incorporated
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ZHCSGD0 –JUNE 2017
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9.2.3.3 Application Curves
100
VOUT 0.2V/DIV
80
60
40
20
0
VIN 5V/DIV
IOUT 5A/DIV
VIN = 6V
VIN = 12V
VIN = 24V
VIN = 36V
PGOOD
2V/DIV
0
2
4
6
8
10
1 ms/DIV
Output Current (A)
VIN step to 24 V
0.11-Ω Load
VOUT = 1.1 V
VAUX = 8 V
Figure 72. Start-Up, 10-A Resistive Load
Figure 71. Efficiency vs IOUT and VIN
VOUT 0.2V/DIV
VOUT 100m/DIV
ENABLE 1V/DIV
IOUT 5A/DIV
PGOOD
2V/DIV
IOUT
2A/DIV
40 ms/DIV
1 ms/DIV
VIN = 24 V
0.11-Ω Load
VIN = 24 V
Figure 73. ENABLE ON and OFF, 10-A Resistive Load
Figure 74. Load Transient Response, 0 A to 10 A to 0 A
46
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LM25145
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ZHCSGD0 –JUNE 2017
10 Power Supply Recommendations
The LM25145 buck controller is designed to operate from a wide input voltage range from 6 V to 42 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions tables. In addition, the input supply must be capable of delivering the required input current
to the fully-loaded regulator. Estimate the average input current with Equation 23.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
where
•
η is the efficiency
(23)
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special
care is required to achieve stable performance. The parasitic inductance and resistance of the input cables may
have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at
VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip
during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false
UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the
input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The
moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage
overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps
to hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for
DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching
regulator.
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11 Layout
11.1 Layout Guidelines
Proper PCB design and layout is important in a high current, fast switching circuit (with high current and voltage
slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must be
considered before designing a PCB layout using the LM25145. The high-frequency power loop of the buck
converter power stage is denoted by #1 in the shaded area of Figure 75. The topological architecture of a buck
converter means that particularly high di/dt current flows in the components of loop #1, and it becomes
mandatory to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important are
the gate drive loops of the low-side and high-side MOSFETs, denoted by #2 and #3, respectively, in Figure 75.
VIN
LM25145
CIN
#1
BST
High frequency
14
17
18
VCC
power loop
CBST
#2
Q1
HO
High-side
gate driver
LF
SW
VOUT
19
14
VCC
CVCC
#3
COUT
Q2
LO
Low-side
gate driver
13
12
PGND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 75. DC-DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops
11.1.1 Power Stage Layout
1. Input capacitors, output capacitors, and MOSFETs are the constituent components in the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective
heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,
small-signal components are typically placed on the bottom side (component side). At least one inner plane
should be inserted, connected to ground, to shield and isolate the small-signal traces from noisy power
traces and lines.
2. The DC-DC converter has several high-current loops. Minimize the area of these loops in order to suppress
generated switching noise and parasitic loop inductance and optimize switching performance.
–
Loop #1: The most important loop to minimize the area of is the path from the input capacitor(s) through
the high- and low-side MOSFETs, and back to the capacitor(s) through the ground connection. Connect
the input capacitor(s) negative terminal close to the source of the low-side MOSFET (at ground).
Similarly, connect the input capacitor(s) positive terminal close to the drain of the high-side MOSFET (at
VIN). Refer to loop #1 of Figure 75.
–
Another loop, not as critical though as loop #1, is the path from the low-side MOSFET through the
inductor and output capacitor(s), and back to source of the low-side MOSFET through ground. Connect
the source of the low-side MOSFET and negative terminal of the output capacitor(s) at ground as close
as possible.
3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, should be short and
wide. However, the SW connection is a source of injected EMI and thus should not be too large.
48
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ZHCSGD0 –JUNE 2017
Layout Guidelines (continued)
4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including
pad geometry and solder paste stencil design.
5. The SW pin connects to the switch node of the power conversion stage, and it acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop #1 in Figure 75 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (>100 MHz) ringing on
the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input
voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the
SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to
GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
11.1.2 Gate Drive Layout
The LM25145 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time
control and low-impedance output stages capable of delivering large peak currents with very fast rise and fall
times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the gate
drive command, thereby increasing MOSFET switching times. The following loops are important:
•
Loop #2: high-side MOSFET, Q1. During the high-side MOSFET turn on, high current flows from the boot
capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop #2 of Figure 75.
•
Loop #3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop #3 of Figure 75.
The following circuit layout guidelines are strongly recommended when designing with high-speed MOSFET gate
drive circuits.
1. Connections from gate driver outputs, HO and LO, to the respective gate of the high-side or low-side
MOSFET should be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or
wider traces. Use via(s), if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO
and SW gate traces as a differential pair from the LM25145 to the high-side MOSFET, taking advantage of
flux cancellation.
2. Minimize the current loop path from the VCC and BST pins through their respective capacitors as these
provide the high instantaneous current, up to 3.5 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the BST and SW pins of the LM25145 to minimize the area of
loop #2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and
PGND pins of the LM25145 to minimize the area of loop #3 associated with the low-side driver.
3. Placing a 2-Ω to 10-Ω resistor in series with the BST capacitor slows down the high-side MOSFET turnon
transition, serving to reduce the voltage ringing and peak amplitude at the SW node at the expense of
increased MOSFET turnon power loss.
11.1.3 PWM Controller Layout
With the proviso to locate the controller as close as possible to the MOSFETs to minimize gate driver trace runs,
the components related to the analog and feedback signals, current limit setting and temperature sense are
considered in the following:
1. Separate power and signal traces, and use a ground plane to provide noise shielding.
2. Place all sensitive analog traces and components such as COMP, FB, RT, ILIM and SS/TRK away from
high-voltage switching nodes such as SW, HO, LO or BST to avoid mutual coupling. Use internal layer(s) as
Copyright © 2017, Texas Instruments Incorporated
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Layout Guidelines (continued)
ground plane(s). Pay particular attention to shielding the feedback (FB) trace from power traces and
components.
3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or
the bulk capacitor at the converter side.
4. Connect the ILIM setting resistor from the drain of the low-side MOSFET to ILIM and make the connections
as close as possible to the LM25145. The trace from the ILIM pin to the resistor should avoid coupling to a
high-voltage switching net.
5. Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the
GND pin. Locate these capacitors as close as possible to the LM25145.
11.1.4 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by:
•
•
•
•
average gate drive current requirements of the power MOSFETs;
switching frequency;
operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation);
thermal characteristics of the package and operating environment.
For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The LM25145 controller
is available in a small 3.5-mm × 4.5-mm 20-pin VQFN (RGY) PowerPAD™ package to cover a range of
application requirements. The thermal metrics of this package are summarized in Thermal Information. The
application report IC Package Thermal Metrics (SPRA953) provides detailed information regarding the thermal
information table.
The 20-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the LM25145 device (ground). This allows a
significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,
thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM25145 is
soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the
thermal resistance to a very low value. Wide traces of the copper tying in the no-connect pins of the LM25145
(pins 9 and 16) and connection to this thermal land helps to dissipate heat.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the
PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow
but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pad of the high-side MOSFET is
normally connected to a VIN plane for heat sinking. The drain pad of the low-side MOSFET is tied to the SW
plane, but the SW plane area is purposely kept relatively small to mitigate EMI concerns.
11.1.5 Ground Plane Design
As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended. A
ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the
control circuitry. Connect the PGND pin to the system ground plane using an array of vias under the exposed
pad. Also connect the PGND directly to the return terminals of the input and output capacitors. The PGND net
contains noise at the switching frequency and can bounce because of load current variations. The power traces
for PGND, VIN and SW can be restricted to one side of the ground plane. The other side of the ground plane
contains much less noise and is ideal for sensitive analog trace routes.
50
Copyright © 2017, Texas Instruments Incorporated
LM25145
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11.2 Layout Example
Figure 76 shows an example PCB layout based on the LM5145EVM-HD-20A 20-A design. The power
component connections are made on the top layer with wide, copper-filled areas. A power ground plane is placed
on layer 2 with 6 mil (0.15 mm) spacing to the top layer. The small area of buck regulator hot loop is denoted by
the white border in Figure 76.
The LM25145 is located on the bottom side with a surrounding analog ground plane for sensitive analog
components as shown in Figure 77. The analog ground plane (AGND) and power ground plane (PGND) are
connected at a single point directly under the IC (at the die attach pad or DAP). Refer to the LM5145 EVM User's
Guide (SNVU545) for more detail.
VOUT
LF
Output
Capacitors
Inductor
Low-side
MOSFET
GND
G
S
Q2
SW
Copper
Input
Capacitors
D
G S
Power
LooQp 1
D
High-side
MOSFET
VIN
Legend
Top Layer Copper
Layer 2 GND Plane
Top Solder
Figure 76. LM25145 Power Stage PCB Layout
Copyright © 2017, Texas Instruments Incorporated
51
LM25145
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Layout Example (continued)
CILIM
To VOUT
RBODE
To SW
RILIM
RC2
10
11
PGND
To Gate of
Low-side
MOSFET
12
9
CC3
AGND
RTRIM
RBOOT
CBOOT
To Gate of
High-side
MOSFET
19
2
20
CC2
CC1
1
To Source of
High-side
MOSFET
CVIN
RVIN
RUV1
To VIN
Legend
Bottom Layer Copper
Layer 3 GND Plane
Bottom Solder
Figure 77. LM25145 Controller PCB Layout (Viewed From Top)
52
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LM25145
www.ti.com.cn
ZHCSGD0 –JUNE 2017
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.1.2 开发支持
相关开发支持请参阅以下文档:
•
•
•
•
LM25145 快速入门计算器
LM25145 仿真模型
有关 TI 的参考设计库,请访问 TI Designs
有关 TI WEBENCH 设计环境,请访问 WEBENCH® 设计中心
12.1.3 使用 WEBENCH® 工具定制设计方案
请单击此处,使用 LM25145 器件并借助 WEBENCH® 电源设计器创建定制设计。
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数,如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下,可执行以下操作:
•
•
•
•
运行电气仿真,观察重要波形以及电路性能
运行热性能仿真,了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息,请访问 www.ti.com/WEBENCH。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档:
•
•
•
•
《LM5145 同步降压控制器高密度 EVM》(SNVU545)
《通过将电感寄生效应降至最低来降低降压转换器 EMI 和电压应力》(SLYT682)
《直流/直流转换器的传导 EMI 的 AN-2162 简单成功案例》(SNVA489)
白皮书:
–
《评估适用于具有成本效益的严苛应用的宽 VIN、低 EMI 同步降压 电路》(SLYY104)
Power House 博客:
同步降压控制器解决方案支持提供宽 VIN 性能和灵活性
•
–
12.2.1.1 PCB 布局资源
•
•
•
•
•
《AN-1149 开关电源布局指南》(SNVA021)
《AN-1229 Simple Switcher PCB 布局指南》(SNVA054)
构建电源 - 布局注意事项 (SLUP230)
《使用 LM4360x 与 LM4600x 简化低辐射 EMI 布局》(SNVA721)
直流/直流转换器的高密度 PCB 布局
12.2.1.2 热设计资源
•
•
《富于洞见而非后知后觉的 AN-2020 热设计》(SNVA419)
《确保外露焊盘封装的最佳热阻性的 AN-1520 电路板布局指南》(SNVA183)
版权 © 2017, Texas Instruments Incorporated
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LM25145
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文档支持 (接下页)
•
•
•
•
•
《半导体和 IC 封装热指标》(文献编号:SPRA953)
《使用 LM43603 和 LM43602 简化热设计》(SNVA719)
《PowerPAD™热增强型封装》(SLMA002)
《PowerPAD 速成》(文献编号:SLMA004)
《使用新的热指标》(SBVA025)
12.3 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的
快速链接。
表 12. 相关链接
器件
产品文件夹
请单击此处
样片与购买
请单击此处
技术文档
工具和软件
请单击此处
支持和社区
请单击此处
LM25145
请单击此处
12.4 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册,即可收到任意产品
信息更改每周摘要。有关更改的详细信息,请查看任意已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.6 商标
NexFET, 《PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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版权 © 2017, Texas Instruments Incorporated
LM25145
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13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时,我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参见左侧的导航栏。
版权 © 2017, Texas Instruments Incorporated
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PACKAGE OUTLINE
RGY0020B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
S
C
A
L
E
3
0
.
0
0
0
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
1.7 0.1
2X 1.5
(0.2) TYP
10
EXPOSED
THERMAL PAD
11
14X 0.5
9
12
21
SYMM
2X
2.7 0.1
3.5
A
A
2
19
0.3
20X
1
20
0.2
PIN 1 ID
(OPTIONAL)
SYMM
20X
0.1
C A B
0.05
0.5
0.3
4222860/B 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
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版权 © 2017, Texas Instruments Incorporated
LM25145
www.ti.com.cn
ZHCSGD0 –JUNE 2017
EXAMPLE BOARD LAYOUT
RGY0020B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.7)
SYMM
1
20
20X (0.6)
2
19
20X (0.25)
(1.1)
(4.3)
21
SYMM
(2.7)
14X (0.5)
(0.6)
9
12
(R0.05) TYP
11
(0.75) TYP
10
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222860/B 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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版权 © 2017, Texas Instruments Incorporated
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EXAMPLE STENCIL DESIGN
RGY0020B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.75)
20
(R0.05) TYP
1
20X (0.6)
2
19
21
20X (0.25)
4X
(1.21)
SYMM
(4.3)
(0.71)
TYP
14X (0.5)
12
9
METAL
TYP
10
11
4X (0.75)
(0.475)
TYP
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222860/B 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
58
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM25145RGYR
LM25145RGYT
ACTIVE
VQFN
VQFN
RGY
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LM
25145
Samples
Samples
ACTIVE
RGY
NIPDAU | SN
LM
25145
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2023
Addendum-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
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