概述
数据手册LM25184-Q1 概述
具有 65V、4.1A 集成式 MOSFET 的汽车类 42V 输入电压非光电反激式转换器
LM25184-Q1 数据手册
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具有 65V、4.1A MOSFET 的 LM25184-Q1 42VIN PSR 反激式直流/直流转换器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准
– 器件温度等级 1：–40°C 至 125°C 的环境温度
范围
LM25184-Q1 是一款初级侧调节 (PSR) 反激式转换
器，在 4.5V 至 42V 的宽输入电压范围内具有高效率，
可通过初级侧反激式电压对隔离输出电压采样。高集成
度可实现简单可靠的高密度设计，其中只有一个元件穿
过隔离层。通过采用边界导电模式 (BCM) 开关，可实
现紧凑的磁解决方案以及优于 ±1.5% 的负载和线路调
节性能。集成的 65V 功率 MOSFET 可提供高达 15W
的输出功率并提高应对线路瞬变的余量。
•
•
提供功能安全
– 可帮助进行功能安全系统设计的文档
专为可靠耐用的应用而设计
– 4.5V 至 42V 的宽输入电压范围，
– 稳定可靠的解决方案，只有一个元件穿过隔离层
– ±1.5% 的总输出稳压精度
LM25184-Q1 简化了隔离式直流/直流电源的实施，
且可通过可选功能优化目标终端设备的性能。该器件通
过一个电阻器来设置输出电压，同时使用可选的电阻器
通过抵消反激式二极管的压降热系数来提高输出电压精
度。其他功能包括内部固定或外部可编程软启动、用于
可调节线路 UVLO 的精密使能输入（带迟滞功能）、
间断模式过载保护和带自动恢复功能的热关断保护。
– 可选 VOUT 温度补偿
– 具有 –40°C 至 +150°C 的结温范围
通过集成技术减小解决方案尺寸，降低成本
– 集成 65V、0.11Ω 功率 MOSFET
– 无需光耦合器或变压器辅助绕组即可进行 VOUT
稳压
•
•
•
•
高效率 PSR 反激运行
LM25184-Q1 转换器符合汽车 AEC-Q100 1 级标准，
并且采用引脚间距为 0.8mm 且具有可湿性侧面的 8 引
脚 WSON 封装。
– MOSFET 在 BCM 模式下实现准谐振关断
– 具有单输出和多输出实施手段
超低的 EMI 传导和辐射信号
– 软开关可避免二极管反向恢复
– 针对 CISPR 25 5 类要求进行了优化
使用 WEBENCH® Power Designer 创建定制反激式
稳压器设计方案
器件信息
器件型号(1)
LM25184-Q1
封装
封装尺寸（标称值）
WSON (8)
4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
汽车 HEV/EV 动力总成系统
AM 以下波段汽车车身电子装置
牵引逆变器：IGBT 和 SiC 驱动器电源
95
90
85
80
75
VIN = 4.5 V...42 V
VOUT = 12 V
DFLY
T1
DZ
COUT
47 ꢀF
1 : 1
CIN
DF
VIN
EN/UVLO
10 ꢀF
SW
70
RFB
VIN = 6 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
LM25184-Q1
124 kW
65
GND
FB
60
RSET
TC
0
200
400
600
Load Current (mA)
800
1000
1200
D001
RSET
SS/BIAS
12.1 kW
典型效率 (VOUT = 12V)
典型应用
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBJ6
LM25184-Q1
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Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Applications.................................................. 17
9 Power Supply Recommendations................................32
10 Layout...........................................................................33
10.1 Layout Guidelines................................................... 33
10.2 Layout Examples.................................................... 34
11 Device and Documentation Support..........................35
11.1 Device Support........................................................35
11.2 Documentation Support.......................................... 36
11.3 接收文档更新通知................................................... 36
11.4 支持资源..................................................................36
11.5 Trademarks............................................................. 37
11.6 静电放电警告...........................................................37
11.7 术语表..................................................................... 37
12 Mechanical, Packaging, and Orderable
Information.................................................................... 38
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2020) to Revision A (August 2020)
Page
将器件状态从“预告信息”更改为“量产数据”..........................................................................................................1
更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
•
•
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5 Pin Configuration and Functions
8
7
6
5
GND
SW
FB
1
2
3
4
RSET
TC
VIN
EN/UVLO
SS/BIAS
图 5-1. 8-Pin WSON NGU Package With Wettable Flanks (Top View)
Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
Switch node that is internally connected to the drain of the N-channel power MOSFET. Connect to
the primary-side switching terminal of the flyback transformer.
1
SW
FB
P
I
Primary-side feedback pin. Connect a resistor from FB to SW. The ratio of the FB resistor to the
resistor at the RSET pin sets the output voltage.
2
3
Input supply connection. Source for internal bias regulators and input voltage sensing pin.
Connect directly to the input supply of the converter with short, low impedance paths.
VIN
P/I
Enable input and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is below
1 V, the converter is in shutdown mode with all functions disabled. If the EN/UVLO voltage is
greater than 1 V and below 1.5 V, the converter is in standby mode with the internal regulator
operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up sequence
begins.
4
EN/UVLO
I
Soft start or bias input. Connect a capacitor from SS/BIAS to GND to adjust the output start-up
time and input inrush current. If SS/BIAS is left open, the internal 6-ms soft-start timer is activated.
Connect an external supply to SS/BIAS to supply bias to the internal voltage regulator and enable
internal soft start.
5
6
SS/BIAS
TC
I
I
Temperature compensation pin. Tie a resistor from TC to RSET to compensate for the
temperature coefficient of the forward voltage drop of the secondary diode, thus improving
regulation at the secondary-side output.
Reference resistor tied to GND to set the reference current for FB. Connect a 12.1-kΩ resistor
from RSET to GND.
7
8
RSET
GND
I
G
Analog and power ground. Ground connection of internal control circuits and power MOSFET.
(1) P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1.5
–3
MAX
UNIT
VIN to GND
45
EN/UVLO to GND
TC to GND
45
6
Input voltage
SS/BIAS to GND
FB to GND
14
V
45.3
0.3
3
FB to VIN
RSET to GND
SW to GND
70
Output voltage
V
SW to GND (20-ns transient)
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–55
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002
HBM ESD Classification Level 2 (1)
±2000
V(ESD)
Electrostatic discharge
All pins except 1, 4,
5, and 8
V
Charged device model (CDM), per
AEC Q100-011
CDM ESD Classification Level C4B
±500
±750
Pins 1, 4, 5, and 8
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VIN
Input voltage
4.5
42
VSW
SW voltage
65
V
VEN/UVLO
VSS/BIAS
TJ
EN/UVLO voltage
SS/BIAS voltage
Operating junction temperature
42
V
13
V
–40
150
°C
6.4 Thermal Information
LM25184-Q1
THERMAL METRIC(1)
NGU (WSON)
8 PINS
40.9
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
36.9
17.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ΨJB
17.7
RΘJC(bot)
2.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.
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6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits aaply over the full –40°C to 150°C junction
temperature range unless otherwise indicated. VIN = 12 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISHUTDOWN
IACTIVE
VIN shutdown current
VEN/UVLO = 0 V
1.8
260
25
µA
µA
µA
VIN active current
VEN/UVLO = 2.5 V, VRSET = 1.8 V
VSS/BIAS = 5 V
375
50
IACTIVE-BIAS
VIN current with BIAS connected
ENABLE AND INPUT UVLO
VSD-FALLING
VSD-RISING
VUV-RISING
VUV-HYST
IUV-HYST
Shutdown threshold
VEN/UVLO falling
VEN/UVLO rising
VEN/UVLO rising
VEN/UVLO falling
VEN/UVLO = 1.6 V
0.3
V
V
Standby threshold
0.8
1.5
0.05
5
1
Enable threshold
1.45
0.04
4.2
1.53
V
Enable voltage hysteresis
Enable current hysteresis
V
5.5
µA
FEEDBACK
IRSET
RSET current
RRSET = 12.1 kΩ
RRSET = 12.1 kΩ
IFB = 80 µA
100
µA
V
VRSET
RSET regulation voltage
FB to VIN voltage
FB to VIN voltage
1.194
–50
1.21
1.22
50
VFB-VIN1
mV
mV
VFB-VIN2
IFB = 120 µA
SWITCHING FREQUENCY
FSW-MIN
FSW-MAX
tON-MIN
Minimum switching frequency
12
350
140
kHz
kHz
ns
Maximum switching frequency
Minimum switch on-time
DIODE THERMAL COMPENSATION
VTC TC voltage
POWER SWITCHES
ITC = ±10 µA, TJ = 25°C
ISW = 100 mA, TJ = 25°C
1.2
1.27
V
RDS(on)
MOSFET on-state resistance
0.11
0.135
Ω
SOFT-START AND BIAS
ISS
tSS
SS ext capacitor charging current
5
6
µA
ms
Internal SS time
VBIAS-UVLO-
BIAS enable voltage
VSS/BIAS rising
VSS/BIAS falling
4.25
130
4.45
4.4
V
RISE
VBIAS-UVLO-
BIAS UVLO hysteresis
mV
HYST
CURRENT LIMIT
ISW-PEAK
Peak current limit threshold
3.6
4.1
A
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
175
10
°C
°C
TSD-HYS
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6.6 Typical Characteristics
VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated).
95
90
85
80
75
12.6
12.4
12.2
12
11.8
11.6
11.4
70
VIN = 6 V
VIN = 6 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
65
60
0
200
400
600
Load Current (mA)
800 1000 1200 1400 1600
0
200
400
600
Load Current (mA)
800
1000
1200
D003
D001
See 图 8-1
See 图 8-1
图 6-2. Output Voltage versus Load
图 6-1. Efficiency versus Load
VSW 10 V/div
VSW 10 V/div
1 ms/div
1 ms/div
See 图 8-1
VIN = 13.5 V, IOUT = 0.5 A
See 图 8-1
VIN = 13.5 V, IOUT = 1 A
图 6-4. Switching Waveform in DCM
图 6-3. Switching Waveform in BCM
VOUT 2 V/div
VOUT 2 V/div
IOUT 0.2 A/div
IOUT 0.2 A/div
VEN/UVLO 10 V/div
VIN 10 V/div
4 ms/div
4 ms/div
See 图 8-1
See 图 8-1
图 6-6. ENABLE ON/OFF Characteristic
图 6-5. Start-up Characteristic
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102
104
102
100
98
101
100
99
98
0
96
-50
6
12
18 24
Input Voltage (V)
30
36
42
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D004
D005
图 6-7. RSET Current versus Input Voltage
1.8
图 6-8. RSET Current versus Temperature
1.54
1.52
1.5
1.6
1.4
1.2
1
1.48
1.46
1.44
1.42
VEN/UVLO Rising
VEN/UVLO Falling
1.4
-50
0.8
-50
-25
0
25
50
75
100 125 150
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D007
D006
图 6-10. EN/UVLO Threshold Voltages versus
图 6-9. TC Voltage versus Temperature
Temperature
5.3
5.2
5.1
5
160
155
150
145
140
135
130
4.9
4.8
4.7
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D008
D011
图 6-11. EN/UVLO Hysteresis Current versus
图 6-12. Minimum Switch On-Time versus
Temperature
Temperature
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13
12.5
12
380
370
360
350
340
330
320
11.5
11
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D012
D013
图 6-13. Minimum Switching Frequency versus
图 6-14. Maximum Switching Frequency versus
Temperature
Temperature
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7 Detailed Description
7.1 Overview
The LM25184-Q1 primary-side regulated (PSR) flyback converter is a high-density, cost-effective solution for
automotive and industrial systems requiring less than 15 W of isolated DC/DC power. This compact, easy-to-
use flyback converter with low IQ can be applied over a wide input voltage range from 4.5 V to 42 V, with
operation down to 3.5 V after start-up. Innovative frequency and current amplitude modulation enables high
conversion efficiency across the entire load and line range. Primary-side regulation of the isolated output voltage
using sampled values of the primary winding voltage eliminates the need for an opto-coupler or an auxiliary
transformer winding for feedback. Regulation performance that rivals that of traditional opto-coupler solutions is
achieved without the associated cost, solution size, and reliability concerns. The LM25184-Q1 converter services
a wide range of applications including automotive on-board chargers and IGBT-based motor drives for HEV/EV
systems.
7.2 Functional Block Diagram
VOUT
VIN
DFLY
NP : NS
DZ
COUT
5 mA
LM25184-Q1
SS/BIAS
BIAS
REGULATOR
CIN
EN/UVLO
Standby
1.5 V
1.45 V
VDD
VIN
DF
VDD UVLO
Shutdown
VIN
SAMPLED
FEEDBACK
THERMAL
SHUTDOWN
1.1 V
65-V Power
MOSFET
FB
SW
RSET
COMP
VDD
gm
VREF
TRIMMED
REFERENCE
CONTROL
LOGIC
RTC
RSET
FB
ILIM
TC
4.1 A
TC
REGULATION
VDD
RFB
SS/BIAS
GND
Internal SS
CSS
7.3 Feature Description
7.3.1 Integrated Power MOSFET
The LM25184-Q1 is a flyback dc/dc converter with integrated 65-V, 4.1-A N-channel power MOSFET. During the
MOSFET on-time, the transformer primary current increases from zero with a slope of VIN / LMAG (where LMAG
is the transformer primary-referred magnetizing inductance) while the output capacitor supplies the load current.
When the high-side MOSFET is turned off by the control logic, the switch (SW) voltage VSW swings up to
approximately VIN + (NPS × VOUT), where NPS = NP/NS is the primary-to-secondary turns ratio of the transformer.
The magnetizing current flows in the secondary side through the flyback diode, charging the output capacitor
and supplying current to the load. Duty cycle D is defined as tON / tSW, where tON is the MOSFET conduction
time and tSW is the switching period.
图 7-1 shows a typical schematic of the LM25184-Q1 PSR flyback circuit. Components denoted in red are
optional depending on the application requirements.
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DFLY
T1
VIN
VOUT
DCLAMP
COUT
DOUT
RUV1
NP : NS
DF
CIN
VIN
SW
EN/UVLO
RUV2
RFB
LM25184
GND
FB
RSET
TC
SS/BIAS
RTC
RSET
CSS
图 7-1. LM25184-Q1 Flyback Converter Schematic (Optional Components in Red)
7.3.2 PSR Flyback Modes of Operation
The LM25184-Q1 uses a variable-frequency, peak current-mode (VFPCM) control architecture with three
possible modes of operation as illustrated in 图 7-2.
Frequency
foldback mode
(FFM)
Discontinuous conduction mode (DCM)
Boundary conduction mode (BCM)
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
% Total Rated Output Power
图 7-2. Three Modes of Operation Illustrated by Variation of Switching Frequency With Load
The LM25184-Q1 operates in boundary conduction mode (BCM) at heavy loads. The power MOSFET turns on
when the current in the secondary winding reaches zero, and the MOSFET turns off when the peak primary
current reaches the level dictated by the output of the internal error amplifier. As the load is decreased, the
frequency increases to maintain BCM operation. 方程式 1 gives the duty cycle of the flyback converter in BCM.
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V
+ VD ∂N
(
)
OUT
PS
D =
V
+ V
+ VD ∂N
(
)
IN
OUT
PS
(1)
where
VD is the forward voltage drop of the flyback diode as its current approaches zero
•
方程式 2 gives the output power in BCM, where the applicable switching frequency and peak primary current are
specified by 方程式 3 and 方程式 4, respectively.
2
LMAG ∂IPRI-PK(BCM)
POUT(BCM)
=
∂FSW(BCM)
2
(2)
1
FSW(BCM)
=
≈
’
LMAG
LMAG
NPS ∂ V
IPRI-PK(BCM)
∂
+
∆
∆
÷
÷
V
+ VD
OUT
(
)
IN
«
◊
(3)
(4)
2∂ V
(
+ VD ∂I
OUT
)
OUT
IPRI-PK(BCM)
=
V ∂D
IN
As the load decreases, the LM25184-Q1 clamps the maximum switching frequency to 350 kHz, and the
converter enters discontinuous conduction mode (DCM). The power delivered to the output in DCM is
proportional to the peak primary current squared as given by 方程式 5 and 方程式 6. Thus, as the load
decreases, the peak current reduces to maintain regulation at 350-kHz switching frequency.
2
LMAG ∂IPRI-PK(DCM)
POUT(DCM)
=
∂FSW(DCM)
2
(5)
2∂IOUT ∂ V
+ VD
(
)
OUT
IPRI-PK(DCM)
=
LMAG ∂FSW(DCM)
(6)
(7)
LMAG ∂IPRI-PK(DCM) ∂FSW(DCM)
DDCM
=
V
IN
At even lighter loads, the primary-side peak current set by the internal error amplifier decreases to a minimum
level of 0.82 A, or 20% of its 4.1-A peak value, and the MOSFET off-time extends to maintain the output load
requirement. The system operates in frequency foldback mode (FFM), and the switching frequency decreases
as the load current is reduced. Other than a fault condition, the lowest frequency of operation of the LM25184-
Q1 is 12 kHz, which sets a minimum load requirement of approximately 0.5% full load.
7.3.3 Setting the Output Voltage
To minimize output voltage regulation error, the LM25184-Q1 senses the reflected secondary voltage when
the secondary current reaches zero. The feedback (FB) resistor, which is connected between SW and FB is
determined using 方程式 8, where RSET is nominally 12.1 kΩ.
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RSET
RFB = V
+ VD ∂N
∂
(
)
OUT
PS
VREF
(8)
7.3.3.1 Diode Thermal Compensation
The LM25184-Q1 employs a unique thermal compensation circuit that adjusts the feedback setpoint based
on the thermal coefficient of the forward voltage drop of the flyback diode. Even though the output voltage
is measured when the secondary current is effectively zero, there is still a non-zero forward voltage drop
associated with the flyback diode. Select the thermal compensation resistor using 方程式 9.
RFB kW
»
ÿ
⁄
3
RTC kW =
∂
»
ÿ
⁄
NPS
TCDiode mV èC
» ÿ
⁄
(9)
The temperature coefficient of the diode voltage drop may not be explicitly provided in the diode data sheet, so
the effective value can be estimated based on the measured output voltage shift over temperature when the TC
resistor is not installed.
7.3.4 Control Loop Error Amplifier
The inputs of the error amplifier include a level-shifted version of the FB voltage and an internal 1.21-V reference
set by the resistor at RSET. A type-2 internal compensation network stabilizes the converter. In BCM operation
when the output voltage is in regulation, an on-time interval is initiated when the secondary current reaches zero.
The power MOSFET is subsequently turned off when an amplified version of the peak primary current exceeds
the error amplifier output.
7.3.5 Precision Enable
The precision EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis for
application specific power-up and power-down requirements. EN/UVLO connects to a comparator with a 1.5-V
reference voltage and 50-mV hysteresis. An external logic signal can be used to drive the EN/UVLO input to
toggle the output on and off for system sequencing or protection. The simplest way to enable the LM25184-Q1 is
to connect EN/UVLO directly to VIN. This allows the LM25184-Q1 to start up when VIN is within its valid operating
range. However, many applications benefit from using resistor divider RUV1 and RUV2 as shown in 图 7-3 to
establish a precision UVLO level.
LM25184
VCC
VIN
5 ꢀA
RUV1
EN/UVLO
+
RUV2
UVLO
Comparator
1.5 V
1.45 V
图 7-3. Programmable Input Voltage UVLO With Hysteresis
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Use 方程式 10 and 方程式 11 to calculate the input UVLO voltages turnon and turnoff voltages, respectively.
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≈
’
÷
◊
RUV1
RUV2
V
= VUV-RISING 1+
∆
IN(on)
«
(10)
(11)
≈
’
÷
◊
RUV1
RUV2
V
= VUV-FALLING 1+
-IUV-HYST ∂RUV1
∆
IN(off)
«
where
•
•
VUV-RISING and VUV-FALLING are the UVLO comparator thresholds
IUV-HYST is the hysteresis current
The LM25184-Q1 also provides a low-IQ shutdown mode when the EN/UVLO voltage is pulled below a base-
emitter voltage drop (approximately 0.6 V at room temperature). If the EN/UVLO voltage is below this hard
shutdown threshold, the internal LDO regulator powers off, and the internal bias-supply rail collapses, shutting
down the bias currents of the LM25184-Q1. The LM25184-Q1 operates in standby mode when the EN/UVLO
voltage is between the hard shutdown and precision-enable thresholds.
7.3.6 Configurable Soft Start
The LM25184-Q1 has a flexible and easy-to-use soft-start control pin, SS/BIAS. The soft-start feature prevents
inrush current impacting the LM25184-Q1 and the input supply when power is first applied. This is achieved by
controlling the voltage at the output of the internal error amplifier. Soft start is achieved by slowly ramping up
the target regulation voltage when the device is first enabled or powered up. Selectable and adjustable start-up
timing options include a 6-ms internally-fixed soft start and an externally-programmable soft start.
The simplest way to use the LM25184-Q1 is to leave SS/BIAS open. The LM25184-Q1 employs an internal
soft-start control ramp and starts up to the regulated output voltage in 6 ms.
However, in applications with a large amount of output capacitance, higher VOUT, or other special requirements,
the soft-start time can be extended by connecting an external capacitor CSS from SS/BIAS to GND. A longer
soft-start time further reduces the supply current needed to charge the output capacitors while sourcing the
required load current. When the EN/UVLO voltage exceeds the UVLO rising threshold and a delay of 20 µs
expires, an internal current source ISS of 5 µA charges CSS and generates a ramp to control the primary current
amplitude. Calculate the soft-start capacitance for a desired soft-start time, tSS, using 方程式 12.
CSS nF = 5 ∂ t
ms
»
»
ÿ
ÿ
⁄
SS
⁄
(12)
CSS is discharged by an internal FET when switching is disabled by EN/UVLO or thermal shutdown.
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7.3.7 External Bias Supply
DFLY
T1
VIN
VOUT
DCLAMP
COUT
DOUT
RUV1
NP : NS
DF
CIN
VIN
EN/UVLO
SW
RUV2
RFB
LM25184
GND
FB
DBIAS1
RSET
TC
SS/BIAS
DBIAS2
12 V
CBIAS
22 nF
RSET
NP : NAUX
图 7-4. External Bias Supply Using Transformer Auxiliary Winding
The LM25184-Q1 has an external bias supply feature that reduces input quiescent current and increases
efficiency. When the voltage at SS/BIAS exceeds a rising threshold of 4.25 V, bias power for the internal LDO
regulator can be derived from an external voltage source or from a transformer auxiliary winding as shown in 图
7-4. With a bias supply connected, the LM25184-Q1 then uses its internal soft-start ramp to control the primary
current during start-up.
When using a transformer auxiliary winding for bias power, the total leakage current related to diodes DBIAS1 and
DBIAS2 in 图 7-4 must be less than 1 µA across the full operating temperature range.
7.3.8 Minimum On-Time and Off-Time
When the internal power MOSFET is turned off, the leakage inductance of the transformer resonates with the
SW node parasitic capacitance. The resultant ringing behavior can be excessive with large transformer leakage
inductance and can corrupt the secondary zero-current detection. To prevent such a situation, a minimum switch
off-time, designated as tOFF-MIN, of a maximum of 425 ns is set internally to ensure proper functionality. This sets
a lower limit for the transformer magnetizing inductance as discussed in 节 8.2.1.2.
Furthermore, noise effects as a result of power MOSFET turnon can impact the internal current sense circuit
measurement. To mitigate this effect, the LM25184-Q1 provides a blanking time after the MOSFET turns on.
This blanking time forces a minimum on-time, tON-MIN, of 140 ns.
7.3.9 Overcurrent Protection
In case of an overcurrent condition on the isolated output or outputs, the output voltage drops lower than the
regulation level since the maximum power delivered is limited by the peak current capability on the primary
side. The peak primary current is maintained at 4.1 A (plus an amount related to the 100-ns propagation delay
of the current limit comparator) until the output decreases to the secondary diode voltage drop to impact the
reflected signal on the primary side. At this point, the LM25184-Q1 assumes the output cannot be recovered
and re-calibrates its switching frequency to 9 kHz until the overload condition is removed. The LM25184-Q1
responds with similar behavior to an output short circuit condition.
For a given input voltage, 方程式 13 gives the maximum output current prior to the engagement of overcurrent
protection. The typical threshold value for ISW-PEAK from 节 6.5 is 4.1 A.
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ISW-PEAK
h
2
IOUT(max)
=
∂
≈
∆
«
’
÷
◊
VOUT
1
+
V
NPS
IN
(13)
7.3.10 Thermal Shutdown
Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related
to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 175°C to
prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and
the LM25184-Q1 restarts when the junction temperature falls to 165°C.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
EN/UVLO facilitates ON and OFF control for the LM25184-Q1. When VEN/UVLO is below approximately 0.6 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current
in shutdown mode drops to 3 μA at VIN = 24 V. The LM25184-Q1 also employs internal bias rail undervoltage
protection. If the internal bias supply voltage is below its UV threshold, the converter remains off.
7.4.2 Standby Mode
The internal bias rail LDO regulator has a lower enable threshold than the converter itself. When VEN/UVLO is
above 0.6 V and below the precision-enable threshold (1.5 V typically), the internal LDO is on and regulating.
The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action
and voltage regulation are not enabled until VEN/UVLO rises above the precision enable threshold.
7.4.3 Active Mode
The LM25184-Q1 is in active mode when VEN/UVLO is above the precision-enable threshold and the internal bias
rail is above its UV threshold. The LM25184-Q1 operates in one of three modes depending on the load current
requirement:
1. Boundary conduction mode (BCM) at heavy loads
2. Discontinuous conduction mode (DCM) at medium loads
3. Frequency foldback mode (FFM) at light loads
Refer to 节 7.3.2 for more detail.
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8 Application and Implementation
备注
以下应用部分的信息不属于 TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LM25184-Q1 requires only a few external components to convert from a wide range of supply voltages to
one or more isolated output rails. To expedite and streamline the process of designing of a LM25184-Q1-based
converter, a comprehensive LM25184-Q1 quick-start calculator is available for download to assist the designer
with component selection for a given application. WEBENCH® online software is also available to generate
complete designs, leveraging iterative design procedures and access to comprehensive component databases.
The following sections discuss the design procedure for both single- and dual-output implementations using
specific circuit design examples.
As mentioned previously, the LM25184-Q1 also integrates several optional features to meet system design
requirements, including precision enable, input UVLO, programmable soft start, output voltage thermal
compensation, and external bias supply connection. Each application incorporates these features as needed
for a more comprehensive design.
The application circuits detailed in 节 8.2 show LM25184-Q1 configuration options suitable for several
application use cases. Refer to the LM25184EVM-S12 EVM user's guide for more detail.
8.2 Typical Applications
For step-by-step design procedures, circuit schematics, bill of materials, PCB files, simulation and test results of LM25184-Q1-powered
implementations, refer to the TI Reference Design library.
8.2.1 Design 1: Wide VIN, Low IQ PSR Flyback Converter Rated at 12 V, 1 A
The schematic diagram of a 12-V, 1-A PSR flyback converter is given in 图 8-1.
DFLY
VIN = 6 V...42 V
T1
VOUT = 12 V
IOUT = 1 A
DCLAMP
20 V
COUT
DOUT
13 V
RUV1
4 x
261 kW
22 ꢀF
1 : 1
CIN
DF
VIN
EN/UVLO
7 mH
10 ꢀF
SW
FB
RUV2
RFB
LM25184
97.1 kW
121 kW
GND
RSET
TC
SS/BIAS
RTC
RSET
CSS
261 kW
12.1 kW
47 nF
图 8-1. Schematic for Design 1 With VIN(nom) = 24 V, VOUT = 12 V, IOUT = 1 A
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8.2.1.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in 表 8-1.
表 8-1. Design Parameters
DESIGN PARAMETER
VALUE
6 V to 36 V
5.5 V on, 4 V off
12 V
Input voltage range
Input UVLO thresholds
Output voltage
Rated load current, VIN ≥ 13.5 V
Output voltage regulation
Output voltage ripple
1 A
±1.5%
< 120 mV pk-pk
The target full-load efficiency is 89% based on a nominal input voltage of 24 V and an isolated output voltage of
12 V. The LM25184-Q1 is chosen to deliver a fixed 12-V output voltage set by resistor RFB connected between
the SW and FB pins. The input voltage turnon and turnoff thresholds are established by RUV1 and RUV2. The
required components are listed in 表 8-2. Transformers for other single-output designs are listed in 表 8-3.
表 8-2. List of Components for Design 1
REF DES QTY SPECIFICATION
VENDOR
PART NUMBER
CIN
1
10 µF, 50 V, X7R, 1210, ceramic
22 µF, 25 V, X7R, 1210, ceramic
TDK
CNA6P1X7R1H106K250AE
TDK
CNA6P1X7R1H106K250AE
COUT1
4
Taiyo Yuden
Kemet
TMK325B7226MM-PR
COUT2
CSS
0
1
1
2
1
1
1
1
1
1
100 µF, 16 V, ±20%, electrolytic
47 nF, 16 V, X7R, 0402
Zener, 20 V, 3 W, SMA
Schottky diode, 60 V, 3 A, SOD-123FL
Zener, 13 V, 2%, SOD-523
121 kΩ, 1%, 0402
T598D107M016ATE050
Std
Std
DCLAMP
DF, DFLY
DOUT
RFB
3SMAJ5932B
FSV360FP
BZX585-B13
Std
Micro Commercial
OnSemi
Nexperia
Std
RSET
RTC
12.1 kΩ, 1%, 0402
Std
Std
261 kΩ, 1%, 0402
Std
Std
RUV1
RUV2
261 kΩ, 1%, 0603
Std
Std
97.6 kΩ, 1%, 0402
Std
Std
Coilcraft
Sumida
Würth Electronik
Texas Instruments
ZA9672-BE
12387-T162
750318701
LM25184QNGURQ1
7 μH, 5 A, 1 : 1, 13 mm × 11 mm × 10 mm
T1
1
1
7 μH, 5 A, 1 : 1, 9.8 mm × 9.5 mm ×10.6 mm
LM25184-Q1 PSR flyback converter, AEC-Q100
U1
表 8-3. Magnetic Components for Single-Output Designs
OUTPUT VOLTAGE RANGE
3.3 V to 5 V
TURNS RATIO
LMAG, ISAT
9 µH, 5 A
7 µH, 5 A
7 µH, 5 A
9 µH, 5 A
7 µH, 5 A
DIMENSIONS
13 × 11 × 10 mm
12 × 10 × 6 mm
VENDOR
PART NUMBER
ZA9671-BE
ZA9672-BE
ZA9673-BE
ZA9674-BE
ZB1067-AE
3 : 1
1 : 1
1 : 2
1 : 3
2 : 1
5 V to 12 V
12 V to 24 V
Coilcraft
24 V to 48 V
3.3 V to 6 V
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25184-Q1 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Custom Design With Excel Quickstart Tool
Use the LM25184-Q1 quick-start calculator to select components based on the converter specifications.
8.2.1.2.3 Flyback Transformer – T1
Choose a turns ratio of 1 : 1 based on an approximate 70% max duty cycle at minimum input voltage using 方程
式 14, rounding up or down as needed. While the maximum duty cycle can approach 80% if a particularly wide
input voltage application is needed, it increases the peak current stress of the secondary-side components.
V
DMAX
0.7
5V
IN(min)
NPS
=
∂
=
∂
= 0.95
1-DMAX VOUT + VD 1- 0.7 12V + 0.3V
(14)
Select a magnetizing inductance based on the minimum off-time constraint using 方程式 15. Choose a value of
7 µH to allow some margin for this application. Specify a saturation current of 5 A, above the maximum switch
current specification of the LM25184-Q1.
V
+ VD ∂NPS ∂ tOFF-MIN
)
ISW-PEAK(FFM)
12V + 0.3V ∂1∂ 425ns
(
(
)
0.82A
OUT
LMAG
í
=
= 6.4ꢀH
(15)
Note that a higher magnetizing inductance provides a larger operating range for BCM and FFM, but the leakage
inductance can increase based on a higher number of primary turns, NP. 方程式 16 and 方程式 17 give the
primary and secondary winding RMS currents, respectively.
D
IPRI-RMS
=
∂IPRI-PK
3
(16)
2∂IOUT ∂IPRI-PK ∂NPS
ISEC-RMS
=
3
(17)
Find the maximum output current for a given turns ratio using 方程式 18, where η is the efficiency and the
typical value for ISW-PEAK is the 4.1-A switch peak current threshold. Iterate by increasing the turns ratio if the
output current capability is too low at minimum input voltage, checking that the SW voltage rating of 65 V is not
exceeded at maximum input voltage.
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0.95A at V = 12V
À
IN
ISW-PEAK
h
2
0.92
2
4.1A
Œ
IOUT(max)
=
∂
=
∂
=
Ã
≈
∆
«
’
÷
◊
≈
∆
«
’
÷
◊
VOUT
1
12V
1
1
1.25A at V = 24V
Œ
Õ
IN
+
+
V
NPS
V
IN
IN
(18)
8.2.1.2.4 Flyback Diode – DFLY
The flyback diode reverse voltage is given by 方程式 19.
V
42V
1
IN(max)
VD-REV
í
+ VOUT
=
+12V = 54V
NPS
(19)
Select a 60-V, 3-A Schottky diode for this application to account for inevitable diode voltage overshoot and
ringing related to the resonance of transformer leakage inductance and diode parasitic capacitance. Connect an
appropriate RC snubber circuit (for example, 100 Ω and 22 pF) across the flyback diode if needed, particularly if
the transformer leakage inductance is high. Also, choose a flyback diode with current rating that aligns with the
maximum peak secondary winding current of NPS × ISW-PEAK
.
8.2.1.2.5 Leakgae Inductance Clamp Circuit – DF, DCLAMP
Connect a diode-Zener clamp circuit across the primary winding to limit the peak switch voltage after MOSFET
turnoff below the maximum level of 65 V, as given by 方程式 20.
VDZ(clamp) < VSW(max) - V
IN(max)
(20)
Choose a 20-V zener diode for DCLAMP to give a clamp voltage of approximately 1.5 times the reflected output
voltage, as specified by 方程式 21. This provides a balance between the maximum switch voltage excursion and
the leakage inductance demagnetization time. Select a Zener diode with low package parasitic inductance to
manage the high slew-rate current during the switch turnoff transition.
VDZ(clamp) = 1.5 ∂NPS ∂ V
+ VD = 1.5 ∂1∂ 12V + 0.4V = 18.6V
(
)
(
)
OUT
(21)
Choose an ultra-fast switching diode or Schottky diode for DF with reverse voltage rating greater than the
maximum input voltage and forward current rating of 3 A or higher.
8.2.1.2.6 Output Capacitor – COUT
The output capacitor determines the voltage ripple at the converter output, limits the voltage excursion during
a load transient, and sets the dominant pole of the small-signal response of the converter. Select an output
capacitance using 方程式 22 to limit the ripple voltage amplitude to less than 1% of the output voltage at
minimum input voltage and maximum load.
2
2
2
2
7ꢀH∂ 4.1A
(
)
LMAG ∂ISW-PEAK
1+ D
2
1+ 0.7
≈
’
≈
’
COUT
í
∂
=
∂
= 30ꢀF
∆
«
÷
◊
∆
«
÷
◊
2∂ DVOUT ∂ VOUT
2∂120mV ∂12V
2
(22)
Mindful of the voltage coefficient of ceramic capacitors, select four 22-µF, 25-V capacitors in 1210 case size with
X7S or better dielectric. Assuming operation in BCM, calculate the capacitive ripple voltage at the output using
方程式 23.
»
…
…
ÿ2
Ÿ
2
2
2
2∂ V
+ VD
(
)
LMAG ∂IOUT
LMAG ∂IOUT
1+ D
1-D
1
≈
’
OUT
DVOUT
=
∂
=
∂
+
∆
«
÷
◊
2
2∂ DVOUT ∂ VOUT
N
V
IN
2∂COUT ∂ VOUT ∂NPS
Ÿ
⁄
PS
(23)
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方程式 24 gives an expression for the output capacitor RMS ripple current.
2∂NPS ∂IPRI-PK
ICOUT-RMS = IOUT
∂
-1
3 ∂IOUT
(24)
8.2.1.2.7 Input Capacitor – CIN
Select an input capacitance using 方程式 25 to limit the ripple voltage amplitude to less than 5% of the input
voltage when operating at nominal input voltage.
2
D
≈
’
IPRI-PK ∂D∂ 1-
∆
÷
◊
2
«
CIN
í
2∂FSW ∂ DV
IN
(25)
Substituting the input current at full load, switching frequency, peak primary current, and peak-to-peak ripple
specification gives CIN greater than 5 μF. Considering the voltage coefficient of ceramic capacitors, select a
10-µF, 50-V, X7R ceramic capacitor in 1210 case size. 方程式 26 gives the input capacitor RMS ripple current.
D ∂IPRI-PK
4
ICIN-RMS
=
∂
-1
2
3 ∂D
(26)
8.2.1.2.8 Feedback Resistor – RFB
Select a feedback resistor, designated RFB, of 121 kΩ based on the secondary winding voltage at the end of the
flyback conduction interval (the sum of the 12-V output voltage and the Schottky diode forward voltage drop as
its current approaches zero) reflected by the transformer turns ratio of 1 : 1.
V
+ VD ∂N
12V + 0.2V ∂1
(
)
0.1mA
(
)
OUT
PS
RFB
=
=
= 122 kW
0.1mA
(27)
8.2.1.2.9 Thermal Compensation Resistor – RTC
Select a resistor for output voltage thermal compensation, designated RTC, based on 方程式 28.
RFB kW
»
ÿ
⁄
3
121kW ∂3
1∂1.4
RTC kW =
∂
=
= 261kW
»
ÿ
⁄
NPS
TCDiode mV èC
» ÿ
⁄
(28)
8.2.1.2.10 UVLO Resistors – RUV1, RUV2
Given VIN(on) and VIN(off) as the input voltage turnon and turnoff thresholds of 5.5 V and 4 V, respectively, select
the upper and lower UVLO resistors using the following expressions:
VUV-FALLING
VUV-RISING
IUV-HYST
1.45 V
1.5 V
5 ꢀA
V
∂
- V
IN(off)
5.5 V ∂
- 4 V
IN(on)
RUV1
=
=
= 263kW
(29)
(30)
VUV-RISING
1.5 V
RUV2 = RUV1
∂
= 263kW ∂
= 98.6kW
V
- VUV-RISING
5.5 V -1.5 V
IN(on)
The nearest standard E96 resistor values for RUV1 and RUV2 are 261 kΩ and 97.6 kΩ, respectively. Calculate the
actual input voltage turnon and turnoff thresholds as follows:
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≈
’
÷
◊
RUV1
RUV2
≈
’
÷
◊
261kW
97.6kW
V
= VUV-RISING 1+
= 1.5V 1+
= 5.51V
∆
∆
IN(on)
«
«
(31)
(32)
≈
’
RUV1
RUV2
≈
’
÷
◊
261kW
97.6kW
V
= VUV-FALLING 1+
-IUV-HYST ∂RUV1 = 1.45V 1+
- 5ꢀA ∂ 261kW = 4.02V
∆
÷
◊
∆
IN(off)
«
«
8.2.1.2.11 Soft-Start Capacitor – CSS
Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start
capacitance of 47 nF based on 方程式 12 to achieve a soft-start time of 9 ms.
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power Management
technical articles.
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8.2.2 Application Curves
Unless otherwise stated, application performance curves were taken at TA = 25°C.
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
55
50
VIN = 6 V
VIN = 6 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
0
200
400
600
Load Current (mA)
800
1000
1200
1
10
100
1000
Load Current (mA)
D001
D002
图 8-2. Efficiency (Linear Scale)
图 8-3. Efficiency (Log Scale)
12.6
12.4
12.2
12
12.4
12.2
12
11.8
11.6
11.4
11.8
11.6
VIN = 6 V
VIN = 6 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
1
10
100
Load Current (mA)
1000 2000
0
200
400
600
Load Current (mA)
800 1000 1200 1400 1600
D004
D003
图 8-5. Load Regulation (Log Scale)
图 8-4. Load Regulation (Linear Scale)
VOUT 2 V/div
VOUT 2 V/div
IOUT 0.2 A/div
IOUT 0.2 A/div
VEN/UVLO 10 V/div
VIN 10 V/div
4 ms/div
4 ms/div
VIN = 24 V
12-Ω Load
VIN stepped to 24 V
12-Ω Load
图 8-7. Enable ON and OFF Characteristic
图 8-6. Start-up Characteristic
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VSW 10 V/div
VSW 10 V/div
1 ms/div
1 ms/div
VIN = 13.5 V
IOUT = 1 A
VIN = 24 V
IOUT = 1 A
图 8-8. Switch Node Voltage
图 8-9. Switch Node Voltage
VSW 10 V/div
VOUT 0.2 V/div
IOUT 0.5 A/div
1 ms/div
200 ms/div
VIN = 36 V
IOUT = 1 A
VIN = 24 V
图 8-10. Switch Node Voltage
图 8-11. Load Transient, 0.1 A to 1 A, 0.1 A/µs
VOUT 0.2 V/div
VOUT 0.2 V/div
IOUT 0.5 A/div
IOUT 0.5 A/div
200 ms/div
200 ms/div
VIN = 13.5 V
VIN = 6 V
图 8-12. Load Transient, 0.1 A to 1 A, 0.1 A/µs
图 8-13. Load Transient, 0.1 A to 0.5 A, 0.1 A/µs
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Average detector
Peak detector
Peak detector
Average detector
Start 150 kHz
Stop 30 MHz
Start 30 MHz
Stop 108 MHz
VIN = 24 V
IOUT = 1 A
150 kHz to 30 MHz
LIN = 4.7 µH
CIN = 10 µF
VIN = 24 V
IOUT = 1 A
30 MHz to 108 MHz
LIN = 4.7 µH
CIN = 10 µF
图 8-14. CISPR 25 Class 5 Conducted EMI Plot
图 8-15. CISPR 25 Class 5 Conducted EMI Plot
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8.2.3 Design 2: PSR Flyback Converter With Dual Outputs of 15 V and –8 V at 0.5 A
The schematic diagram of a dual-output flyback converter intended for isolated IGBT and SiC MOSFET gate
drive power supply applications is given in 图 8-16.
DFLY1
VIN = 4.5 V...42 V
T1
VOUT1 = 15 V
IOUT1 = 0.5 A
DCLAMP
DOUT1
18 V
COUT1
20 V
2 x
22 ꢀF
1 : 1.5 : 0.8
CIN
DF
VIN
EN/UVLO
7 mH
10 ꢀF
SW
FB
COUT2
DOUT2
9.1 V
RFB
2 x
LM25184
102 kW
47 ꢀF
VOUT2 = œ8 V
IOUT2 = œ0.5 A
GND
DFLY2
RSET
TC
RTC
RSET
12.1 kW
SS/BIAS
221 kW
图 8-16. Schematic for Design 2 With VIN(nom) = 13.5 V, VOUT1 = 15 V, VOUT2 = –8 V, IOUT = 0.5 A
8.2.3.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in 表 8-4.
表 8-4. Design Parameters
DESIGN PARAMETER
Input voltage range (steady state)
Output 1 voltage and current (at VIN ≥ 24 V)
Output 2 voltage and current (at VIN ≥ 24 V)
Input UVLO thresholds
VALUE
4.5 V to 42 V
15 V, 0.5 A
–8 V, 0.5 A
4.5 V on, 4 V off
±2%
Output voltage regulation
The target full-load efficiency of this LM25184-Q1 design is 89% based on a nominal input voltage of 13.5 V and
isolated output voltages of 15 V and –8 V sharing a common return. The selected flyback converter components
are cited in 表 8-5, including the following:
•
•
•
•
A multi-winding flyback transformer
Input and output capacitors
Flyback rectifying diodes
A flyback converter IC
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表 8-5. List of Components for Design 2
REF DES
QTY SPECIFICATION
VENDOR
PART NUMBER
CNA6P1X7R1H106K250AE
UMJ325KB7106KMHP
CGA6P3X7R1E226M250AB
TMK325B7226KMHT
GRM32EC81C476KE15L
EMK325AC6476MM-P
GRM32ER71A476KE15L
LMK325B7476MM-TR
C1210C476K8RAC7800
Micro Commercial
OnSemi
TDK
CIN
1
2
10 µF, 50 V, X7R, 1210, ceramic, AEC-Q200
Taiyo Yuden
TDK
COUT1
22 µF, 25 V, X7R, 1210, ceramic, AEC-Q200
47 μF, 16 V, X7S, 1210, Ceramic
Taiyo Yuden
Murata
Taiyo Yuden
Murata
COUT2
2
47 μF, 16 V, X7R, 1210, Ceramic
Taiyo Yuden
Kemet
DCLAMP
DF, DFLY2
DFLY1
DOUT1
DOUT2
RFB
1
1
2
1
1
1
1
1
Zener, 20 V, 3 W, SMA
3SMAJ5932B
FSV360FP
DFLS1100-7
BZX585-C18
BZX585-C9V1
Std
Schottky diode, 60 V, 3 A, SOD-123FL
Schottky diode, 100 V, 1 A, POWERDI123
Zener, 18 V, 5%, SOD-523, AEC-Q101
Zener, 9.1 V, 5%, SOD-523, AEC-Q101
102 kΩ, 1%, 0402
Diodes Inc.
Nexperia
Nexperia
Std
RSET
12.1 kΩ, 1%, 0402
Std
Std
RTC
221 kΩ, 1%, 0402
Std
Std
7 μH, 5 A, 1 : 1.5 : 0.8, 9.2 mm × 9.8 mm × 9.8 mm
7 μH, 5 A, 1 : 1.5 : 0.8, 13 mm × 11 mm × 10 mm
LM25184-Q1 PSR flyback converter, VSON-8, AEC-Q100
Würth Electronik
Coilcraft
750318704
T1
1
1
ZA9675-BE
U1
Texas Instruments
LM25184QNGURQ1
8.2.3.2 Detailed Design Procedure
Using the LM25184-Q1 quick-start calculator, components are selected based on the flyback converter
specifications.
8.2.3.2.1 Flyback Transformer – T1
Set the turns ratio of the transformer secondary windings using 方程式 33, where NS1 and NS2 are the number of
secondary turns for the respective outputs.
NS2 VOUT2 + VD2
NS1 VOUT1 + VD1 15 V + 0.3 V
8 V + 0.3 V
=
=
= 0.542
(33)
Choose a primary-secondary turns ratio for a 15-V output based on an approximate 70% max duty cycle at
minimum input voltage using 方程式 34. The transformer turns ratio when considering both outputs is thus
specified as 1 : 1.5 : 0.8.
V
DMAX
0.7
4.5V
IN(min)
NPS
=
∂
=
∂
= 0.69
1-DMAX VOUT + VD 1- 0.7 15V + 0.3V
(34)
Select a magnetizing inductance based on the minimum off-time constraint using 方程式 35. Choose a value of 7
µH and a saturation current of 5 A for this application.
V
+ VD ∂NPS ∂ tOFF-MIN
)
ISW-PEAK(FFM)
15V + 0.3V ∂11.5∂ 425ns
(
(
)
0.82A
OUT
LMAG
í
=
= 5.3ꢀH
(35)
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Find the maximum output current for a given turns ratio, assuming the outputs are symmetrically loaded, using
方程式 36.
0.45A at V = 12V
À
IN
ISW-PEAK
h
2
0.9
2
4.1A
Œ
IOUT(max)
=
∂
=
∂
=
Ã
≈
∆
«
’
÷
◊
≈
’
VOUT
1
0.57A at V = 24V
23V
1
Œ
Õ
IN
+
+
∆
∆
÷
÷
V
NPS
V
1 2.3
(
)
IN
IN
«
◊
(36)
8.2.3.2.2 Flyback Diodes – DFLY1 and DFLY2
The flyback diode reverse voltages for the positive and negative outputs are given respectively by 方程式 37 and
方程式 38.
V
42V
11.5
IN(max)
VD1-REV
í
+ VOUT1
=
+15V = 79V
NPS1
(
)
(37)
V
42V
IN(max)
VD2-REV
í
+ VOUT2 =
+ 8V = 42V
NPS2
1 0.8
(
)
(38)
Choose 100-V, 1-A and 60-V, 3-A Schottky diodes for the positive and negative outputs, respectively, to allow
some margin for inevitable voltage overshoot and ringing related to leakage inductance and diode capacitance.
Use an RC snubber circuit across each diode, for example, 100 Ω and 22 pF, to mitigate such overshoot and
ringing, particularly if the transformer leakage inductance is high.
8.2.3.2.3 Input Capacitor – CIN
The input capacitor filters the primary-winding current waveform. To prevent large ripple voltage, use a low-ESR
ceramic input capacitor sized according to 方程式 25 for the RMS ripple current given by 方程式 26. In this
design example, choose a 10-µF, 50-V ceramic capacitor with X7R dielectric and 1210 footprint.
8.2.3.2.4 Output Capacitors – COUT1, COUT2
The output capacitors determine the voltage ripple at the converter outputs, limit the voltage excursion during a
load transient, and set the dominant pole of the small-signal response of the converter.
Mindful of the voltage coefficient of ceramic capacitors, select two 22-µF, 25-V, X7R capacitors in 1210 case size
for the positive output and two 47-µF, 10-V, X7R capacitors in 1210 case size for the negative output.
8.2.3.2.5 Feedback Resistor – RFB
Install a 102-kΩ resistor from SW to FB based on an output voltage setpoint of 15 V (plus a flyback diode voltage
drop) reflected to the primary side by a transformer turns ratio of 1 : 1.5.
V
OUT1 + VD1 ∂N
15V + 0.3V ∂ 11.5
(
)
(
) (
)
= 102 kW
PS1
RFB
=
=
0.1mA
0.1mA
(39)
8.2.3.2.6 Thermal Compensation Resistor – RTC
Select a resistor value for output voltage thermal compensation based on 方程式 40.
RFB kW
»
ÿ
⁄
3
102 kW ∂3
11/ 5 ∂2
RTC kW =
∂
=
= 230 kW
»
ÿ
⁄
NPS
TCDiode mV èC
» ÿ
(
)
⁄
(40)
8.2.3.2.7 Output Voltage Clamp Zeners – DOUT1 and DOUT2
Calculate the power delivered to the output at no load based on 方程式 41.
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2
2
LMAG ∂ISW-PEAK(FFM)
7ꢀH∂ 0.82A
(
)
POUT(min)
=
∂FSW(min)
=
∂12kHz = 28mW
2
2
(41)
Select Zener clamp diodes to limit the voltages to a range of 110% to 120% of the nominal output voltage
setpoints during no-load operation. Connect 18-V and 9.1-V Zener diodes with ±5% tolerance and SOD-523
package across the positive and negative outputs, respectively.
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8.2.3.3 Application Curves
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
55
50
VIN = 6 V
VIN = 6 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
0
100
200
300
Load Current (mA)
400
500
600
1
10
100
1000
Load Current (mA)
D005
D006
图 8-17. Efficiency (Linear Scale)
图 8-18. Efficiency (Log Scale)
23.8
23.8
23.6
23.4
23.2
23
23.6
23.4
23.2
23
22.8
22.6
22.4
22.2
22.8
22.6
22.4
22.2
VIN = 6 V
VIN = 6 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
0
200
400
Load Current (mA)
600
800
1
10
100
1000
Load Current (mA)
D007
D008
Total of VOUT1 and VOUT2
Total of VOUT1 and VOUT2
图 8-19. Load Regulation (Linear Scale)
图 8-20. Load Regulation (Log Scale)
VIN 10 V/div
VOUT1 5 V/div
IOUT1 0.5 A/div
VSW 10 V/div
VOUT2 5 V/div
2 ms/div
20 ms/div
VIN stepped to 24 V
30-Ω and 16-Ω Loads
VIN = 24 V
IOUT1 = IOUT2 = 0 A
图 8-21. Start-Up Characteristic
图 8-22. Switch Voltage, No Load
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VSW 10 V/div
VSW 10 V/div
1 ms/div
1 ms/div
VIN = 24 V
IOUT1 = IOUT2 = 0.3 A
VIN = 24 V
IOUT1 = IOUT2 = 0.5 A
图 8-23. Switch Voltage, Medium Load
图 8-24. Switch Voltage, Full Load
VOUT1 0.2 V/div
VOUT1 0.2 V/div
VOUT2 0.2 V/div
VOUT2 0.2 V/div
IOUT1 0.2 A/div
IOUT2 0.2 A/div
IOUT2 0.2 A/div
IOUT1 0.2 A/div
200 ms/div
200 ms/div
VIN = 24 V
IOUT2 = 0.5 A
VIN = 24 V
IOUT1 = 0.5 A
图 8-25. Positive Output Load Transient, 0.25 A to
图 8-26. Negative Output Load Transient, 0.25 A to
0.5 A
0.5 A
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9 Power Supply Recommendations
The LM25184-Q1 flyback converter operates over a wide input voltage range from 4.5 V to 42 V. The
characteristics of the input supply must be compatible with 节 6.1 and 节 6.3. In addition, the input supply
must be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input
current with 方程式 42.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
(42)
where
•
η is the efficiency
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special
care is required to achieve stable performance. The parasitic inductance and resistance of the input cables
can have an adverse effect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients
at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to
dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause
false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from
the input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics.
The moderate ESR of the electrolytic capacitors helps damp the input resonant circuit and reduce any voltage
overshoots. A capacitance in the range of 22 µF to 100 µF is usually sufficient to provide input damping and
helps to hold the input voltage steady during large load transients. A typical ESR of 200 mΩ provides enough
damping for most input circuit configurations.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability
as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for
DC-DC Converters provides helpful suggestions when designing an input filter for any switching regulator.
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10 Layout
The performance of any switching converter depends as much upon PCB layout as it does the component
selection. The following guidelines are provided to assist with designing a PCB with the best power conversion
performance, thermal performance, and minimized generation of unwanted EMI. 图 10-1 and 图 10-2 provide
layout examples for single-output and dual-output designs, respectively.
10.1 Layout Guidelines
PCB layout is critical for good power supply design. There are several paths that conduct high slew-rate currents
or voltages that can interact with transformer leakage inductance or parasitic capacitance to generate noise and
EMI or degrade the performance of the power supply.
1. Bypass VIN to GND with a low-ESR ceramic capacitor, preferably of X7R or X7S dielectric. Place CIN as
close as possible to the LM25184-Q1 VIN and GND pins. Ground return paths for the input capacitor or
capacitors must consist of localized top-side planes that connect to the GND pin and exposed PAD.
2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.
3. Locate the transformer close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive
e-field or capacitive coupling.
4. Minimize the loop area formed by the diode-Zener clamp circuit connections and the primary winding
terminals of the transformer.
5. Minimize the loop area formed by the flyback rectifying diode, output capacitor, and the secondary winding
terminals of the transformer.
6. Tie the GND pin directly to the DAP under the device and to a heat-sinking PCB ground plane.
7. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
8. Have a single-point ground connection to the plane. Route the return connections for the reference resistor,
soft start, and enable components directly to the GND pin. This prevents any switched or load currents from
flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation
or erratic output voltage ripple behavior.
9. Make VIN+, VOUT+, and ground bus connections short and wide. This reduces any voltage drops on the input
or output paths of the converter and maximizes efficiency.
10. Minimize trace length to the FB pin. Locate the feedback resistor close to the FB pin.
11. Locate components RSET, RTC, and CSS as close as possible to their respective pins. Route with minimal
trace lengths.
12. Place a capacitor between input and output return connections to route common-mode noise currents
directly back to their source.
13. Provide adequate heatsinking for the LM25184-Q1 to keep the junction temperature below 150°C. For
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array
of heat-sinking vias to connect the DAP to the PCB ground plane. If the PCB has multiple copper layers,
connect these thermal vias to inner-layer ground planes. The connection to VOUT+ provides heatsinking for
the flyback diode.
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10.2 Layout Examples
Keep the DZ clamp and RC snubber
components close to the primary winding
pins and use heatsinking for the Zener
Place the input capacitor close
to the VIN pin and connect to
the GND plane under the IC
Locate the RC snubber
components close to
the flyback diode
Use adequate heatsinking
copper connected to the
cathode of the flyback
diode (VOUT)
Locate the converter IC close
to the transformer and connect
to the GND plane as shown
Keep the secondary
winding, flyback diode
and output capacitor
loop as tight as possible
Locate the RSET, TC and FB resistors and
the SS capacitor close to their respective pins
Place the Y-cap close to the transformer so that common-mode
currents from the secondary to the primary side return in a tight loop
图 10-1. Single-Output PCB Layout Example
Use heatsinking for the clamp
Zener, especially if the transformer
leakage inductance is high
Place the ceramic input
capacitor close to the IC to
minimize the switching loop area
Locate the converter IC close
to the transformer and connect
to the GND plane as shown
Minimize the area of the
secondary winding,
flyback diode and output
capacitor switching loops
Maintain the appropriate primary-
to-secondary clearance distance
Place the RSET, TC, FB and SS small-signal
components near their respective pins
图 10-2. Dual-Output PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 Development Support
With input voltage range and current capability as specified in 表 11-1, the PSR flyback DC/DC converter family
of parts from TI provides flexibility, scalability and optimized solution size for a range of applications. Using
an 8-pin WSON package with 4-mm × 4-mm footprint and 0.8-mm pin pitch, these converters enable isolated
DC/DC solutions with high density and low component count.
表 11-1. PSR Flyback DC/DC Converter Family
MAXIMUM LOAD CURRENT, VOUT = 12 V, NPS = 1
PSR FLYBACK
DC/DC CONVERTER
INPUT VOLTAGE
RANGE
PEAK SWITCH CURRENT
VIN = 4.5 V
90 mA
VIN = 13.5 V
180 mA
360 mA
360 mA
600 mA
1 A
LM5181-Q1
LM5180-Q1
LM25180-Q1
LM25183-Q1
LM25184-Q1
4.5 V to 65 V
4.5 V to 65 V
4.5 V to 42 V
4.5 V to 42 V
4.5 V to 42 V
0.75 A
1.5 A
1.5 A
2.5 A
4.1 A
180 mA
180 mA
300 mA
500 mA
For development support, see the following:
•
•
•
•
•
•
LM25184-Q1 Quick-start Calculator
LM25184-Q1 Simulation Models
For TI's reference design library, visit TI Designs
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
To view a related device of this product, see the LM25183-Q1 product page
TI Designs:
– Isolated IGBT Gate-Drive Power Supply Reference Design With Integrated Switch PSR Flyback Controller
– Compact, Efficient, 24-V Input Auxiliary Power Supply Reference Design for Servo Drives
– Reference Design for Power-Isolated Ultra-Compact Analog Output Module
– HEV/EV Traction Inverter Power Stage with 3 Types of IGBT/SiC Bias-Supply Solutions Reference Design
– 4.5-V to 65-V Input, Compact Bias Supply With Power Stage Reference Design for IGBT/SiC Gate Drivers
– Channel-to-Channel Isolated Analog Input Module Reference Design
– SiC/IGBT Isolated Gate Driver Reference Design With Thermal Diode and Sensing FET
– >95% Efficiency, 1-kW Analog Control AC/DC Reference Design for 5G Telecom Rectifier
– 3.5-W Automotive Dual-output PSR Flyback Regulator Reference Design
TI Technical Articles:
•
– Flyback Converters: Two Outputs are Better Than One
– Common Challenges When Choosing the Auxiliary Power Supply for Your Server PSU
– Maximizing PoE PD Efficiency on a Budget
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25184-Q1 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
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•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
LM25184 Single-Output EVM User's Guide (SNVU680)
LM5180 Single-Output EVM User's Guide (SNVU592)
LM5180 Dual-Output EVM User's Guide (SNVU609)
How an Auxless PSR Flyback Converter can Increase PLC Reliability and Density (SLYT779)
Why Use PSR-Flyback Isolated Converters in Dual-Battery mHEV Systems (SLYT791)
IC Package Features Lead to Higher Reliability in Demanding Automotive and Communications Equipment
Systems (SNVA804)
•
•
•
•
PSR Flyback DC/DC Converter Transformer Design for mHEV Applications (SNVA805)
Flyback Transformer Design Considerations for Efficiency and EMI (SLUP338)
Under the Hood of Flyback SMPS Designs (SLUP261)
White Papers:
– Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications
(SLYY104)
– An Overview of Conducted EMI Specifications for Power Supplies (SLYY136)
– An Overview of Radiated EMI Specifications for Power Supplies (SLYY142)
Using New Thermal Metrics Application Report (SBVA025)
Semiconductor and IC Package Thermal Metrics Application Report (SPRA953)
AN-2162: Simple Success with Conducted EMI from DC-DC Converters (SNVA489)
Automotive Cranking Simulator User's Guide (SLVU984)
•
•
•
•
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的使用条款。
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11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages have mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: LM25184-Q1
MECHANICAL DATA
NGU0008B
SDC08B (Rev A)
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
LM25184-Q1 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LM25184NGUR | TI | 具有 65V、4.1A 集成式 MOSFET 的 42V 输入电压非光电反激式转换器 | NGU | 8 | -40 to 150 | 获取价格 |
|
| LM25184QNGURQ1 | TI | 具有 65V、4.1A 集成式 MOSFET 的汽车类 42V 输入电压非光电反激式转换器 | NGU | 8 | -40 to 150 | 获取价格 |
|
| LM25185 | TI | 具有低 IQ 和低 EMI 的 42V 输入电压初级侧调节反激式控制器 | 获取价格 |
|
| LM25185-Q1 | TI | 具有低 IQ 和低 EMI 的汽车类 42V 输入电压初级侧调节反激式控制器 | 获取价格 |
|
| LM25185PWPR | TI | 具有低 IQ 和低 EMI 的 42V 输入电压初级侧调节反激式控制器 | PWP | 14 | -40 to 125 | 获取价格 |
|
| LM25185QPWPRQ1 | TI | 具有低 IQ 和低 EMI 的汽车类 42V 输入电压初级侧调节反激式控制器 | PWP | 14 | -40 to 125 | 获取价格 |
|
| LM2524 | NSC | Regulating Pulse Width Modulator | 获取价格 |
|
| LM2524D | NSC | Regulating Pulse Width Modulator | 获取价格 |
|
| LM2524DMDC | NSC | 暂无描述 | 获取价格 |
|
| LM2524DMWC | NSC | 暂无描述 | 获取价格 |
|
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