LM26001BMH/NOPB [TI]
具有高效睡眠模式的 1.5A 开关稳压器 | PWP | 16 | -40 to 125;
| 型号： | LM26001BMH/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高效睡眠模式的 1.5A 开关稳压器 | PWP | 16 | -40 to 125 开关 光电二极管 稳压器 |
| 文件： | 总31页 (文件大小：748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM26001B
www.ti.com
SNVS491B –MAY 2007–REVISED APRIL 2013
LM26001B 1.5A Switching Regulator with High Efficiency Sleep Mode
Check for Samples: LM26001B
1
FEATURES
DESCRIPTION
The LM26001B is a switching regulator designed for
the high efficiency requirements of applications with
stand-by modes. The device features a low-current
sleep mode to maintain efficiency under light-load
conditions and current-mode control for accurate
regulation over a wide input voltage range. Quiescent
current is reduced to 10 µA typically in shutdown
mode and less than 40 µA in sleep mode. Forced
PWM mode is also available to disable sleep mode.
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Efficiency Sleep Mode
40 µA Typical Iq in Sleep Mode
10 µA Typical Iq in Shutdown Mode
3.0V Minimum Input Voltage
4.0V to 18V Continuous Input Range
2.0% Reference Accuracy
Cycle-by-Cycle Current Limit
Adjustable Frequency (150 kHz to 500 kHz)
Synchronizable to an External Clock
Power Good Flag
The LM26001B can deliver up to 1.5A of continuous
load current with a fixed current limit, through the
internal N-channel switch. The part has a wide input
voltage range of 4.0V to 18V and can operate with
input voltages as low as 3V during line transients.
Forced PWM Function
Adjustable Soft-Start
Operating frequency is adjustable from 150 kHz to
HTSSOP-16 Exposed Pad Package
Thermal Shut Down
500 kHz with
a single resistor and can be
synchronized to an external clock.
Other features include Power good, adjustable soft-
start, enable pin, input under-voltage protection, and
an internal bootstrap diode for reduced component
count.
APPLICATIONS
•
•
•
•
•
Automotive Telematics
Navigation Systems
In-Dash Instrumentation
Battery Powered Applications
Stand-by Power for Home Gateways/Set-Top
Boxes
Typical Application Circuit
VIN
1
2
12
VIN
VIN
VBIAS
VOUT
C6
16
15
SW
C1
L
3
4
PGOOD
EN
+
SW
C4
D1
R1
14
7
R4
BOOT
EN
LM26001B
11
SYNC
SS
FB
VDD
5
9
6
13
8
COMP
SYNC
R6
FREQ
FPWM
VDD
GND
C8
R2
C5
10
EP
17
C3
R3
R5
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LM26001B
SNVS491B –MAY 2007–REVISED APRIL 2013
www.ti.com
Connection Diagram
Top View
VIN
VIN
1
2
3
4
5
6
7
16 SW
15 SW
PGOOD
EN
14 BOOT
13 VDD
12 VBIAS
11 SYNC
10 FPWM
SS
COMP
FB
GND
8
9 FREQ
Exposed Pad
Connect to GND
Figure 1. 16-Lead Exposed Pad HTSSOP Package
See Package Number PWP0016A
Pin Descriptions
Description
Pin #
Pin Name
VIN
1
2
3
Power supply input
VIN
Power supply input
PGOOD
Power Good pin. An open drain output which goes high when the output voltage is greater than 92% of
nominal.
4
5
EN
SS
Enable is an analog level input pin. When pulled below 0.8V, the device enters shutdown mode.
Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time.
Compensation pin. Connect to a resistor capacitor pair to compensate the control loop.
Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage.
Ground
6
COMP
FB
7
8
GND
FREQ
FPWM
9
Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency.
10
FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode
operation is disabled.
11
12
SYNC
VBIAS
Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC
must be pulled low for non-synchronized operation.
Connect to an external 3V or greater supply to bypass the internal regulator for improved efficiency. If
not used, VBIAS should be tied to GND.
13
14
VDD
The output of the internal regulator. Bypass with a minimum 1.0 µF capacitor.
BOOT
Bootstrap capacitor pin. Connect a 0.1µF minimum ceramic capacitor from this pin to SW to generate
the gate drive bootstrap voltage.
15
16
SW
SW
EP
Switch pin. The source of the internal N-channel switch.
Switch pin. The source of the internal N-channel switch.
Exposed Pad thermal connection. Connect to GND.
EP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNVS491B –MAY 2007–REVISED APRIL 2013
Absolute Maximum Ratings(1)
Voltages from the indicated pins to GND:
VIN
SW(2)
-0.3V to 20V
-0.5V to 20V
-0.3V to 7V
-0.3V to 10V
-0.3V to 6V
SW-0.3V to SW+7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 20V
-0.3V to 7V
-0.3V to 7V
-65°C to +150°C
2.6 W
VDD
VBIAS
FB
BOOT
PGOOD
FREQ
SYNC
EN
FPWM
SS
Storage Temperature
Power Dissipation(3)
Vapor Phase (70s)
Infrared (15s)
215°C
Recommended Lead Temperature
ESD Susceptibility(4)
220°C
Machine Model
200V
Human Body Model
Charged Device Model
2KV
1kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) The absolute maximum specification applies to DC voltage. An extended negative voltage limit of -2V applies for a pulse of up to 1µs,
and -1V for a pulse of up to 20µs.
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD_MAX = (TJ_MAX - TA) /θJA. The maximum power dissipation of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX
= 125°C.
(4) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin. The charged device model is per JESD22-C101-C.
Operating Ratings(1)
Operating Junction Temp.
Supply Voltage(2)
−40°C to 125°C
3.0V to 18V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) Below 4.0V input, power dissipation may increase due to increased RDS(ON). Therefore, a minimum input voltage of 4.0V is required to
operate continuously within specification. A minimum of 3.9V (typical) is also required for startup.
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Electrical Characteristics
Specifications in standard type are for TJ = 25°C only, and limits in boldface type apply over the junction temperature (TJ)
range of -40°C to +125°C. Unless otherwise stated, Vin=12V. Minimum and Maximum limits are ensured through test, design,
or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
System
(2)
ISD
Iq_Sleep_VB
Shutdown Current
EN = 0V
10.8
38
20
70
µA
µA
µA
µA
mA
µA
mA
V
(2)
Quiescent Current
Quiescent Current
Quiescent Current
Quiescent Current
Bias Current
Sleep mode, VBIAS = 5V
Sleep mode, VBIAS = GND
PWM mode, VBIAS = 5V
PWM mode, VBIAS = GND
Sleep mode, VBIAS = 5V
PWM mode, VBIAS = 5V
5V < Vin < 18V
Iq_Sleep_VDD
Iq_PWM_VB
Iq_PWM_VDD
75
125
150
0.65
33
230
0.85
85
(2)
IBIAS_Sleep
IBIAS_PWM
VFB
Bias Current
0.5
0.70
1.2589
±200
Feedback Voltage
FB Bias Current
Vout Line Regulation
Vout Load Regulation
1.2093
1.234
IFB
nA
%/V
%
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
VDD
5V < Vin < 18V
0.001
0.07
0.8V < VCOMP < 1.15V
7V < Vin < 18V, IVDD= 0 mA to 5
mA
VDD Output Voltage
Soft-Start Source Current
VBIAS On Voltage
5.50
1.5
5.95
2.2
6.50
4.6
V
µA
V
ISS_Source
Vbias_th
Specified at IBIAS = 92.5% of full
value
2.64
2.9
3.07
Switching
RDS(ON)
Isw_off
Switch On Resistance
Switch Off State Leakage Current
Switching Frequency
Isw = 1A
0.12
0.2
0.42
5.0
Ω
µA
%
Vin = 18V, VSW = 0V
RFREQ = 62k, 124k, 240k
0.002
fsw
±10
VFREQ
FREQ Voltage
1.0
V
fSW range
VSYNC
Switching Frequency Range
150
0.8
500
1.6
kHz
SYNC rising
SYNC falling
1.2
1.1
114
6
Sync Pin Threshold
V
Sync Pin Hysteresis
mV
nA
%
ISYNC
SYNC Leakage Current
FSYNC_UP
FSYNC_DN
TOFFMIN
TONMIN
Upper frequency synchronization range As compared to nominal fSW
Lower frequency synchronization range As compared to nominal fSW
Minimum Off-time
+30
-20
%
365
155
ns
ns
%
Minimum On-time
THSLEEP_HYS
THWAKE
Sleep Mode Threshold Hysteresis
VFB rising, % of THWAKE
101.2
Measured at falling FB,
COMP = 0.6V
Wake Up Threshold
1.234
V
IBOOT
BOOT Pin Leakage Current
BOOT = 16V, SW = 10V
0.0006
5.0
µA
(1) All room temperature limits are 100% production tested. All limits at temperature extremes are specified through correlation using
standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Iq and ISD specify the current into the VIN pin. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3V. All
quiescent current specifications apply to non-switching operation.
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Electrical Characteristics (continued)
Specifications in standard type are for TJ = 25°C only, and limits in boldface type apply over the junction temperature (TJ)
range of -40°C to +125°C. Unless otherwise stated, Vin=12V. Minimum and Maximum limits are ensured through test, design,
or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only(1)
Symbol
Protection
Parameter
Conditions
Min
Typ
Max
Unit
ILIMPK
Peak Current Limit
1.80
2.5
3.25
A
V
VFB_SC
Short Circuit Frequency Foldback
Threshold
Measured at FB falling
0.87
F_min_sc
Min Frequency in Foldback
Power Good Threshold
PGOOD Hysteresis
VFB < 0.3V
71
92
kHz
%
VTH_PGOOD
Measured at FB, PGOOD rising
89
95
2
7
8
%
IPGOOD_HI
RDS_PGOOD
VUVLO
PGOOD Leakage Current
PGOOD On Resistance
PGOOD = 5V
0.2
64
nA
Ω
PGOOD sink current = 500 µA
Vin falling , shutdown, VDD = VIN
Vin rising, soft-start, VDD = VIN
2.60
3.60
2.9
3.9
160
3.20
4.20
Under-Voltage Lock-Out Threshold
V
TSD
Thermal Shutdown Threshold
Thermal Resistance
°C
θJA
Power dissipation = 1W,
0 lfpm air flow
38
°C/W
Logic
VthEN
Enable Threshold voltage
Enable Hysteresis
0.8
0.8
1.2
120
4.5
1.2
35
1.4
1.6
V
mV
µA
V
IEN_Source
VTH_FPWM
IFPWM
EA
EN Source Current
FPWM Threshold
EN = 0V
FPWM Leakage Current
FPWM = 5V
nA
gm
Error Amp Trans-Conductance
COMP Source Current
COMP Sink Current
400
0.64
670
56
1000
1.27
µmho
µA
ICOMP
VCOMP = 0.9V
VCOMP = 0.9V
56
µA
VCOMP
COMP Pin Voltage Range
V
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Typical Performance Characteristics
Unless otherwise specified the following conditions apply: Vin = 12V, TJ = 25°C.
VFB vs Vin
(IDC = 300 mA)
VFB vs Temperature
1.236
1.235
1.236
1.234
1.232
1.230
1.228
1.234
1.233
1.232
-20
0
4
8
12
(V)
16
20
-40
0
20
40 60
120 140
80 100
TEMPERATURE (ºC)
V
IN
Figure 2.
Figure 3.
IQ and IVBIAS vs
Temperature (Sleep Mode)
IQ and IVBIAS vs
Temperature (PWM Mode)
90
80
70
60
50
700
600
500
IQ
IQ
(VBIAS=0V)
(VBIAS=0V)
IVBIAS
(VBIAS=5V)
400
300
IVBIAS
(VBIAS=5V)
40
30
20
IQ
IQ
200
100
(VBIAS=5V)
(VBIAS=5V)
140
-40
100
120
-20
0
20 40 60 80
-40
100
120 140
-20
0
20 40 60 80
TEMPERATURE (ºC)
TEMPERATURE (ºC)
Figure 4.
Figure 5.
Normalized Switching Frequency
vs Temperature (300kHz)
UVLO Threshold vs
Temperature (VDD = VIN)
102
101
4.1
3.9
3.7
3.5
On Threshold
100
99
3.3
3.1
Off Threshold
2.9
2.7
2.5
98
-40
-20
0
20 40
120
140
80 100
60
-40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (ºC)
TEMPERATURE (ºC)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: Vin = 12V, TJ = 25°C.
Peak Current Limit
vs Temperature
Short Circuit Foldback Frequency
vs VFB (325 kHz nominal)
350
300
3.0
2.8
2.6
2.4
2.2
2.0
250
200
150
100
50
0
-40 -20
0
20 40 60 80 100 120 140
0.2
0.4
0.6
0.8
(V)
1.0
1.2
V
TEMPERATURE (ºC)
FB
Figure 8.
Figure 9.
Efficiency vs
Load Current (330kHz)
Efficiency vs
Load Current (500kHz)
100
100
5Vout
5Vout
90
80
90
80
3.3Vout
3.3Vout
70
60
70
60
FPWM
mode
FPWM
mode
50
50
1
10
100
(mA)
1000
10000
1
10
100
(mA)
1000
10000
I
I
DC
DC
Figure 10.
Figure 11.
Startup Waveforms
Vout
1V/Div
PGOOD
5V/Div
SS
1V/Div
EN
10V/Div
1 ms/DIV
Figure 12.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: Vin = 12V, TJ = 25°C.
Low Input Voltage Dropout
Nominal VOUT = 5V
Load Transient Response
500
1A 125°C
Vout
450
40 mV/Div
400
1A 25°C
350
300
Iout
1A -40°C
250
500 mA/Div
200
150
100
50
40mA -40°C
40mA
25 to 125°C
0
3
3.5
4
4.5
VIN (V)
5
5.5
200 ms/DIV
Figure 13.
Figure 14.
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Block Diagram
VIN
5 mA
BG
IREF
TSD
on
LDO
UVLO
VDD
SD
qn
VDD_low
EN
Switchover
control
fpwm
VBIAS
FPWM
LG
wake
+
-
BG
VREG
Sync and
bootstrap
control
Sleep
Set
Sleep
Reset
fpwm
sleep
+
0.6V
+
-
FPWM / Sleep
Peak Current
Control
BOOT
EA
-
+
FB
-
+
V clamp
BG
VIN
I Sense
blanking
COMP
frequency
foldback
Corrective
Ramp
-
+
ff
qn
0.9V
+
-
PWM Control
Logic
-
+
PWM
Comp
0.92BG
SW
PG
sleep
PGOOD
Clock / Sync
SW
LG
-
+
ss end
2 mA
-
ff
+
FREQ
SYNC
SS
VDD_low
TSD
on
SS
logic
+
-
soft start
SD
EP
GND
Operation Description
GENERAL
The LM26001B is a current mode PWM buck regulator. At the beginning of each clock cycle, the internal high-
side switch turns on, allowing current to ramp up in the inductor. The inductor current is internally monitored
during each switching cycle. A control signal derived from the inductor current is compared to the voltage control
signal at the COMP pin, derived from the feedback voltage. When the inductor current reaches the threshold, the
high-side switch is turned off and inductor current ramps down. While the switch is off, inductor current is
supplied through the catch diode. This cycle repeats at the next clock cycle. In this way, duty cycle and output
voltage are controlled by regulating inductor current. Current mode control provides superior line and load
regulation. Other benefits include cycle by cycle current limiting and a simplified compensation scheme. Typical
PWM waveforms are shown in Figure 15.
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Vout
10 mV/Div
IL
500 mA/Div
ID
1A/Div
V
SW
5V/Div
1 ms/DIV
Figure 15. PWM Waveforms
1A Load, Vin = 12V
SLEEP MODE
In light load conditions, the LM26001B automatically switches into sleep mode for improved efficiency. As loading
decreases, the voltage at FB increases and the COMP voltage decreases. When the COMP voltage reaches the
0.6V (typical) clamp threshold, and the FB voltage rises 1% above nominal, sleep mode is enabled and switching
stops. The regulator remains in sleep mode until the FB voltage falls to the reset threshold, at which point
switching resumes. This 1% FB window limits the corresponding output ripple to approximately 1% of nominal
output voltage. The sleep cycle will repeat until load current is increased. Figure 16 shows typical switching and
output voltage waveforms in sleep mode.
Vout
50 mV/Div
IL
200 mA/Div
V
SW
5V/Div
100 ms/DIV
Figure 16. Sleep Mode Waveforms
25mA Load, Vin = 12V
In sleep mode, quiescent current is reduced to less than 40 µA when not switching. The DC sleep mode
threshold can be calculated according to the equation below:
2
Vin - Vout
L
fsw x L
ISleep
=
Imin + 0.13 m
x
D x 2 x (Vin œ Vout)
where
•
Imin=Ilim/16 (2.5A/16 typically) and D=duty cycle, defined as (Vout+Vdiode)/Vin
(1)
When load current increases above this limit, the LM26001B is forced back into PWM operation. The sleep mode
threshold varies with frequency, inductance, and duty cycle as shown in Figure 17.
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160
140
120
100
80
500 kHz
22 mH
15 mH
22 mH
60
330 kHz
15 mH
40
20
10 12 14 16 18 20
VIN (V)
4
8
6
Figure 17. Sleep Mode Threshold vs Vin
Vout = 3.3V
FPWM
Pulling the FPWM pin high disables sleep mode and forces the LM26001B to always operate in PWM mode.
Light load efficiency is reduced in PWM mode, but switching frequency remains stable. The FPWM pin can be
connected to the VDD pin to pull it high. In FPWM mode, under light load conditions, the regulator operates in
discontinuous conduction mode (DCM) . In discontinuous conduction mode, current through the inductor starts at
zero and ramps up to its peak, then ramps down to zero again. Until the next cycle, the inductor current remains
at zero. At nominal load currents, in FPWM mode, the device operates in continuous conduction mode, where
positive current always flows in the inductor. Typical discontinuous operation waveforms are shown below.
Vout
10 mV/Div
IL
200 mA/Div
V
SW
5V/Div
1 ms/DIV
Figure 18. Discontinuous Mode Waveforms
75mA Load, Vin = 12V
At very light load, in FPWM mode, the LM26001B may enter sleep mode. This is to prevent an over-voltage
condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation.
ENABLE
The LM26001B provides a shutdown function via the EN pin to disable the device when the output voltage does
not need to be maintained. EN is an analog level input with typically 120 mV of hysteresis. The device is active
when the EN pin is above 1.2V (typical) and in shutdown mode when EN is below this threshold. When EN goes
high, the internal VDD regulator turns on and charges the VDD capacitor. When VDD reaches 3.9V (typical), the
soft-start pin begins to source current. In shutdown mode, the VDD regulator shuts down and total quiescent
current is reduced to 10 µA (typical). Because the EN pin sources 4.5 µA (typical) of pull-up current, this pin can
be left open or connected to VIN for always-on operation. When open, EN will be pulled up to VIN.
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SOFT-START
The soft-start feature provides a controlled output voltage ramp up at startup. This reduces inrush current and
eliminates output overshoot at turn-on. The soft-start pin, SS, must be connected to GND through a capacitor. At
power-on, enable, or UVLO recovery, an internal 2.2 µA (typical) current charges the soft-start capacitor. During
soft-start, the error amplifier output voltage is controlled by both the soft-start voltage and the feedback loop. As
the SS pin voltage ramps up, the duty cycle increases proportional to the soft-start ramp, causing the output
voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft-start
capacitor. The higher the capacitance, the slower the output voltage ramps up. The soft-start capacitor value can
be calculated with the following equation:
Iss x tss
Css =
1.234V
(2)
Where tss is the desired soft-start time and Iss is the soft-start source current. During soft-start, current limit and
synchronization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends
when the SS pin voltage reaches 1.23V typical. At this point, output voltage control is transferred to the FB pin
and the SS pin is discharged.
CURRENT LIMIT
The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To
ensure accurate current sensing, VIN should be bypassed with a minimum 1µF ceramic capacitor placed directly
at the pin.
When the inductor current reaches the current limit threshold, the internal FET turns off immediately allowing
inductor current to ramp down until the next cycle. This reduction in duty cycle corresponds to a reduction in
output voltage.
The current limit comparator is disabled for less than 100ns at the leading edge for increased immunity to
switching noise.
Because the current limit monitors peak inductor current, the DC load current limit threshold varies with
inductance and frequency. Assuming a minimum current limit of 1.80A, maximum load current can be calculated
as follows:
Iripple
Iloadmax = 1.80A -
2
where
(Vin œ Vout) x Vout
Iripple =
fsw x L x Vin
•
Iripple is the peak-to-peak inductor ripple current, calculated as
(3)
To find the worst case (lowest) current limit threshold, use the maximum input voltage and minimum current limit
specification.
During high over-current conditions, such as output short circuit, the LM26001B employs frequency foldback as a
second level of protection. If the feedback voltage falls below the short circuit threshold of 0.9V, operating
frequency is reduced, thereby reducing average switch current. This is especially helpful in short circuit
conditions, when inductor current can rise very high during the minimum on-time. Frequency reduction begins at
20% below the nominal frequency setting. The minimum operating frequency in foldback mode is 71 kHz typical.
If the FB voltage falls below the frequency foldback threshold during frequency synchronized operation, the
SYNC function is disabled. Operating frequency versus FB voltage in short circuit conditions is shown in the
Typical Performance Characteristics section.
In conditions where the on time is close to minimum (less than 200nsec typically), such as high input voltage and
high switching frequency, the current limit may not function properly. This is because the current limit circuit
cannot reduce the on-time below minimum which prevents entry into frequency foldback mode. There are two
ways to ensure proper current limit and foldback operation under high input voltage conditions. First, the
operating frequency can be reduced to increase the nominal on time. Second, the inductor value can be
increased to slow the current ramp and reduce the peak over-current.
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FREQUENCY ADJUSTMENT AND SYNCHRONIZATION
The switching frequency of the LM26001B can be adjusted between 150 kHz and 500 kHz using a single
external resistor. This resistor is connected from the FREQ pin to ground as shown in the Typical Application
Circuit. The resistor value can be calculated with the following empirically derived equation:
-1.042
RFREQ = (6.25 x 1010) x fSW
(4)
600
500
400
300
200
100
0
50
100
150
200
250
300
R
FREQ
(kW)
Figure 19. Swtiching Frequency vs RFREQ
The switching frequency can also be synchronized to an external clock signal using the SYNC pin. The SYNC
pin allows the operating frequency to be varied above and below the nominal frequency setting. The adjustment
range is from 30% above nominal to 20% below nominal. External synchronization requires a 1.2V (typical) peak
signal level at the SYNC pin. The FREQ resistor must always be connected to initialize the nominal operating
frequency. The operating frequency is synchronized to the falling edge of the SYNC input. When SYNC goes
low, the high-side switch turns on. This allows any duty cycle to be used for the sync signal when synchronizing
to a frequency higher than nominal. When synchronizing to a lower frequency, however, there is a minimum duty
cycle requirement for the SYNC signal, given in the equation below:
fsync
Sync_Dmin
1 -
í
fnom
(5)
Where fnom is the nominal switching frequency set by the FREQ resistor, and fsync is a square wave. If the
SYNC pin is not used, it must be pulled low for normal operation. A 10kΩ pull-down resistor is recommended to
protect against a missing sync signal. Although the LM26001B is designed to operate at up to 500 kHz,
maximum load current may be limited at higher frequencies due to increased temperature rise. See the Thermal
Considerations section.
VBIAS
The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26001B. When
the VBIAS pin is connected to a voltage greater than 3V, the internal regulator automatically switches over to the
VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS pin has the
added benefit of reducing power dissipation within the device.
For most applications where 3V < Vout < 10V, VBIAS can be connected to Vout. If not used, VBIAS should be
tied to GND.
If VBIAS drops below 2.9V (typical), the device automatically switches over to supply the internal bias voltage
from Vin.
Total device input current is the sum of Iq, gate drive current, and VBIAS current, plus some negligible current
into the FB pin. Total minimum input supply current can be calculated as shown below:
IBIAS x D
≈
«
’
Iinput = Iq + IQG
+
eff ◊
where
•
IQG is the gate drive current, calculated as IQG = (4.6 x 10-9) x fSW
(6)
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Total supply input current varies according to load, system efficiency, and operating frequency. To calculate
minimum input current during sleep mode, use Iq_Sleep_VB, and IBIAS_SLEEP
.
For input current in PWM mode, use the same equation, with Iq_PWM_VB, and IBIAS_PWM
.
If VBIAS is connected to ground, use the same equation with the Ibias term eliminated and either Iq_Sleep_VDD or
Iq_PWM_VDD
.
LOW VIN OPERATION AND UVLO
The LM26001B is designed to remain operational during short line transients when input voltage may drop as low
as 3.0V. Minimum nominal operating input voltage is 4.0V. Below this voltage, switch RDS(ON) increases, due to
the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately 3.5V for normal
operation within specification.
VDD can also be used as a pull-up voltage for functions such as PGOOD and FPWM. Note that if VDD is used
externally, the pin is not recommended for loads greater than 1 mA.
If the input voltage approaches the nominal output voltage, the duty cycle is maximized to hold up the output
voltage. In this mode of operation, once the duty cycle reaches its maximum, the LM26001B can skip a
maximum of seven off pulses, effectively increasing the duty cycle and thus minimizing the dropout from input to
output. Typical off-pulse skipping waveforms are shown below.
Vout
20 mV/Div
IL
100 mA/Div
V
SW
2V/Div
4 ms/DIV
Figure 20. Off-pulse Skipping Waveforms
Vin = 3.5V, Vnom = 3.3V, fnom = 305kHz
UVLO is sensed at both VIN and VDD, and is activated when either voltage falls below 2.9V (typical). Although
VDD is typically less than 200mV below VIN, it will not discharge through VIN. Therefore when the VIN voltage
drops rapidly, VDD may remain high, especially in sleep mode. For fast line voltage transients, using a larger
capacitor at the VDD pin can help to hold off a UVLO shutdown by extending the VDD discharge time. By
holding up VDD, a larger cap can also reduce the RDS(ON) (and dropout voltage) in low VIN conditions.
Alternately, under heavy loading the VDD voltage can fall several hundred mV below VIN. In this case, UVLO
may be triggered by VDD even though the VIN voltage is above the UVLO threshold.
When UVLO is activated the LM26001B enters a standby state in which VDD remains charged. As input voltage
and VDD voltage rise above 3.9V (typical) the device will restart from softstart mode.
PGOOD
A power good pin, PGOOD, is available to monitor the output voltage status. The pin is internally connected to
an open drain MOSFET, which remains open while the output voltage is within operating range. PGOOD goes
low (low impedance to ground) when the output falls below 85% of nominal or EN is pulled low. When the output
voltage returns to within 92% of nominal, as measured at the FB pin, PGOOD returns to a high state. For
improved noise immunity, there is a 5us delay between the PGOOD threshold and the PGOOD pin going low.
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Design Information
EXAMPLE CIRCUIT
Figure 21 shows a complete typical application schematic. The components have been selected based on the
design criteria given in the following sections.
Vin: 4V œ 18V
C1
3.3 mF
25V
C2
47 mF
25V
+
L
1
2
12
16
22 mH
3.5A
VIN
VIN
VBIAS
SW
Vout: 3.3V
15
3
4
C6
+
D1
3A
30V
PGOOD
SW
C4
0.1 mF
R1
56k
1%
100 mF
8V
PGOOD
R4
14
7
EN
BOOT
200k
12 mW
EN
LM26001B
11
VDD
SYNC
FB
5
9
6
13
8
SS
COMP
R2
33k
1%
SYNC
C8
4.7 nF
FREQ
FPWM
VDD
GND
C5
10 nF
R6
10k
10
C9
47 pF
R3
120k
1%
R5
15k
EP
17
C3
10 mF
Figure 21. Example Circuit
1.5A Max, 305 kHz
SETTING OUTPUT VOLTAGE
The output voltage is set by the ratio of a voltage divider at the FB pin as shown in the Typical Application
Circuit. The resistor values can be determined by the following equation:
R1
R2 =
Vout
Vfb
≈
«
’
◊
-1
where
•
Vfb = 1.234V typically
(7)
A maximum value of 150kΩ is recommended for the sum of R1 and R2.
As input voltage decreases towards the nominal output voltage, the LM26001B can skip up to seven off-pulses
as described in the Low Vin Operation section. In low output voltage applications, if the on-time reaches TonMIN
,
the device will skip on-pulses to maintain regulation. There is no limit to the number of pulses that are skipped. In
this mode of operation, however, output ripple voltage may increase slightly.
INDUCTOR
The output inductor should be selected based on inductor ripple current. The amount of inductor ripple current
compared to load current, or ripple content, is defined as Iripple/Iload. Ripple content should be less than 40%.
Inductor ripple current, Iripple, can be calculated as shown below:
(Vin œ Vout) x Vout
Iripple =
fsw x L x Vin
(8)
Larger ripple content increases losses in the inductor and reduces the effective current limit.
Larger inductance values result in lower output ripple voltage and higher efficiency, but a slightly degraded
transient response. Lower inductance values allow for smaller case size, but the increased ripple lowers the
effective current limit threshold.
Remember that inductor value also affects the sleep mode threshold as shown in Figure 17.
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When choosing the inductor, the saturation current rating must be higher than the maximum peak inductor
current and the RMS current rating should be higher than the maximum load current. Peak inductor current,
Ipeak, is calculated as:
Iripple
Ipeak = Iload +
2
(9)
For example, at a maximum load of 1.5A and a ripple content of 33%, peak inductor current is equal to 1.75A
which is safely below the minimum current limit of 1.80A. By increasing the inductor size, ripple content and peak
inductor current are lowered, which increases the current limit margin.
The size of the output inductor can also be determined using the desired output ripple voltage, Vrip. The
equation to determine the minimum inductance value based on Vrip is as follows:
(Vin œ Vout) x Vout x Re
LMIN
=
Vin x fsw x Vrip
where
•
•
Re is the ESR of the output capacitors
Vrip is a peak-to-peak value
(10)
This equation assumes that the output capacitors have some amount of ESR. It does not apply to ceramic output
capacitors.
If this method is used, ripple content should still be verified to be less than 40%.
OUTPUT CAPACITOR
The primary criterion for selecting an output capacitor is equivalent series resistance, or ESR.
ESR (Re) can be selected based on the requirements for output ripple voltage and transient response. Once an
inductor value has been selected, ripple voltage can be calculated for a given Re using the equation above for
Lmin. Lower ESR values result in lower output ripple.
Re can also be calculated from the following equation:
DVt
ReMAX
=
DIt
where
•
•
ΔVt is the allowed voltage excursion during a load transient
ΔIt is the maximum expected load transient
(11)
If the total ESR is too high, the load transient requirement cannot be met, no matter how large the output
capacitance.
If the ESR criteria for ripple voltage and transient excursion cannot be met, more capacitors should be used in
parallel.
For non-ceramic capacitors, the minimum output capacitance is of secondary importance, and is determined only
by the load transient requirement.
If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if
the maximum ESR requirement is met. The minimum capacitance is calculated as follows:
≈
(DVt)2 - (DIt x Re)2
≈
DVt -
L x
«
CMIN
=
Vout x Re2
(12)
It is assumed the total ESR, Re, is no greater than ReMAX. Also, it is assumed that L has already been selected.
Generally speaking, the output capacitance requirement decreases with Re, ΔIt, and L. A typical value greater
than 100 µF works well for most applications.
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INPUT CAPACITOR
In a switching converter, very fast switching pulse currents are drawn from the input rail. Therefore, input
capacitors are required to reduce noise, EMI, and ripple at the input to the LM26001B. Capacitors must be
selected that can handle both the maximum ripple RMS current at highest ambient temperature as well as the
maximum input voltage. The equation for calculating the RMS input ripple current is shown below:
Vout x (Vin œ Vout)
Iload x
Irms =
Vin
(13)
For noise suppression, a ceramic capacitor in the range of 1.0 µF to 10 µF should be placed as close as possible
to the VIN pin.
A larger, high ESR input capacitor should also be used. This capacitor is recommended for damping input
voltage spikes during power on and for holding up the input voltage during transients. In low input voltage
applications, line transients may fall below the UVLO threshold if there is not enough input capacitance. Both
tantalum and electrolytic type capacitors are suitable for the bulk capacitor. However, large tantalums may not be
available for high input voltages and their working voltage must be derated by at least 2X.
BOOTSTRAP
The drive voltage for the internal switch is supplied via the BOOT pin. This pin must be connected to a ceramic
capacitor, Cboot, from the switch node, shown as C4 in the typical application. The LM26001B provides the VDD
voltage internally, so no external diode is needed. A minimum value of 0.1 uF is recommended for Cboot.
Smaller values may result in insufficient hold up time for the drive voltage and increased power dissipation.
During low Vin operation, when the on-time is extended, the bootstrap capacitor is at risk of discharging. If the
Cboot capacitor is discharged below approximately 2.5V, the LM26001B enters a high frequency re-charge
mode. The Cboot cap is re-charged via the LG synchronous FET shown in the Block Diagram. Switching returns
to normal when the Cboot cap has been recharged.
CATCH DIODE
When the internal switch is off, output current flows through the catch diode. Alternately, when the switch is on,
the diode sees a reverse voltage equal to Vin. Therefore, the important parameters for selecting the catch diode
are peak current and peak inverse voltage. The average current through the diode is given by:
IDAVE = Iload x (1-D)
(14)
Where D is the duty cycle, defined as Vout/Vin. The catch diode conducts the largest currents during the lowest
duty cycle. Therefore IDAVE should be calculated assuming maximum input voltage. The diode should be rated to
handle this current continuously. For over-current or short circuit conditions, the catch diode should be rated to
handle peak currents equal to the peak current limit.
The peak inverse voltage rating of the diode must be greater than maximum input voltage.
A Schottky diode must be used. It's low forward voltage maximizes efficiency and BOOT voltage, while also
protecting the SW pin against large negative voltage spikes
COMPENSATION
The purpose of loop compensation is to ensure stable operation while maximizing dynamic performance. Stability
can be analyzed with loop gain measurements, while dynamic performance is analyzed with both loop gain and
load transient response. Loop gain is equal to the product of control-output transfer function (power stage) and
the feedback transfer function (the compensation network).
For stability purposes, our target is to have a loop gain slope that is -20dB /decade from a very low frequency to
beyond the crossover frequency. Also, the crossover frequency should not exceed one-fifth of the switching
frequency, i.e. 60 kHz in the case of 300 kHz switching frequency.
For dynamic purposes, the higher the bandwidth, the faster the load transient response. A large DC gain means
high DC regulation accuracy (i.e. DC voltage changes little with load or line variations). To achieve this loop gain,
the compensation components should be set according to the shape of the control-output bode plot. A typical
plot is shown in Figure 22 below.
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fp
fz
fn
0
20
0
-45
-20
-40
-60
-90
-135
-180
1000
0.01
0.1
1
10
100
FREQUENCY (kHz)
Figure 22. Control-Output Transfer Function
The control-output transfer function consists of one pole (fp), one zero (fz), and a double pole at fn (half the
switching frequency).
Referring to Figure 22, the following should be done to create a -20dB /decade roll-off of the loop gain:
1. Place a pole at 0Hz (fpc)
2. Place a zero at fp (fzc)
3. Place a second pole at fz (fpc1)
The resulting feedback (compensation) bode plot is shown below in Figure 23. Adding the control-output
response to the feedback response will then result in a nearly continuous -20db/decade slope.
0dB/dec
B
fzc
fpc1
fpc
(0Hz)
FREQUENCY
Figure 23. Feedback Transfer Function
The control-output corner frequencies can be determined approximately by the following equations:
1
fz =
2p x Re x Co
(15)
(16)
0.5
1
+
fp =
2 x p x L x fsw x Co
10 x p x Ro x Co
fsw
2
fn =
where
•
•
•
•
Co is the output capacitance
Ro is the load resistance
Re is the output capacitor ESR
fsw is the switching frequency
(17)
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The effects of slope compensation and current sense gain are included in this equation. However, the equation is
an approximation intended to simplify loop compensation calculations. To derive the exact transfer function, use
0.2V/V sense amp gain and 36mVp-p slope compensation.
Since fp is determined by the output network, it shifts with loading. Determine the range of frequencies
(fpmin/max) across the expected load range. Then determine the compensation values as described below and
shown in Figure 24.
5
SS
6
COMP
7
FB
C8
R5
C9
C10
R2
R1
To Vout
Figure 24. Compensation Network
1. The compensation network automatically introduces a low frequency pole (fpc), which is close to 0Hz.
2. Once the fp range is determined, R5 should be calculated using:
B
R1 + R2
R2
≈
«
’
◊
x
R5 =
gm
where
•
•
B is the desired feedback gain in v/v between fp and fz
gm is the transconductance of the error amplifier
(18)
A gain value around 10dB (3.3v/v) is generally a good starting point. Bandwidth increases with increasing values
of R5.
3. Next, place a zero (fzc) near fp using C8. C8 can be determined with the following equation:
1
C8 =
2 x p x fPMAX x R5
(19)
The selected value of C8 should place fzc within a decade above or below fpmax, and not less than fpmin. A
higher C8 value (closer to fpmin) generally provides a more stable loop, but too high a value will slow the
transient response time. Conversely, a smaller C8 value will result in a faster transient response, but lower phase
margin.
4. A second pole (fpc1) can also be placed at fz. This pole can be created with a single capacitor, C9. The
minimum value for this capacitor can be calculated by:
1
C9 =
2 x p x fz x R5
(20)
C9 may not be necessary in all applications. However if the operating frequency is being synchronized below the
nominal frequency, C9 is recommended. Although it is not required for stability, C9 is very helpful in suppressing
noise.
A phase lead capacitor can also be added to increase the phase and gain margins. The phase lead capacitor is
most helpful for high input voltage applications or when synchronizing to a frequency greater than nominal. This
capacitor, shown as C10 in Figure 24, should be placed in parallel with the top feedback resistor, R1. C10
introduces an additional zero and pole to the compensation network. These frequencies can be calculated as
shown below:
1
fzff =
2 x p x R1 x C10
(21)
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fzff x Vout
fpff =
Vfb
(22)
A phase lead capacitor will boost loop phase around the region of the zero frequency, fzff. fzff should be placed
somewhat below the fpz1 frequency set by C9. However, if C10 is too large, it will have no effect.
PCB Layout
Good board layout is critical for switching regulators such as the LM26001B. First, the ground plane area must
be sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the
effects of switching noise.
Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current
combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the
VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike
noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance.
Therefore, care must be taken in layout to minimize the effect of this switching noise.
The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can
cause duty cycle jitter which leads to increased spectral noise. Although the LM26001B has 100ns blanking time
at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the
important guidelines below will help minimize switching noise and its effect on current sensing.
The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors
should be grounded to a large ground plane, with the bulk input capacitor grounded as close as possible to the
catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy
and should be somewhat isolated from the rest of the ground plane.
A ceramic input capacitor must be connected as close as possible to the VIN pin and grounded close to the GND
pin. Often this capacitor is most easily located on the bottom side of the pcb. If placement close to the GND pin
is not practical, the ceramic input capacitor can also be grounded close to the catch diode ground. The above
layout recommendations are illustrated below in Figure 25.
Vout
Vin
GND
SW
EP
GND
Figure 25. Example PCB Layout
It is a good practice to connect the EP, GND pin, and small signal components (COMP, FB, FREQ) to a separate
ground plane, shown in Figure 25 as EP GND, and in the schematics as a signal ground symbol. Both the
exposed pad and the GND pin must be connected to ground. This quieter plane should be connected to the high
current ground plane at a quiet location, preferably near the Vout ground as shown by the dashed line in
Figure 25.
The EP GND plane should be made as large as possible, since it is also used for thermal dissipation. Several
vias can be placed directly below the EP to increase heat flow to other layers when they are available. The
recommended via hole diameter is 0.3mm.
The trace from the FB pin to the resistor divider should be short and the entire feedback trace must be kept away
from the inductor and switch node. See Application Note AN-1229 for more information regarding PCB layout for
switching regulators.
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Thermal Considerations and TSD
Although the LM26001B has a built in current limit, at ambient temperatures above 80°C, device temperature rise
may limit the actual maximum load current. Therefore, temperature rise must be taken into consideration to
determine the maximum allowable load current.
Temperature rise is a function of the power dissipation within the device. The following equations can be used to
calculate power dissipation (PD) and temperature rise, where total PD is the sum of FET switching losses, FET
DC losses, drive losses, Iq, and VBIAS losses:
PDTOTAL = PswAC + PswDC + PQG + PIq + PVBIAS
(23)
Vin x 10-9
≈
«
’
◊
PswAC = Vin x Iload x fsw x
1.33
(24)
(25)
(26)
(27)
(28)
PswDC = D x Iload2 x (0.2 + 0.00065 x (Tj - 25))
PQG = Vin x 4.6 x 10-9 x fsw
PIq = Vin x Iq
PVBIAS = Vbias x IVBIAS
Given this total power dissipation, junction temperature can be calculated as follows:
Tj = Ta + (PDTOTAL x θJA)
where
•
θJA=38°C/W (typically) when using a multi-layer board with a large copper plane area
(29)
θJA varies with board type and metallization area.
To calculate the maximum allowable power dissipation, assume Tj = 125°C. To ensure that junction temperature
does not exceed the maximum operating rating of 125°C, power dissipation should be verified at the maximum
expected operating frequency, maximum ambient temperature, and minimum and maximum input voltage. The
calculated maximum load current is based on continuous operation and may be exceeded during transient
conditions.
If the power dissipation remains above the maximum allowable level, device temperature will continue to rise.
When the junction temperature exceeds its maximum, the LM26001B engages Thermal Shut Down (TSD). In
TSD, the part remains in a shutdown state until the junction temperature falls to within normal operating limits. At
this point, the device restarts in soft-start mode.
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
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23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM26001BMH/NOPB
LM26001BMHX/NOPB
ACTIVE
HTSSOP
HTSSOP
PWP
16
16
92
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
L26001
BMH
Samples
Samples
ACTIVE
PWP
2500 RoHS & Green
Call TI | SN
L26001
BMH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM26001BMHX/NOPB HTSSOP PWP
16
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LM26001BMHX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM26001BMH/NOPB
16
92
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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